Display panel, manufacturing method thereof and display device

Abstract

The invention relates to a display panel, a manufacturing method of the display panel and a display device. The pixel array comprises m pixel units, and each pixel unit comprises a sub-pixels; in each pixel unit, the sub-pixels are arranged according to a polygon, and each sub-pixel is located at the vertex of the polygon; m groups of anode pads and m groups of cathode pads; the m common bonding pads are located in the polygons in the pixel units; the common bonding pad is a common cathode bonding pad electrically connected with the cathode bonding pads; the common bonding pad connecting lines are electrically connected with the common bonding pads of each row of pixel units, and the common bonding pad connecting lines of each row are located on the same straight line; and the electrode connecting lines are located on the same straight line and electrically connected with the bonding pads of the same seed pixels in one row or one column in the pixel array. The circuit design is simplified, the area occupied by the bonding pads, the connecting lines and the through holes is small, and therefore the number of pixels in the unit area can be increased, and the resolution ratio of a display screen is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of display equipment, and in particular to a display panel, a method for manufacturing a display panel, and a display device. Background Art

[0002] With the development of display technology, improving resolution has become an important research topic in the field of LED (light emitting diode) display. To this end, it is necessary to increase the number of pixels per unit area.

[0003] Traditional LED display panels have complex circuit designs, so it is difficult to improve the resolution of the display. Summary of the invention

[0004] Based on this, it is necessary to provide a display panel with a relatively simple circuit.

[0005] A display panel comprises: a substrate; a pixel array, located on a first main surface of the substrate, comprising m pixel units, each pixel unit comprising a sub-pixels, the pixel array comprising at most a sub-pixels, a being an integer greater than 2, and m being a positive integer greater than 3; in each pixel unit, the sub-pixels are arranged in a polygonal manner, and each sub-pixel is located at a vertex of the polygon; m groups of anode pads and m groups of cathode pads, located on the first main surface of the substrate, each group of anode pads comprising a anode pads corresponding to the a sub-pixels one-to-one, and each group of cathode pads comprising a cathode pads corresponding to the a sub-pixels one-to-one; m common pads, located on the first main surface and located inside the polygon in each pixel unit; the common pads The pad is a common cathode pad electrically connected to each cathode pad, or a common anode pad electrically connected to each anode pad; a common pad connection line electrically connected to the common pad of each row of pixel units, and the common pad connection line of each row is located on a straight line; or the common pad connection line electrically connected to the common pad of each column of pixel units, and the common pad connection line of each column is located on a straight line; electrode connection lines, each of which is located on a straight line, electrically connecting pads of the same seed pixels in a row or a column in the pixel array, and the electrically connected pads are pads of the anode pad and the cathode pad that are not connected to the common pad, and the pads of the anode pad and the cathode pad that are not connected to the common pad are located outside the polygon in each pixel unit.

[0006] The above display panel adopts a special pad and connecting wire design, which simplifies the circuit design. The pads, connecting wires and through holes occupy a smaller area, so the number of pixels per unit area can be increased, thereby improving the resolution of the display screen.

[0007] In one embodiment, the substrate is a glass substrate.

[0008] In one of the embodiments, the common pad of each pixel unit is located at the geometric center of each polygon.

[0009] In one embodiment, the polygon of each pixel unit has the same shape, size and orientation.

[0010] In one embodiment, a=3, and each pixel unit includes sub-pixels of three colors: RGB.

[0011] In one of the embodiments, a first insulating layer is further included on the first main surface, and the common pad connection line is isolated from at least part of the electrode connection line by the first insulating layer.

[0012] In one embodiment, it also includes a second insulating layer located on the first insulating layer, and the electrode connection line electrically connected to at least one sub-pixel is isolated from other electrode connection lines by the second insulating layer, and / or the electrode connection line electrically connected to at least one sub-pixel is isolated from the common pad connection line by the second insulating layer.

[0013] In one embodiment, it also includes electronic materials and material pads located on the second main surface of the substrate, the electronic materials are electrically connected to the material pads, the second main surface is opposite to the first main surface, and the substrate is provided with through holes that electrically connect the pads on the second main surface with the pads on the first main surface.

[0014] A display device comprises the display panel described in any one of the above embodiments.

[0015] A method for manufacturing a display panel, comprising: obtaining a substrate; arranging a pixel array and pads of the pixel array on a first main surface of the substrate; the pixel array comprises m pixel units, each pixel unit comprises a sub-pixels, the pixel array comprises a maximum of a sub-pixels, a is an integer greater than 2, and m is a positive integer greater than 3; in each pixel unit, the sub-pixels are arranged in a polygon, and each sub-pixel is located at a vertex of the polygon; the pads of the pixel array comprise m groups of anode pads, m groups of cathode pads, and m common pads, each group of anode pads comprises a anode pads corresponding to the a sub-pixels one-to-one, each group of cathode pads comprises a cathode pads corresponding to the a sub-pixels one-to-one, and each of the common pads is located inside the polygon in each pixel unit; The common pad is a common cathode pad electrically connected to each cathode pad, or a common anode pad electrically connected to each anode pad; a common pad connection line is formed; the common pad connection line electrically connects the common pad of each row of pixel units, and the common pad connection line of each row is located on a straight line; or the common pad connection line electrically connects the common pad of each column of pixel units, and the common pad connection line of each column is located on a straight line; an electrode connection line is formed; each of the electrode connection lines is located on a straight line, electrically connecting the pads of the same seed pixel in a row or a column in the pixel array, and the electrically connected pads are the pads of the anode pad and the cathode pad that are not connected to the common pad, and the pads of the anode pad and the cathode pad that are not connected to the common pad are located outside the polygon in each pixel unit.

[0016] The manufacturing method of the display panel adopts a special pad and connecting wire design, which simplifies the circuit design. The pad, connecting wire and through hole occupy a smaller area, so the number of pixels per unit area can be increased, thereby improving the resolution of the display screen.

[0017] In one embodiment, after the step of forming the common pad connection line, the step also includes forming a first insulating layer on the first main surface; the common pad connection line and at least part of the electrode connection line are isolated by the first insulating layer; in the step of forming the electrode connection line, at least part of the electrode connection line is formed after forming the first insulating layer.

[0018] In one embodiment, after forming the first insulating layer, the step further includes forming a second insulating layer on the first insulating layer, wherein at least one electrode connection line electrically connected to a sub-pixel is isolated from other electrode connection lines by the second insulating layer, and / or at least one electrode connection line electrically connected to a sub-pixel is isolated from the common pad connection line by the second insulating layer; in the step of forming electrode connection lines, at least one electrode connection line electrically connected to a pixel is formed after forming the second insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural diagram of a part of the structure of a display panel in one embodiment of the present application.

[0020] Figure 2 FIG. 1 is a schematic diagram of a common pad connection line 132 extending along a column direction in an embodiment of the present application.

[0021] Figure 3 Schematic diagram of sub-pixel positions of a pixel unit in an embodiment of the present application.

[0022] Figure 4 yes Figure 1 The structure shown is a schematic diagram of the structure after the LED chip is installed.

[0023] Figure 5 FIG. 1 is a schematic diagram of a pixel design of a display panel using virtual pixels in an embodiment of the present application.

[0024] Figure 6 4 is a flow chart of a method for manufacturing a display panel in one embodiment of the present application.

[0025] Figure 7 is a flow chart of a method for manufacturing a display panel in another embodiment of the present application.

[0026] Figure 8 It is a structural diagram of a part of the structure of the display panel after step S642 is completed in one embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0029] It should be understood that when an element or layer is referred to as "on ...," "adjacent to ...," "connected to" or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...," "directly adjacent to ...," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as the second element, component, region, layer or part.

[0030] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0031] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0032] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0033] Figure 1 1 is a schematic diagram of a partial structure of a display panel in an embodiment of the present application. The display panel includes a substrate 110, a pixel array ( Figure 1 ), anode pad, cathode pad, common pad 121, common pad connection line 132 and electrode connection line 134. In one embodiment of the present application, the display panel is an LED (light emitting diode) display panel. The pixel array is located on the first main surface of the substrate 110 (i.e., the front surface of the substrate), including i rows and j columns, a total of i×j=m pixel units ( Figure 1 In the figure, four squares of the substrate are used to represent four pixel units). Each pixel unit includes a sub-pixels, and the pixel array includes at most a seed pixels, where a is an integer greater than 2 and m is a positive integer greater than 3. In one embodiment of the present application, the a sub-pixels of each pixel unit are also a seed pixels. For example, each pixel unit includes three sub-pixels of RGB (red, green and blue), and the pixel array includes sub-pixels of three colors of RGB. In another embodiment of the present application, each pixel unit includes RGBG4 sub-pixels, but there are only three RGB sub-pixels, and the pixel array also includes sub-pixels of three colors of RGB. Figure 1 In the embodiment shown, a=3, and the pixel unit includes sub-pixels of three colors, RGB. In each pixel unit, the sub-pixels are arranged in a polygon, denoted as polygon β. Each sub-pixel is located at the vertex of polygon β. Figure 1 In the embodiment shown, the polygon β is a triangle, and the three RGB (red, green and blue) sub-pixels in each pixel unit serve as the three vertices of the triangle. In one embodiment of the present application, the polygon β of each pixel unit has the same shape, size and orientation.

[0034] There are a total of m groups of anode pads and cathode pads, that is, each pixel unit is provided with a group of anode pads and cathode pads on the front side of the substrate. Each group of anode pads includes a anode pads corresponding to a sub-pixels, and each group of cathode pads includes a cathode pads corresponding to a sub-pixels. Common pads 121 are also provided on the front side of the substrate in a one-to-one correspondence with the pixel units, and are located inside polygon β in the corresponding pixel unit. For an embodiment in which the pixel array adopts a common cathode connection, common pad 121 is a common cathode pad electrically connected to each cathode pad; for an embodiment in which the pixel array adopts a common anode connection, common pad 121 is a common anode pad electrically connected to each anode pad. Figure 1 In the embodiment shown, the display panel adopts a common cathode connection, and the common pad 121 in each pixel unit is electrically connected to the cathode pad 122a (cathode pad of the red sub-pixel), the cathode pad 122b (cathode pad of the blue sub-pixel) and the cathode pad 122c (cathode pad of the green sub-pixel). The substrate 110 is provided with a through hole at the position of the common pad 121 to electrically connect the common pad 121 to the back of the substrate.

[0035] In one embodiment of the present application, the common pad connection line 132 electrically connects the common pads 121 of each row of pixel units, and the common pad connection lines 132 of each row are located on a straight line. To this end, the common pads 121 of each row of pixel units need to be arranged on a straight line. In order to facilitate the distinction of each structure, Figure 1 Only the common pad connection lines 132 of the first row of pixel units are shown (but the common pad connection lines 132 of other rows are not shown). In another embodiment of the present application, the common pad connection lines 132 are electrically connected to the common pads 121 of each column of pixel units, and the common pad connection lines 132 of each column of pixel units are located on a straight line. Figure 2 . Figure 2 The triangle of each pixel unit in is Figure 2 The polygon β in the illustrated embodiment. The common pads 121 of each column of pixel units are located on a straight line.

[0036] The pads of the anode pad and the cathode pad that are not connected to the common pad 121 are located outside the polygon β in each pixel unit and are electrically connected to the electrode connection line 134. Figure 1In the embodiment shown, the common pad 121 is electrically connected to the cathode pad, so each anode pad (including anode pad 124a, anode pad 124b and anode pad 124c) is located outside the polygon β and is electrically connected through the electrode connection line 134. For the embodiment in which the common pad 121 is electrically connected to the anode pad, the electrode connection line 134 is electrically connected to each cathode pad, and each cathode pad is located outside the polygon β. Each electrode connection line 134 connects the pads of the same seed pixel (whether it is the same type of pixel is divided according to the a seed pixel of the pixel array) in a row or a column in the pixel array, and each electrode connection line 134 is located on a straight line. For this reason, the anode pad or cathode pad of the same seed pixel needs to be set on a straight line. In one embodiment of the present application, in each row of pixel units, the same seed pixel is located on a straight line in the row direction; and / or, in each column of pixel units, the same seed pixel is located on a straight line in the column direction.

[0037] The above-mentioned display panel adopts a special pad and connecting line design to simplify the circuit design. The pads (including anode pads, cathode pads and common pads 121), connecting lines (including common pad connecting lines 132 and electrode connecting lines 134) and through holes occupy a smaller area, so the number of pixels per unit area can be increased, thereby improving the resolution of the display screen.

[0038] In one embodiment of the present application, the substrate 110 may be one layer or more than two layers. In one embodiment of the present application, the substrate 110 is a glass substrate, and the substrate 110 is made of single-layer glass or multi-layer glass. The glass substrate has a lower plate cost and can reduce the use cost. In addition, the glass substrate can carry smaller LED chips.

[0039] In one embodiment of the present application, the display panel further includes electronic materials and material pads located on the second main surface (i.e., the back surface of the substrate) of the substrate 110. The electronic materials may be electronic components such as resistors, capacitors, inductors, or other integrated circuits, and the electronic materials are electrically connected to the material pads. The substrate 110 is provided with through holes that electrically connect the pads on the back surface of the substrate (material pads) to the pads on the front surface of the substrate (anode pads, cathode pads, and common pads 121).

[0040] In one embodiment of the present application, each common pad 121 is located at the geometric center of the polygon β in the corresponding pixel unit, and the geometric center of the polygon β of each row is located on a straight line, or the geometric center of the polygon β of each column is located on a straight line, so as to ensure that the common pad connection line 132 of each row is located on a straight line, or the common pad connection line 132 of each column is located on a straight line. In one embodiment of the present application, the geometric center of the polygon β coincides with the geometric center of each pixel unit, see Figure 3 .exist Figure 3 In the embodiment shown, the common pad 121 ( Figure 3 (not shown) is located at the center of a triangle whose vertices are the three RGB sub-pixels.

[0041] In one embodiment of the present application, the display panel further includes a first insulating layer ( Figure 1 (not shown), the common pad connection line 132 and at least part of the electrode connection line 134 are isolated by a first insulating layer. In one embodiment of the present application, the common pad connection line 132, the first insulating layer and part of the electrode connection line 134 are a three-layer structure stacked in sequence from bottom to top. Figure 1 In the embodiment shown, the electrode connection line 134 connecting the anode pad 124b and the anode pad 124c is disposed on the first insulating layer. Since the electrode connection line 134 connecting the anode pad 124b and the anode pad 124c extends in the column direction, it will intersect with the common pad connection line 132 extending in the row direction, so the first insulating layer is provided to insulate and isolate them.

[0042] In one embodiment of the present application, the first insulating layer may be formed only at the intersection of the common pad connection line 132 and the electrode connection line 134 (connecting the anode pad 124b and the anode pad 124c), that is, an insulating layer with a "cap" structure is formed at the intersection. In other embodiments, a first insulating layer with a large area or covering the entire surface of the substrate 110 may also be formed. In one embodiment of the present application, the electrode connection line 134 provided on the first insulating layer passes through the through hole of the first insulating layer and connects to each anode pad (at Figure 1 In the illustrated embodiment, anode pad 124b and anode pad 124c are electrically connected.

[0043] In one embodiment of the present application, the display panel further includes a second insulating layer ( Figure 1 (not shown), at least one electrode connection line 134 electrically connected to a sub-pixel is isolated from other electrode connection lines 134 by a second insulating layer, or at least one electrode connection line 134 electrically connected to a sub-pixel is isolated from the common pad connection line 132 by a second insulating layer. Figure 1 In the embodiment shown, the common pad connection line 132, the first insulating layer, a portion of the electrode connection line 134, the second insulating layer, and another portion of the electrode connection line 134 are a five-layer structure stacked sequentially from bottom to top. Figure 1In the embodiment shown, the electrode connection line 134 connected to the anode pad 124a is disposed on the second insulating layer and extends in the row direction. Since the electrode connection line 134 connected to the anode pad 124a extends in the row direction, it will cross the electrode connection line 134 connected to the anode pad 124b and the anode pad 124c extending in the column direction, so the second insulating layer is provided to insulate and isolate them.

[0044] In one embodiment of the present application, the second insulating layer may be formed only at the intersection of the electrode connection line 134 (connecting the anode pad 124a) and the electrode connection line 134 (connecting the anode pad 124b and the anode pad 124c), that is, an insulating layer with a "cap" structure is formed at the intersection. In other embodiments, a second insulating layer with a large area or covering the entire surface of the substrate 110 may also be formed. In one embodiment of the present application, the electrode connection line 134 provided on the second insulating layer passes through the through hole of the second insulating layer and the through hole of the first insulating layer, and is connected to each anode pad (at Figure 1 In the illustrated embodiment, the anode pad 124 a is electrically connected.

[0045] In one embodiment of the present application, the display panel is an LED (light emitting diode) display panel. Figure 4 yes Figure 1 The structure shown is a schematic diagram of the structure after the LED chip is installed. The LED chip can be a micro LED chip without a substrate or a miniLED chip. The pixel unit includes a red sub-pixel 120a, a blue sub-pixel 120b and a green sub-pixel 120c, the red sub-pixel 120a is a red light LED chip, the blue sub-pixel 120b is a blue light LED chip, and the green sub-pixel 120c is a green light LED chip. In one embodiment of the present application, the long side dimension of the LED chip is 30 microns to 200 microns. When the spacing between the LED chips is appropriate, adjacent red, green, and blue LED chips can also be used to form virtual pixels. Figure 5 This is a pixel design of a display panel using virtual pixels. Each circle in the figure is a real pixel or a virtual pixel.

[0046] The present application accordingly proposes a display device, including the display panel described in any of the above embodiments. The display device can be an LED display screen, or a display screen of a terminal device such as a personal computer, a mobile phone, a portable game console, or a display screen of a head-mounted display device (such as VR, AR, MR, etc.).

[0047] The present application accordingly proposes a method for manufacturing a display panel, which can be used to manufacture the display panel described in any of the aforementioned embodiments. Figure 6 : is a flow chart of a method for manufacturing a display panel in an embodiment of the present application, comprising the following steps:

[0048] S610, obtaining a substrate.

[0049] In one embodiment of the present application, the substrate 110 may be one layer or more than two layers. In one embodiment of the present application, the substrate 110 is a glass substrate. The glass substrate has a lower plate cost and can reduce the use cost. In addition, the glass substrate can carry smaller LED chips.

[0050] S620, a pixel array and pads of the pixel array are provided on the first main surface of the substrate.

[0051] The first main surface is the front side of the substrate. The pixel array includes i rows and j columns, a total of i×j=m pixel units. Each pixel unit includes a sub-pixels, and the pixel array includes a maximum of a seed pixels, where a is an integer greater than 2 and m is a positive integer greater than 3. In one embodiment of the present application, a=3, and the pixel unit includes sub-pixels of three colors, RGB. In each pixel unit, the sub-pixels are arranged in a polygon, denoted as polygon β. Each sub-pixel is located at a vertex of polygon β. In one embodiment of the present application, polygon β is a triangle, and the three sub-pixels of RGB (red, green and blue) in each pixel unit serve as the three vertices of the triangle. In one embodiment of the present application, the polygon β of each pixel unit has the same shape, size and orientation.

[0052] The pads of the pixel array include m groups of anode pads, m groups of cathode pads and m common pads. There are a total of m groups of anode pads and cathode pads, that is, one group is arranged corresponding to each pixel unit on the front side of the substrate. Each group of anode pads includes a anode pads corresponding to a sub-pixels one-to-one, and each group of cathode pads includes a cathode pads corresponding to a sub-pixels one-to-one. Common pads 121 are also arranged on the front side of the substrate in a one-to-one correspondence with the pixel units, and are located inside the polygon β in each pixel unit. For the embodiment in which the pixel array adopts a common cathode connection, common pad 121 is a common cathode pad electrically connected to the cathode pads; for the embodiment in which the pixel array adopts a common anode connection, common pad 121 is a common anode pad electrically connected to the anode pads. Figure 4 In the embodiment shown, the display panel adopts a common cathode connection, and the common pad 121 in each pixel unit is electrically connected to the cathode pad 122a (the cathode pad of the red sub-pixel), the cathode pad 122b (the cathode pad of the blue sub-pixel) and the cathode pad 122c (the cathode pad of the green sub-pixel).

[0053] In one embodiment of the present application, before the common pad 121 is formed, a through hole is first opened at a position of the substrate 110 where the common pad 121 is required to be disposed, and then the common pad 121 is deposited around the through hole.

[0054] S630, forming a common pad connection line.

[0055] In one embodiment of the present application, the common pad connection line 132 electrically connects the common pads 121 of each row of pixel units, and the common pad connection lines 132 of each row are located on a straight line. To this end, the common pads 121 of each row need to be arranged on a straight line. In order to facilitate the distinction of each structure, Figure 4 Only the common pad connection line 132 of the first row of pixel units is shown. In another embodiment of the present application, the common pad connection line 132 electrically connects the common pads 121 of each column of pixel units, and the common pad connection line 132 of each column is located on a straight line. Figure 2 . Figure 2 The triangle of each pixel unit in is Figure 2 The polygon β in the illustrated embodiment. The common pads 121 of each column are located on a straight line.

[0056] S640, forming electrode connection lines.

[0057] The pads of the anode pad and the cathode pad that are not connected to the common pad 121 are located outside the polygon β in each pixel unit and are electrically connected to the electrode connection line 134. Figure 4 In the embodiment shown, the common pad 121 is electrically connected to the cathode pad, so each anode pad (including anode pad 124a, anode pad 124b and anode pad 124c) is electrically connected through the electrode connection line 134. For the embodiment in which the common pad 121 is electrically connected to the anode pad, the electrode connection line 134 is electrically connected to each cathode pad. Each electrode connection line 134 connects the pads of the same seed pixel (the same seed pixel in the a seed pixel of the pixel array) in a row or a column in the pixel array, and each electrode connection line 134 is located on a straight line. To this end, the anode pad or cathode pad of the same seed pixel needs to be arranged on a straight line.

[0058] The manufacturing method of the display panel adopts a special pad and connecting wire design, which simplifies the circuit design. The pad, connecting wire and through hole occupy a smaller area, so the number of pixels per unit area can be increased, thereby improving the resolution of the display screen.

[0059] Figure 7 is a flow chart of a method for manufacturing a display panel in another embodiment of the present application, wherein steps S610 to S630 can be Figure 6 The embodiment shown is the same. After step S630, the method further includes:

[0060] S634, forming a first insulating layer on the front surface of the substrate.

[0061] The first insulation is used to insulate and isolate the common pad connection line 132 from at least a portion of the electrode connection line 134 .

[0062] S642, forming a portion of the electrode connection line.

[0063] Reference Figure 8 In one embodiment of the present application, step S642 includes forming an electrode connection line 134 connecting the anode pad 124b and the anode pad 124c. Since the electrode connection line 134 connecting the anode pad 124b and the anode pad 124c extends in the column direction, it will intersect with the common pad connection line 132 extending in the row direction, so a first insulating layer is provided to insulate and isolate them. In one embodiment of the present application, before performing step S642, a step of opening a through hole in the first insulating layer is also included. The electrode connection line 134 formed in step S642 passes through the through hole of the first insulating layer and connects to each anode pad (in Figure 8 In the illustrated embodiment, anode pad 124b and anode pad 124c are electrically connected.

[0064] S644, forming a second insulating layer on the first insulating layer.

[0065] The second insulating layer is used to insulate and isolate a portion of the electrode connection lines 134 from another portion of the electrode connection lines 134 , or to insulate and isolate a portion of the electrode connection lines 134 from the common pad connection lines 132 .

[0066] S646, forming another part of the electrode connection line.

[0067] In one embodiment of the present application, step S646 includes forming an electrode connection line 134 connected to the anode pad 124a. Since the electrode connection line 134 connected to the anode pad 124a extends in the row direction, it will intersect with the electrode connection line 134 connecting the anode pad 124b and the anode pad 124c extending in the column direction, so a second insulating layer is provided to insulate and isolate them. In one embodiment of the present application, before performing step S646, it also includes the step of opening a through hole in the second insulating layer. The electrode connection line 134 formed in step S646 passes through the through hole of the second insulating layer and the through hole of the first insulating layer, and connects to each anode pad (in Figure 1 In the illustrated embodiment, the anode pad 124 a is electrically connected.

[0068] S650, forming electronic materials and material pads on the back side of the substrate.

[0069] The electronic material may be an electronic component such as a resistor, a capacitor, an inductor or other integrated circuits, and the electronic material is electrically connected to the material pad.

[0070] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0071] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0072] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: include: substrate; A pixel array, located on the first main surface of the substrate, including m pixel units, each pixel unit including a sub-pixels, the pixel array including at most a sub-pixels, a being an integer greater than 2, and m being a positive integer greater than 3; in each pixel unit, the sub-pixels are arranged in a polygon, and each sub-pixel is located at a vertex of the polygon; m groups of anode pads and m groups of cathode pads, located on the first main surface of the substrate, each group of anode pads includes a anode pads corresponding to the a sub-pixels one-to-one, and each group of cathode pads includes a cathode pads corresponding to the a sub-pixels one-to-one; m common pads, located on the first main surface and inside the polygon in each pixel unit; the common pad is a common cathode pad electrically connected to each cathode pad, or a common anode pad electrically connected to each anode pad; A common pad connection line electrically connects the common pads of each row of pixel units, and the common pad connection lines of each row are located on a straight line; or the common pad connection line electrically connects the common pads of each column of pixel units, and the common pad connection lines of each column are located on a straight line; Electrode connection lines, each of which is located on a straight line, electrically connecting pads of the same seed pixels in a row or a column in the pixel array, and the electrically connected pads are pads of the anode pad and the cathode pad that are not connected to the common pad, and the pads of the anode pad and the cathode pad that are not connected to the common pad are located outside the polygon in each pixel unit.

2. The display panel according to claim 1, characterized in that: The substrate is a glass substrate.

3. The display panel according to claim 1, characterized in that: The common pad of each pixel unit is located at the geometric center of each polygon; and / or The shape, size and orientation of the polygon of each pixel unit are the same; and / or a=3, each pixel unit includes sub-pixels of three colors: RGB.

4. The display panel according to claim 1, characterized in that: It also includes a first insulating layer located on the first main surface, and the common pad connection line is isolated from at least part of the electrode connection line by the first insulating layer.

5. The display panel according to claim 4, characterized in that: It also includes a second insulating layer located on the first insulating layer, and the electrode connection line electrically connected to at least one sub-pixel is isolated from other electrode connection lines or the common pad connection line by the second insulating layer.

6. The display panel according to any one of claims 1 to 5, characterized in that: It also includes electronic materials and material pads located on the second main surface of the substrate, the electronic materials are electrically connected to the material pads, the second main surface is opposite to the first main surface, and the substrate is provided with through holes that electrically connect the pads on the second main surface with the pads on the first main surface.

7. A display device, characterized in that: The invention comprises a display panel as claimed in any one of claims 1 to 6.

8. A method for manufacturing a display panel, comprising: Obtaining a substrate; A pixel array and pads of the pixel array are arranged on the first main surface of the substrate; the pixel array includes m pixel units, each pixel unit includes a sub-pixels, the pixel array includes at most a sub-pixels, a is an integer greater than 2, and m is a positive integer greater than 3; in each pixel unit, the sub-pixels are arranged in a polygon, and each sub-pixel is located at the vertex of the polygon; the pads of the pixel array include m groups of anode pads, m groups of cathode pads, and m common pads, each group of anode pads includes a anode pads corresponding to the a sub-pixels one-to-one, each group of cathode pads includes a cathode pads corresponding to the a sub-pixels one-to-one, and each of the common pads is located inside the polygon in each pixel unit; the common pad is a common cathode pad electrically connected to each cathode pad, or a common anode pad electrically connected to each anode pad; Forming a common pad connection line; the common pad connection line electrically connects the common pads of each row of pixel units, and the common pad connection lines of each row are located on a straight line; or the common pad connection line electrically connects the common pads of each column of pixel units, and the common pad connection lines of each column are located on a straight line; Electrode connection lines are formed; each of the electrode connection lines is located on a straight line, electrically connecting pads of the same seed pixels in a row or a column in the pixel array, and the electrically connected pads are pads of the anode pad and the cathode pad that are not connected to the common pad, and the pads of the anode pad and the cathode pad that are not connected to the common pad are located outside the polygon in each pixel unit.

9. The method for manufacturing a display panel according to claim 8, characterized in that: After the step of forming the common pad connection line, the step of forming a first insulating layer on the first main surface is also included; the common pad connection line is isolated from at least part of the electrode connection line by the first insulating layer; In the step of forming the electrode connection lines, at least a portion of the electrode connection lines are formed after forming the first insulating layer.

10. The method for manufacturing a display panel according to claim 9, wherein: After forming the first insulating layer, the method further includes forming a second insulating layer on the first insulating layer, wherein the electrode connection line electrically connected to at least one sub-pixel is isolated from other electrode connection lines or common pad connection lines by the second insulating layer; In the step of forming the electrode connection line, the electrode connection line electrically connected to the at least one pixel is formed after forming the second insulating layer.

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