Display panel and display device

Abstract

The application discloses a display panel and a display device; the pixel circuit of the display panel comprises a driving transistor and a storage capacitor connected with each other, the light shielding layer in the display panel comprises a driving light shielding part corresponding to the driving transistor, the first active layer comprises an active part of the driving transistor, the first gate layer comprises a gate of the driving transistor and one plate of the storage capacitor, the second active layer comprises the other plate of the storage capacitor, the driving light shielding parts in two adjacent sub-pixels in a first direction are connected, and the driving light shielding parts in two adjacent sub-pixels in a second direction are electrically connected through an electric connection line; the application electrically connects the two adjacent driving light shielding parts in the second direction through the electric connection line extending along the second direction, that is, the driving light shielding parts in different sub-pixels are electrically connected with each other in the first direction and the second direction, the impedance of the driving light shielding part is reduced, the potential difference of different regions of the light shielding layer is improved, and the display effect of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] OLED (Organic Light-Emitting Diode) display technology is a new type of display technology, which gradually attracts people's attention with its unique advantages of low power consumption, high saturation, fast response time and wide viewing angle, and occupies a certain position in the field of panel display technology.

[0003] In the current LTPO (Low Temperature Polysilicon Oxide) display device, the bottom gate of part of the transistor is prepared by using a light shielding layer. However, due to the large impedance of the light shielding layer, there is a potential difference between the middle region and the edge region of the light shielding layer when transmitting the corresponding control signal, that is, the display panel has different control signals with different potentials in different regions, which causes the display panel to display abnormally. SUMMARY

[0004] The present application provides a display panel and a display device to improve the technical problem of abnormal display of the existing display panel.

[0005] To solve the above-mentioned scheme, the technical scheme provided by the present application is as follows:

[0006] In a first aspect, the present application provides a display panel, which includes a plurality of sub-pixels arranged in a first direction and a second direction, at least one of the sub-pixels including a pixel circuit, the pixel circuit including a driving transistor and a storage capacitor connected in series; wherein the display panel includes:

[0007] a light shielding layer including a driving light shielding part corresponding to the driving transistor, the driving light shielding parts in two adjacent sub-pixels in the first direction being connected in series;

[0008] a first active layer including an active part of the driving transistor;

[0009] a first gate layer including a gate of the driving transistor and one plate of the storage capacitor;

[0010] a second active layer including the other plate of the storage capacitor;

[0011] wherein the display panel further includes an electrically connecting line extending along the second direction, the driving light shielding parts in two adjacent sub-pixels in the second direction being electrically connected through the electrically connecting line.

[0012] In a second aspect, the present application also provides a display device comprising the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0013] The technical scheme and other beneficial effects of the present application will be apparent from the following detailed description of specific embodiments of the present application, taken in conjunction with the accompanying drawings.

[0014] Figure 1 Structure diagram of the display panel of the present application;

[0015] Figure 2 Equivalent circuit diagram of the pixel circuit in the display panel of the present application;

[0016] Figure 3 Schematic diagram of the film layers in the display panel of the present application;

[0017] Figure 4 Film layer stack diagram of one sub-pixel in the display panel of the present application;

[0018] Figure 5 Structure diagram of the first gate layer in the present application;

[0019] Figure 6 Structure diagram of the first active layer in the present application; Figure 4

[0020] Structure diagram of the first gate layer and the first active layer in the present application; Figure 7 Figure 4 Structure diagram of the light shielding layer in the present application;

[0021] Figure 8 Figure 4 Structure diagram of the first gate layer and the light shielding layer in the present application;

[0022] Figure 9 Structure diagram of the second active layer in the present application; Figure 4

[0023] Structure diagram of the second gate layer in the present application; Figure 10 Figure 4 Structure diagram of the light shielding layer, the first gate layer, the first active layer, the second active layer and the second gate layer in the present application;

[0024] Figure 11 Figure 4 Structure diagram of the first source-drain layer in the present application;

[0025] Figure 12 Structure diagram of the first source-drain layer, the first gate layer, the first active layer, the second active layer and the second gate layer in the present application; Figure 4

[0026] Structure diagram of the first source-drain layer in the present application; Figure 13 Figure 4 Structure diagram of the first source-drain layer, the first gate layer, the first active layer, the second active layer and the second gate layer in the present application;

[0027] Figure 14 Figure 4 Structure diagram of the first source-drain layer, the first gate layer, the first active layer, the second active layer and the second gate layer in the present application;​​​​​​Figure 4 A structure diagram of the second source-drain layer;

[0028] Figure 15 A structure diagram of the second source-drain layer; Figure 4 A structure diagram of the second source-drain layer;

[0029] Figure 16 A structure diagram of the second source-drain layer; Figure 1 A structure diagram of the second source-drain layer;

[0030] Figure 17 A structure diagram of the second source-drain layer; Figure 4 A structure diagram of the second source-drain layer. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the orientation words such as “upper” and “lower” generally refer to the upper and lower in the actual use or working state of the device, and specifically refer to the direction of the drawing surface in the drawings; and “inner” and “outer” refer to the contour of the device.

[0032] Referring to Figures 1 to 17 The display panel 100 can include a display portion 200 and a gate circuit 300 located on one side of the display portion 200, and the gate circuit 300 is configured to input a control signal to the display portion 200.

[0033] In the present embodiment, referring to Figure 1 The display portion 200 includes a plurality of sub-pixels PX arranged along a first direction and a second direction, each of the sub-pixels PX is provided with a light emitting device EL and a pixel circuit PC connected to the light emitting device EL, and the gate circuit 300 is configured to input a gate control signal to a transistor in the pixel circuit PC.

[0034] In the present embodiment, the pixel circuit PC includes a driving transistor T1 and a storage capacitor Cst connected to each other, and the display panel 100 includes a light shielding layer 121, a first active layer 123, a first gate layer 125, and a second active layer 127.

[0035] In this embodiment, the light shielding layer 121 includes a driving light shielding portion T1L corresponding to the driving transistor T1, and the driving light shielding portions T1L in two adjacent sub-pixels PX in the first direction X are connected.

[0036] In this embodiment, the display panel 100 further includes an electric connection line 50 extending along the second direction Y, and the driving light shielding portions T1L in two adjacent sub-pixels PX in the second direction Y are electrically connected through the electric connection line 50.

[0037] In this embodiment, the display panel 100 further includes an electric connection line 50 extending along the second direction Y, and the driving light shielding portions T1L in two adjacent sub-pixels PX in the second direction Y are electrically connected through the electric connection line 50.

[0038] The technical solutions of the present application will be described in detail with reference to specific embodiments.

[0039] Please refer to Figure 1 , the display panel 100 includes a display area AA and a non-display area NA arranged adjacent to the display area AA, and the display area AA is provided with a display portion 200. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is an area in the display panel 100 for displaying, and is internally provided with a plurality of sub-pixels PX for displaying. The non-display area NA can be a frame area of the display panel 100, and can be internally provided with functional components for assisting the sub-pixels PX in the display area AA to display.

[0040] Please refer to Figure 1 , the lower side of the display area AA is provided with a binding terminal 400, which can be connected with an external circuit. The binding terminal 400 transmits signals input by the external circuit to the data wire, so as to drive the display panel 100 to display a picture. For example, the binding terminal 400 can be connected with a chip or a chip on film, etc., for providing power supply and driving signals for the display panel 100.

[0041] In this embodiment, the gate circuit 300 is arranged in the non-display area NA, and the gate circuit 300 can be arranged on both sides of the display area AA. The gate circuit 300 can include a plurality of gate driving units connected in cascade, and the structure of the gate driving unit is not limited herein.

[0042] In this embodiment, a plurality of light emitting devices EL and pixel circuits PC for driving the light emitting devices EL can be arranged in an array in the display region AA. The pixel circuit PC can be a 7T1C, 7T2C, 8T1C, 8T2C, 8T3C, 8T4C, or the like. In the following embodiments, an 8T2C pixel circuit PC will be described as an example.

[0043] Referring to Figure 2 , the pixel circuit PC can include a switching transistor T2, a driving transistor T1, a compensation transistor T3, a first reset transistor T4, a second reset transistor T7, a first light emitting transistor T5, a second light emitting transistor T6, a storage capacitor Cst, and a boost capacitor Cboost. The storage capacitor Cst includes a first plate Cst1 and a second plate Cst1.

[0044] Referring to Figure 2The drain of the switch transistor T2 is connected to the data line Data, the source of the switch transistor T2 is connected to the first node A, and the switch gate T2G of the switch transistor T2 is connected to the switch control line Pscan1; the drain of the drive transistor T1 is connected to the first node A, the source of the drive transistor T1 is connected to the second node B, and the drive gate T1G of the drive transistor T1 is connected to the third node Q; the drain of the compensation transistor T3 is connected to the third node Q, the source of the compensation transistor T3 is connected to the second node B, and the compensation gate T3G of the compensation transistor T3 is connected to the compensation control line Nscan1; the drain of the first reset transistor T4 is connected to the first reset signal line Vi1, the source of the first reset transistor T4 is connected to the third node Q, and the gate T4G of the first reset transistor T4 is connected to the first reset control line Nscan2; the drain of the second reset transistor T7 is connected to the second reset signal line Vi2, the source of the second reset transistor T7 is connected to the anode of the light emitting device EL, and the gate T7G of the second reset transistor T7 is connected to the second reset control line Pscan2; the drain of the first light emitting transistor T5 is connected to the high potential line VDD, the source of the first light emitting transistor T5 is connected to the first node A, and the first light emitting gate T5G of the first light emitting transistor T5 is connected to the light emitting control line EM; the drain of the second light emitting transistor T6 is connected to the second node B, the source of the second light emitting transistor T6 is connected to the anode of the light emitting device EL, and the second light emitting gate T6G of the second light emitting transistor T6 is connected to the light emitting control line EM; the drain of the third reset transistor T8 is connected to the third reset signal line Vi3, the source of the third reset transistor T8 is connected to the first node A, and the third reset gate T8G of the third reset transistor T8 is connected to the second reset control line Pscan2; the first plate Cst1 of the storage capacitor Cst is connected to the third node Q, and the second plate Cst1 of the storage capacitor Cst is connected to the high potential line VDD; one plate of the boost capacitor Cboost is connected to the switch control line Pscan1, and the other plate of the boost capacitor Cboost is connected to the third node Q; and the cathode of the light emitting device EL is connected to the low potential line VSS.

[0045] It should be noted that the data signal lines connected to the switch transistors T2 in different sub-pixels PX are different, and only one of them is taken as an example for description.

[0046] It should be noted that the light emitting device EL in the present application can be an organic light emitting diode, a Mini LED, a Micro LED, a regular size LED, or other light emitting source.

[0047] In the present embodiment, the high potential line VDD is used to provide a constant voltage high level to the pixel circuit PC, and the low potential line VSS is used to provide a constant voltage low level to the pixel circuit PC.

[0048] In the embodiment, the switch transistor T2, the drive transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5, the second light-emitting transistor T6, the compensation transistor T3 and the first reset transistor T4 can be one of a P-type transistor or an N-type transistor; the application is described by taking the switch transistor T2, the drive transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5, the second light-emitting transistor T6 as P-type transistors, and the compensation transistor T3 and the first reset transistor T4 as N-type transistors as an example.

[0049] In the embodiment, the source is only the output end of the application, and the drain is only the input end of the application, which only has a difference in naming.

[0050] In the following embodiment, the first direction is perpendicular to the extension direction of the data line, and the included angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90°, for example, the first direction X is transverse, and the second direction Y is longitudinal.

[0051] The film layer structure of the pixel circuit PC of the application is described below in the structure of Figure 2 .

[0052] Please refer to Figure 3 , the display area AA and the non-display area NA of the display panel 100 can be provided with a substrate 110 and an array driving layer 120 arranged on the substrate 110; in the display area AA, the display panel 100 can also be provided with a pixel definition layer PDL arranged on the array driving layer 120, a light-emitting device layer arranged in the same layer as the pixel definition layer PDL, and a packaging layer TFE arranged on the pixel definition layer PDL. The film layer structure in the display area AA is mainly described below.

[0053] In the embodiment, the substrate 110 supports each layer arranged on the substrate 110. When the display panel 100 is a bottom emission light-emitting display device or a double-sided emission light-emitting display device, a transparent substrate is used. When the display panel 100 is a top emission light-emitting display device, a semi-transparent or opaque substrate and a transparent substrate can be used.

[0054] In the embodiment, the substrate 110 is used to support each film layer arranged on the substrate 110, and the substrate 110 can be made of an insulating material such as glass, quartz or polymer resin. The substrate 110 can be a rigid substrate or a flexible substrate that can be bent, folded, curled, etc. Examples of flexible materials for flexible substrates include polyimide (PI), but are not limited to polyimide (PI).

[0055] In the present embodiment, the substrate 110 can include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 which are stacked, the first flexible substrate 111 and the second flexible substrate 113 can be formed of the same material such as polyimide, and the first barrier layer 112 and the second barrier layer 114 can be formed of an inorganic material including at least one of SiOx and SiNx, for example.

[0056] Referring to Figure 3 , the array driving layer 120 can include a plurality of thin film transistors, the thin film transistors can be etch barrier type, back channel etch type, or divided into bottom gate thin film transistors, top gate thin film transistors, etc. according to the position of the gate and the active layer, or divided into N-type thin film transistors, P-type thin film transistors according to the performance of the thin film transistors; wherein, Figure 3 The thin film transistors in Figure 2 are not representative of the structure diagram of any transistor in

[0057] Referring to Figure 3 , the array driving layer 120 can include a barrier insulating layer BF disposed on the substrate 110, a light shielding layer 121 embedded in the barrier insulating layer BF, a buffer layer 122 disposed on the barrier insulating layer BF, a first active layer 123 disposed on the buffer layer 122, a first insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first insulating layer 124, a second insulating layer 126 disposed on the first gate layer 125, a second active layer 127 disposed on the second insulating layer 126, a third insulating layer 128 disposed on the second active layer 127, a second gate layer 129 disposed on the third insulating layer 128, a fourth insulating layer 130 disposed on the second gate layer 129, a first source-drain layer 131 disposed on the fourth insulating layer 130, a first planar layer 132 disposed on the first source-drain layer 131, a second source-drain layer 133 disposed on the first planar layer 132, and a second planar layer 134 disposed on the second source-drain layer 133, a light emitting device layer and a pixel definition layer PDL disposed on the second planar layer 134, and a packaging layer TFE disposed on the pixel definition layer PDL.

[0058] Referring to Figure 3 , the light shielding layer 121 is disposed on the second barrier layer 114, the light shielding layer 121 is used to shield external light from entering the thin film transistor from the bottom, the material of the light shielding layer 121 can be composed of black light shielding material, such as black light shielding metal or black organic material, etc.

[0059] Referring to Figure 3The buffer layer 122 is arranged on the light shielding layer 121, and is used to isolate the light shielding layer 121 and the upper metal material. The material of the buffer layer 122 can include a compound composed of nitrogen element, silicon element and oxygen element, for example, a single-layer silicon oxide film layer or a silicon oxide-silicon nitride stacked structure.

[0060] In the embodiment, the light shielding layer 121 can also be embedded in the buffer layer 122.

[0061] Referring to Figure 3 The first active layer 123 is arranged on the buffer layer 122, and the second active layer 127 is arranged on the second insulating layer 126. In the application, the material of the first active layer 123 can be silicon semiconductor, for example, low-temperature polysilicon, and the material of the second active layer 127 can be oxide semiconductor, for example, metal oxide. The pixel circuit PC has N-type transistor and P-type transistor, so the display area AA in the application is provided with metal oxide semiconductor and low-temperature polysilicon semiconductor.

[0062] Referring to Figure 3 The first insulating layer 124, the second insulating layer 126, the third insulating layer 128 and the fourth insulating layer 130 are respectively arranged on the corresponding metal layer or semiconductor layer, and are separated by different layers of metal layer or semiconductor layer. The material of the first insulating layer 124, the second insulating layer 126, the third insulating layer 128 and the fourth insulating layer 130 can be inorganic material composed of at least two elements of silicon, nitrogen and oxygen or organic material with flatness.

[0063] Referring to Figure 3 The first gate layer 125 and the second gate layer 129 are respectively arranged on the corresponding insulating layer. The material of the first gate layer 125 and the second gate layer 129 can be copper, molybdenum or molybdenum-titanium alloy.

[0064] Referring to Figure 3 The first source-drain layer 131 is arranged on the fourth insulating layer 130, and the second source-drain layer 133 is arranged on the first flat layer 132. The material of the first source-drain layer 131 and the second source-drain layer 133 can be copper or molybdenum-titanium alloy, copper or titanium.

[0065] Referring to Figure 3 The first flat layer 132 and the second flat layer 134 are integrally laid to ensure the flatness of the film layer of the array driving layer 120. The material of the first flat layer 132 and the second flat layer 134 can be inorganic material composed of silicon, nitrogen and oxygen or organic material with flatness.

[0066] Referring to Figure 3 The light emitting device layer can include a plurality of light emitting devices EL. The light emitting device EL has an anode AN connected to the pixel circuit, a light emitting unit and a cathode CA.

[0067] According to Figure 1 The structure can be known that two plates of the storage capacitor Cst in the display area AA of the application are respectively composed of the material of the first gate layer 125 and the material of the second active layer 127, for example, the first plate Cst1 is located in the first gate layer 125, and the second plate Cst2 is located in the second active layer 127, the metal layer and the insulating layer between the original second active layer 127 and the first gate layer 125 are removed, the number of film layers of the display panel 100 is reduced, the preparation process of the display panel 100 is simplified, and the cost of the display panel 100 is reduced.

[0068] Please refer to Figure 17 and Figure 4 , a plurality of the sub-pixels PX include a plurality of repeating units RU arranged along a first direction X and a second direction Y, each of the repeating units RU has two sub-pixels PX, and the patterns of part of the film layers in the two pixel circuits PC in one of the repeating units RU are symmetrically arranged about the middle line of the repeating unit RU, which can be parallel to the second direction Y; for example, the patterns of the first active layer 123, the first gate layer 125, the second active layer 127, the second gate layer 129, and the first source-drain layer 131 in the repeating unit RU are symmetrically arranged about the middle line, and part of the patterns of the light shielding layer 121 and the second source-drain layer 133 in different pixel circuits PC have small differences.

[0069] It should be noted that due to the limitations of process and equipment, there are slight differences in the film layer patterns in different pixel circuits PC in the actual product of the application, so the symmetric arrangement of the application is only a symmetric arrangement within the error range; at the same time, in order to set the connection points with the upper structure, the patterns of the regions where the connection points are located are widened, which leads to the non-symmetric arrangement of the patterns also within the error range.

[0070] It should be noted that the structures of the pixel circuits PC and the film layer structures described above are applicable to all the sub-pixels PX of the application.

[0071] In the following examples, the structures of each film layer in two pixel circuits PC in one repeating unit RU are taken as examples to describe the technical solutions of the application, for example, the repeating unit RU includes a first pixel circuit PC1 and a second pixel circuit PC2.

[0072] Please refer to Figure 5 and Figure 4 , Figure 5 is a film layer stacking diagram of one repeating unit RU in the display panel 100 of the application, Figure 4 is Figure 5The structure diagram of the first gate layer 125 is shown in FIG. 1 , and the patterns in the first gate layer 125 within a repeating unit RU can be symmetrically arranged.

[0073] See also Figure 5 The first gate layer 125 includes a first reset signal line Vi1, a switch control line Pscan1, a light emitting control line EM, and a second reset control line Pscan2 extending along the first direction X. The first reset signal line Vi1, the switch control line Pscan1, the light emitting control line EM, and the second reset control line Pscan2 are arranged in sequence along the second direction Y, and the first reset signal line Vi1, the switch control line Pscan1, the light emitting control line EM, and the second reset control line Pscan2 in a repeating unit RU are connected to each other.

[0074] See also Figure 4 The first gate layer 125 also includes a first plate Cst1 of a storage capacitor Cst arranged between the switch control line Pscan1 and the light-emitting control line EM. The first plate Cst1 and the switch control line Pscan1 and the light-emitting control line EM are spaced apart, and the distance between the first plate Cst1 and the switch control line Pscan1 is greater than the distance between the first plate Cst1 and the light-emitting control line EM; at the same time, the two first plates Cst1 in a repeating unit RU are spaced apart.

[0075] See also Figure 6 and Figure 6 , Figure 4 for Figure 6 1 , the patterns in the first active layer 123 within a repeating unit RU are symmetrically arranged.

[0076] See also Figure 6 The first active layer 123 includes a switch active portion T2A of the switch transistor T2, a first light emitting active portion T5A of the first light emitting transistor T5, a driving active portion T1A of the driving transistor T1, a second light emitting active portion T6A of the second light emitting transistor T6, a second reset active portion T7A of the second reset transistor T7, a third reset active portion T8A of the third reset transistor T8, a first extension segment ET1 and a second extension segment ET2.

[0077] See also Figure 6The switch active part T2A, the first light-emitting active part T5A and the driving active part T1A are connected to the first connection point N1, the driving active part T1A and the second light-emitting active part T6A are connected to the second connection point N2, the first extension ET1, the second light-emitting active part T6A and the second reset active part T7A are connected to the third connection point N3, the first extension ET1 extends from the third connection point N3 to the side close to the first light-emitting active part T5A, the third reset active part T8A is arranged apart from the above active parts and is located between the first extension ET1 and the first light-emitting active part T5A, the second extension ET2 is connected to the first connection point N1 and is located between the driving active part T1A and the first light-emitting active part T5A, and the two first light-emitting active parts T5A in one repeating unit RU are connected at the end away from the first node.

[0078] Please refer to Figure 7 The switch active part T2A, the first light-emitting active part T5A, the second light-emitting active part T6A, the second reset active part T7A and the third reset active part T8A extend along the second direction Y and are in a strip shape, the first extension ET1 extends along the first direction X and is in a strip shape, and the driving active part T1A can be in a U shape.

[0079] Please refer to Figure 7 , Figure 4 is Figure 7 the stack diagram of the first gate layer 125 and the first active layer 123 in

[0080] Please refer to Figure 7 The light-emitting control line EM has an overlapping part with the first light-emitting active part T5A, the light-emitting control line EM in the overlapping part is multiplexed as the first light-emitting gate T5G, the first light-emitting active part T5A in the overlapping part is the channel of the first light-emitting transistor T5, one end of the first light-emitting active part T5A away from the first connection point N1 is multiplexed as the drain T5D of the first light-emitting transistor T5, and one end of the first light-emitting active part T5A close to the first connection point N1 is multiplexed as the source T5S of the first light-emitting transistor T5, that is, the structure of the region where the first connection point N1 is located is the first node A in the pixel circuit PC.

[0081] Please refer to Figure 7The light-emitting control line EM has an overlapping portion with the second light-emitting active part T6A, the light-emitting control line EM of the overlapping portion is multiplexed as the second light-emitting gate T6G, the second light-emitting active part T6A of the overlapping portion is the channel of the second light-emitting transistor T6, one end of the second light-emitting active part T6A away from the second connection point N2 is multiplexed as the source T6S of the second light-emitting transistor T6, and one end of the second light-emitting active part T6A close to the second connection point N2 is multiplexed as the drain T6D of the second light-emitting transistor T6, that is, the structure of the region where the second connection point N2 is located is the second node B in the pixel circuit PC, and the structure of the region where the third connection point N3 is located is the position connected with the anode AN in the pixel circuit PC.

[0082] Please refer to Figure 7 The second reset control line Pscan2 has an overlapping portion with the second reset active part T7A, the second reset control line Pscan2 of the overlapping portion is multiplexed as the second reset gate T7G, the second reset active part T7A of the overlapping portion is the channel of the second reset transistor T7, one end of the second reset active part T7A close to the third connection point N3 is multiplexed as the source T7S of the second reset transistor T7, and one end of the second reset active part T7A away from the third connection point N3 is multiplexed as the drain T7D of the second reset transistor T7.

[0083] Please refer to Figure 7 The second reset control line Pscan2 has an overlapping portion with the third reset active part T8A, the second reset control line Pscan2 of the overlapping portion is multiplexed as the third reset gate T8G, the third reset active part T8A of the overlapping portion is the channel of the third reset transistor T8, one end of the third reset active part T8A close to the light-emitting control line EM is multiplexed as the source T8S of the third reset transistor T8, and one end of the third reset active part T8A away from the light-emitting control line EM is multiplexed as the drain T8D of the third reset transistor T8.

[0084] Please refer to Figure 4 The switch control line Pscan1 has an overlapping portion with the switch active part T2A, the switch control line Pscan1 of the overlapping portion is multiplexed as the switch gate T2G, the switch active part T2A of the overlapping portion is the channel of the switch transistor T2, one end of the switch active part T2A close to the first connection point N1 is multiplexed as the source T2S of the switch transistor T2, and one end of the switch active part T2A away from the first connection point N1 is multiplexed as the drain T2D of the switch transistor T2.

[0085] Please refer to Figure 8 and Figure 8 , Figure 4 is Figure 8The structure of the light shielding layer 121 in the repeating unit RU can be symmetrically arranged or asymmetrically arranged. Figure 8 The patterns in the light shielding layer 121 are arranged asymmetrically.

[0086] See also Figure 8 The light-shielding layer 121 includes a reset light-shielding portion T4L, a compensation light-shielding portion T3L, and a drive light-shielding portion T1L, which are spaced apart along the second direction Y. The reset light-shielding portion T4L and the compensation light-shielding portion T3L both extend along the first direction X. In the first direction X, the drive light-shielding portions T1L in two adjacent sub-pixels PX are connected, the reset light-shielding portions T4L in two adjacent sub-pixels PX are connected, and the compensation light-shielding portions T3L in two adjacent sub-pixels PX are connected.

[0087] exist Figure 9 In the structure, the shading layer 121 also includes a first connecting segment CT1 connected to the driving shading portion T1L, the first connecting segment CT1 is arranged between the driving shading portion T1L and the compensation shading portion T3L, and the end of the first connecting segment CT1 away from the driving shading portion T1L is spaced apart from the compensation shading portion T3L, and the electrical connector is electrically connected to the first connecting segment CT1.

[0088] It should be noted that in some repeating units RU, since no corresponding electrical connection line 50 is set inside the pixel circuit PC, that is, the first connection segment CT1 is not required in the repeating unit RU, the pattern in the light shielding layer 121 in the corresponding repeating unit RU can be symmetrically arranged.

[0089] See also Figure 9 , Figure 4 for Figures 10 to 12 FIG. 1 is a stacked diagram of the first gate layer 125 and the light shielding layer 121. FIG.

[0090] exist Figure 10 In the structure, the reset shading portion T4L is arranged between the first reset signal line Vi1 and the switch control line Pscan1, the compensation shading portion T3L is arranged between the switch control line Pscan1 and the driving shading portion T1L, and the compensation shading portion T3L overlaps with a portion of the switch control line Pscan1, and the driving shading portion T1L overlaps with the first electrode Cst1.

[0091] In this embodiment, since the driving light shielding portion T1L can also serve as a shielding structure, the outer contour area of ​​the driving light shielding portion T1L of the present application can be larger than the area of ​​the first electrode plate Cst1, and the positive projection of the first electrode plate Cst1 on the light shielding layer 121 can be located within the driving light shielding portion T1L.

[0092] Referring to Figure 4 , Figure 11 For Figure 4 the structural diagram of the second active layer 127 in the second embodiment, Figure 12 For Figure 4 the structural diagram of the second gate layer 129 in the second embodiment, Figure 10 For Figure 10 the stack diagram of the first gate layer 125, the light shielding layer 121, the first active layer 123, the second active layer 127 and the second gate layer 129 in the second embodiment, and the patterns in the second active layer 127 in one repeating unit RU can be symmetrically arranged, and the patterns in the second gate layer 129 in one repeating unit RU can be symmetrically arranged.

[0093] In Figure 11 the structure, the second active layer 127 includes a first reset active part T4A of the first reset transistor T4 and a compensation active part T3A of the compensation transistor T3, both of which extend along the second direction Y and are in a strip shape, and are connected to the fourth connection point N4.

[0094] In Figure 12 the structure, the second active layer 127 further includes a second plate Cst2 of the storage capacitor Cst, and the second plates Cst2 in one repeating unit RU are connected, and the second plates Cst2 are arranged opposite to the first plates Cst1, the outer contour area of the first plates Cst1 can be smaller than the outer contour area of the second plates Cst2, and the outer contour area of the second plates Cst2 is smaller than the outer contour area of the driving light shielding part T1L.

[0095] In Figure 12 the structure, the second gate layer 129 includes the first reset control line Nscan2, the compensation control line Nscan1 and the third reset signal line Vi3 arranged at intervals along the second direction Y, and both of the first reset control line Nscan2 and the compensation control line Nscan1 extend along the first direction X.

[0096] In Figure 12In the structure, the first reset control line Nscan2 and the reset light shielding part T4L both have an overlapping part with the first reset active part T4A, the first reset control line Nscan2 in the overlapping part is multiplexed as the first reset gate T4G, the first reset active part T4A in the overlapping part is the channel of the first reset transistor T4, one end of the first reset active part T4A close to the fourth connection point N4 is multiplexed as the source T4S of the first reset transistor T4, and the other end of the first reset active part T4A away from the fourth connection point N4 is multiplexed as the drain T4D of the first reset transistor T4, that is, the structure of the region where the fourth connection point N4 is located is the third node Q in the pixel circuit PC, and the control signals transmitted by the first reset control line Nscan2 and the reset light shielding part T4L are the same.

[0097] In the structure, Figure 4 In the structure, the compensation light shielding part T3L and the compensation control line Nscan1 both have an overlapping part with the compensation active part T3A of the compensation transistor T3, the compensation control line Nscan1 in the overlapping part is multiplexed as the compensation gate T3G, the compensation active part T3A in the overlapping part is the channel of the compensation transistor T3, one end of the compensation active part T3A close to the fourth connection point N4 is multiplexed as the drain T3D of the compensation transistor T3, and the other end of the compensation active part T3A away from the fourth connection point N4 is multiplexed as the source T3S of the compensation transistor T3, and the control signals transmitted by the compensation light shielding part T3L and the compensation control line Nscan1 are the same.

[0098] In the structure, Figure 13 In the structure, the first reset control line Nscan2 and the reset light shielding part T4L have an overlapping part, and the compensation control line Nscan1 and the compensation light shielding part T3L have an overlapping part, and the area of the overlapping part of the first reset control line Nscan2 and the active part of the first reset transistor T4 is greater than the area of the overlapping part of the reset light shielding part T4L and the active part of the first reset transistor T4, and the area of the overlapping part of the compensation light shielding part T3L and the active part of the compensation transistor T3 is greater than the area of the overlapping part of the compensation control line Nscan1 and the active part of the compensation transistor T3.

[0099] Please refer to Figure 14 , Figure 13 and Figure 4 , Figure 14 In the structure of the first source-drain layer 131 in Figure 14 Please refer to Figure 4 , Figure 13 In the structure of the first source-drain layer 131 in Figure 14In the stack diagram of the first gate layer 125, the first active layer 123, the second active layer 127, the second gate layer 129, and the first source-drain layer 131, the pattern in the first source-drain layer 131 within one repeating unit RU can be symmetrically arranged.

[0100] Referring to Figure 14 and Figure 14 , the first source-drain layer 131 includes a lateral fan-out line FIAH and a second reset signal line Vi2, the lateral fan-out line FIAH is arranged on the side of the first reset signal line Vi1 away from the switch control line Pscan1, and the second reset signal line Vi2 is arranged between the third reset signal line Vi3 and the second reset control line Pscan2.

[0101] Referring to Figure 14 , the first source-drain layer 131 further includes a third connection segment CT3, one end of the third connection segment CT3 is connected to the first reset signal line Vi1 through a via, and the other end of the third connection segment CT3 is connected to one end of the first reset active part T4A away from the fourth connection point N4 through a via.

[0102] Referring to Figure 14 , the first source-drain layer 131 further includes a fourth connection segment CT4, one end of the fourth connection segment CT4 is connected to the data line Data through a via, and the other end of the fourth connection segment CT4 is connected to one end of the switch active part T2A away from the first connection point N1 through a via.

[0103] Referring to Figure 14 , the first source-drain layer 131 further includes a fifth connection segment CT5, one end of the fifth connection segment CT5 is connected to one end of the fourth connection point N4 of the compensation active part T3A through a via, and the other end of the fifth connection segment CT5 is connected to the first plate Cst1 through the avoidance hole HLO in the second plate Cst2.

[0104] Referring to Figure 14 , the first source-drain layer 131 further includes a sixth connection segment CT6, one end of the sixth connection segment CT6 is connected to one end of the compensation active part T3A away from the fourth connection point N4 through a via, and the other end of the sixth connection segment CT6 is connected to one end of the second light-emitting active part T6A away from the third connection point N3 through a via.

[0105] Referring to Figure 14 , the first source-drain layer 131 further includes a seventh connection segment CT7, one end of the seventh connection segment CT7 is connected to one end of the first extension segment ET1 away from the third connection point N3 through a via, and the other end of the seventh connection segment CT7 is connected to an upper metal layer through a via.

[0106] Referring to Figure 13The first source-drain layer 131 further comprises an eighth connection segment CT8, one end of the eighth connection segment CT8 is connected to the second extension segment ET2 through a via, and the other end of the eighth connection segment CT8 is connected to one end of the third reset active part T8A close to the light-emitting control line EM.

[0107] In the embodiment, the third reset signal line Vi3 comprises a reset horizontal segment Vi3a and a reset extension segment Vi3b, the reset horizontal segment Vi3a extends along the first direction X, the reset extension segment Vi3b extends along the second direction Y, and the reset extension segment Vi3b has an overlapping part with the eighth connection segment CT8, i.e., the reset extension segment Vi3b overlaps the area where the first node is located.

[0108] Referring to Figure 14 The first source-drain layer 131 further comprises a ninth connection segment CT9, one end of the ninth connection segment CT9 is connected to the reset extension segment Vi3b through a via, and the other end of the ninth connection segment CT9 is connected to one end of the third reset active part T8A away from the light-emitting control line EM, and the two ninth connection segments CT9 in one repeat unit RU are electrically connected at the position overlapping with the reset extension segment Vi3b.

[0109] Referring to Figure 4 and Figure 15 The first source-drain layer 131 further comprises a first sub-line 510 constituting the electric connection line 50, the first sub-line 510 comprises a first horizontal segment 511 and a first longitudinal segment 512 connected to each other, the first horizontal segment 511 is arranged along the first direction X, and the first longitudinal segment 512 is arranged along the second direction Y; the orthogonal projection of the first horizontal segment 511 on the light-blocking layer 121 is located between the driving light-blocking part T1L and the compensation light-blocking part T3L, and has an overlapping part with the first connection segment CT1, and the first horizontal segment 511 is electrically connected to the first connection segment CT1 through a first via H11.

[0110] In the embodiment, the first horizontal segments 511 in one repeat unit RU are connected to each other, and the first longitudinal segments 512 in one repeat unit RU are shared; meanwhile, the first longitudinal segment 512 comprises a first part 512a close to the first horizontal segment 511 and a second part 512b away from the first horizontal segment 511, one end of the first part 512a close to the second part 512b is electrically connected to the second electrode plate Cst2 through a via, and one end of the second part 512b away from the first part 512a is connected to one end of the first light-emitting active part T5A away from the first connection point N1 through a via.

[0111] In the embodiment, the line width of the first part 512a is greater than the line width of the second part 512b.

[0112] Referring to Figure 15 and Figure 4 , Figure 4 As Figure 15 FIG. 6 is a structural diagram of the second source-drain layer 133 in the second embodiment, and the pattern in the second source-drain layer 133 in one repeat unit RU is asymmetrically arranged.

[0113] Referring to Figure 15 and Figure 16 , the second source-drain layer 133 includes the high-potential line VDD arranged along the first direction X, the second sub-line 520 constituting the electrically connecting line 50, and the data line Data, and the high-potential line VDD, the second sub-line 520, and the data line Data all extend along the second direction Y.

[0114] In the present embodiment, the second source-drain layer 133 further includes a second connecting segment CT2, one end of the second connecting segment CT2 is connected with the second sub-line 520, the other end of the second connecting segment CT2 is connected with the high-potential line VDD, and one end of the first transverse segment 511 away from the first longitudinal segment 512 has an overlapping part with the high-potential line VDD, and the high-potential line VDD is electrically connected with the first transverse segment 511 through the second via hole HL2.

[0115] It should be noted that, referring to Figure 16 , in one repeat unit RU, the pixel circuit PC on the left side can include the high-potential line VDD, the second sub-line 520, and the data line Data arranged along the first direction X, and the pixel circuit PC on the right side can include the data line Data, the longitudinal fan-out line FIAZ, and the high-potential line VDD arranged along the first direction X, each column of sub-pixels PX corresponds to one high-potential line VDD and one data line Data, and one longitudinal fan-out line FIAZ is arranged in one sub-pixel PX in each repeat unit RU, which can be electrically connected with the transverse fan-out line FIAH.

[0116] It should be noted that the second sub-line 520 only exists in part of the repeat units RU, and in different repeat units RU, the position of the second sub-line 520 can be arranged with the first reset connecting line Vi1c, the second reset connecting line Vi2c, and the third reset connecting line Vi3c extending along the second direction Y.

[0117] For example, referring to Figure 16 , Figure 17Two rows of sub-pixels PX are shown, and each row of sub-pixels PX includes 4 repeating units RU, in the two repeating units RU of the third column, the first reset connection line Vi1c is arranged in the left sub-pixel PX, and the two adjacent first reset signal lines Vi1 are electrically connected through the first reset connection line Vi1c in the second direction Y; in the two repeating units RU of the second column, the second reset connection line Vi2c is arranged in the left sub-pixel PX, and the two adjacent second reset signal lines Vi2 are electrically connected through the second reset connection line Vi2c in the second direction Y; in the two repeating units RU of the first column, the third reset connection line Vi3c is arranged in the left sub-pixel PX, and the two adjacent third reset signal lines Vi3 are electrically connected through the third reset connection line Vi3c in the second direction Y; in the two repeating units RU of the fourth column, the second sub-line 520 is arranged in the left sub-pixel PX, and the high potential line VDD, the first sub-line 510, the second plate Cst2 and the driving light shielding part T1L of the adjacent two rows are connected with each other and all transmit high level in the second direction Y.

[0118] In Figure 17 In the structure, the first reset connection line Vi1c, the second reset connection line Vi2c, the third reset connection line Vi3c and the electric connection line 50 are arranged in the first direction X.

[0119] It should be noted that the first reset connection line Vi1c, the second reset connection line Vi2c, the third reset connection line Vi3c and the electric connection line 50 can be arranged at intervals of 1 repeating unit RU, or can be designed differently according to the difference of the signals transmitted by different connection lines; for example, the number of repeating units RU spaced between the two adjacent first reset connection lines Vi1c is less than the number of repeating units RU spaced by the other three connection lines.

[0120] It should be noted that in the first direction X, the third reset connection line Vi3c, the second reset connection line Vi2c, the first reset connection line Vi1c and the electric connection line 50 are arranged in sequence.

[0121] In this embodiment, the longitudinal electric connection line 50 is arranged to electrically connect the driving light shielding part T1L, the second plate Cst2 of the storage capacitor Cst and the high potential line VDD in the light shielding layer 121 with each other, so that the structure transmitting high potential signals forms a horizontal and vertical mesh structure, reduces the impedance of the driving light shielding part T1L, improves the potential difference of different regions of the light shielding layer 121, and improves the display effect of the display panel 100.

[0122] Please refer to Figure 4 , Figure 17The pattern and the stack of anode layers in the present application ​ The stack of the pattern and the anode layer in the present application.

[0123] Please refer to ​ The display panel 100 can include a first pixel circuit PC1 and a second pixel circuit PC2, and a first anode AN1 connected with the first pixel circuit PC1 and a second anode AN2 connected with the second pixel circuit PC2, the first anode overlaps with the first pixel circuit PC1 and the second pixel circuit PC2, and in order to avoid the influence of the high potential line VDD on the anode potential as much as possible, the first anode and the second anode AN2 of the present application are arranged as far away from the high potential line VDD as possible.

[0124] In the embodiment, the first pixel circuit PC1 can be one of a red sub-pixel PX, a green sub-pixel PX and a blue sub-pixel PX, and the second pixel circuit PC2 can be another one of the red sub-pixel PX, the green sub-pixel PX and the blue sub-pixel PX.

[0125] It should be noted that the conductive line for transmitting signals in the present application extends along the first direction X or the second direction Y, which only represents that the conductive line extends in the direction, and does not represent that the conductive line is a straight line, for example, the conductive line in the present application can be a curved line or a broken line.

[0126] The present application also provides a display device, which includes the display panel described above. The display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0127] The present application discloses a display panel and a display device; the pixel circuit of the display panel includes a driving transistor and a storage capacitor connected with each other, the light shielding layer in the display panel includes a driving light shielding part corresponding to the driving transistor, the first active layer includes an active part of the driving transistor, the first gate layer includes a gate of the driving transistor and one plate of the storage capacitor, the second active layer includes the other plate of the storage capacitor, the driving light shielding parts in two adjacent sub-pixels in the first direction are connected with each other, and the driving light shielding parts in two adjacent sub-pixels in the second direction are electrically connected through an electrical connection line; the present application makes the two adjacent driving light shielding parts in the second direction electrically connected through the electrical connection line extending along the second direction, that is, the driving light shielding parts in different sub-pixels are electrically connected with each other in the first direction and the second direction, the impedance of the driving light shielding part is reduced, the potential difference between different regions of the light shielding layer is improved, and the display effect of the display panel is improved.

[0128] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0129] The above has carried out the detailed introduction to the display panel and the display device provided by the embodiment of the application, the principle and the implementation mode of the application are described in the text by applying specific examples, the above embodiment is only used for helping understanding the technical scheme of the application and its core idea; the ordinary skilled in the art should understand that: it can still modify the technical scheme recorded by the foregoing each embodiment, or equivalent replacement is carried out to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical scheme deviate from the scope of the technical scheme of the embodiments of the application.

Claims

1. A display panel, characterized in that: The display panel comprises a plurality of sub-pixels arranged in a first direction and a second direction, at least one of the sub-pixels comprises a pixel circuit, and the pixel circuit comprises a driving transistor, a compensation transistor, and a storage capacitor connected to each other; wherein the display panel comprises: a light shielding layer comprising a driving light shielding portion corresponding to the driving transistor and a compensation light shielding portion corresponding to the compensation transistor, wherein the driving light shielding portions in two adjacent sub-pixels are connected in the first direction; a first active layer including an active portion of the driving transistor; a first gate layer, comprising a gate of the driving transistor and a plate of the storage capacitor; a second active layer comprising another plate of the storage capacitor; The display panel further includes an electrical connection line extending along the second direction, and in the second direction, the driving light shielding portions in two adjacent sub-pixels are electrically connected via the electrical connection line; The light-shielding layer further includes a first connecting segment connected to the driving light-shielding portion, the first connecting segment is arranged between the driving light-shielding portion and the compensation light-shielding portion, and an end of the first connecting segment away from the driving light-shielding portion is spaced apart from the compensation light-shielding portion.

2. The display panel according to claim 1, wherein: The pixel circuit further includes a switch transistor and a first reset transistor, the switch transistor and the drive transistor are connected to a first node, the drive transistor and the compensation transistor are connected to a second node, and the first reset transistor, the drive transistor and the compensation transistor are connected to a third node; In which, the shading layer also includes a reset shading portion corresponding to the reset transistor, and the reset shading portion, the compensation shading portion and the drive shading portion are arranged at intervals along the second direction, and in the first direction, the reset shading portions in two adjacent sub-pixels are connected, and the compensation shading portions in two adjacent sub-pixels are connected.

3. The display panel according to claim 2, wherein: The display panel further includes: a first source-drain electrode layer, disposed on a side of the second active layer away from the first active layer, the first source-drain electrode layer including a first sub-line constituting the electrical connection line, the first sub-line including a first transverse segment and a first longitudinal segment connected to each other, the first transverse segment being disposed along the first direction, and the first longitudinal segment being disposed along the second direction; The orthographic projection of the first transverse segment on the light-shielding layer is located between the driving light-shielding portion and the compensation light-shielding portion, and has an overlapping portion with the first connecting segment. The first transverse segment is electrically connected to the first connecting segment through a first via hole.

4. The display panel according to claim 3, wherein: The display panel further includes: a second source-drain electrode layer, disposed on a side of the first source-drain electrode layer away from the second active layer, the second source-drain electrode layer comprising a high-potential line arranged along the first direction, a second sub-line constituting the electrical connection line, and a data line, the high-potential line, the second sub-line, and the data line all extending along the second direction; Wherein, the second sub-line is electrically connected to the first transverse segment.

5. The display panel according to claim 4, wherein: The second source-drain layer further includes a second connecting segment, one end of the second connecting segment is connected to the second sub-line, and the other end of the second connecting segment is connected to the high-potential line; The end of the first transverse segment away from the first longitudinal segment has an overlapping portion with the high-potential line, and the high-potential line passes through the second via hole and is electrically connected to the first transverse segment.

6. The display panel according to any one of claims 2 to 5, characterized in that: The display panel further includes: a second gate layer, disposed on a side of the second active layer away from the first active layer, the second gate layer comprising a first reset control line and a compensation control line arranged along the second direction, the first reset control line and the compensation control line both extending along the first direction; Among them, the first reset control line and the reset shading portion both have overlapping portions with the active portion of the first reset transistor, the compensation shading portion and the compensation control line both have overlapping portions with the active portion of the compensation transistor, and the control signals transmitted by the first reset control line and the reset shading portion are the same, and the control signals transmitted by the compensation shading portion and the compensation control line are the same.

7. The display panel according to claim 6, wherein: An area of ​​an overlapping portion between the first reset control line and the active portion of the first reset transistor is larger than an area of ​​an overlapping portion between the reset light shielding portion and the active portion of the first reset transistor; An area of ​​an overlapping portion between the compensation light shielding portion and the active portion of the compensation transistor is larger than an area of ​​an overlapping portion between the compensation control line and the active portion of the compensation transistor.

8. The display panel according to any one of claims 2 to 5, characterized in that: The first gate layer further includes a first reset signal line connected to the drain of the first reset transistor, and the first reset signal line extends along the first direction; The display panel further includes a first reset connection line extending along the second direction. In the second direction, two adjacent first reset signal lines are electrically connected via the first reset connection line, and the first reset connection line and the electrical connection line are spaced apart in the first direction.

9. The display panel according to claim 8, wherein: The pixel circuit further includes a second reset transistor and a third reset transistor, wherein the drain of the second reset transistor is connected to the second reset signal line, the source of the second reset transistor is connected to the anode of the light emitting device, the drain of the third reset transistor is connected to the third reset signal line, and the source of the third reset transistor is connected to the switch transistor and the driving transistor; In which, the display panel also includes a second reset connection line and a third reset connection line extending along the second direction, two adjacent second reset signal lines are electrically connected through the second reset connection line, two adjacent third reset signal lines are electrically connected through the third reset connection line, and the first reset connection line, the second reset connection line, the third reset connection line and the electrical connection line are arranged at intervals in the first direction.

10. A display device, characterized in that: The display device includes the display panel according to any one of claims 1 to 9.

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