Display device

Abstract

A display device is provided. The display device includes: a substrate including a display area and a peripheral area surrounding at least a portion of the display area in plan view; a first data line in the display area and extending in a second direction; a second data line separated from the first data line in a first direction crossing the second direction, extending in the second direction, and having a length greater than a length of the first data line; and a branch line connected to the first data line and protruding from the first data line in the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0137035, filed on October 13, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] One or more embodiments relate to a display device. Background Art

[0004] The display device visually displays data. The display device may provide an image by using a light emitting diode. The use of the display device has been diversified, and various designs have been tried to improve the quality of the display device. Summary of the invention

[0005] One or more embodiments include a display device.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0007] According to one or more embodiments, a display device includes: a substrate including a display area and a peripheral area surrounding at least a portion of the display area in a plan view; a first data line in the display area and extending in a second direction; a second data line separated from the first data line in a first direction intersecting the second direction, extending in the second direction and having a length greater than that of the first data line; and a branch line connected to the first data line and protruding from the first data line in the first direction.

[0008] The branch line may include a first branch line extending in the second direction and a second branch line connecting the first branch line to the first data line and extending in the first direction.

[0009] The first data line and the branch line may be at the same layer, and may include the same material.

[0010] The display device may further include a first bridge line that is separated from the first data line in the first direction and extends in the second direction, wherein the first data line and the first bridge line are connected to each other.

[0011] One end of the first bridge line may be connected to one end of the first data line.

[0012] The first data line and the first bridge line may be at the same layer, and may include the same material.

[0013] A thickness of the first bridge line in the first direction may be greater than a thickness of the first data line in the first direction.

[0014] According to one or more embodiments, a display device includes a substrate, a third data line, and a second bridge line, the substrate including a display area having a circular shape and a peripheral area surrounding at least a portion of the display area in a plan view, the third data line is arranged in the display area and extends in a second direction, and the second bridge line is separated from the third data line in a first direction intersecting the second direction, extends in the second direction and is connected to the third data line.

[0015] One end of the third data line may be connected to one end of the second bridge line.

[0016] The third data line and the second bridge line may be at the same layer, and may include the same material.

[0017] A thickness of the second bridge line in the first direction may be greater than a thickness of the third data line in the first direction.

[0018] The display device may further include a third bridge line connected to the first end of the third data line and extending in the first direction.

[0019] The third bridge line and the third data line may be at different corresponding layers.

[0020] A thickness of the third bridge line in the second direction may be greater than a thickness of the third data line in the first direction.

[0021] The display device may further include a fourth bridge line separated from the third data line in the first direction, extending in the second direction, and connected to the third bridge line.

[0022] The third data line may be disposed between the second bridge line and the fourth bridge line.

[0023] The third bridge line and the fourth bridge line may be at different respective layers.

[0024] The fourth bridge line and the third data line may be at the same layer, and may include the same material.

[0025] The display device may further include a fifth bridge line connected to the second end of the third data line and extending in the first direction.

[0026] The fifth bridge line and the third data line may be at different corresponding layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects of certain embodiments of the present disclosure will become more apparent through the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1is a schematic plan view of a portion of a display device according to one or more embodiments;

[0029] Figure 2 is included in Figure 1 An equivalent circuit diagram of a pixel in a display device;

[0030] Figure 3 is a schematic cross-sectional view of a display device according to one or more embodiments;

[0031] Figure 4 yes Figure 1 A schematic enlarged plan view of a first data line and a branch line;

[0032] Figure 5 is a schematic plan view of a portion of a display device according to one or more embodiments;

[0033] Figure 6 yes Figure 5 A schematic enlarged plan view of a first data line, a first bridge line, and a branch line;

[0034] Figure 7 is a schematic plan view of a display device according to one or more embodiments;

[0035] Figure 8 yes Figure 7 A schematic enlarged plan view of area A;

[0036] Fig. 9 is a schematic plan view of a display device according to one or more embodiments;

[0037] Fig.10 yes Fig. 9 A schematic enlarged plan view of region B;

[0038] Fig.11 is a schematic plan view of a display device according to one or more embodiments; and

[0039] Fig.12 yes Fig.11 Schematic enlarged plan view of area C. DETAILED DESCRIPTION

[0040] By referring to the detailed description and drawings of the embodiments, it is easier to understand the various aspects of some embodiments of the present disclosure and the methods for realizing them. On the contrary, the described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the various aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the various aspects of the present disclosure can be omitted. Unless otherwise noted, similar reference numerals, symbols or combinations thereof indicate similar elements throughout the drawings and written descriptions, and therefore their repeated descriptions can be omitted.

[0041] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The use of "can", "may" or "maynot" in describing the embodiments corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and replacements within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various technical interlocks and drives are possible. The various embodiments may be implemented independently of each other, or may be implemented together in association.

[0042] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements.

[0043] Various embodiments are described herein with reference to schematic cross-sectional illustrations of embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances will be expected. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be construed as being limited to the shapes of the elements, layers, or regions shown, but will include deviations in shape due to, for example, manufacturing.

[0044] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface where the implantation takes place.

[0045] Spatially relative terms, such as "beneath", "below", "lower", "lower side", "under", "above", "upper", "upper side" and the like, may be used herein for convenience of explanation to describe the relationship of one element or feature to another element or feature as shown in the figures. It will be understood that in addition to the orientations depicted in the figures, spatially relative terms are intended to also include different orientations of the device in use or operation. For example, if the device in the figure is turned over, the elements described as being "below", "beneath" or "under" other elements or features will subsequently be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "under" can include both the orientations of above and below. The device can be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Similarly, when a first portion is described as being disposed “on” a second portion, this indicates that the first portion is disposed at an upper side or a lower side of the second portion without being limited to an upper side thereof based on the gravity direction.

[0046] In addition, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting the object portion is viewed from the side. The term "overlap" or "overlapped" means that the first object may be above or below the second object, or to the side of the second object, and vice versa. In addition, the term "overlap" may include stacking, facing or facing, extending on, covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" may include meanings such as "separated from" or "set aside" or "offset from" and any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art. The terms "face" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing each other.

[0047] It will be understood that when an element, layer, region, or component is referred to as being formed on, "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it can be directly formed on, directly on, directly connected to, or directly coupled to another element, layer, region, or component, or can be indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to another element, layer, region, or component, such that there may be one or more intervening elements, layers, regions, or components. Furthermore, this may collectively mean direct or indirect coupling or connection, as well as integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected to" or "electrically coupled to" another layer, region, or component, it can be directly electrically connected to or coupled to another layer, region, and / or component, or there may be one or more intervening layers, regions, or components. One or more intermediate components may include switches, resistors, capacitors, and / or the like. In describing the embodiments, expressions of connection indicate electrical connection unless explicitly described as directly connected, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component, or is on another component without intermediate components.

[0048] In addition, in this specification, when a portion of a layer, film, region, plate or the like is formed on another part, the formation direction is not limited to the upper direction, but includes forming the portion on the side surface or forming the portion in the lower direction. On the contrary, when a portion of a layer, film, region, plate or the like is formed "below" another part, this includes not only the situation that the portion is "directly" "below" another part, but also includes the situation that there is another part between the portion and the other part. At the same time, other expressions such as "between", "immediately between" or "adjacent" and "directly adjacent" describing the relationship between parts can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0049] For the purposes of this disclosure, when expressions such as "at least one of" or "any one of" or "one or more of" follow a list of elements, the entire list of elements is modified, and the individual elements in the list are not modified. For example, "at least one of X, Y, and Z", "at least one of X, Y, or Z", "at least one selected from the cluster consisting of X, Y, and Z", and "at least one selected from the cluster consisting of X, Y, or Z" may be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as XYZ, XY, YZ, and XZ as examples), or any variation thereof. Similarly, the expressions "at least one of A and B" and "at least one of A or B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases, when preceding or following a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0050] It will be understood that, although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, areas, layers and / or sections, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or superiority, and are only used to distinguish an element, member, component, area, region, layer, section or part from another element, member, component, area, region, layer, section or part. Therefore, the first element, first component, first area, first layer or first section discussed below can be referred to as the second element, second component, second area, second layer or second section without departing from the spirit and scope of the present disclosure. The description of the element as the "first" element may not require or imply the existence of the second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish different categories or groups of elements. For simplicity, the terms "first", "second", etc. can respectively represent "first class (or first group)", "second class (or second group)", etc.

[0051] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted as having a broader meaning. For example, the x-axis, y-axis and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0052] The terms used herein are for the purpose of describing the embodiments only and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular forms "a" and "an" as used herein are also intended to include the plural forms, and the plural forms are also intended to include the singular forms. It will also be understood that when the terms "comprises", "comprising", "have", "having", "includes" and "including" are used in this specification, the existence of the stated features, integers, steps, operations, elements and / or parts is explained, but the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or clusters thereof is not excluded.

[0053] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as terms of approximation and not as terms of degree, and are intended to take into account the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. Taking into account the errors associated with the measurement and the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the stated value and mean within the acceptable deviation range for the particular value as determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0054] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0055] Figure 1 1 is a schematic plan view of a portion of a display device 10 according to one or more embodiments. Figure 1As shown in , the display device 10 according to one or more embodiments may include a substrate 100, and the substrate 100 may include a display area DA and a peripheral area PA outside the display area DA. An image may be displayed in the display area DA. The peripheral area PA may be a type of non-display area where a display device is not arranged. The display area DA may be completely surrounded by the peripheral area PA (for example, in a plan view). The peripheral area PA may include a first peripheral area PA1 and a second peripheral area PA2 at opposite sides of the display area DA.

[0056] The display area DA of the display device 10 may have an amorphous shape instead of a rectangular shape. For example, the display area DA of the display device 10 may not have a constant length from any point along the second direction (e.g., the y direction or the -y direction) toward the first direction (e.g., the x direction or the -x direction). In detail, the display area DA may include a first display area DA1 and a second display area DA2. The length of the first display area DA1 in the first direction (e.g., the x direction or the -x direction) may be different from the maximum distance of the second display area DA2 in the first direction (e.g., the x direction or the -x direction). In addition, the length of the first display area DA1 in the second direction (e.g., the y direction or the -y direction) may be different from the maximum distance of the second display area DA2 in the second direction (e.g., the y direction or the -y direction). However, the present disclosure is not limited thereto. According to one or more other embodiments, the display area DA of the display device 10 may have a circular shape.

[0057] The substrate 100 may include glass, metal or polymer resin. When the substrate 100 has a flexible or bendable property, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate or cellulose acetate propionate. However, various modifications of the substrate 100 may be possible. For example, the substrate 100 may have a multilayer structure including two layers including the above-mentioned polymer resin and a barrier layer between the two layers, the barrier layer including an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride or the like.

[0058] The display device 10 may provide an image by using a plurality of pixels Pm arranged in a display area DA of the substrate 100. Each of the pixels Pm may include a pixel circuit PCm and a display device EDm electrically connected to the pixel circuit PCm. The pixel circuit PCm may include at least one thin film transistor TFT (e.g., referring to FIG. 1 ) configured to control emission, emission degree, etc. of the display device EDm. Figure 3 ). The pixel circuit PCm may be arranged to overlap with the display device EDm.

[0059] Hereinafter, an organic light-emitting display device will be described as an example of a display device 10 according to one or more embodiments. That is, a case where the display device EDm is an organic light-emitting device will be described. However, the display device 10 according to the present disclosure is not limited thereto. For example, the display device 10 according to the present disclosure may include an inorganic light-emitting display device, an inorganic electroluminescent (EL) display device, or a quantum dot light-emitting display device. For example, the emission layer of the display device provided in the display device 10 may include an organic material, an inorganic material, or an organic material and quantum dots. In addition, the display device 10 may include quantum dots and may convert the wavelength of light.

[0060] The pixel circuit PCm included in the pixel Pm in the display area DA may be electrically connected to an external circuit disposed in the peripheral area PA. A scan driving circuit SDR, a pad portion PAD, a driving voltage supply line 11, and a common voltage supply line 13 may be disposed in the peripheral area PA.

[0061] The scan drive circuit SDR may be arranged at one side of the display area DA. The scan drive circuit SDR may be connected to one or more of the pixel circuits PCm through a scan line SL and may be configured to apply a scan signal. The scan drive circuit SDR may be connected to one or more of the pixel circuits PCm through an emission control line EL and may be configured to apply an emission control signal. However, the present disclosure is not limited thereto. According to one or more other embodiments, the scan drive circuit SDR may also be arranged at the other side of the display area DA, and therefore, two scan drive circuits SDR may be provided.

[0062] The pad portion PAD may be disposed in the second peripheral area PA2 at one side of the substrate 100. The pad portion PAD may not be covered by the insulating layer and may be exposed so as to be connected to the display circuit board 30. A display driver 32 may be disposed on the display circuit board 30.

[0063] The display driver 32 may be configured to generate a control signal transmitted to the scan driving circuit SDR. In addition, the display driver 32 may be configured to generate a data signal, and the generated data signal may be transmitted to the pixel circuit PCm through the fan-out line FW and the data line DL connected to the fan-out line FW.

[0064] The data lines DL may include first and second data lines DL1 and DL2. The first and second data lines DL1 and DL2 may be arranged in the display area DA. In detail, the first data line DL1 may be arranged in the first display area DA1, and the second data line DL2 may be arranged in the second display area DA2.

[0065] The first data line DL1 and the second data line DL2 may be arranged to be separated from each other in a first direction (e.g., an x ​​direction or a -x direction). The length of the first data line DL1 in a second direction (e.g., a y direction or a -y direction) may be different from the length of the second data line DL2 in the second direction (e.g., a y direction or a -y direction). The length of the first data line DL1 in the second direction (e.g., a y direction or a -y direction) may be less than the length of the second data line DL2 in the second direction (e.g., a y direction or a -y direction).

[0066] According to one or more embodiments, the branch line BL connected to the first data line DL1 may be arranged in the display area DA. In detail, the branch line BL protruding from the first data line DL1 in a first direction (e.g., x direction or -x direction) may be arranged in the display area DA. The branch line BL may include a first branch line BL1 and a second branch line BL2. Figure 4 This aspect is described in more detail.

[0067] The display driver 32 may be configured to provide a driving voltage ELVDD (eg, Figure 2 ) is supplied to the driving voltage supply line 11, and the common voltage ELVSS (eg, reference Figure 2 ) is supplied to the common voltage supply line 13. The driving voltage ELVDD may be applied to the pixel circuit PCm through the driving voltage line PL connected to the driving voltage supply line 11, and the common voltage ELVSS may be applied to the opposite electrode of the display device EDm through the common voltage supply line 13.

[0068] The driving voltage supply line 11 may be arranged below the display area DA and may have a shape extending in the x-axis direction or the first direction (e.g., the x direction or the -x direction). The common voltage supply line 13 may have a ring shape with an open side in a plan view and may partially surround the display area DA.

[0069] Figure 2 is included in Figure 1 Here, the pixel P refers to the equivalent circuit diagram of the pixel P in the display device 10. Figure 1 The pixel indicated by the reference symbol Pm in .

[0070] like Figure 2 As shown in FIG. 1 , the pixel P may include a pixel circuit PC and an organic light emitting diode OLED electrically connected to the pixel circuit PC. The pixel circuit PC refers to a Figure 1 The pixel circuit indicated by the reference symbol PCm in FIG. 1 and the organic light emitting diode OLED refers to the pixel circuit indicated by the reference symbol PCm in FIG. Figure 1 A display device indicated by reference symbol EDm in FIG.

[0071] The pixel P may include an organic light emitting diode OLED as a display element connected to the pixel circuit PC. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each pixel P may emit, for example, red light, green light, or blue light, or red light, green light, blue light, or white light through the organic light emitting diode OLED.

[0072] The second thin film transistor T2 may be a switching thin film transistor, may be connected to the scan line SL and the data line DL, and may be configured to transfer a data voltage input from the data line DL to the first thin film transistor T1 based on a switching voltage input from the scan line SL. The storage capacitor Cst may be connected to the second thin film transistor T2 and the driving voltage line PL, and may be configured to store a voltage corresponding to a difference between a voltage received from the second thin film transistor T2 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0073] The first thin film transistor T1 may be a driving thin film transistor, may be connected to the driving voltage line PL and the storage capacitor Cst, and may be configured to control a driving current flowing from the driving voltage line PL through the organic light emitting diode OLED according to the value of the voltage stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light having a corresponding brightness according to the driving current. An opposite electrode (e.g., a cathode) of the organic light emitting diode OLED may receive a common voltage ELVSS.

[0074] Figure 2 The pixel circuit PC is shown to include two thin film transistors and one storage capacitor. However, the present disclosure is not limited thereto. The number of thin film transistors and the number of storage capacitors may be variously modified according to the design of the pixel circuit PC. For example, the pixel circuit PC may include two thin film transistors as described above, or four or five or more thin film transistors.

[0075] Figure 3 is a schematic cross-sectional view of a display device 10 according to one or more embodiments. In detail, Figure 3 It is taken along line I-I' Figure 1 Schematic cross-sectional view of a display device 10.

[0076] Reference Figure 3 , the substrate 100 may include a first base layer 100a, a first barrier layer 100b, a second base layer 100c, and a second barrier layer 100d. According to one or more embodiments, the first base layer 100a, the first barrier layer 100b, the second base layer 100c, and the second barrier layer 100d may be sequentially stacked in a thickness direction (eg, z direction) of the substrate 100.

[0077] At least one of the first base layer 100a and the second base layer 100c may include a polymer resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, or the like.

[0078] The first barrier layer 100b and the second barrier layer 100d may reduce or prevent penetration of external impurities, and may include a material including silicon nitride (SiN x ), silicon oxide (SiO 2 ) and / or a single layer or multiple layers of inorganic materials of silicon oxynitride (SiON).

[0079] A buffer layer 111 may be positioned on the substrate 100. The buffer layer 111 may include, for example, SiN x , SiON or SiO 2 and may include a single layer or multiple layers containing the above-mentioned inorganic insulating material.

[0080] An inorganic insulating layer IIL may be positioned on the buffer layer 111. The inorganic insulating layer IIL may include a first gate insulating layer 112, a second gate insulating layer 113, and an interlayer insulating layer 114.

[0081] The pixel circuit PC may be arranged in the display area DA. The pixel circuit PC may include a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0082] A semiconductor layer Act may be positioned on the buffer layer 111. The semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, or an organic semiconductor. The semiconductor layer Act may include a channel region and a drain region and a source region arranged at respective sides of the channel region.

[0083] A gate electrode GE may be positioned on the semiconductor layer Act. The gate electrode GE may overlap the channel region. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including Mo, Al, Cu, Ti, etc., and may include a multilayer or a single layer including the above conductive material.

[0084] A first gate insulating layer 112 may be positioned between the semiconductor layer Act and the gate electrode GE. The first gate insulating layer 112 may include an inorganic insulating material such as SiO 2 、SiN x , SiON, Alumina (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO).

[0085] A second gate insulating layer 113 may be positioned on the gate electrode GE. The second gate insulating layer 113 may cover the gate electrode GE. The second gate insulating layer 113 may include an inorganic insulating material such as SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 or ZnO.

[0086] A second storage plate CE2 of the storage capacitor Cst may be positioned on the second gate insulating layer 113. The second storage plate CE2 may overlap the gate electrode GE positioned therebelow. Here, the gate electrode GE and the second storage plate CE2 overlapping each other with the second gate insulating layer 113 therebetween may be included in the storage capacitor Cst. That is, the gate electrode GE may serve as the first storage plate CE1 of the storage capacitor Cst.

[0087] As described above, the storage capacitor Cst and the thin film transistor TFT may be formed to overlap each other. However, the present disclosure is not limited thereto. For example, the storage capacitor Cst may be formed not to overlap with the thin film transistor TFT. That is, the first storage plate CE1 of the storage capacitor Cst may be an element separated from the gate electrode GE of the thin film transistor TFT, and may be separated from the gate electrode GE of the thin film transistor TFT.

[0088] The second storage plate CE2 may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W, and / or Cu, and may include a single layer or a multilayer including the above materials.

[0089] An interlayer insulating layer 114 may be positioned on the second storage plate CE2. The interlayer insulating layer 114 may cover the second storage plate CE2. The interlayer insulating layer 114 may include SiO 2 、SiN x 、SiON、Al 2 O 3 、TiO 2 、 2 O 5 , HfO 2 , ZnO, or the like. The interlayer insulating layer 114 may include a single layer or a plurality of layers including the above-mentioned inorganic insulating material.

[0090] Each of the drain electrode DE and the source electrode SE may be positioned on the interlayer insulating layer 114. Each of the drain electrode DE and the source electrode SE may be connected to the semiconductor layer Act through a contact hole provided in the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 114. The drain electrode DE and the source electrode SE may include a highly conductive material. The drain electrode DE and the source electrode SE may include a conductive material including Mo, Al, Cu, Ti, etc., and may include a multilayer or a single layer including the above materials. For example, the drain electrode DE and the source electrode SE may have a multilayer structure of Ti / Al / Ti.

[0091] An organic insulating layer OIL may be positioned on the inorganic insulating layer IIL. The organic insulating layer OIL may include a first organic insulating layer 115 and a second organic insulating layer 116. Figure 6 It is shown that the organic insulating layer OIL includes two organic insulating layers. However, the present disclosure is not limited thereto. The organic insulating layer OIL may include three or four organic insulating layers.

[0092] The first organic insulating layer 115 may cover the drain electrode DE and the source electrode SE. The first organic insulating layer 115 may include an organic insulating material such as a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acryl-based polymer, an imide-based polymer, an aromatic ether-based polymer, an amide-based polymer, a fluorine-based polymer, a paraxylene-based polymer, a vinyl alcohol-based polymer, and / or a blend thereof.

[0093] A connection electrode CM may be positioned on the first organic insulating layer 115. Here, the connection electrode CM may be connected to the drain electrode DE or the source electrode SE through a contact hole of the first organic insulating layer 115. The connection electrode CM may include a highly conductive material. The connection electrode CM may include a conductive material including Mo, Al, Cu, Ti, etc., and may include a multilayer or a single layer including the above conductive materials. For example, the connection electrode CM may have a multilayer structure of Ti / Al / Ti.

[0094] A second organic insulating layer 116 may be positioned on the connection electrode CM. The second organic insulating layer 116 may cover the connection electrode CM. The second organic insulating layer 116 may include the same material as the first organic insulating layer 115 or may include a different material from the first organic insulating layer 115.

[0095] A light emitting diode may be positioned on the second organic insulating layer 116. For example, an organic light emitting diode OLED may be positioned on the second organic insulating layer 116. Alternatively, in one or more embodiments, an inorganic light emitting diode or the like may also be positioned on the second organic insulating layer 116.

[0096] The organic light emitting diode OLED may emit red light, green light, or blue light, or red light, green light, blue light, or white light. The organic light emitting diode OLED may include a first electrode 211, an emission layer 212b, a functional layer 212f, a second electrode 213, and a cover layer 215. The first electrode 211 may be a pixel electrode (e.g., an anode) of the organic light emitting diode OLED, and the second electrode 213 may be an opposite electrode (e.g., a cathode) of the organic light emitting diode OLED.

[0097] The first electrode 211 may be positioned on the second organic insulating layer 116. The first electrode 211 may be electrically connected to the connection electrode CM through a contact hole defined in the second organic insulating layer 116. The first electrode 211 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). According to one or more embodiments, the first electrode 211 may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a compound thereof. According to one or more embodiments, the first electrode 211 may also include a reflective layer including ITO, IZO, ZnO or In above / below the reflective layer. 2 O 3 For example, the first electrode 211 may have a multi-layer structure of ITO / Ag / ITO.

[0098] A pixel defining layer 118 having an opening exposing at least a portion of the first electrode 211 may be positioned on the first electrode 211. The opening defined in the pixel defining layer 118 may define an emission region of light emitted from the organic light emitting diode OLED. For example, the width of the opening may correspond to the width of the emission region.

[0099] The pixel defining layer 118 may include an organic insulating material. Alternatively, the pixel defining layer 118 may include an inorganic insulating material such as SiN x , SiON or SiO x . Alternatively, the pixel defining layer 118 may include an organic insulating material and an inorganic insulating material. According to some embodiments, the pixel defining layer 118 may include a light shielding material. The light shielding material may include a resin or paste containing carbon black, carbon nanotubes and / or a black dye, metal particles such as Ni, Al, Mo and / or alloys thereof, metal oxide (e.g., chromium oxide) particles, metal nitride (e.g., chromium nitride) particles, or the like. When the pixel defining layer 118 includes a light shielding material, reflection of external light caused by a metal structure arranged below the pixel defining layer 118 may be reduced.

[0100] A spacer 119 may be positioned on the pixel defining layer 118. The spacer 119 may include an organic insulating material such as polyimide. Alternatively, the spacer 119 may include an organic insulating material such as SiN x or SiO 2 of inorganic insulating materials, or may include organic insulating materials and inorganic insulating materials.

[0101] According to one or more embodiments, the spacer 119 may include the same material as the pixel defining layer 118. In this case, the pixel defining layer 118 and the spacer 119 may be formed together through a mask process using a half-tone mask, etc. Alternatively, the spacer 119 may include a different material from the pixel defining layer 118.

[0102] The emission layer 212b may be positioned in the opening of the pixel defining layer 118. The emission layer 212b may include a high molecular weight or low molecular weight organic material for emitting light of a corresponding color.

[0103] The functional layer 212f may include a first functional layer 212a and a second functional layer 212c. The first functional layer 212a may be positioned between the first electrode 211 and the emission layer 212b, and the second functional layer 212c may be positioned between the emission layer 212b and the second electrode 213. However, at least one of the first functional layer 212a and the second functional layer 212c may be omitted. Hereinafter, the present disclosure will be described in detail mainly based on the case where each of the first functional layer 212a and the second functional layer 212c is positioned.

[0104] The first functional layer 212a may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer 212c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer 212a and / or the second functional layer 212c may be a common layer formed to completely cover the substrate 100, similar to the second electrode 213 to be described below.

[0105] The second electrode 213 may be positioned on the functional layer 212f. The second electrode 213 may include a conductive material having a low work function. For example, the second electrode 213 may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca or an alloy thereof. Alternatively, the second electrode 213 may also include a conductive material such as ITO, IZO, ZnO or In on the (semi) transparent layer including the above materials. 2 O 3 layer.

[0106] According to one or more embodiments, the capping layer 215 may be positioned on the second electrode 213. The capping layer 215 may include an inorganic material and / or an organic material. For example, the capping layer 215 may include LiF.

[0107] An encapsulation layer 300 may be positioned on the organic light emitting diode OLED. The encapsulation layer 300 may cover the organic light emitting diode OLED. The encapsulation layer 300 may be positioned on the second electrode 213 and / or the cover layer 215. According to one or more embodiments, the encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 3 It is shown that the encapsulation layer 300 may include a first inorganic encapsulation layer 310 , an organic encapsulation layer 320 , and a second inorganic encapsulation layer 330 , which are sequentially stacked.

[0108] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include Al 2 O 3 , TiO, TA 2 O 5 , HfO 2 、ZnO、SiO x 、SiN x or SiON. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include a single layer or multiple layers containing the above materials. The organic encapsulation layer 320 may include a polymer material. The polymer material may include acryl resin, epoxy resin, polyimide, polyethylene, etc. According to one or more embodiments, the organic encapsulation layer 320 may include acrylate.

[0109] An input sensing layer 400 may be positioned on the encapsulation layer 300. The input sensing layer 400 may include a first touch insulating layer 410, a second touch insulating layer 420, a first conductive layer 430, a third touch insulating layer 440, a second conductive layer 450, and a planarization layer 460.

[0110] According to one or more embodiments, the first touch insulating layer 410 may be positioned on the second inorganic encapsulation layer 330, and the second touch insulating layer 420 may be positioned on the first touch insulating layer 410. According to one or more embodiments, the first touch insulating layer 410 and the second touch insulating layer 420 may include an inorganic insulating material and / or an organic insulating material. For example, the first touch insulating layer 410 and the second touch insulating layer 420 may include an inorganic insulating material such as SiO x 、SiN x and / or SiON inorganic insulating material.

[0111] According to one or more embodiments, at least one of the first touch insulating layer 410 and the second touch insulating layer 420 may be omitted. For example, the first touch insulating layer 410 may be omitted. In this case, the second touch insulating layer 420 may be positioned on the second inorganic encapsulation layer 330, and the first conductive layer 430 may be positioned on the second touch insulating layer 420.

[0112] The first conductive layer 430 may be positioned on the second touch insulating layer 420, and the third touch insulating layer 440 may be positioned on the first conductive layer 430. According to one or more embodiments, the third touch insulating layer 440 may include an inorganic insulating material and / or an organic insulating material. For example, the third touch insulating layer 440 may include a silicon-based insulating material such as SiO x 、SiN x and / or SiON inorganic insulating material.

[0113] The second conductive layer 450 may be positioned on the third touch insulating layer 440. The touch electrode TE of the input sensing layer 400 may be provided as a structure in which the first conductive layer 430 and the second conductive layer 450 are connected to each other. Alternatively, the touch electrode TE may be formed on any one of the first conductive layer 430 and the second conductive layer 450, and may include a metal wire provided in the corresponding conductive layer. Each of the first conductive layer 430 and the second conductive layer 450 may include at least one of Al, Cu, Ti, Mo and ITO, and may include a single layer or multiple layers containing the above materials. For example, each of the first conductive layer 430 and the second conductive layer 450 may have a three-layer structure of Ti layer / Al layer / Ti layer.

[0114] According to one or more embodiments, the planarization layer 460 may cover the second conductive layer 450. The planarization layer 460 may include an organic insulating material.

[0115] Figure 4 yes Figure 1 FIG. 1 is a schematic enlarged plan view of a first data line DL1 and a branch line BL.

[0116] According to one or more embodiments, the first display area DA1 (see Figure 1 ) may extend in a second direction (e.g., a y direction or a −y direction). A branch line BL may be arranged in the first display area DA1, may be connected to the first data line DL1, and may protrude from the first data line DL1 in a first direction (e.g., an x ​​direction or a −x direction). The first data line DL1 and the branch line BL may be positioned on (or at) the same layer as each other, and may include the same material as each other.

[0117] The branch line BL may include a first branch line BL1 and a second branch line BL2. The first branch line BL1 may extend in the second direction. The second branch line BL2 may connect the first branch line BL1 with the first data line DL1 and may extend in the first direction.

[0118] In the case of a display device having an amorphous shape, a capacitor is formed by separately providing lines in some regions to reduce the amount of power transmitted to the pixel circuit PCm (see Figure 1) is loaded with a data signal. When the capacitor is formed by separately providing lines in some areas, the peripheral area PA (see Figure 1 ) increases, and relative to the display area DA (see Figure 1 ) ratio decreases.

[0119] According to one or more embodiments, the branch line BL may be arranged in the display area DA to be connected to the first data line DL1 and arranged to protrude from the first data line DL1 in the first direction, and a capacitor may be formed by the branch line BL and the first data line DL1, and therefore, the load of the data signal transmitted to the pixel circuit PCm may be reduced, and the expansion of the peripheral area PA which is a non-display area may be reduced or prevented.

[0120] Figure 5 is a schematic plan view of a portion of a display device 10 according to one or more embodiments. Figure 6 yes Figure 5 FIG. 1 is a schematic enlarged plan view of a first data line DL1 , a first bridge line BR1 , and a branch line BL.

[0121] Reference Figure 5 and Figure 6 , a first data line DL1 extending in a second direction (e.g., a y direction or a −y direction) may be arranged in the first display area DA1. A branch line BL may be connected to the first data line DL1 and may protrude from the first data line DL1 in a first direction (e.g., an x ​​direction or a −x direction). The branch line BL may include a first branch line BL1 extending in the second direction and a second branch line BL2 connected to the first branch line BL1 and the first data line DL1 and extending in the first direction.

[0122] The first bridge wire BR1 may be arranged in the first display area DA1, may be separated from the first data line DL1 in a first direction (e.g., an x ​​direction or a −x direction), and may extend in a second direction (e.g., a y direction or a −y direction). The first bridge wire BR1 may be connected to the first data line DL1. In detail, one end of the first bridge wire BR1 may be connected to one end of the first data line DL1 adjacent thereto.

[0123] The first data line DL1 and the first bridge line BR1 may be positioned on (or at) the same layer as each other and may include the same material as each other. In detail, the first data line DL1, the branch line BL, and the first bridge line BR1 may be positioned on (or at) the same layer as each other and may include the same material as each other.

[0124] According to one or more embodiments, a capacitor can be formed not only between the first data line DL1 and the branch line BL, but also between the first data line DL1 and the first bridge line BR1, and therefore, the load of the data signal transmitted to the pixel circuit PCm can be effectively reduced, and the expansion of the peripheral area PA which is a non-display area can be reduced or prevented.

[0125] The thickness of the first bridge wire BR1 in the first direction (e.g., the x direction or the -x direction) may be greater than the thickness of the first data line DL1 in the first direction (e.g., the x direction or the -x direction). The thickness of the first bridge wire BR1 may be greater than the thickness of the first data line DL1, and therefore, an increased capacitor may be formed between the first bridge wire BR1 and the first data line DL1. Therefore, the load of the data signal transmitted to the pixel circuit PCm may be effectively reduced, and the expansion of the peripheral area PA which is a non-display area may be reduced or prevented. However, the present disclosure is not limited thereto. The thickness of the first bridge wire BR1 in the first direction may be the same as or substantially the same as the thickness of the first data line DL1 in the first direction.

[0126] Figure 7 is a schematic plan view of a display device 10 according to one or more embodiments. Figure 8 yes Figure 7 Schematic enlarged plan view of area A. In detail, Figure 8 yes Figure 7 Schematic enlarged view of a portion of a third data line DL3, a second bridge line BR2, and a third bridge line BR3.

[0127] Reference Figure 7 and Figure 8 , the display device 10 may have a circular shape. In other words, the display area DA of the display device 10 may have a circular shape. The peripheral area PA may be arranged to surround at least a portion of the display area DA having a circular shape.

[0128] The third data line DL3 extending in the second direction (e.g., the y direction or the -y direction) may be arranged in the display area DA having a circular shape. The second bridge line BR2 may be arranged to be separated from the third data line DL3 in the first direction (e.g., the x direction or the -x direction), and may extend in the second direction. The third data line DL3 and the second bridge line BR2 may be connected to each other. In detail, one end of the third data line DL3 may be connected to one end of the second bridge line BR2 adjacent thereto. The third data line DL3 and the second bridge line BR2 may be positioned on (or at) the same layer as each other, and may include the same material as each other.

[0129] According to one or more embodiments, a third bridge line BR3 connected to one end of the third data line DL3 and extending in the first direction may be arranged in the display area DA. The third bridge line BR3 and the third data line DL3 may be positioned on (or at) different layers from each other and may be connected to each other through a contact hole.

[0130] The capacitor may be formed between the third data line DL3 and the second and third bridge lines BR2 and BR3, and thus, the power transmitted to the pixel circuit PCm (see FIG. 1 ) may be reduced. Figure 1 ) and the expansion of the peripheral area PA which is a non-display area can be reduced or prevented.

[0131] According to one or more embodiments, the thickness of the second bridge wire BR2 in the first direction may be greater than the thickness of the third data line DL3 in the first direction. In addition, the thickness of the third bridge wire BR3 in the second direction may be greater than the thickness of the third data line DL3 in the first direction. The thickness of the second bridge wire BR2 and the thickness of the third bridge wire BR3 may be greater than the thickness of the third data line DL3, and therefore, an increased capacitor may be formed between the third data line DL3 and the second bridge wire BR2 and the third bridge wire BR3. Therefore, the load of the data signal transmitted to the pixel circuit PCm can be effectively reduced, and the expansion of the peripheral area PA which is a non-display area can be reduced or prevented. However, the present disclosure is not limited thereto. The thickness of the second bridge wire BR2 in the first direction may be the same or substantially the same as the thickness of the third data line DL3 in the first direction. The thickness of the third bridge wire BR3 in the second direction may be the same or substantially the same as the thickness of the third data line DL3 in the first direction.

[0132] Fig. 9 is a schematic plan view of a display device 10 according to one or more embodiments. Fig.10 yes Fig. 9 Schematic enlarged plan view of area B.

[0133] Reference Fig. 9 and Fig.10 , according to the corresponding Figure 7 and Figure 8 In one or more embodiments, a fourth bridge line BR4 connected to the third bridge line BR3 and extending in the second direction (e.g., the y direction or the -y direction) may be additionally arranged in the display area DA. The fourth bridge line BR4 may be arranged to be separated from the third data line DL3 in the first direction (e.g., the x direction or the -x direction). In addition, the third data line DL3 may be arranged between the second bridge line BR2 and the fourth bridge line BR4.

[0134] The third bridge wire BR3 and the fourth bridge wire BR4 may be positioned on (or at) different layers from each other. The third bridge wire BR3 and the fourth bridge wire BR4 may be connected to each other through a contact hole. However, the fourth bridge wire BR4 and the third data line DL3 may be positioned on (or at) the same layer as each other and may include the same material as each other. In detail, the third data line DL3, the second bridge wire BR2, and the fourth bridge wire BR4 may be positioned on (or at) the same layer as each other and may include the same material as each other.

[0135] According to one or more embodiments, not only capacitors between the third data line DL3 and the second and third bridge lines BR2 and BR3 but also capacitors between the third data line DL3 and the fourth bridge line BR4 may be formed. Therefore, the load of the data signal transmitted to the pixel circuit PCm may be effectively reduced, and the expansion of the peripheral area PA which is a non-display area may be reduced or prevented.

[0136] Fig.11 is a schematic plan view of a display device 10 according to one or more embodiments. Fig.12 yes Fig.11 Schematic enlarged plan view of area C.

[0137] Reference Fig.11 and Fig.12 , according to the corresponding Figure 7 and Figure 8 According to one or more embodiments, a fifth bridge line BR5 connected to the other end of the third data line DL3 and extending in the first direction (e.g., the x direction or the −x direction) may be further provided in the display area DA. The fifth bridge line BR5 may be positioned on (or at) a different layer from the third data line DL3, and the fifth bridge line BR5 and the third data line DL3 may be connected to each other through a contact hole.

[0138] Not only capacitors can be formed between the third data line DL3 and the second and third bridge lines BR2 and BR3, but also capacitors can be formed between the third data line DL3 and the fifth bridge line BR5. Therefore, the voltage transmitted to the pixel circuit PCm (see Figure 1 ) and the expansion of the peripheral area PA which is a non-display area can be reduced or prevented.

[0139] In the case of a display device having an amorphous shape, a capacitor is formed by separately providing a line in some areas to reduce the load of a data signal transmitted to the pixel circuit PCm. When the capacitor is formed by separately providing a line in some areas, the peripheral area PA which is a non-display area increases, and the ratio of the display area DA for realizing display relative to the display device is reduced.

[0140] According to an embodiment, branch lines BL and bridge lines (eg, Figure 5 The first bridge line BR1 in the embodiment of the present invention is connected to the first data line DL1 and the branch line BL and the bridge line (eg, Figure 5 Therefore, a load of a data signal transmitted to the pixel circuit PCm can be reduced, and expansion of the peripheral area PA which is a non-display area can be reduced or prevented.

[0141] As described above, according to one or more of the above embodiments, a display device with improved reliability and quality may be realized. However, the scope of the present disclosure is not limited to these effects as described above.

[0142] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of aspects within each embodiment should generally be considered applicable to other similar aspects in other embodiments. Although one or more embodiments have been described with reference to the drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims, with their functional equivalents to be included therein.

Claims

1. A display device, comprising: a substrate including a display area and a peripheral area surrounding at least a portion of the display area in a plan view; a first data line, the first data line being in the display area and extending in a second direction; a second data line that is separated from the first data line in a first direction crossing the second direction, extends in the second direction, and has a length greater than that of the first data line; as well as A branch line is connected to the first data line and protrudes from the first data line in the first direction.

2. The display device according to claim 1, wherein: The branch lines include a first branch line extending in the second direction and a second branch line connecting the first branch line to the first data line and extending in the first direction.

3. The display device according to claim 1, wherein: The first data line and the branch line are at the same layer and include the same material.

4. The display device according to claim 1, further comprising a first bridge line separated from the first data line in the first direction and extending in the second direction, in, The first data line and the first bridge line are connected to each other.

5. The display device according to claim 4, wherein: One end of the first bridge line is connected to one end of the first data line.

6. The display device according to claim 4, wherein: The first data line and the first bridge line are at the same layer and include the same material.

7. The display device according to claim 4, wherein: A thickness of the first bridge line in the first direction is greater than a thickness of the first data line in the first direction.

8. A display device, comprising: a substrate including a display area having a circular shape and a peripheral area surrounding at least a portion of the display area in a plan view; a third data line, the third data line being arranged in the display area and extending in a second direction; as well as A second bridge line is separated from the third data line in a first direction crossing the second direction, extends in the second direction, and is connected to the third data line.

9. The display device according to claim 8, wherein: One end of the third data line is connected to one end of the second bridge line.

10. The display device according to claim 8, wherein: The third data line and the second bridge line are at the same layer and include the same material.

11. The display device according to claim 8, wherein: A thickness of the second bridge line in the first direction is greater than a thickness of the third data line in the first direction. 12 . The display device of claim 8 , further comprising a third bridge line connected to a first end of the third data line and extending in the first direction.

13. The display device according to claim 12, wherein: The third bridge line and the third data line are at different corresponding layers.

14. The display device according to claim 12, wherein: A thickness of the third bridge line in the second direction is greater than a thickness of the third data line in the first direction. 15 . The display device of claim 12 , further comprising a fourth bridge line separated from the third data line in the first direction, extending in the second direction and connected to the third bridge line.

16. The display device according to claim 15, wherein: The third data line is disposed between the second bridge line and the fourth bridge line.

17. The display device according to claim 15, wherein: The third bridge line and the fourth bridge line are at different respective layers.

18. The display device according to claim 15, wherein: The fourth bridge line and the third data line are at the same layer and include the same material. 19 . The display device of claim 15 , further comprising a fifth bridge line connected to the second end of the third data line and extending in the first direction.

20. The display device according to claim 19, wherein: The fifth bridge line and the third data line are at different corresponding layers.

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