Silicon wafer texturing pretreatment liquid, silicon wafer texturing pretreatment method, silicon wafer texturing method and application of silicon wafer texturing pretreatment liquid and silicon wafer texturing method

Abstract

The embodiment of the invention provides a silicon wafer texturing pretreatment liquid, a silicon wafer texturing pretreatment method, a silicon wafer texturing method and application thereof, the silicon wafer texturing pretreatment liquid comprises a first treatment liquid and a second treatment liquid, the first treatment liquid is a mixed solution of a first metal salt, hydrofluoric acid and nitric acid, and the second treatment liquid is a mixed solution of a second metal salt, hydrofluoric acid and nitric acid. The second treating fluid is a mixed solution of second metal salt, hydrofluoric acid and nitric acid; in the first treatment liquid, the concentration of first metal salt is 0.01-0.1 g / L, the concentration of hydrofluoric acid is 3-15 wt%, and the concentration of nitric acid is 5-20 wt%; in the second treatment liquid, the concentration of the second metal salt is 0.02-0.08 g / L, the mass concentration of hydrofluoric acid is 5-30 wt%, and the mass concentration of nitric acid is 10-20 wt%. The silicon wafer with the porous microstructure prepared by the embodiment of the invention not only provides a plurality of texturing points for alkaline etching in subsequent texturing treatment, but also can change reaction kinetics, and the outer layer of the porous silicon is gradually peeled off within an extremely short time and at a relatively low temperature, and finally grows into uniform pyramid-shaped textures.

Description

Technical Field

[0001] The present application relates to the technical field of silicon wafer texturing, and in particular to a silicon wafer texturing pretreatment liquid, a silicon wafer texturing pretreatment method, a silicon wafer texturing method and applications thereof. Background Art

[0002] As the global demand for clean energy increases, solar cells, as a green, renewable clean energy, have gradually become a research hotspot. At present, the conversion efficiency of solar cells has made great breakthroughs, but there are still many problems in the production process. For example, after the original silicon wafer is cut, it will form polycrystalline domains, fracture domains, elastic distortion domains, and matrix silicon regions, which are generally removed by pre-cleaning and texturing processes.

[0003] Texturing mainly utilizes the anisotropic corrosion characteristics of silicon wafers in low-concentration alkali solution, that is, the corrosion rate of silicon on the 110 and 100 crystal planes is much greater than the corrosion rate of the 111 crystal plane. The specific texturing process is: the silicon wafer undergoes a pre-cleaning process to remove organic dirt and metal impurities on the surface of the silicon wafer, and at the same time removes the mechanical damage layer generated by the silicon wafer wire cutting process, thereby reducing the recombination center; then, under the synergistic effect of alkali and additives, it is immersed at a high temperature of 82°C for about 7 minutes, thereby forming an uneven velvet surface, i.e., a pyramid, on the surface of the silicon wafer, resulting in a long time and high temperature in the current texturing tank process, and there are problems of low texturing efficiency and high texturing cost. Summary of the invention

[0004] The embodiments of the present application provide a silicon wafer texturing pretreatment liquid, a silicon wafer texturing pretreatment method, a silicon wafer texturing method and applications thereof, aiming to solve the problems of low texturing efficiency and high texturing cost existing in traditional texturing technology.

[0005] In a first aspect, an embodiment of the present application provides a silicon wafer texturing pretreatment liquid, including a first treatment liquid and a second treatment liquid, wherein the first treatment liquid is a mixed solution of a first metal salt, hydrofluoric acid and nitric acid, and the second treatment liquid is a mixed solution of a second metal salt, hydrofluoric acid and nitric acid; In the first treatment solution, the concentration of the first metal salt is 0.01-0.1 g / L, the concentration of hydrofluoric acid is 3wt%-15wt%, and the concentration of nitric acid is 5wt%-20wt%; In the second treatment liquid, the concentration of the second metal salt is 0.02-0.08 g / L, the mass concentration of hydrofluoric acid is 5wt%-30wt%, and the mass concentration of nitric acid is 10wt%-20wt%.

[0006] Optionally, the first metal salt includes one of silver nitrate and silver fluoride, and the second metal salt includes one of copper nitrate, copper chloride and copper sulfate.

[0007] In a second aspect, an embodiment of the present application provides a silicon wafer texturing pretreatment method, the method comprising: A first metal salt, hydrofluoric acid and nitric acid are mixed to obtain a first treatment solution, wherein the concentration of the first metal salt is 0.01-0.1 g / L, the concentration of the hydrofluoric acid is 3 wt%-15 wt%, and the concentration of the nitric acid is 5 wt%-20 wt%; A second metal salt, hydrofluoric acid and nitric acid are mixed to obtain a second treatment solution, wherein the concentration of the second metal salt is 0.02-0.08 g / L, the mass concentration of the hydrofluoric acid is 5wt%-30wt%, and the mass concentration of the nitric acid is 10wt%-20wt%; placing the silicon wafer in the first treatment solution for treatment; Washing the silicon wafer treated with the first treatment solution; The washed silicon wafer is placed in the second pretreatment solution for catalytic etching to obtain a silicon wafer with a porous microstructure.

[0008] Optionally, before placing the original silicon wafer in the first treatment solution for treatment, the process further includes: The silicon wafer is placed in a mixed solution of 0.25wt%-0.5wt% NaOH and 1.5wt%-3.0wt% H2O2 for cleaning at a cleaning temperature of 60-70°C and a cleaning time of 180-220s.

[0009] Optionally, in the first treatment solution, the concentration of the first metal salt is 0.01-0.03 g / L, the concentration of hydrofluoric acid is 5wt%-10wt%, and the concentration of nitric acid is 10wt%-15wt%.

[0010] Optionally, in the second treatment solution, the concentration of the second metal salt is 0.04-0.06 g / L, the concentration of hydrofluoric acid is 10wt%-25wt%, and the concentration of nitric acid is 15wt%-16wt%.

[0011] Optionally, in the step of placing the silicon wafer in the first treatment liquid for treatment: The processing temperature is 25-35°C and the processing time is 50-70s.

[0012] Optionally, in the step of placing the washed silicon wafer in the second pretreatment liquid for catalytic etching: The catalytic etching temperature is 25-35° C., and the catalytic etching time is 110-130 s.

[0013] In a third aspect, an embodiment of the present application provides a silicon wafer texturing method, including the above-mentioned silicon wafer texturing pretreatment method. After the silicon wafer texturing pretreatment method, the silicon wafer texturing method further includes: The catalytically etched silicon wafer is placed in NH3·H2O and H2O2 for cleaning at a temperature of 60-70°C and a cleaning time of 160-200s; The cleaned silicon wafer is placed in a texturing bath containing 0.5wt%-1.5wt% NaOH and 5wt%-10wt% androstenedione for etching at an etching temperature of 50-70°C and an etching time of 200-280s.

[0014] In a fourth aspect, an embodiment of the present application provides an application of a silicon wafer texturing product obtained according to the above-mentioned silicon wafer texturing method in a solar cell.

[0015] The above technical solution adopted in the embodiment of the present application may have the following advantages: 1. The silicon wafer is treated with a first treatment solution containing a low concentration of a first metal salt and then treated with a second treatment solution containing a high concentration of a second metal salt, so that the silicon wafer forms a porous microstructure under the metal catalysis of a mixed solution of AgNO3 / Cu(NO3)2, HF and HNO3. The aspect ratio of the obtained porous silicon is about 5, the diameter is 100-200 nm, and the depth is 500-1000 nm. The main reason is that Ag + / Ag、Cu 2+ / Cu has a stronger electronegativity than silicon, and then Ag + , Cu 2+ They will be reduced and grow into Ag and Cu nanoparticles (Ag / Cu NPs). The potential difference between the upper and lower surfaces of Ag / Cu NPs and the influence of the built-in electric field and solution environment lead to the oxidation of the single crystal under the Ag / Cu NPs and the corrosion of a large number of porous structures, thus obtaining a porous silicon wafer. In addition, these Ag / Cu NPs are not always oriented vertically downward along the (100) crystal surface, resulting in spiral etching and lateral etching of the silicon wafer, making the porous structure of the silicon wafer more dense and uniform.

[0016] 2. After the treatment, a second treatment liquid containing copper metal salt is used for treatment. Copper acts as a catalyst. During the process of electron transfer from silicon, oxidation of silicon occurs in the part in contact with silver and copper. The oxidized silicon is dissolved and removed by HF, which is beneficial to further improve the metal-catalyzed chemical etching effect.

[0017] 3. The porous microstructured silicon wafer prepared in the embodiment of the present application not only provides many velvet removal points for alkaline etching in the subsequent velvet making process, but also can change the reaction kinetics. In an extremely short time and at a relatively low temperature, the outer layer of the porous silicon gradually peels off and eventually grows into a uniform pyramid-shaped texture.

[0018] 4. The nucleation of the pyramid structure obtained after the texturing in the embodiment of the present application starts from the porous structure of the metal catalytic etching. The surface of the silicon wafer evolves from the porous structure to a partially inverted pyramid, and finally to a completely covered upright pyramid as the alkaline etching time increases. This is significantly different from the mechanism of nucleation and growth of pyramids on the surface of the current texturing process. The traditional technology mainly relies on nucleating agents in additives. However, the present application realizes the high surface chemical state of the porous silicon structure, and thus can quickly (200-280s) and low temperature (50-70°C) realize the alkaline texture of the texturing surface in the subsequent texturing treatment. The obtained pyramid structure is more independent and neat, with less broken wool. When matched with the subsequent coating process and LECO technology, it is beneficial to the passivation ability and contact improvement, thereby improving the open circuit voltage and fill factor. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0020] Figure 1 This is a flow chart of a silicon wafer texturing pretreatment method provided in one embodiment of the present application; Figure 2 This is a rendering of the effect of a silicon wafer texturing method provided in one embodiment of the present application. DETAILED DESCRIPTION

[0021] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0022] It should be understood that when an element or layer is referred to as "on", "under", "adjacent to", "connected to" or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "under", "directly adjacent to", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section must be present in the present disclosure.

[0023] In this application, unless otherwise clearly specified and limited, the terms "set", "install", "connect", "connect", "fix" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0025] To facilitate those skilled in the art to understand the technical solutions provided in the embodiments of the present application, the relevant technologies are described below: The applicant found that the texturing process mainly utilizes the anisotropic corrosion characteristics of silicon wafers in low-concentration alkali solution, that is, the corrosion rate of silicon on the (110) and (100) crystal planes is much greater than the corrosion rate of the 111 crystal plane. The specific texturing process is: the silicon wafer undergoes a pre-cleaning process to remove organic dirt and metal impurities on the surface of the silicon wafer, and at the same time removes the mechanical damage layer generated by the silicon wafer wire cutting process, thereby reducing the recombination center; then, under the synergistic effect of alkali and additives, it is immersed at a high temperature of 82°C for about 7 minutes, thereby forming an uneven velvet surface, i.e., a pyramid, on the surface of the silicon wafer, resulting in a long time and high temperature in the current texturing tank process, and there are problems of low texturing efficiency and high texturing cost.

[0026] In view of the above problems, the texturing pretreatment solution proposed in the embodiment of the present application uses a mixed solution of AgNO3 / Cu(NO3)2, HF and HNO3 to form porous silicon. The main mechanism is that Ag + / Ag、Cu 2+ / Cu has a stronger electronegativity than silicon, and then Ag + , Cu 2+ will be reduced and grow into Ag and Cu nanoparticles (Ag / Cu NPs). The potential difference between the upper and lower surfaces of Ag / Cu NPs and the influence of the built-in electric field and solution environment lead to the oxidation of single crystals under Ag / Cu NPs and the corrosion of a large number of porous structures; in addition, these Ag / CuNPs are not always oriented vertically downward along the (100) crystal surface, resulting in spiral etching and lateral etching of the silicon wafer, which makes the porous structure of the silicon wafer more dense and uniform. In addition, the obtained porous microstructured silicon wafer not only provides many velvet exit points for alkaline etching in the subsequent texturing process, but also changes the reaction kinetics, so that the subsequent texturing process can form a uniform pyramid-shaped texture in a very short time and at a lower temperature.

[0027] Hereinafter, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. It should be noted that these exemplary embodiments can be implemented in many different forms and should not be construed as being limited to the embodiments described herein.

[0028] See also Figure 1 The present application embodiment provides a silicon wafer texturing pretreatment method, comprising steps S101 to S105, wherein: Step 101: Mix a first metal salt, hydrofluoric acid and nitric acid to obtain a first treatment solution; It should be noted that in the configured first treatment solution, the concentration of the first metal salt is 0.01-0.1 g / L, the concentration of hydrofluoric acid is 3wt%-15wt%, and the concentration of nitric acid is 5wt%-20wt%; In some embodiments, the first metal salt includes at least one of silver nitrate and silver fluoride, and the concentration of the first metal salt must be lower than that of the second metal salt. If the concentration of the first metal salt is too low, the metal catalytic etching effect of the first treatment solution will be affected. If the concentration of the first metal salt is too high, the metal catalytic etching effect of the second treatment solution will be affected. By controlling the concentration of the first metal salt in a suitable concentration range of 0.01-0.1 g / L, Ag can be + It is reduced and grows into Ag nanoparticles (Ag NPs), thereby achieving initial corrosion of the silicon wafer.

[0029] In some embodiments, the concentration of the first metal salt is preferably 0.01-0.03 g / L, the concentration of hydrofluoric acid is preferably 5wt%-10wt%, and the concentration of nitric acid is preferably 10wt%-15wt%.

[0030] Step 102: Mix a second metal salt, hydrofluoric acid and nitric acid to obtain a second treatment solution, in the second treatment solution; It should be noted that in the configured second treatment solution, the concentration of the second metal salt is 0.02-0.08 g / L, the mass concentration of hydrofluoric acid is 5wt%-30wt%, and the mass concentration of nitric acid is 10wt%-20wt%.

[0031] In some embodiments, the second metal salt includes one of copper nitrate, copper chloride, and copper sulfate. If the concentration of the second metal salt is too low, the reaction rate is slow and the size of the porous structure formed is small. If the concentration of the second metal salt is too high, the reaction rate is fast and the porous structure may be uneven. By controlling the concentration of the second metal salt in a suitable range, i.e., 0.01-0.03 g / L, the Cu 2+ It will be reduced and grow into Cu nanoparticles, and under the combined action of the potential difference between the upper and lower surfaces of the Cu nanoparticles, the built-in electric field and the solution environment, the single crystal under the Ag / Cu NPs will be oxidized and a large number of porous structures will be corroded, thus ensuring the formation of porous silicon.

[0032] In some embodiments, the concentration of the second metal salt is preferably 0.04-0.06 g / L, the concentration of hydrofluoric acid is preferably 10 wt %-25 wt %, and the concentration of nitric acid is preferably 15 wt %-16 wt %.

[0033] Step 103: placing the silicon wafer in a first treatment liquid for treatment; In some embodiments, the treatment temperature of the first treatment liquid is 25-35°C, and the treatment time is 50-70s. By way of example, the treatment temperature of pretreatment using the first treatment liquid can be 25°C, 30°C, 35°C, etc., and the treatment time of pretreatment using the first treatment liquid can be 50s, 60s, 70s, etc.

[0034] Step 104: washing the silicon wafer treated with the first treatment solution; It should be pointed out that in order to avoid the influence of excessive silver ions on the subsequent catalytic etching effect of copper ions, after treatment with the first treatment solution containing silver ions, the silicon wafer needs to be washed with deionized water to remove some or even all of the residual silver ions.

[0035] Step 105: placing the washed silicon wafer in a second pretreatment solution for catalytic etching to obtain a silicon wafer with a porous microstructure.

[0036] In some embodiments, the catalytic etching temperature of the second treatment liquid for catalytic etching is 25-35°C, and the catalytic etching time is 110-130s. By way of example, the catalytic etching temperature for pretreatment with the second treatment liquid can be 25°C, 30°C, 35°C, etc., and the catalytic etching time for pretreatment with the second treatment liquid is 110s, 120s, 130s, etc.

[0037] In addition, in some embodiments, before the original silicon wafer is placed in the first treatment liquid for treatment, the silicon wafer is also placed in a mixed solution of 0.25wt%-0.5wt% NaOH and 1.5wt%-3.0wt% H2O2 for cleaning, the cleaning temperature is 60-70°C, the cleaning time is 180-220s, to remove organic matter and part of the mechanical damage layer on the silicon surface, and then washed with water, and the washed silicon wafer is placed in the first treatment liquid for pretreatment.

[0038] In summary, the porous silicon prepared in the present application not only provides many velvet-exiting points for alkaline etching, but also can change the reaction kinetics, so that the outer layer of the porous silicon can be gradually peeled off in a very short time and at a low temperature during the velvet treatment, and finally grow into a uniform pyramid-shaped texture.

[0039] The embodiment of the present application also provides a silicon wafer texturing method. After the silicon wafer texturing pretreatment method, the method comprises the following steps: Step S201: placing the catalytically etched silicon wafer in 11wt%-14wt% NH3·H2O and 15wt%-20 wt% H2O2 for cleaning at a temperature of 60-70°C for a cleaning time of 160-200s; It should be noted that the purpose of this step is to remove metal residues on the surface of the silicon wafer. The cleaning temperature can be 60°C, 65°C, 70°C, etc., and the cleaning time can be 160s, 180s, 200s, etc.

[0040] Step S202: placing the cleaned silicon wafer in a texturing bath containing 0.5wt%-1.5wt% NaOH and 5wt%-10wt% androstenedione for etching at an etching temperature of 50-70° C. for an etching time of 200-280 s; After the pyramid velvet structure is prepared in this step, it is necessary to wash it with water. In addition, the final pyramid size is 1.65-1.70um in width, 1.0±0.2um in height, the velvet quantity is maintained above 20w, the specific surface area is about 1.25, and the reflectivity is maintained at 9%-10%.

[0041] In addition, by pre-treating with the first treatment liquid and the second treatment liquid, the prepared porous silicon not only provides many velvet exit points for alkaline etching, but also can change the reaction kinetics, so that during the actual velvet treatment in this step, the etching temperature is lower and the etching time is shorter.

[0042] Step S203: placing the silicon wafer in a mixed solution containing 0.25wt%-0.5wt% NaOH and 1.5wt%-3.0wt% H2O2 for cleaning; The purpose of this step is to remove residual organic matter through alkali washing, and the silicon wafer needs to be washed with water after alkali washing.

[0043] Step S204: placing the silicon wafer in a mixture of 10wt%-13wt% HF and 60wt%-65wt% HNO3 at 30°C for 3-7s, and then washing with water; Treatment with a mixture of HF and can smooth the bottom of the pyramid structure.

[0044] Step S205: immersing the silicon wafer in an acid tank containing a mixed solution of 2wt%-5wt% HF and HCl, and then washing with water; In this step, the silicon wafer is pickled to remove the oxide layer and some metal ion impurities.

[0045] Step S206: placing the silicon wafer in a 70-75° C. hot water bath for 15-25 seconds; In actual operation, this step requires entering the slow-lifting tank, and the robot slowly lifts the flower basket to dehydrate the surface of the silicon wafer to prevent water marks and lamination on the surface.

[0046] Step S207: drying the silicon wafer at high temperature, the drying temperature is 80-90° C., and the drying time is 650-750 seconds.

[0047] In summary, compared with the prior art, this application has the following advantages: 1. The pyramid structure prepared in the embodiment of the present application is more independent, highly uniform and concentrated, which is beneficial to the improvement of passivation ability and contact when matched with the back-end passivation process and LECO technology, thereby increasing the open circuit voltage and fill factor, and finally the battery cell has a gain of about 0.03-0.05%.

[0048] 2. The embodiments of the present application prepare denser and smaller submicron pyramids, so that the silicon wafer prepared by the new process has slight improvement in short-wavelength absorption, which is beneficial to increase the possibility of short-wavelength photons being refracted into silicon and is beneficial to the improvement of short-circuit current.

[0049] 3. The nucleation of the pyramids involved in the embodiments of the present application starts from the porous structure of metal catalytic etching. The wafer surface evolves from the porous structure to partially inverted pyramids, and finally to completely covered upright pyramids as the alkaline etching time increases. The high surface chemical state of the porous silicon structure is the fundamental reason why the embodiments of the present application can achieve fast and low-temperature alkaline texturing.

[0050] The following specific examples further illustrate the present application, but should not be construed as limiting the present application. Without departing from the spirit and substance of the present application, modifications or replacements made to the methods, steps or conditions of the present application are within the scope of the present application.

[0051] [Example 1] (1) silver nitrate, hydrofluoric acid and nitric acid are mixed to obtain a first treatment solution, wherein the concentration of silver nitrate is 0.01 g / L, the concentration of hydrofluoric acid is 3 wt %, and the concentration of nitric acid is 5 wt %; (2) mixing copper nitrate, hydrofluoric acid and nitric acid to obtain a second treatment solution, wherein the concentration of copper nitrate is 0.02 g / L, the mass concentration of hydrofluoric acid is 5 wt %, and the mass concentration of nitric acid is 10 wt %; (3) The silicon wafer was placed in a mixed solution of 0.35wt% NaOH and 2.0wt% H2O2 for cleaning at a temperature of 65°C for 200s. (4) placing the silicon wafer in the first treatment solution for treatment for 60 seconds at a treatment temperature of 30° C. (5) washing the silicon wafer treated with the first treatment solution; (6) placing the washed silicon wafer in the second pretreatment solution for catalytic etching to obtain a silicon wafer with a porous microstructure, the catalytic etching time is 120 seconds, and the catalytic etching time is 30° C.; (7) The catalytically etched silicon wafer was placed in 13wt% NH3·H2O and 18wt% H2O2 for cleaning at a temperature of 65°C for 180s. (8) The cleaned silicon wafer was placed in a texturing bath containing 1 wt% NaOH and 7.5 wt% androstenedione for etching at a temperature of 60 °C and an etching time of 240 s; (9) The silicon wafer was placed in a mixed solution containing 0.35wt% NaOH and 2.0wt% H2O2 for cleaning, and then washed with water; (10) Place the silicon wafer in a mixture of 12wt% HF and 62wt% HNO3 at 30°C for 3-7s and then wash with water; (11) Immersing the silicon wafer in an acid tank containing a mixed solution of 3.5 wt% HF and HCl, and then washing with water; (12) Place the silicon wafer in a 75°C hot water bath for 20 seconds; (13) Dry the silicon wafer at a high temperature of 85°C for 700 seconds.

[0052] [Example 2] - [Example 7] The scheme of Example 2-7 is basically the same as that of Example 1, except that the ratio of the first treatment liquid in step (1), the ratio of the second treatment liquid in step (2), the treatment temperature of the first treatment liquid in step (4), the treatment time of the first treatment liquid in step (6), the etching time in step (8), and the etching temperature in step (8) are adjusted, as shown in Table 1 below: Table 1

[0053] In order to more clearly illustrate the technical effects of the embodiments of the present application, the present application also points out the silicon wafer texturing methods of [Comparative Example 1] to [Comparative Example 6].

[0054] [Comparative Example 1] - [Comparative Example 4] Comparative Examples 1 to 4 are basically the same as the scheme of Example 1, except that the ratio of the first treatment liquid in step (1), the ratio of the second treatment liquid in step (2), the treatment temperature of the first treatment liquid in step (4), the treatment time of the first treatment liquid in step (6), the etching time in step (8), and the etching temperature in step (8) are adjusted, as shown in Table 2 below: Table 2

[0055] [Comparative Example 5] Comparative Example 5 is substantially the same as Example 1, except that step (1), step (3), step (4) and step (5) are deleted, that is, only the second processing liquid is used to pre-treat the silicon wafer.

[0056] [Comparative Example 6] Comparative Example 6 is substantially the same as Example 1, except that step (2), step (3), step (5) and step (6) are deleted, that is, only the first treatment solution is used to pretreat the silicon wafer.

[0057] The following is a performance test of the silicon wafer texturing products obtained by the silicon wafer texturing method according to Examples 1-7 of the present application and Comparative Examples 1-6, so as to obtain the pyramid height, pyramid width, number of velvet, reflectivity, specific surface area, open circuit voltage, filling factor, and short circuit current of the silicon wafer texturing products. The test results are shown in Table 3 below: Table 3 Performance test results of Examples 1-6 and Comparative Examples 1-6

[0058] Data result analysis: According to the data recorded in Table 3, the pyramid velvet structure prepared in the embodiment of the present application has a pyramid width of 1.65-1.70 um and a pyramid height of 1.0±0.2 um. The process is stable and can meet the production line preparation requirements, while the velvet structure obtained in the comparative example either has a tower width that does not meet the requirements or a tower height that does not meet the requirements; in addition, the number of texturing in the present application is all above 20w, which is significantly higher than the number of texturing in comparative examples 1-6, which means that the embodiment of the present application has a good texturing effect; in addition, the reflectivity of the embodiment of the present application is significantly lower than that of the comparative example, and the lowest can reach 9.14; in addition, the battery prepared in the embodiment of the present application has improvements in open circuit voltage, short-circuit current and fill factor, which means that the solar cell obtained in the embodiment of the present application has good performance.

[0059] In summary, the porous microstructured silicon wafer prepared in the present application not only provides many velvet removal points for the alkaline etching in the subsequent velvet treatment, but also can change the reaction kinetics. In a very short time and at a low temperature, the outer layer of the porous silicon gradually peels off and eventually grows into a uniform pyramid-shaped texture. In addition, Figure 2 It can be seen that by achieving a high surface chemical state of the porous silicon structure, the alkaline texture of the texturing surface can be achieved quickly (200-280s) and at a low temperature (50-70°C) in the subsequent texturing treatment. The resulting pyramid structure is more independent and neat, with less broken hair. When matched with the subsequent coating process and LECO technology, it is beneficial to the passivation ability and contact improvement, thereby improving the open circuit voltage and filling factor.

[0060] The embodiment of the present application also provides an application of a silicon wafer texturing product obtained by the above-mentioned silicon wafer texturing method in a solar cell.

[0061] An embodiment of the present application provides a photovoltaic module (not shown), including a plurality of solar cells connected in series and / or in parallel, wherein at least one solar cell is the above-mentioned perovskite solar cell, and adjacent perovskite solar cells can be connected together by serial welding.

[0062] The embodiment of the present application can provide a photovoltaic system, including the photovoltaic components in any of the above embodiments. The advantages of the above photovoltaic components are also possessed by the photovoltaic system, which will not be repeated here. The above photovoltaic system has a wide range of applications, not only limited to photovoltaic power stations, such as ground power stations, rooftop power stations and water power stations, but also includes various equipment and devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars and solar buildings. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to this, that is to say, the photovoltaic system can be used in all fields where solar energy is required for power generation. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components may form multiple photovoltaic arrays. The photovoltaic array is connected to a junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.

[0063] It should be noted that the terms "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The orientation words "inside" and "outside" refer to the inside and outside relative to the outline of each component itself. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Therefore, the exemplary term "above..." can include both "above..." and "below..." orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used here are interpreted accordingly.

[0064] It should also be noted that "one embodiment", "another embodiment", "embodiment", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Further, when a specific feature, structure or characteristic is described in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0065] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0066] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A silicon wafer texturing pretreatment solution, characterized in that: The method comprises a first treatment liquid and a second treatment liquid, wherein the first treatment liquid is a mixed solution of a first metal salt, hydrofluoric acid and nitric acid, and the second treatment liquid is a mixed solution of a second metal salt, hydrofluoric acid and nitric acid; In the first treatment solution, the concentration of the first metal salt is 0.01-0.1 g / L, the concentration of hydrofluoric acid is 3wt%-15wt%, and the concentration of nitric acid is 5wt%-20wt%; In the second treatment liquid, the concentration of the second metal salt is 0.02-0.08 g / L, the mass concentration of hydrofluoric acid is 5wt%-30wt%, and the mass concentration of nitric acid is 10wt%-20wt%.

2. The silicon wafer texturing pretreatment solution according to claim 1, characterized in that: The first metal salt includes one of silver nitrate and silver fluoride, and the second metal salt includes one of copper nitrate, copper chloride and copper sulfate.

3. A silicon wafer texturing pretreatment method, characterized in that: The method comprises: A first metal salt, hydrofluoric acid and nitric acid are mixed to obtain a first treatment solution, wherein the concentration of the first metal salt is 0.01-0.1 g / L, the concentration of the hydrofluoric acid is 3 wt%-15 wt%, and the concentration of the nitric acid is 5 wt%-20 wt%; A second metal salt, hydrofluoric acid and nitric acid are mixed to obtain a second treatment solution, wherein the concentration of the second metal salt is 0.02-0.08 g / L, the mass concentration of the hydrofluoric acid is 5wt%-30wt%, and the mass concentration of the nitric acid is 10wt%-20wt%; placing the silicon wafer in the first treatment solution for treatment; Washing the silicon wafer treated with the first treatment solution; The washed silicon wafer is placed in the second pretreatment solution for catalytic etching to obtain a silicon wafer with a porous microstructure.

4. The silicon wafer texturing pretreatment method according to claim 3, characterized in that: The placing of the original silicon wafer in the first treatment solution for treatment may also include: The silicon wafer is placed in a mixed solution of 0.25wt%-0.5wt% NaOH and 1.5wt%-3.0wt% H2O2 for cleaning at a cleaning temperature of 60-70°C and a cleaning time of 180-220s.

5. The silicon wafer texturing pretreatment method according to claim 3, characterized in that: In the first treatment solution, the concentration of the first metal salt is 0.01-0.03 g / L, the concentration of hydrofluoric acid is 5wt%-10wt%, and the concentration of nitric acid is 10wt%-15wt%.

6. The silicon wafer texturing pretreatment method according to claim 3, characterized in that: In the second treatment solution, the concentration of the second metal salt is 0.04-0.06 g / L, the concentration of hydrofluoric acid is 10wt%-25wt%, and the concentration of nitric acid is 15wt%-16wt%.

7. The silicon wafer texturing pretreatment method according to claim 3, characterized in that: In the step of placing the silicon wafer in the first treatment liquid for treatment: The processing temperature is 25-35°C and the processing time is 50-70s.

8. The silicon wafer texturing pretreatment method according to claim 3, characterized in that: In the step of placing the washed silicon wafer in the second pretreatment solution for catalytic etching: The catalytic etching temperature is 25-35° C., and the catalytic etching time is 110-130 s.

9. A method for texturing a silicon wafer, characterized in that: The method for pretreating silicon wafer texturing comprises the method according to any one of claims 3 to 6, and after the method for pretreating silicon wafer texturing, the method for pretreating silicon wafer texturing further comprises: The catalytically etched silicon wafer is placed in NH3·H2O and H2O2 for cleaning at a temperature of 60-70°C and a cleaning time of 160-200s; The cleaned silicon wafer is placed in a texturing bath containing 0.5wt%-1.5wt% NaOH and 5wt%-10wt% androstenedione for etching at an etching temperature of 50-70°C and an etching time of 200-280s.

10. Application of a silicon wafer texturing product obtained by the silicon wafer texturing method according to claim 9 in a solar cell.

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