Multi-chip test method and system, semiconductor test device and computer program product

Abstract

The invention is suitable for the technical field of chip testing, and provides a multi-chip testing method and system, a semiconductor testing device and a computer program product, and the method comprises the steps: detecting that a target chip in a plurality of chips to be tested outputs target data, and transmitting a target interrupt signal corresponding to the target chip to a main control module; after the main control module completes one-time collection of target data based on the target interrupt signal, an interrupt completion signal corresponding to the target interrupt signal is written into an interrupt completion file; taking out interrupt completion signals from the interrupt completion file according to a preset sequence under the condition that the communication module is idle; and performing communication configuration on the communication module according to the interruption completion signal, so that the main control module sends corresponding target data to an upper computer by controlling the communication module. According to the method provided by the invention, low-cost and efficient data acquisition and transmission in the multi-chip test are realized, and meanwhile, the expansibility of the multi-chip test is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor testing technology, and in particular, relates to a multi-chip testing method, system, semiconductor testing device and computer program product. Background Art

[0002] Under the current fingerprint chip testing technology framework, when faced with the need to test multiple chips simultaneously, the internal logic design of the system usually requires the ability to support the simultaneous operation of multiple network transmission modules. The purpose of this design is to ensure that the image data of each chip can be independently and undisturbedly transmitted to the corresponding host computer for display and processing. However, such a configuration often requires external connections to multiple personal computers (PCs) and additional network interface cards to effectively collect and transmit these image data. This approach inevitably brings higher detection costs and obvious waste of resources.

[0003] Furthermore, as the number of fingerprint chips that need to be tested increases, the limitations of the existing system architecture in terms of processing power begin to emerge. Since the internal logic has limited support for running multiple modules simultaneously, the scalability of the entire system is greatly restricted. In this case, as the scale of testing grows, the system will find it difficult to maintain the original work efficiency and service quality, thus affecting the overall test process and the reliability of the results. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a multi-chip testing method, system, semiconductor testing device and computer program product to achieve low-cost and efficient data collection and transmission in multi-chip testing, while improving the scalability of multi-chip testing.

[0005] A first aspect of an embodiment of the present application provides a multi-chip testing method, which is applied to an MCU module. The method includes:

[0006] If it is detected that a target chip among the multiple chips to be tested outputs target data, a target interrupt signal corresponding to the target chip is sent to the main control module; the target interrupt signal is used to instruct the main control module to collect the target data once;

[0007] After the main control module completes the acquisition of target data once based on the target interrupt signal, an interrupt completion signal corresponding to the target interrupt signal is written into an interrupt completion file;

[0008] When the communication module is idle, the interrupt completion signal is taken out from the interrupt completion file in a preset order;

[0009] The communication module is configured for communication according to the interrupt completion signal, so that the main control module sends the corresponding target data to the host computer by controlling the communication module.

[0010] In an implementation of the first aspect, the method further includes:

[0011] By polling the flag register of each chip to be tested among the multiple chips to be tested, it is detected whether a target chip among the multiple chips to be tested outputs target data according to the value in the flag register.

[0012] In an implementation of the first aspect, the method further includes:

[0013] Before the test begins, configure communication parameters for each chip to be tested; the communication parameters include a communication port and a data storage address;

[0014] The communication module is configured for communication according to the interrupt completion signal, so that the main control module sends corresponding target data to the host computer by controlling the communication module, including:

[0015] According to the interrupt completion signal, the data reading address of the communication module is configured to be the data storage address of the target chip corresponding to the interrupt completion signal, and the communication port of the communication module is configured to be the communication port of the target chip corresponding to the interrupt completion signal.

[0016] In an implementation of the first aspect, the method further includes:

[0017] The working parameters of each chip to be tested are set; the working parameters are used to instruct the chip to be tested to output target data in a preset format.

[0018] A second aspect of an embodiment of the present application provides a multi-chip testing method, which is applied to a main control module. The method includes:

[0019] After receiving the target interrupt signal sent by the MCU module, completing the collection of target data based on the target interrupt signal; the target data is output by the target chip among the multiple chips to be tested;

[0020] Based on the communication configuration of the communication module performed by the MCU module according to the interrupt completion signal, the communication module is controlled to send the corresponding target data to the host computer.

[0021] In an implementation of the second aspect, completing the acquisition of target data based on the target interrupt signal includes:

[0022] Determine a corresponding target chip according to the target interrupt signal;

[0023] Collecting target data output by the target chip;

[0024] The target data is stored in the data storage space corresponding to the target chip.

[0025] In an implementation of the second aspect, the communication configuration of the communication module performed by the MCU according to the interrupt completion signal, controlling the communication module to send corresponding target data to the host computer, includes:

[0026] Control the communication module to read the target data from the data storage address of the target chip corresponding to the interrupt completion signal;

[0027] The control communication module sends the target data to the host computer through the communication port of the target chip corresponding to the interrupt completion signal.

[0028] The third aspect of the present application embodiment provides a multi-chip testing system, the system comprising:

[0029] The MCU module is used for sending a target interrupt signal corresponding to the target chip to the main control module after the test starts, if it is detected that a target chip among multiple chips to be tested outputs target data; the target interrupt signal is used to instruct the main control module to collect the target data once; after the main control module completes the collection of target data once based on the target interrupt signal, writing an interrupt completion signal corresponding to the target interrupt signal into an interrupt completion file; when the communication module is idle, taking out the interrupt completion signal from the interrupt completion file in a preset order; and configuring the communication module for communication according to the interrupt completion signal, so that the main control module sends the corresponding target data to the host computer by controlling the communication module;

[0030] The main control module is used to complete the collection of target data based on the target interrupt signal sent by the MCU module after receiving the target interrupt signal; the target data is output by the target chip among the multiple chips to be tested; based on the communication configuration of the communication module performed by the MCU module according to the interrupt completion signal, control the communication module to send the corresponding target data to the host computer.

[0031] The fourth aspect of the application embodiment provides a semiconductor testing device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the semiconductor testing device implements the method described in the first or second aspect above.

[0032] The fifth aspect of the application embodiment provides a computer program product, including a computer program, and when the computer program is run, the method described in the first aspect or the second aspect above is executed.

[0033] The beneficial effect of the first aspect of the embodiment of the present application is: the method provided by the present application outputs a corresponding interrupt signal to the main control module when it is detected that a target chip among multiple chips to be tested outputs target data; instructs the main control module through the interrupt signal to collect the target data once; then after the main control module completes the collection of target data once based on the target interrupt signal, writes an interrupt completion signal corresponding to the target interrupt signal into an interrupt completion file, thereby completing the collection and recording of the target data output by the target chip; when the communication module is idle, the interrupt completion signal is taken out from the interrupt completion file in a preset order, and then the communication module is configured for communication according to the interrupt completion signal, so that the main control module sends the corresponding target data to the host computer by controlling the communication module, thereby completing the sending of the collected target data to the host computer in a preset order, thereby realizing low-cost and efficient data collection and transmission in multi-chip testing, and improving the scalability of multi-chip testing.

[0034] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 This is a schematic diagram of the implementation process of the first multi-chip testing method provided in the embodiment of the present application;

[0037] Figure 2 It is a schematic diagram of the implementation flow of the second multi-chip testing method provided in the embodiment of the present application;

[0038] Figure 3 is a schematic diagram of a multi-chip testing system provided in an embodiment of the present application;

[0039] Figure 4 It is a framework diagram of data collection and transmission for multi-chip testing provided by an embodiment of the present application;

[0040] Figure 5 It is a timing diagram of data collection and transmission for a multi-chip test provided by an embodiment of the present application;

[0041] Figure 6 is a schematic diagram of a semiconductor testing device provided by an embodiment of the present application;

[0042] Figure 7It is a schematic diagram of a computing program product provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0044] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0045] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0046] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0047] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0048] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0049] The embodiment of the present application provides a multi-chip test method, which is applied to the MCU module to achieve low-cost, high-efficiency and scalable multi-chip testing. The multi-chip test method provided by the present application outputs a corresponding interrupt signal to the main control module when it is detected that a target chip outputs target data among multiple chips to be tested; the main control module is instructed by the interrupt signal to collect the target data once; then after the main control module completes the collection of target data based on the target interrupt signal, the interrupt completion signal corresponding to the target interrupt signal is written into the interrupt completion file to complete the collection and recording of the target data output by the target chip; when the communication module is idle, the interrupt completion signal is taken out from the interrupt completion file in a preset order, and then the communication module is configured for communication according to the interrupt completion signal, so that the main control module sends the corresponding target data to the host computer by controlling the communication module, and completes the sending of the collected target data to the host computer in a preset order; low-cost and efficient data collection and transmission are achieved in multi-chip testing, while improving the scalability of multi-chip testing.

[0050] like Figure 1 As shown, the embodiment of the present application provides a multi-chip testing method, which is applied to an MCU module, and the method comprises the following steps:

[0051] Step S11, after the test starts, if it is detected that a target chip among multiple chips to be tested outputs target data, a target interrupt signal corresponding to the target chip is sent to the main control module; the target interrupt signal is used to instruct the main control module to collect the target data once.

[0052] In applications, in actual test scenarios, multiple chips to be tested may be chips of the same model or chips of different models; the test tasks that need to be performed by the chips to be tested may be the same or different; the chips to be tested also have differences in hardware design and technical parameters. Therefore, after the test starts, the target data output by each chip to be tested may be the same or different, and this time difference is usually unpredictable.

[0053] The method provided in the embodiment of the present application is that after the test starts, no matter when each chip to be tested outputs target data, as long as the microprocessor detects that a target chip (any chip among the chips to be tested) outputs target data, it sends a target interrupt signal corresponding to the target chip to the main control module. Through the target interrupt signal corresponding to the target chip, the main control module collects the target data output by the target chip.

[0054] In the application, the target interrupt signal includes a unique identifier of the target chip. The unique identifier can be a hardware identifier of the target chip, and different chips to be tested have different hardware identifiers; or it can be a temporary chip number assigned to each chip to be tested in each multi-chip test task, and each chip to be tested has a different temporary chip number. The unique identifier of the target chip in a target interrupt signal uniquely determines a target chip that outputs target data from multiple chips to be tested.

[0055] In applications, the target interrupt signal may also include the time when the target chip outputs the target data, the priority level of the target data, etc.

[0056] It can be understood that by sending a target interrupt signal corresponding to the target chip to the main control module after detecting that the target chip outputs target data, the main control module can be accurately instructed to timely and accurately collect the target data output by the target chip among multiple chips to be tested.

[0057] Step S12, after the main control module completes the acquisition of target data based on the target interrupt signal, writes an interrupt completion signal corresponding to the target interrupt signal into an interrupt completion file.

[0058] In the application, after the main control module receives the target interrupt signal, it will complete the target data collection based on the target interrupt signal, that is, the target data collection task corresponding to the target interrupt signal is completed. After each target data collection is completed, the MCU module writes the interrupt completion signal corresponding to the target interrupt signal into the interrupt completion file for recording. In the application, in addition to the interrupt completion signal, the interrupt completion file can also include the generation time of the interrupt completion signal, the level of the interrupt signal, etc.

[0059] In the application, the interrupt completion signal can be generated by the MCU module after the main control module completes the acquisition of target data based on the target interrupt signal, or it can be generated by the main control module after completing the acquisition of target data based on the target interrupt signal and then sent to the MCU module. The interrupt completion signal can include the unique identifier of the target chip in the target interrupt signal.

[0060] Step S13, when the communication module is idle, taking out the interruption completion signal from the interruption completion file in a preset order.

[0061] In the application, after the test starts, the communication module may be idle or may be occupied while transmitting target data to the host computer. The preset order is sorted according to the generation time of the interrupt completion signal, the priority of the interrupt signal, or the combination of the generation time of the interrupt completion signal and the priority of the interrupt signal. The preset order can be flexibly set according to the chip test task.

[0062] In the application, the MCU module can directly detect whether the communication module is in an idle state, or the main control module can determine whether the communication module is in an idle state and send an idle flag to the MCU module when the communication module is in an idle state. The idle state means that the communication module has sufficient resources to transmit a target data.

[0063] In the application, if the interrupt completion signal is sorted according to the generation time of the interrupt completion signal, the interrupt completion signal generated first will be written into the interrupt completion file first, so the interrupt completion signal can be organized in the interrupt completion file in the form of a first in first out (FIFO) queue, so that the interrupt completion signal stored first in the interrupt completion file is taken out first. If the interrupt signal is sorted according to its priority, the interrupt completion signal can be organized in the interrupt completion file through multiple FIFO queues. Different FIFO queues have different priority identifications. Interrupt completion signals of different priority levels are stored in the corresponding FIFO queues. Then, according to the priority level, all interrupt completion signals are taken out from the FIFO queue in order from high to low. When all interrupt signals in a high-priority FIFO queue are taken out, the next priority FIFO queue is accessed.

[0064] Step S14, performing communication configuration on the communication module according to the interrupt completion signal, so that the main control module sends the corresponding target data to the host computer by controlling the communication module.

[0065] In the application, the interrupt completion signal is taken from the interrupt completion file, indicating that the acquisition of the target data of the corresponding target interrupt signal has been completed, but has not yet been sent to the host computer. Each time the terminal completion signal is taken out, it corresponds to a different target interrupt signal. The target data output by the corresponding target chip needs to be obtained from different storage locations and sent to the host computer through different communication ports. Therefore, for different interrupt signals, the communication module needs to be configured accordingly.

[0066] In one embodiment, the method further comprises:

[0067] Step S111 , by polling the flag register of each chip under test among the multiple chips under test, detecting whether there is a target chip among the multiple chips under test outputting target data according to the value in the flag register.

[0068] In the application, before the test starts, each chip under test will be set with a preset flag value. If the value stored in the flag register of the chip under test is the same as the preset flag value, it can be determined that the chip under test outputs the target data. The preset flag values ​​of different chips under test may be different.

[0069] In one embodiment, the method further comprises:

[0070] Step S101, configuring communication parameters for each chip to be tested before the test begins; the communication parameters include a communication port and a data storage address;

[0071] The step S14, configuring the communication module for communication according to the interrupt completion signal, so that the main control module sends the corresponding target data to the host computer by controlling the communication module, includes:

[0072] Step S141, configuring the data reading address of the communication module to be the data storage address of the target chip corresponding to the interrupt completion signal according to the interrupt completion signal, and configuring the communication port of the communication module to be the communication port of the target chip corresponding to the interrupt completion signal.

[0073] In the application, before the test starts, a communication port and data storage address are configured for each chip to be tested. The target data output by the target chip is stored in the corresponding data storage address and sent to the host computer by the communication module through the corresponding network port.

[0074] In the application, the communication parameters (communication port and data storage address) of the corresponding target chip can be obtained through the unique identifier of the target chip in the interrupt completion signal, and the communication module is configured for communication based on the communication parameters. The data reading address of the communication module is configured to be the data storage address of the target chip corresponding to the interrupt completion signal, and the communication port of the communication module is configured to be the communication port of the target chip corresponding to the interrupt completion signal.

[0075] In one embodiment, the method further comprises:

[0076] Step S102, before the test starts, setting the working parameters of each chip to be tested; the working parameters are used to instruct the chip to be tested to output target data in a preset format.

[0077] In the application, the multiple chips to be tested include chips of different models, and the test tasks for each chip to be tested may also be different. Therefore, before the test starts, it is necessary to set the working parameters of each chip to be tested according to the test task to instruct the chip to be tested to output the target data in a preset format. Taking the chip to be tested as a fingerprint chip as an example, by setting the image width, height and image format of each chip to be tested, each chip to be tested can output image data in a specific format.

[0078] like Figure 2 As shown, an embodiment of the present application provides a multi-chip testing method, which is applied to a main control module, and the method includes:

[0079] Step S21, after receiving the target interrupt signal sent by the MCU module, completing a target data collection based on the target interrupt signal; the target data is output by a target chip among the multiple chips to be tested.

[0080] In the application, after the test starts, the MCU module will send a target interrupt signal corresponding to the target chip after detecting that there is a target chip outputting target data in the chip under test. The main control module always detects whether it has received the target interrupt signal sent by the MCU module. If it has received the target interrupt signal, it will collect the target data output by the target chip according to the target interrupt signal.

[0081] In the application, the target interrupt signal includes a unique identifier of the target chip, such as a hardware identifier or a temporary chip number of the target chip. The target chip corresponding to the target interrupt signal can be uniquely determined through the unique identifier.

[0082] In the application, multiple chips to be tested may output target data at the same time, or output target data in sequence in a short time; therefore, the main control module may receive multiple target interrupt signals sent by the MCU module at the same time, or receive multiple target interrupt signals in a short time, so it is necessary to complete the acquisition of target data output by multiple target chips at the same time, but the performance of the main control module to support simultaneous acquisition has certain limitations. For the above situation, it can be processed according to the time when the target chip outputs the target data or the priority level of the target data.

[0083] In the application, the main control module can generate an interrupt completion signal corresponding to the target interrupt signal after completing the acquisition of target data based on the target interrupt signal. The interrupt completion signal can include a unique identifier in the target interrupt signal, and the interrupt completion signal or the target interrupt signal can be uniquely corresponding to the target chip through the unique identifier.

[0084] Step S22, based on the communication configuration of the communication module performed by the MCU module according to the interrupt completion signal, control the communication module to send the corresponding target data to the host computer.

[0085] In the application, based on the communication configuration of the communication module by the MCU module according to the interrupt completion signal, the communication module takes out the target data from the corresponding storage location and sends the target data corresponding to the interrupt completion signal to the host computer through the corresponding communication port.

[0086] It can be understood that the method provided in the embodiment of the present application collects target data based on the target interrupt signal, and after the MCU module configures the communication module for communication based on the interrupt completion signal, the target data is sent to the host computer, thereby realizing low-cost and efficient data collection and transmission in multi-chip testing, while improving the scalability of multi-chip testing.

[0087] In one embodiment, the step S21, completing a target data collection based on the target interrupt signal, includes:

[0088] Step S211, determining a corresponding target chip according to the target interrupt signal.

[0089] The unique identifier of the target chip in the target interrupt signal of the application is used to uniquely identify the corresponding target chip among the multiple chips to be tested.

[0090] Step S212, collecting target data output by the target chip.

[0091] In the application, the target data output by the target chip is collected through the data acquisition module. The data acquisition module can simultaneously process the target data output by multiple target chips, and the maximum number of parallel operations depends on the performance of the acquisition module.

[0092] Step S213, storing the target data in the data storage space corresponding to the target chip.

[0093] In the application, each chip to be tested will be allocated a data storage space before the test begins. The target data output by the same chip to be tested is collected by the data collection module and stored in the data storage space corresponding to the chip.

[0094] In one embodiment, the step S22, based on the communication configuration of the communication module by the MCU according to the interrupt completion signal, controls the communication module to send the corresponding target data to the host computer, including:

[0095] Step S221 , controlling the communication module to read target data from the data storage address of the target chip corresponding to the interrupt completion signal.

[0096] Step S222, controlling the communication module to send the target data to the host computer through the communication port of the target chip corresponding to the interrupt completion signal.

[0097] In the application, before the test starts, each chip to be tested will be configured with a communication port and data storage address. The MCU determines the corresponding communication port and data storage address based on the unique identifier of the target chip in the interrupt completion signal, and then configures the data reading address of the communication module to be the data storage address of the target chip corresponding to the interrupt completion signal, and configures the communication port of the communication module to be the communication port of the target chip corresponding to the interrupt completion signal. Under the above communication configuration, the communication module can be controlled to read the target data from the data storage address of the target chip corresponding to the interrupt completion signal, and then send the target data to the host computer through the communication port of the target chip corresponding to the interrupt completion signal.

[0098] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0099] The present application also provides a multi-chip test system for executing the steps in the multi-chip test method embodiment. The multi-chip test system can be a virtual appliance in a semiconductor test device, which is run by a processor of the semiconductor test device, or it can be the semiconductor test device itself.

[0100] In applications, each module in the data storage device may be a software program module, or may be implemented by different logic circuits integrated in a processor, or may be implemented by multiple distributed processors.

[0101] like Figure 3 As shown, the present application embodiment provides a multi-chip test system, and the multi-chip test system 3 includes:

[0102] The MCU module 301 is used for sending a target interrupt signal corresponding to the target chip to the main control module after the test starts, if it is detected that a target chip among multiple chips to be tested outputs target data; the target interrupt signal is used to instruct the main control module to collect the target data once; after the main control module completes the collection of target data once based on the target interrupt signal, the interrupt completion signal corresponding to the target interrupt signal is written into the interrupt completion file; when the communication module is idle, the interrupt completion signal is taken out from the interrupt completion file in a preset order; the communication module is configured for communication according to the interrupt completion signal, so that the main control module sends the corresponding target data to the host computer by controlling the communication module;

[0103] The main control module 302 is used to complete the collection of target data based on the target interrupt signal sent by the MCU module after receiving the target interrupt signal; the target data is output by the target chip among the multiple chips to be tested; based on the communication configuration of the communication module performed by the MCU module according to the interrupt completion signal, control the communication module to send the corresponding target data to the host computer.

[0104] In one embodiment, the multi-chip testing system further includes a data acquisition module 303 for acquiring target data output by the chips.

[0105] In applications, the data acquisition module 303 can simultaneously acquire target data output by multiple chips.

[0106] In one embodiment, the multi-chip test system further includes a communication module 304 for sending the target data collected by the data acquisition module 304 to a host computer under the control of the main control module 302 according to the configuration of the MCU module 301 .

[0107] In the application, the communication module reads the target data from the data storage address of the target chip corresponding to the interrupt completion signal, and then sends the target data to the host computer through the communication port of the target chip corresponding to the interrupt completion signal.

[0108] In applications, the communication module can provide communication solutions including wireless local area networks (WLAN) (such as Wi-Fi networks), Bluetooth, Zigbee, mobile communication networks, global navigation satellite systems (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc. The communication module can be one or more devices integrating at least one communication processing module. The communication module may include an antenna, which may have only one array element or an antenna array including multiple array elements. The communication module can receive electromagnetic waves through the antenna, frequency modulate and filter the electromagnetic wave signals, and send the processed signals to the processor. The communication module can also receive the signal to be sent from the processor, frequency modulate and amplify it, and convert it into electromagnetic waves for radiation through the antenna.

[0109] like Figure 4 As shown, it is a framework diagram of data collection and transmission for a multi-chip test according to an embodiment of the present application.

[0110] like Figure 5 As shown, it is a timing diagram of data collection and transmission of a multi-chip test according to an embodiment of the present application.

[0111] One of the timing sequences can be described as follows: after the test starts, if the MCU module detects that a target chip among multiple chips to be tested outputs target data, it sends a target interrupt signal corresponding to the target chip to the main control module; the target interrupt signal is used to instruct the main control module to collect the target data once;

[0112] After receiving the target interrupt signal sent by the MCU module, the main control module completes the collection of target data based on the target interrupt signal; the target data is output by the target chip among the multiple chips to be tested;

[0113] The main control module stores the target data in the corresponding storage space after each acquisition is completed;

[0114] The MCU module writes the interrupt completion signal corresponding to the target interrupt signal into the interrupt completion file;

[0115] When the communication module is idle, the MCU module takes out the interrupt completion signal from the interrupt completion file in a preset order; and performs communication configuration on the communication module according to the interrupt completion signal;

[0116] The main control module sends the corresponding target data to the host computer by controlling the communication module.

[0117] Figure 6 This is a schematic diagram of the structure of a semiconductor testing device provided by an embodiment of the present application. Figure 6 As shown, the semiconductor testing device 6 of this embodiment includes: at least one processor 60 ( Figure 6 Only one is shown in the figure) a processor, a memory 61, and a computer program 62 stored in the memory 61 and executable on the at least one processor 60, and when the processor 60 executes the computer program 62, the steps in any of the above-mentioned multi-chip testing method embodiments are implemented.

[0118] The semiconductor testing device 6 can be a computing device such as a desktop computer, a notebook, a PDA, or a cloud server. The semiconductor testing device can include, but is not limited to, a processor 60 and a memory 61. Those skilled in the art can understand that Figure 6 It is only an example of the semiconductor testing device 6 and does not constitute a limitation of the semiconductor testing device 6. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components, for example, it may also include input and output devices, network access devices, etc.

[0119] The processor 60 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0120] In some embodiments, the memory 61 may be an internal storage unit of the semiconductor test device 6, such as a hard disk or memory of the semiconductor test device 6. In other embodiments, the memory 61 may also be an external storage device of the semiconductor test device 6, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the semiconductor test device 6. Further, the memory 61 may also include both the internal storage unit of the semiconductor test device 6 and an external storage device. The memory 61 is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as the program code of the computer program, etc. The memory 61 may also be used to temporarily store data that has been output or is to be output.

[0121] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0122] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0123] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0124] like Figure 7 As shown, an embodiment of the present application provides a computer program product 7, including a computer program 70. When the computer program 70 is run, the multi-chip testing method described above is executed.

[0125] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electric carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0126] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0127] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0128] In the embodiments provided in the present application, it should be understood that the disclosed multi-chip test system and method can be implemented in other ways. For example, the multi-chip test system embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0129] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0130] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A multi-chip testing method, characterized in that: Applied to an MCU module, the method includes: If it is detected that a target chip among the multiple chips to be tested outputs target data, a target interrupt signal corresponding to the target chip is sent to the main control module; the target interrupt signal is used to instruct the main control module to collect the target data once; After the main control module completes the acquisition of target data once based on the target interrupt signal, an interrupt completion signal corresponding to the target interrupt signal is written into an interrupt completion file; When the communication module is idle, the interrupt completion signal is taken out from the interrupt completion file in a preset order; The communication module is configured for communication according to the interrupt completion signal, so that the main control module sends the corresponding target data to the host computer by controlling the communication module.

2. The multi-chip testing method according to claim 1, characterized in that: The method further comprises: By polling the flag register of each chip to be tested among the multiple chips to be tested, it is detected whether a target chip among the multiple chips to be tested outputs target data according to the value in the flag register.

3. The multi-chip testing method according to claim 1, characterized in that: The method further comprises: Before the test begins, configure communication parameters for each chip to be tested; the communication parameters include a communication port and a data storage address; The communication module is configured for communication according to the interrupt completion signal, so that the main control module sends corresponding target data to the host computer by controlling the communication module, including: According to the interrupt completion signal, the data reading address of the communication module is configured to be the data storage address of the target chip corresponding to the interrupt completion signal, and the communication port of the communication module is configured to be the communication port of the target chip corresponding to the interrupt completion signal.

4. The multi-chip testing method according to any one of claims 1 to 3, characterized in that: The method further comprises: The working parameters of each chip to be tested are set; the working parameters are used to instruct the chip to be tested to output target data in a preset format.

5. A multi-chip testing method, characterized in that: Applied to the main control module, the method includes: After receiving the target interrupt signal sent by the MCU module, completing the collection of target data based on the target interrupt signal; the target data is output by the target chip among the multiple chips to be tested; Based on the communication configuration of the communication module performed by the MCU module according to the interrupt completion signal, the communication module is controlled to send the corresponding target data to the host computer.

6. The multi-chip testing method according to claim 5, characterized in that: The step of completing a target data collection based on the target interrupt signal includes: Determine a corresponding target chip according to the target interrupt signal; Collecting target data output by the target chip; The target data is stored in the data storage space corresponding to the target chip.

7. The multi-chip testing method according to claim 6, characterized in that: The communication configuration of the communication module performed by the MCU module according to the interrupt completion signal, and controlling the communication module to send corresponding target data to the host computer, includes: Control the communication module to read the target data from the data storage address of the target chip corresponding to the interrupt completion signal; The control communication module sends the target data to the host computer through the communication port of the target chip corresponding to the interrupt completion signal.

8. A multi-chip testing system, characterized in that: The system comprises: The MCU module is used for sending a target interrupt signal corresponding to the target chip to the main control module after the test starts, if it is detected that a target chip among multiple chips to be tested outputs target data; the target interrupt signal is used to instruct the main control module to collect the target data once; after the main control module completes the collection of target data once based on the target interrupt signal, writing an interrupt completion signal corresponding to the target interrupt signal into an interrupt completion file; when the communication module is idle, taking out the interrupt completion signal from the interrupt completion file in a preset order; and configuring the communication module for communication according to the interrupt completion signal, so that the main control module sends the corresponding target data to the host computer by controlling the communication module; The main control module is used to complete the collection of target data based on the target interrupt signal sent by the MCU module after receiving the target interrupt signal; the target data is output by the target chip among the multiple chips to be tested; based on the communication configuration of the communication module performed by the MCU module according to the interrupt completion signal, control the communication module to send the corresponding target data to the host computer.

9. A semiconductor testing device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the semiconductor testing device is caused to implement the method according to any one of claims 1 to 7.

10. A computer program product, characterized in that The invention comprises a computer program, which enables the method according to any one of claims 1 to 7 to be executed when the computer program is executed.

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