High-voltage integrated circuit test method

Abstract

The invention relates to the technical field of intelligent power module testing, in particular to a high-voltage integrated circuit testing method, which comprises the following steps of: starting a control signal generation unit, controlling to output a high-low level PWM pulse signal according to a preset frequency, and transmitting the high-low level PWM pulse signal to a controllable delay circuit through a line; after the controllable time delay circuit receives the PWM pulse signal, an instantaneous pulse signal is sent out according to the PWM pulse signal and is transmitted to an upper bridge arm transistor and / or a lower bridge arm transistor of the tested intelligent power module; the oscilloscope detects the on-off action time of an upper bridge arm transistor and / or a lower bridge arm of the detected intelligent power module and judges whether the on-off action time is matched with the PWM pulse signal output by the signal generation unit or not, if yes, the detected intelligent power module is qualified, and if not, the detected intelligent power module is unqualified. Accurate intelligent power module input and output action signal parameter electrical test results can be obtained, the test process is simple and convenient, the reliability is high, the cost is low, and the method can be suitable for intelligent power modules of various models.

Description

Technical Field

[0001] The present invention relates to the technical field of intelligent power module testing, and in particular to a high-voltage integrated circuit testing method. Background Art

[0002] Intelligent Power Module (IPM) is an advanced power switch device that integrates power switch elements and high-voltage integrated drive circuits, and has built-in fault detection circuits such as overvoltage, overcurrent and overheating. Its core component is the high-speed, low-power IGBT (insulated gate bipolar transistor) chip, which combines the advantages of GTR (high-power transistor) and MOSFET (field effect transistor).

[0003] The high-voltage integrated drive circuit is the core component of the power module. 80% of the hundreds of parameters of the module are the parameters of the high-voltage integrated driver, so testing and verifying the electrical parameters of the module is an indispensable part of development. In mass production mode, the power module has dedicated precision test equipment and test procedures, and the whole process is automatically tested. However, in the process of power module development, especially in the early stage of product development, it is necessary to test the parameters of the module, such as driver chips, power devices, etc. Since the power module is a non-standard product, each manufacturer produces different ones. Therefore, in the early stage of development, there is no tooling that can meet the unified testing of various models. If you develop related vehicle tooling and test it through high-precision equipment system, the cost is relatively high, and the equipment development time is long, resulting in a long project development cycle and affecting efficiency. Therefore, engineers need to build test circuits for testing in the early stage. For example, the VDD power supply undervoltage action delay test method of the module is: all the signals of the power module are connected, the upper and lower bridge arms of the module start to work, and then the signal generator is manually adjusted to output the predetermined DC source voltage value until the undervoltage threshold appears, the module stops working, and the action delay time is recorded. Since the response time of the components under test is in the nanosecond level, if the voltage is stepped down and stepped up directly through manual control for testing, the output test signal will be a non-instantaneous signal because the human reaction is far from reaching the ns level. The non-instantaneous signal will cause the switching action of the components under test to be delayed or advanced, resulting in deviations in the measured results and errors in the calibration of product parameters. Summary of the invention

[0004] The present invention proposes a high-voltage integrated circuit testing method to solve the problem that the existing method of testing an intelligent power module by manually adjusting an output test signal will make the output test signal a non-instantaneous signal, resulting in a deviation between the test result and the actual result, thereby causing errors in parameter calibration.

[0005] According to one aspect of the present invention, there is provided a high voltage integrated circuit testing method, comprising: The intelligent power module under test is connected to a controllable delay circuit and an oscilloscope through lines respectively, the controllable delay circuit is connected to a test signal generating unit, and the intelligent power module under test is connected to an adjustable power supply; Control the signal generating unit to start, control the output of high and low level PWM pulse signals at a predetermined frequency, and transmit them to the controllable delay circuit through the line; After the controllable delay circuit receives the PWM pulse signal, it issues an instantaneous pulse signal according to the PWM pulse signal and transmits the instantaneous pulse signal to the upper bridge arm transistor and / or the lower bridge arm transistor of the intelligent power module under test; The oscilloscope detects the on / off action time of the upper bridge arm transistor and / or the lower bridge arm of the intelligent power module under test, and determines whether the on / off action time matches the PWM pulse signal output by the signal generating unit. If so, the intelligent power module under test is qualified, otherwise, it is unqualified.

[0006] Preferably, the controllable delay circuit comprises: The signal generating unit is connected to a group of first NPN transistors and second NPN transistors connected in parallel, the NPN transistors are connected to electromagnetic relays, and the electromagnetic relays are respectively connected to the intelligent power module under test and the adjustable power supply; When the signal generating unit outputs a high level, the first NPN transistor is turned on, so that the signal generating unit outputs a high level and transmits it to the relay, and the relay outputs an instantaneous high level signal according to the signal generating unit, and transmits it to the intelligent power module under test; When the signal generating unit outputs a low level, the second NPN transistor is turned on, and the residual inductance in the relay is discharged through the second NPN transistor.

[0007] Preferably, a bias resistor for enhancing the signal is provided between the signal generating unit and the first NPN transistor and the second NPN transistor connected in parallel.

[0008] Preferably, a pull-down resistor is provided between the bias resistor and the output end of the second NPN transistor for preventing the first NPN transistor from being erroneously started.

[0009] Preferably, the first NPN transistor is connected to a relay power supply; A first current limiting resistor is provided between the first NPN transistor and the second NPN transistor connected in parallel and the relay; A second current limiting resistor is provided between the relay power supply and the first NPN transistor; The first current limiting resistor and the second current limiting resistor are used to prevent the current in the circuit from exceeding a predetermined value.

[0010] Preferably, a diode is provided between the first current limiting resistor and the relay to prevent the relay signal from flowing back to the first NPN transistor.

[0011] Preferably, a third current limiting resistor is provided between the first and second NPN transistors connected in parallel and the relay, for preventing residual current of the relay from entering the first NPN transistor.

[0012] Preferably, an RC circuit for preventing surge signals is provided between the adjustable power supply and the relay; Wherein, the RC circuit includes a fourth current limiting resistor and a first capacitor.

[0013] Preferably, the signal generating unit comprises: a first signal generator, a second signal generator and a third signal generator; The first signal generator is connected to the signal input terminal of the upper bridge arm transistor of the intelligent power module under test through the controllable delay circuit, and the PWM pulse signal emitted by the first signal generator is transmitted to the upper bridge arm transistor through the controllable delay circuit; The second signal generator is connected to the power supply output terminal of the intelligent power module under test through the controllable delay circuit, and the PWM pulse signal emitted by the second signal generator is transmitted to the upper bridge arm transistor and the lower bridge arm transistor through the controllable delay circuit; The third signal generator is connected to the signal input terminal of the lower bridge arm transistor of the intelligent power module under test through the controllable delay circuit, and the PWM pulse signal emitted by the third signal generator is transmitted to the lower bridge arm transistor through the controllable delay circuit.

[0014] Preferably, the upper bridge arm transistor of the intelligent power module under test is connected to a 15V DC power supply; The bus voltage input terminal of the intelligent power module under test is connected to the signal connection line through an energy storage capacitor.

[0015] The present invention has at least the following beneficial effects: The present invention proposes a high-voltage integrated circuit testing method. Based on the existing testing equipment, a controllable delay circuit for testing is added to accurately output nanosecond-level instantaneous voltage signals for testing, thereby obtaining accurate electrical test results of intelligent power module input and output action signal parameters. The testing process is simple, reliable, and low-cost, and can be applied to various models of intelligent power modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present invention and, together with the specification, are used to explain the technical solutions of the present invention.

[0017] Figure 1 A flow chart showing a high voltage integrated circuit testing method according to an embodiment of the present invention; Figure 2 A circuit diagram of an intelligent power module according to an embodiment of the present invention is shown; Figure 3 A circuit diagram showing a high voltage integrated circuit testing method according to an embodiment of the present invention; Figure 4 A schematic structural diagram of a controllable delay circuit according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0018] Various exemplary embodiments, features and aspects of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0019] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0020] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0021] In addition, in order to better illustrate the present invention, numerous specific details are provided in the following specific embodiments. It should be understood by those skilled in the art that the present invention can be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0022] Figure 1 A flow chart showing a high voltage integrated circuit testing method according to an embodiment of the present invention; Figure 2 A circuit diagram of an existing intelligent power module is shown; Figure 3 A circuit diagram showing a high voltage integrated circuit testing method according to an embodiment of the present invention; Figure 4 FIG. 2 shows a schematic diagram of a controllable delay circuit according to an embodiment of the present invention. Figure 1-4As shown, a high-voltage integrated circuit testing method includes: step S01: connecting the tested intelligent power module to a controllable delay circuit and an oscilloscope through lines respectively, the controllable delay circuit is connected to a test signal generating unit, and the tested intelligent power module is connected to an adjustable power supply; step S02: controlling the signal generating unit to start, controlling the output of high and low level PWM pulse signals according to a predetermined frequency, and transmitting them to the controllable delay circuit through a line; step S03: after the controllable delay circuit receives the PWM pulse signal, an instantaneous pulse signal is issued according to the PWM pulse signal, and the instantaneous pulse signal is transmitted to the upper bridge arm transistor and / or the lower bridge arm transistor of the tested intelligent power module; step S04: the oscilloscope detects the on / off action time of the upper bridge arm transistor and / or the lower bridge arm of the tested intelligent power module, and determines whether the on / off action time matches the PWM pulse signal output by the signal generating unit. If yes, the tested intelligent power module is qualified, otherwise, it is unqualified.

[0023] like Figure 2 The figure shows the electrical topology of the multi-energy power module. The intelligent power module 001 includes a control chip 002 and three inverter units. The inverter unit includes three groups of inverter modules. Each group of inverter modules includes two triode transistors, wherein 003 and 006 form a group, 004 and 007 form a group, and 005 and 008 form a group. Each group of two triode transistors is divided into an upper bridge arm and a lower bridge arm, wherein triode transistor 003 is an upper bridge arm, triode transistor 006 is a lower bridge arm, triode transistor 004 is an upper bridge arm, triode transistor 007 is a lower bridge arm, triode transistor 005 is an upper bridge arm, and triode transistor 008 is a lower bridge arm. The drain of the triode transistor 003 of the upper bridge arm is connected to the high voltage input terminal P of the module, the source of the triode transistor 003 of the upper bridge arm is connected to the drain of the triode transistor 006 of the lower bridge arm, the source of the triode transistor 006 of the lower bridge arm is connected to the external pin NU of the module, and the gates of the two triode transistors are connected to the control chip 002; the source of the triode transistor 004 of the upper bridge arm is connected to the drain of the triode transistor 007 of the lower bridge arm, and the source of the triode transistor 007 of the lower bridge arm is connected to the external pin NU of the module. NV terminal is connected, and the gates of the two triode transistors are connected to the control chip 002; the source of the triode transistor 005 of the upper bridge arm is connected to the drain of the triode transistor 008 of the lower bridge arm, and the source of the triode transistor 008 of the lower bridge arm is connected to the NW terminal of the module external pin, and the gates of the two triode transistors are connected to the control chip 002; 009 is the high-frequency filter capacitor C4 of the control chip, which is connected to VCC or VDD, COM, as close as possible to the output terminal of the control chip, and its function is to filter out high-frequency signals. 010 is a high-frequency filter capacitor, whose purpose is to filter out the coupling signal of the line and avoid false triggering of the power module.

[0024] The high voltage integrated circuit testing method provided by the embodiment of the present invention specifically comprises the following steps: Step S01: connecting the intelligent power module under test to a controllable delay circuit and an oscilloscope through lines respectively, wherein the controllable delay circuit is connected to a test signal generating unit, and the intelligent power module under test is connected to an adjustable power supply.

[0025] In the embodiment of the present invention, Figure 3 As shown, 500 is a DC power supply, 504 is a Fault power pull-up resistor, 505 is an inductive load, 506 is an energy storage capacitor, and 507 is an oscilloscope.

[0026] The U-phase bootstrap terminal VBU of the intelligent power module is connected to the control power supply (DC power supply) 500 separately, and is connected to the positive pole of the power supply, and the negative pole of the power supply is connected to the common ground; the V-phase bootstrap terminal VBV is connected to the control power supply separately, and is connected to the positive pole of the power supply, and the negative pole of the power supply is connected to the common ground; the W-phase bootstrap terminal VBW is connected to the control power supply separately, and is connected to the positive pole of the power supply, and the negative pole of the power supply is connected to the common ground.

[0027] Intelligent Power Module IN UH , IN VH , IN WH , and / or power supply input VDD, and / or IN UL , IN VL , IN WL , connected to the signal generator, as a high or low level PWM pulse signal (control signal) to control the corresponding tube (insulated gate bipolar transistor or triode transistor) of the IPM module to turn on and off.

[0028] 504 is the intelligent power module enable input / output terminal EN, V FAULT , pull up to 5V enable signal through a 5.1k resistor.

[0029] 505 is a load R2 at the U, V, W phase output end of the three-phase inverter of the power module. One end of R2 is connected to the U, V, W bootstrap end of the intelligent power module, and the other end is connected to the signal ground.

[0030] 506 is an energy storage capacitor C1, and the bus voltage input terminal P of the intelligent power module is connected to the signal ground through the other end of the energy storage capacitor C1.

[0031] 507 is an oscilloscope, which is used to detect the turn-on and turn-off signals of the three-stage transistors U, V, and W of the intelligent power module and read the required test parameter data.

[0032] Step S02: Control the signal generating unit to start, output high and low level PWM pulse signals at a predetermined frequency, and transmit them to the controllable delay circuit 502-1 through the line.

[0033] In the present invention, the controllable delay circuit includes: the signal generating unit is connected to a group of first NPN transistors Q1 and second NPN transistors Q2 connected in parallel, the NPN transistors are connected to an electromagnetic relay 602, and the electromagnetic relay 602 is respectively connected to the intelligent power module 001 under test and the adjustable power supply 604; when the signal generating unit outputs a high level, the first NPN transistor Q1 is turned on, so that the high level output of the signal generating unit is transmitted to the relay 602, and the relay 602 outputs an instantaneous high level signal and transmits it to the intelligent power module 001 under test; when the signal generating unit outputs a low level, the second NPN transistor Q2 is turned on, and the residual inductance in the relay 602 is discharged through the second NPN transistor Q2.

[0034] In the embodiment of the present invention, the electromagnetic relay 602 is connected to the power terminal 603 of the intelligent power module 001. The VDD adjustable DC power supply 604 can output different power threshold currents and transmit them to the intelligent power module under test for testing. Among them, the output current of the VDD adjustable power supply is 20V, that is, P, NU / NV / NW of the intelligent power module = 20V.

[0035] During the test, the VDD adjustable power supply 604 is controlled to start and supply power to the intelligent control module; the Fault power supply pull-up resistor is used to pass through the enable input / output terminals EN and V FAULT Input the enable signal to control the intelligent control module to start. The enable signal value range is 0-15V; in this embodiment, the value is EN=5V, V FAULT =5V.

[0036] The control signal generating unit is started, and the output voltage of the predetermined test signal, i.e., the high and low level PWM pulse signal, is adjusted by manually rotating the adjustment knob on the signal generating unit. The pulse signal is transmitted to the controllable delay circuit through the line.

[0037] The PWM pulse test signal emitted by the signal generating unit is converted into an instantaneous predetermined voltage pulse signal output after passing through the controllable delay circuit, and is transmitted to the intelligent power module 001 through the line.

[0038] Step S03: After the controllable delay circuit receives the PWM pulse signal, it issues an instantaneous pulse signal and transmits it to the upper bridge arm transistor and / or the lower bridge arm transistor of the intelligent power module under test.

[0039] In the embodiment of the present invention, Figure 4 As shown, the PWM pulse test signal sent by the signal generating unit is transmitted through the line to the first NPN transistor Q1 and the second NPN transistor Q2 connected in parallel.

[0040] When the PWM pulse signal output by the signal generator is at a high level, the first NPN transistor Q1 at the top is turned on and the second NPN transistor Q2 at the bottom is turned off; the current signal enters the electromagnetic relay 602 through Q1. When a high-level signal flows through the relay, an electromagnetic is generated to turn on the power supply of the relay 602, and its internal switch is attracted, thereby outputting an instantaneous predetermined voltage signal, which is transmitted to the three-stage transistor of the intelligent control module through the line; the electromagnetic relay can automatically control the time and realize the delay control of the circuit.

[0041] When the PWM pulse signal output by the signal generator is at a low level, the first NPN transistor Q1 at the top is turned off and the second NPN transistor Q2 at the bottom is turned on; at this time, the residual inductance of the power supply EP1 in the electromagnetic relay 602 will flow to the ground through Q2, achieving rapid discharge and keeping the circuit in a high-resistance state.

[0042] The instantaneous predetermined voltage signal (instantaneous pulse signal) output by the electromagnetic relay 602 passes through the IN pin of the intelligent power module. UH , IN VH , IN WH Transmitted to the upper bridge arm (003, 004 and 005) of the three-stage transistor, or transmitted to the upper bridge arm and lower bridge arm (003, 004, 005, 006, 007, 008) of the three-stage transistor through the power input terminal VDD of the intelligent power module, or transmitted to the upper bridge arm and lower bridge arm (003, 004, 005, 006, 007, 008) of the three-stage transistor through the power input terminal VDD of the intelligent power module UL , IN VL , IN WL Transmitted to the lower bridge arms of the three-stage transistors (006, 007 and 008).

[0043] Step S04: The oscilloscope detects the on / off action time of the upper bridge arm transistor and / or the lower bridge arm of the intelligent power module under test, and determines whether the on / off action time matches the PWM pulse signal output by the signal generating unit. If so, the intelligent power module under test is qualified, otherwise, it is unqualified.

[0044] In the embodiment of the present invention, the three-stage transistor performs a corresponding switching action according to the instantaneous pulse signal output by the electromagnetic relay 602. If the pulse signal is greater than the turn-on threshold, the module transistor performs an on action, and if the pulse signal is less than the turn-on threshold, the intelligent power module transistor performs a turn-off action. The control oscilloscope 507 is started, and the on and off action delay time of the intelligent power module transistor can be detected and recorded by the oscilloscope 507. By comparing the detected transistor on and off action time with the PWM pulse signal output by the signal generating unit, it can be determined whether the tested intelligent power module is qualified.

[0045] In the present invention, a bias resistor for enhancing the signal is provided between the signal generating unit and the first NPN transistor and the second NPN transistor connected in parallel.

[0046] In the embodiment of the present invention, the bias resistor R1 has a resistance of 100Ω, and is used to enhance the signal, thereby providing a suitable circuit for the first NPN transistor Q1 and the second NPN transistor Q2.

[0047] In the present invention, a pull-down resistor is provided between the bias resistor and the output end of the second NPN transistor to prevent the first NPN transistor from being erroneously started.

[0048] In the embodiment of the present invention, the pull-down resistor R2 has a resistance of 10Ω, which can quickly turn off the first NPN transistor Q1 and maintain a low potential at a low level to prevent residual power from causing self-excitation of the first NPN transistor Q1 signal and causing the first NPN transistor Q1 to be mistakenly turned on.

[0049] In the present invention, the first NPN transistor is connected to a relay power supply; a first current limiting resistor is arranged between the first NPN transistor and the second NPN transistor connected in parallel and the relay; a second current limiting resistor is arranged between the relay power supply and the first NPN transistor; the first current limiting resistor and the second current limiting resistor are used to prevent the current in the circuit from exceeding a predetermined value.

[0050] In the embodiment of the present invention, the first NPN transistor Q1 of the controllable delay circuit is connected to the relay power supply (constant current power supply) EP2, which is used to power the electromagnetic relay 602. The current of the relay power supply EP2 passes through the second current limiting resistor R4 and then flows to the relay.

[0051] The first current limiting resistor R3 and the second current limiting resistor R4 are used to prevent the transistor and the relay from being damaged when the current is too large and exceeds a predetermined value.

[0052] In the present invention, a diode is provided between the first current limiting resistor and the relay to prevent the relay signal from flowing back to the first NPN transistor.

[0053] In the embodiment of the present invention, the first current limiting resistor R3 is connected to the relay 602 through the diode D2. The relay 602 has a large load, and the diode D2 can prevent the high-level signal from flowing, and conduct the residual current of the relay 602 to the ground through D2, R3, and Q2, thereby preventing the relay 602 signal from flowing back to the first NPN transistor Q1.

[0054] In the present invention, a third current limiting resistor is provided between the first and second NPN transistors connected in parallel and the relay, for preventing residual current of the relay from entering the first NPN transistor.

[0055] In the embodiment of the present invention, the first NPN transistor Q1 and the second NPN transistor Q2 connected in parallel are connected to the relay 602 via the third current limiting resistor R5. The third current limiting resistor R5 can prevent the relay closing signal from flowing back, that is, prevent the relay current from flowing back to Q1.

[0056] In the present invention, an RC circuit for preventing surge signals is provided between the adjustable power supply and the relay; wherein the RC circuit includes a fourth current limiting resistor and a first capacitor.

[0057] In the embodiment of the present invention, the fourth current limiting resistor R6 and the first capacitor C1 are RC circuits. Because a large surge signal will be generated when the relay is closed instantaneously, the whole machine filter circuit RC can filter out high-frequency signals, effectively protecting the safety of the intelligent power module and preventing it from being burned by surge signals.

[0058] In the present invention, the signal generating unit includes: a first signal generator, a second signal generator and a third signal generator; the first signal generator is connected to the signal input end of the upper bridge arm transistor of the intelligent power module under test through the controllable delay circuit, and the PWM pulse signal emitted by the first signal generator is transmitted to the upper bridge arm transistor through the controllable delay circuit; the second signal generator is connected to the power supply output end of the intelligent power module under test through the controllable delay circuit, and the PWM pulse signal emitted by the second signal generator is transmitted to the upper bridge arm transistor and the lower bridge arm transistor through the controllable delay circuit; the third signal generator is connected to the signal input end of the lower bridge arm transistor of the intelligent power module under test through the controllable delay circuit, and the PWM pulse signal emitted by the third signal generator is transmitted to the lower bridge arm transistor through the controllable delay circuit.

[0059] In the present invention, the upper bridge arm transistor of the intelligent power module under test is connected to a 15V DC power supply; the bus voltage input terminal of the intelligent power module under test is connected to a signal connection line through an energy storage capacitor.

[0060] In the embodiment of the present invention, the three signal generators 501 , 502 , and 503 can realize separate testing of the upper bridge arm, separate testing of the lower bridge arm, and simultaneous testing of the upper and lower bridge arms of the intelligent control module.

[0061] like Figure 3 As shown, the first signal generator 501 is connected to the IN of the intelligent control module through a controllable delay circuit. UH , IN VH , IN WHport; when testing the upper arm, the upper arm transistor is controlled to connect to the 15V DC power supply 500, that is, the intelligent control module U and VBU, V and VBV, W and VBW = 15V; the first signal generator 501 is controlled to start and output a PWM pulse signal, which is converted into an instantaneous pulse signal through the controllable delay circuit, and then transmitted to the input terminal of the controllable delay circuit; UH , IN VH , IN WH The signals are transmitted to the upper bridge arms 003, 004 and 005 of the three-stage transistors for on or off testing.

[0062] The second signal generator 502 is connected to the power supply input terminal VDD of the intelligent control module (high-voltage integrated circuit) through a controllable delay circuit; when performing the upper bridge arm and lower bridge arm test, the second signal generator 502 is controlled to start and output a PWM pulse signal, which is converted into an instantaneous pulse signal by the controllable delay circuit and then transmitted to the upper bridge arm 003, 004, 005 and the lower bridge arm 006, 007, 008 of the three-stage transistor through the VDD power pin for an on or off test.

[0063] The third signal generator 503 is connected to the IN of the intelligent control module through a controllable delay circuit. UL , IN VL , IN WL When the lower arm test is performed, the third signal generator 503 is controlled to start and output a PWM pulse signal, which is converted into an instantaneous pulse signal through a controllable delay circuit, and then transmitted through IN UL , IN VL , IN WL Transmitted to the lower bridge arms 006, 007, and 008 of the three-stage transistor for on or off testing.

[0064] Use an oscilloscope to test the action signals of each bridge arm of the module's transistors.

[0065] It can be understood that the above-mentioned various method embodiments mentioned in the present invention can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present invention will not go into details.

[0066] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0067] The present invention measures the chip input and output action signal parameter electricity by using signal generator, relay and oscilloscope equipment. The operation process is simple. It only needs to put the tested sample on the test fixture, fix the tested sample, connect the test line, apply necessary fixed power supply conditions to the functional pins of the intelligent power module, set the test voltage value of the VDD adjustable power supply, and then input high and low level test pulse signals. The oscilloscope monitors and captures the collector and emitter signals of the power supply terminal, the module power tube (transistor) to perform the test.

[0068] The existing intelligent power module testing method is a factory mass production test method that uses automatic equipment for testing. The test speed is too fast and is not suitable for routine product development testing. The present invention sets a controllable delay circuit, first outputs a control signal through a signal generator, gives it to a relay, and controls the high and low levels of the signal to make the relay switch, thereby outputting an instantaneous test signal, and using an oscilloscope to control and measure accurate data. An RC circuit with a filtering function is set in the controllable delay circuit to prevent overshoot signals from damaging the module. There is no need to change the structure of the original test signal generator, and it can match various types of signal generators and intelligent power modules. The test results are accurate and reliable, and the test cost is low.

[0069] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A high voltage integrated circuit testing method, characterized in that: include: The intelligent power module under test is connected to a controllable delay circuit and an oscilloscope through lines respectively, the controllable delay circuit is connected to a test signal generating unit, and the intelligent power module under test is connected to an adjustable power supply; Control the signal generating unit to start, control the output of high and low level PWM pulse signals at a predetermined frequency, and transmit them to the controllable delay circuit through the line; After the controllable delay circuit receives the PWM pulse signal, it issues an instantaneous pulse signal according to the PWM pulse signal and transmits the instantaneous pulse signal to the upper bridge arm transistor and / or the lower bridge arm transistor of the intelligent power module under test; The oscilloscope detects the on / off action time of the upper bridge arm transistor and / or the lower bridge arm of the intelligent power module under test, and determines whether the on / off action time matches the PWM pulse signal output by the signal generating unit. If so, the intelligent power module under test is qualified, otherwise, it is unqualified.

2. The high voltage integrated circuit testing method according to claim 1, characterized in that: The controllable delay circuit comprises: The signal generating unit is connected to a group of first NPN transistors and second NPN transistors connected in parallel, the NPN transistors are connected to electromagnetic relays, and the electromagnetic relays are respectively connected to the intelligent power module under test and the adjustable power supply; When the signal generating unit outputs a high level, the first NPN transistor is turned on, so that the signal generating unit outputs a high level and transmits it to the relay, and the relay outputs an instantaneous high level signal according to the signal generating unit, and transmits it to the intelligent power module under test; When the signal generating unit outputs a low level, the second NPN transistor is turned on, and the residual inductance in the relay is discharged through the second NPN transistor.

3. The high voltage integrated circuit testing method according to claim 2, characterized in that: A bias resistor for enhancing the signal is provided between the signal generating unit and the first NPN transistor and the second NPN transistor connected in parallel.

4. The high voltage integrated circuit testing method according to claim 3, characterized in that: A pull-down resistor is provided between the bias resistor and the output end of the second NPN transistor to prevent the first NPN transistor from being erroneously started.

5. The high voltage integrated circuit testing method according to claim 2, characterized in that: The first NPN transistor is connected to a relay power supply; A first current limiting resistor is provided between the first NPN transistor and the second NPN transistor connected in parallel and the relay; A second current limiting resistor is provided between the relay power supply and the first NPN transistor; The first current limiting resistor and the second current limiting resistor are used to prevent the current in the circuit from exceeding a predetermined value.

6. The high voltage integrated circuit testing method according to claim 5, characterized in that: A diode is provided between the first current limiting resistor and the relay to prevent the relay signal from flowing back to the first NPN transistor.

7. The high voltage integrated circuit testing method according to claim 2, characterized in that: A third current limiting resistor is provided between the first and second NPN transistors connected in parallel and the relay, and is used to prevent residual current of the relay from entering the first NPN transistor.

8. The high voltage integrated circuit testing method according to claim 2, characterized in that: An RC circuit for preventing surge signals is provided between the adjustable power supply and the relay; Wherein, the RC circuit includes a fourth current limiting resistor and a first capacitor.

9. The high voltage integrated circuit testing method according to claim 1, characterized in that: The signal generating unit comprises: a first signal generator, a second signal generator and a third signal generator; The first signal generator is connected to the signal input terminal of the upper bridge arm transistor of the intelligent power module under test through the controllable delay circuit, and the PWM pulse signal emitted by the first signal generator is transmitted to the upper bridge arm transistor through the controllable delay circuit; The second signal generator is connected to the power supply output terminal of the intelligent power module under test through the controllable delay circuit, and the PWM pulse signal emitted by the second signal generator is transmitted to the upper bridge arm transistor and the lower bridge arm transistor through the controllable delay circuit; The third signal generator is connected to the signal input terminal of the lower bridge arm transistor of the intelligent power module under test through the controllable delay circuit, and the PWM pulse signal emitted by the third signal generator is transmitted to the lower bridge arm transistor through the controllable delay circuit.

10. The high voltage integrated circuit testing method according to any one of claims 1 to 9, characterized in that: The upper bridge arm transistor of the intelligent power module under test is connected to a 15V DC power supply; The bus voltage input terminal of the intelligent power module under test is connected to the signal connection line through an energy storage capacitor.

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