Test conversion component and test system

Abstract

The invention relates to the field of chip testing, and discloses a test conversion component and a test system. The first test packaging array is located on the first surface of the substrate and is used for being electrically connected with a target test circuit board; the first test package array comprises a plurality of first contacts; the target test circuit board is used for testing a current device; the second test packaging array and the peripheral circuit are located on the second surface of the substrate, and the second test packaging array is used for being electrically connected with a to-be-tested device; the second test package array comprises a plurality of second contacts, the peripheral circuit comprises a circuit element, the circuit element is electrically connected with a signal network, different from the current device, of the device to be tested, and signal lines in the signal network are electrically connected with the second contacts. Through the test conversion part, connection between the to-be-tested device and the target test circuit board can be realized, so that the to-be-tested device is adjusted and tested by using the current target test circuit board, a new test circuit board does not need to be designed for the to-be-tested device, and time and cost are saved.

Description

Technical Field

[0001] The invention relates to the field of chip testing, and in particular to a test conversion component and a test system. Background Art

[0002] Various learning models have been widely used in various fields (such as text classification, image classification, language understanding and generation, autonomous driving, etc.), and the operation of the models requires a large amount of memory to support it. At present, the mainstream memory configuration of PC (Personal Computer) is 16GB, which limits the development of artificial intelligence personal computers.

[0003] The maximum single-chip density of the fourth-generation double data rate synchronous dynamic random access memory (Double Data Rate 4 Generation Synchronous Dynamic Random Access Memory, referred to as DDR4 SDRAM) is 4GB, which can provide higher memory and support the development of various learning models and artificial intelligence personal computers. However, with the trend of model-side operation, the demand for memory will become higher and higher. The maximum single-chip density of the fifth-generation double data rate synchronous dynamic random access memory (Double Data Rate 5 Generation Synchronous Dynamic Random Access Memory, referred to as DDR5 SDRAM) can reach 16GB, which can provide higher memory than the fourth-generation double data rate synchronous dynamic random access memory.

[0004] Currently, there is only a test circuit board for debugging the fourth-generation double-speed synchronous dynamic random access memory. Since the fifth-generation double-speed synchronous dynamic random access memory is not compatible with the fourth-generation double-speed synchronous dynamic random access memory iterative packaging, it cannot be verified on the current test circuit board. If the scheme, schematic diagram, PCB (Printed Circuit Board) drawing, and PCBA (Printed Circuit Board Assembly) production are redesigned, it will take a lot of time and cost. Therefore, how to test the new memory based on the current test circuit board should be the focus of technical personnel in this field. Summary of the invention

[0005] The purpose of the present invention is to provide a test conversion component and a test system to achieve the debugging of the device under test by using the current target test circuit board, without designing a new test circuit board for the device under test, thus saving time and cost.

[0006] In order to solve the above technical problems, the present invention provides a test conversion component, comprising:

[0007] substrate;

[0008] A first test package array located on the first surface of the substrate is used to be electrically connected to a target test circuit board; the first test package array includes a plurality of first contacts; the target test circuit board is used to test the current device;

[0009] A second test package array and peripheral circuits are located on the second surface of the substrate, the second test package array is used to be electrically connected to the device under test; the second test package array includes a plurality of second contacts, the peripheral circuit includes a circuit element, the circuit element is electrically connected to a signal network of the device under test that is different from the current device, and a signal line in the signal network is electrically connected to the second contact;

[0010] The first surface and the second surface are two opposite surfaces of the substrate.

[0011] As an implementable embodiment, when the current device is a fourth-generation double-speed synchronous dynamic random access memory and the device under test is a fifth-generation double-speed synchronous dynamic random access memory, the signal network includes: a command address mirror signal line, a command address on-chip terminal signal line and a command address signal flip signal line.

[0012] As an implementable embodiment, the signal network includes a command address mirror signal line, and the circuit element includes a first pull-up resistor and a first pull-down resistor;

[0013] A first end of the first pull-up resistor is connected to the command address mirror signal line, and a second end of the first pull-up resistor is connected to a power supply;

[0014] A first end of the first pull-down resistor is connected to the command address mirror signal line, and a second end of the first pull-up resistor is grounded.

[0015] As an implementable embodiment, the signal network includes a command address on-chip terminal signal line, and the circuit element includes a second pull-up resistor and a second pull-down resistor;

[0016] A first end of the second pull-up resistor is connected to the command address on-chip terminal signal line, and a second end of the second pull-up resistor is connected to a power supply;

[0017] A first end of the second pull-down resistor is connected to the command address on-chip terminal signal line, and a second end of the second pull-up resistor is grounded.

[0018] As an implementable embodiment, the network includes a command address mirror signal line, and the circuit element includes a third pull-up resistor and a third pull-down resistor;

[0019] A first end of the third pull-up resistor is connected to the command address mirror signal line, and a second end of the third pull-up resistor is connected to a power supply;

[0020] A first end of the third pull-down resistor is connected to the command address mirror signal line, and a second end of the third pull-up resistor is grounded.

[0021] As an implementable embodiment, it also includes:

[0022] A loopback test point is provided at a side end of the second test package array.

[0023] As an implementable embodiment, the loopback test point includes a loopback data signal test point and a loopback data clock signal test point.

[0024] As an implementable embodiment, the fourth-generation double rate synchronous dynamic random access memory and the fifth-generation double rate synchronous dynamic random access memory include a double rate address signal, a double rate data signal, a double rate clock signal, a double rate data selection signal, a double rate alarm signal, a double rate reset signal, and a double rate chip select signal, wherein the number of the double rate address signals is 14, the number of the double rate data signals is 8, the number of the double rate clock signals is 2, the number of the double rate data selection signals is 2, the number of the double rate alarm signal is 1, the number of the double rate reset signal is 1, and the number of the double rate chip select signal is 1;

[0025] The signal interfaces of the double rate address signal, the double rate data signal, the double rate clock signal, the double rate data select signal, the double rate alarm signal, the double rate reset signal and the double rate chip select signal in the fifth generation double rate synchronous dynamic random access memory are connected to the signal interfaces of the double rate address signal, the double rate data signal, the double rate clock signal, the double rate data select signal, the double rate alarm signal, the double rate reset signal and the double rate chip select signal in the fourth generation double rate synchronous dynamic random access memory.

[0026] As an implementation method, a projection of the first surface of the substrate on a horizontal plane is located within a range of a projection of the second surface of the substrate on a horizontal plane.

[0027] The present invention also provides a test system, comprising any one of the test conversion components described above.

[0028] A test conversion component provided by the present invention includes a substrate; a first test package array located on the first surface of the substrate, which is used to be electrically connected to a target test circuit board; the first test package array includes a plurality of first contacts; the target test circuit board is used to test a current device; a second test package array and peripheral circuits located on the second surface of the substrate, the second test package array is used to be electrically connected to a device to be tested; the second test package array includes a plurality of second contacts, the peripheral circuits include circuit elements, the circuit elements are electrically connected to a signal network of the device to be tested that is different from the current device, and the signal lines in the signal network are electrically connected to the second contacts; the first surface and the second surface are two opposite surfaces of the substrate.

[0029] It can be seen that the test conversion component in the present invention includes a substrate, a first test package array is provided on the first surface of the substrate, and a second test package array and peripheral circuits are provided on the second surface of the substrate. Since the signal networks of the device to be tested and the current device are different, the signal lines in the redundant signal network of the device to be tested compared to the current device are electrically connected to the second contact, that is, the signal lines different from the current device are led out to the second surface of the substrate, and at the same time, the redundant signals can be debugged through circuit elements to make the corresponding connection between the device to be tested and the second contact. Since the first test package array can be directly electrically connected to the target test circuit board used for testing the current device, when the device to be tested is connected to the second test package array of the substrate through the test conversion component, the connection between the device to be tested and the target test circuit board can be realized, thereby realizing the debugging of the device to be tested using the current target test circuit board, without the need to design a new test circuit board for the device to be tested, saving time and cost.

[0030] In addition, the present invention also provides a testing system having the above advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A side view of a substrate provided by an embodiment of the present invention Figure 1 ;

[0033] Figure 2 A top view of a substrate provided by an embodiment of the present invention;

[0034] Figure 3A bottom view of a substrate provided by an embodiment of the present invention Figure 1 ;

[0035] Figure 4 A bottom view of a substrate provided by an embodiment of the present invention Figure 2 ;

[0036] Figure 5 A side view of a substrate provided by an embodiment of the present invention Figure 2 ;

[0037] Figures 6 to 9 A schematic diagram of a second surface side of a substrate provided by an embodiment of the present invention;

[0038] Fig.10 A schematic diagram of a first surface side of a substrate provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0040] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0041] As mentioned in the background technology section, different types of memory iterative packaging are not compatible and cannot be verified on the current test circuit board. Redesigning the scheme, schematic, PCB drawing, and PCBA production will cost a lot of time.

[0042] In view of this, the present invention provides a test conversion component, please refer to Figures 1 to 3 , which may include:

[0043] substrate1;

[0044] A first test package array located on the first surface 1a of the substrate 1 is used to be electrically connected to a target test circuit board; the first test package array includes a plurality of first contacts 11; the target test circuit board is used to test the current device;

[0045] A second test package array and peripheral circuits are located on the second surface 1b of the substrate 1, the second test package array is used to be electrically connected to the device under test; the second test package array includes a plurality of second contacts 12, the peripheral circuit includes a circuit element 2, the circuit element 2 is electrically connected to a signal network of the device under test that is different from the current device, and a signal line in the signal network is electrically connected to the second contact 12;

[0046] The first surface 1 a and the second surface 1 b are two opposite surfaces of the substrate 1 .

[0047] The substrate 1 may be a PCB board. When the substrate 1 is placed horizontally, the first surface 1a and the second surface 1b of the substrate 1 may be the upper surface and the lower surface of the substrate 1, respectively. For example, when the first surface 1a of the substrate 1 is the lower surface, the second surface 1b of the substrate 1 is the upper surface; when the first surface 1a of the substrate 1 is the upper surface, the second surface 1b of the substrate 1 is the lower surface.

[0048] The first test package array includes a first contact 11 and a first placeholder 13, wherein the first placeholder 13 is a position without a contact. It should be noted that the number of the first contacts 11 is not limited in this embodiment and depends on the situation. For example, Figure 2 In the figure, the number of the first contacts 11 is 78 as an example.

[0049] The first contact 11 may be a solder ball, such as a tin ball, etc., which is not specifically limited in this embodiment.

[0050] The first test package array may be presented in the form of M×N. It should be noted that the size of the first test package array is not limited in this embodiment and depends on the situation. For example, the first test package array may be distributed in the form of 13×9. Figure 2 shown.

[0051] The target test circuit board is an existing one designed for testing the current device.

[0052] The second test package array includes a second contact 12 and a second placeholder 14, wherein the second placeholder 14 is a position without a contact. It should be noted that the number of the second contacts 12 is not limited in this embodiment and depends on the situation. For example, Figure 3 In the figure, the number of the second contacts 12 is 82 as an example.

[0053] The second test package array may be presented in the form of J×K. It should be noted that the size of the second test package array is not limited in this embodiment and depends on the situation. For example, the second test package array may be distributed in the form of 13×11, such as Figure 3 shown.

[0054] The second contact 12 may be a solder ball, such as a tin ball, etc., which is not specifically limited in this embodiment.

[0055] Due to the differences between the device under test and the current device, the device under test may contain signals that do not exist in the current device. Of course, the current device may also contain signals that do not exist in the device under test. At the same time, the device under test and the current device may also contain signals of the same type.

[0056] The current device may include multiple signals, and the signal lines corresponding to the signals are electrically connected to the first contact 11 . The device under test may include multiple signals, and the signal lines corresponding to the signals are electrically connected to the second contact 12 .

[0057] The same signals of the device under test and the current device can be connected, that is, the corresponding first contact 11 and second contact 12 can be connected.

[0058] For signals that exist in the current device but not in the device under test, simply leave them floating without connecting them to the signal network.

[0059] For signals existing in the device under test but not in the current device, debugging is usually required, which can be performed by setting peripheral circuits. The circuit element 2 in the peripheral circuit is connected to a signal network existing in the device under test but not in the current device.

[0060] It should be noted that in this embodiment, the structure of the peripheral circuit and the type of the circuit element 2 in the peripheral circuit are not specifically limited and depend on the situation.

[0061] It should also be noted that the current device and the device under test are not limited in this embodiment, and it depends on the situation. For example, the current device may be a fourth-generation double data rate synchronous dynamic random access memory, and the device under test may be a fifth-generation double data rate synchronous dynamic random access memory, a sixth-generation double data rate synchronous dynamic random access memory, and so on.

[0062] In this embodiment, the test conversion component includes a substrate 1, a first test package array is provided on the first surface 1a of the substrate 1, and a second test package array and peripheral circuits are provided on the second surface 1b of the substrate 1. Since the signal networks of the device under test and the current device are different, the signal lines in the redundant signal network of the device under test compared with the current device are electrically connected to the second contact 12, that is, the signal lines different from the current device are led out to the second surface 1b of the substrate 1, and the redundant signals can be debugged through the circuit element 2 to make the corresponding connection between the device under test and the second contact 12. Since the first test package array can be directly electrically connected to the target test circuit board used for testing the current device, when the device under test is connected to the second test package array of the substrate 1 through the test conversion component, the connection between the device under test and the target test circuit board can be realized, thereby realizing the debugging of the device under test using the current target test circuit board, without the need to design a new test circuit board for the device under test, saving time and cost.

[0063] On the basis of the above embodiments, in one embodiment of the present invention, when the current device is a fourth-generation double data rate synchronous dynamic random access memory and the device to be tested is a fifth-generation double data rate synchronous dynamic random access memory, the test conversion component may include

[0064] substrate1;

[0065] A first test package array located on the first surface 1a of the substrate 1 is used to be electrically connected to a target test circuit board; the first test package array includes a plurality of first contacts 11; the target test circuit board is used to test the current device;

[0066] A second test package array and peripheral circuits are located on the second surface 1b of the substrate 1, the second test package array is used to be electrically connected to the device under test; the second test package array includes a plurality of second contacts 12, the peripheral circuit includes a circuit element 2, the circuit element 2 is electrically connected to a signal network of the device under test that is different from the current device, and a signal line in the signal network is electrically connected to the second contact 12;

[0067] The first surface 1a and the second surface 1b are two opposite surfaces of the substrate 1;

[0068] The signal network includes: a command address mirror signal line, a command address on-chip terminal signal line and a command address signal flip signal line.

[0069] The command address mirror signal (MIR signal for short) is a new signal used to improve the signal integrity of the memory module. The command address mirror signal allows the pins of the command / address (CA) bus to be swapped at the physical level, which can reduce the wiring length between the DRAM chips on the front and back sides of the memory module, thereby reducing the stub length and optimizing the signal transmission quality.

[0070] Specifically, when the command address mirror signal is set high, the fifth-generation double-rate synchronous dynamic random access memory will swap the even-numbered CA pin with the next odd-numbered CA pin. This swap is symmetrical, that is, CA2 is swapped with CA3 (rather than with CA1), CA4 is swapped with CA5, and so on. This design allows memory module designers to have more flexibility in layout, especially when designing "clamshell" modules, where dynamic random access memory chips can be arranged on the front and back of the module without worrying about the wiring of the CA bus.

[0071] The command address mirror signal function also helps reduce noise and interference in signal transmission because it reduces the required stub length. A stub is a small section in the signal wiring. Its presence increases signal reflection and attenuation, affecting signal integrity. With the command address mirror signal function, the length of the stub can be minimized, thereby improving signal stability and reliability.

[0072] In general, command address mirror signals optimize signal paths through internal pin swapping, reduce routing complexity, and improve signal integrity and performance.

[0073] The Command Address On-die Termination (CA OTD) signal allows the address / command / control (CA) signals to be terminated inside the memory chip. This termination can be adjusted inside the chip to optimize signal integrity and reduce reflections, thereby improving the performance of the memory interface.

[0074] In the fifth generation of double rate synchronous dynamic random access memory, CA signals include command and address signals, which share a set of buses. These signals are critical to memory operation because they tell the memory which operations to perform. The OTD function allows these signals to be properly terminated inside the chip, which can reduce reflection and attenuation during signal transmission and improve signal stability and reliability.

[0075] The operation of the command address on-chip termination signal can be controlled by specific mode register settings. These settings allow the system to adjust the resistance of the OTD according to the specific memory configuration and performance requirements. For example, the CA_OTD pin can be grounded to a fixed VSS (Voltage Series, ground terminal voltage) or connected to a fixed VDD (Voltage Designated Drain, power supply voltage) on the DIMM (Dual In-line Memory Module) or system board to select different ODT setting groups (Group A or Group B).

[0076] The command address on-chip termination signal allows the memory controller to set different termination resistors depending on the configuration of the DRAM on the DIMM or system board. The CA ODT pin is used to distinguish the ODT settings of the two groups of CA / CS / CK, which are called "Group A" when the CA_ODT pin is grounded and "Group B" when the CA_ODT pin is turned on. Typically, Group A devices apply weaker termination settings, while Group B devices (located at the end of the fly-by routing on the DIMM) apply stronger termination settings. This design helps optimize signal integrity and reduce reflection noise.

[0077] In summary, the command address on-chip termination signal is a key feature in the fifth-generation double-rate synchronous dynamic random access memory design, which helps to improve the performance and reliability of the memory interface.

[0078] Command Address Inversion (CAI) When the CAI pin is connected to VDDQ, the DRAM internally inverts the logic levels on all command / address (CA) signals. If CA inversion is not required, the CAI pin must be connected to VSSQ.

[0079] The command address signal inversion function allows the current consumption of signal transmission to be optimized by inverting the logic level on the command and address lines in specific operations, thereby improving energy efficiency. For example, if the main transmission in an operation is logic 0, the current consumption of the bus can be reduced through the CAI function, which is very beneficial for improving the energy efficiency of the system and extending battery life.

[0080] Based on any of the above embodiments, in one embodiment of the present invention, when the current device is a fourth-generation double data rate synchronous dynamic random access memory and the device to be tested is a fifth-generation double data rate synchronous dynamic random access memory, the test conversion component may include

[0081] substrate1;

[0082] A first test package array located on the first surface 1a of the substrate 1 is used to be electrically connected to a target test circuit board; the first test package array includes a plurality of first contacts 11; the target test circuit board is used to test the current device;

[0083] A second test package array and peripheral circuits are located on the second surface 1b of the substrate 1, the second test package array is used to be electrically connected to the device under test; the second test package array includes a plurality of second contacts 12, the peripheral circuit includes a circuit element 2, the circuit element 2 is electrically connected to a signal network of the device under test that is different from the current device, and a signal line in the signal network is electrically connected to the second contact 12;

[0084] The first surface 1a and the second surface 1b are two opposite surfaces of the substrate 1;

[0085] The signal network includes: a command address mirror signal line, a command address on-chip terminal signal line, and a command address signal flip signal line;

[0086] The circuit element 2 includes a first pull-up resistor 21 and a first pull-down resistor 22;

[0087] A first end of the first pull-up resistor 21 is connected to the command address mirror signal line, and a second end of the first pull-up resistor 21 is connected to the power supply;

[0088] A first end of the first pull-down resistor 22 is connected to the command address mirror signal line, and a second end of the first pull-up resistor 21 is grounded.

[0089] The function of the first pull-up resistor 21 is to make the pin high level at ordinary times, and the function of the first pull-down resistor 22 is to make the pin low level at ordinary times.

[0090] The command address mirror signal line and the first pull-up resistor 21 and the first pull-down resistor 22 can debug the command address mirror signal. The power supply of the first pull-up resistor 21 can be selected as VDD 1.1V.

[0091] Based on any of the above embodiments, in one embodiment of the present invention, when the current device is a fourth-generation double data rate synchronous dynamic random access memory and the device to be tested is a fifth-generation double data rate synchronous dynamic random access memory, the test conversion component may include

[0092] substrate1;

[0093] A first test package array located on the first surface 1a of the substrate 1 is used to be electrically connected to a target test circuit board; the first test package array includes a plurality of first contacts 11; the target test circuit board is used to test the current device;

[0094] A second test package array and peripheral circuits are located on the second surface 1b of the substrate 1, the second test package array is used to be electrically connected to the device under test; the second test package array includes a plurality of second contacts 12, the peripheral circuit includes a circuit element 2, the circuit element 2 is electrically connected to a signal network of the device under test that is different from the current device, and a signal line in the signal network is electrically connected to the second contact 12;

[0095] The first surface 1a and the second surface 1b are two opposite surfaces of the substrate 1;

[0096] The signal network includes: a command address mirror signal line, a command address on-chip terminal signal line, and a command address signal flip signal line;

[0097] The circuit element 2 includes a first pull-up resistor 21 and a first pull-down resistor 22, a second pull-up resistor 23 and a second pull-down resistor 24;

[0098] A first end of the first pull-up resistor 21 is connected to the command address mirror signal line, and a second end of the first pull-up resistor 21 is connected to the power supply;

[0099] A first end of the first pull-down resistor 22 is connected to the command address mirror signal line, and a second end of the first pull-up resistor 21 is grounded;

[0100] A first end of the second pull-up resistor 23 is connected to the command address chip terminal signal line, and a second end of the second pull-up resistor 23 is connected to the power supply;

[0101] A first end of the second pull-down resistor 24 is connected to the command address on-chip terminal signal line, and a second end of the second pull-up resistor 23 is grounded.

[0102] The second pull-up resistor 23 is used to normally use the pin at a high level, and the second pull-down resistor 24 is used to normally make the pin at a low level.

[0103] The command address chip terminal signal line and the second pull-up resistor 23 and the second pull-down resistor 24 can debug the command address chip terminal signal. The power supply of the second pull-up resistor 23 can be selected as VDD 1.1V.

[0104] Please refer to Figure 4 Based on any of the above embodiments, in one embodiment of the present invention, when the current device is a fourth-generation double data rate synchronous dynamic random access memory and the device to be tested is a fifth-generation double data rate synchronous dynamic random access memory, the test conversion component may include

[0105] substrate1;

[0106] A first test package array located on the first surface 1a of the substrate 1 is used to be electrically connected to a target test circuit board; the first test package array includes a plurality of first contacts 11; the target test circuit board is used to test the current device;

[0107] A second test package array and peripheral circuits are located on the second surface 1b of the substrate 1, the second test package array is used to be electrically connected to the device under test; the second test package array includes a plurality of second contacts 12, the peripheral circuit includes a circuit element 2, the circuit element 2 is electrically connected to a signal network of the device under test that is different from the current device, and a signal line in the signal network is electrically connected to the second contact 12;

[0108] The first surface 1a and the second surface 1b are two opposite surfaces of the substrate 1;

[0109] The signal network includes: a command address mirror signal line, a command address on-chip terminal signal line, and a command address signal flip signal line;

[0110] The circuit element 2 includes a first pull-up resistor 21 and a first pull-down resistor 22, a second pull-up resistor 23 and a second pull-down resistor 24, a third pull-up resistor 25 and a third pull-down resistor 26;

[0111] A first end of the first pull-up resistor 21 is connected to the command address mirror signal line, and a second end of the first pull-up resistor 21 is connected to the power supply;

[0112] A first end of the first pull-down resistor 22 is connected to the command address mirror signal line, and a second end of the first pull-up resistor 21 is grounded;

[0113] A first end of the second pull-up resistor 23 is connected to the command address chip terminal signal line, and a second end of the second pull-up resistor 23 is connected to the power supply;

[0114] A first end of the second pull-down resistor 24 is connected to the command address chip terminal signal line, and a second end of the second pull-up resistor 23 is grounded;

[0115] A first end of the third pull-up resistor 25 is connected to the command address mirror signal line, and a second end of the third pull-up resistor 25 is connected to the power supply;

[0116] A first end of the third pull-down resistor 26 is connected to the command address mirror signal line, and a second end of the third pull-up resistor 25 is grounded.

[0117] The function of the third pull-up resistor 25 is to make the pin high level at normal times, and the function of the third pull-down resistor 26 is to make the pin low level at normal times.

[0118] The command address mirror signal line and the third pull-up resistor 25 and the third pull-down resistor 26 can debug the command address mirror signal. The power supply of the third pull-up resistor 25 can be selected as VDD 1.1V.

[0119] Please refer to Figure 4 Based on any of the above embodiments, in one embodiment of the present invention, when the current device is a fourth-generation double data rate synchronous dynamic random access memory and the device to be tested is a fifth-generation double data rate synchronous dynamic random access memory, the test conversion component may include

[0120] substrate1;

[0121] A first test package array located on the first surface 1a of the substrate 1 is used to be electrically connected to a target test circuit board; the first test package array includes a plurality of first contacts 11; the target test circuit board is used to test the current device;

[0122] A second test package array and peripheral circuits located on the second surface 1b of the substrate 1, and a loopback test point 3 provided at the side end of the second test package array; the second test package array is used to be electrically connected to the device under test; the second test package array includes a plurality of second contacts 12, the peripheral circuits include a circuit element 2, the circuit element 2 is electrically connected to a signal network of the device under test that is different from the current device, and a signal line in the signal network is electrically connected to the second contact 12;

[0123] The first surface 1a and the second surface 1b are two opposite surfaces of the substrate 1;

[0124] The signal network includes: a command address mirror signal line, a command address on-chip terminal signal line, and a command address signal flip signal line;

[0125] The circuit element 2 includes a first pull-up resistor 21 and a first pull-down resistor 22, a second pull-up resistor 23 and a second pull-down resistor 24, a third pull-up resistor 25 and a third pull-down resistor 26;

[0126] A first end of the first pull-up resistor 21 is connected to the command address mirror signal line, and a second end of the first pull-up resistor 21 is connected to the power supply;

[0127] A first end of the first pull-down resistor 22 is connected to the command address mirror signal line, and a second end of the first pull-up resistor 21 is grounded;

[0128] A first end of the second pull-up resistor 23 is connected to the command address chip terminal signal line, and a second end of the second pull-up resistor 23 is connected to the power supply;

[0129] A first end of the second pull-down resistor 24 is connected to the command address chip terminal signal line, and a second end of the second pull-up resistor 23 is grounded;

[0130] A first end of the third pull-up resistor 25 is connected to the command address mirror signal line, and a second end of the third pull-up resistor 25 is connected to the power supply;

[0131] A first end of the third pull-down resistor 26 is connected to the command address mirror signal line, and a second end of the third pull-up resistor 25 is grounded.

[0132] It should be noted that in this embodiment, the type of loopback test point is not limited and depends on the situation.

[0133] In one embodiment of the present invention, the loopback test point 3 may include a loopback data signal test point 31 and a loopback data clock signal test point 32 .

[0134] The loopback data signal (DDR_LBDQ) is related to the loopback function and is used to return the received data directly to the transmitter in loopback mode. The loopback data signal helps to evaluate the signal integrity of the entire link during testing.

[0135] The loopback data clock signal (DDR_LBDQS) is related to the loopback function and is used to synchronize the output of the loopback data in the loopback mode. The loopback mode allows the fifth-generation double-rate synchronous dynamic random access memory to send the received data directly without being affected by the read and write commands. It is mainly used to test the signal quality of the link.

[0136] The loopback data signal and the loopback data clock signal allow for more efficient testing and help ensure the reliability and performance of the memory modules at high speeds.

[0137] Based on any of the above embodiments, in one embodiment of the present invention, the test conversion component includes:

[0138] substrate1;

[0139] A first test package array located on the first surface 1a of the substrate 1 is used to be electrically connected to a target test circuit board; the first test package array includes a plurality of first contacts 11; the target test circuit board is used to test the current device;

[0140] A second test package array and peripheral circuits are located on the second surface 1b of the substrate 1, the second test package array is used to be electrically connected to the device under test; the second test package array includes a plurality of second contacts 12, the peripheral circuit includes a circuit element 2, the circuit element 2 is electrically connected to a signal network of the device under test that is different from the current device, and a signal line in the signal network is electrically connected to the second contact 12;

[0141] The first surface 1a and the second surface 1b are two opposite surfaces of the substrate 1;

[0142] The projection of the first surface 1 a of the substrate 1 on the horizontal plane overlaps with the projection of the second surface 1 b of the substrate 1 on the horizontal plane.

[0143] In this embodiment, the upper surface and the lower surface of the substrate 1 are surfaces of equal size. For example, when the substrate 1 is rectangular, the length and width of the upper surface and the lower surface of the substrate 1 are equal.

[0144] like Figure 5 As shown, based on any of the above embodiments, in one embodiment of the present invention, the test conversion component includes:

[0145] substrate1;

[0146] A first test package array located on the first surface 1a of the substrate 1 is used to be electrically connected to a target test circuit board; the first test package array includes a plurality of first contacts 11; the target test circuit board is used to test the current device;

[0147] A second test package array and peripheral circuits are located on the second surface 1b of the substrate 1, the second test package array is used to be electrically connected to the device under test; the second test package array includes a plurality of second contacts 12, the peripheral circuit includes a circuit element 2, the circuit element 2 is electrically connected to a signal network of the device under test that is different from the current device, and a signal line in the signal network is electrically connected to the second contact 12;

[0148] The first surface 1a and the second surface 1b are two opposite surfaces of the substrate 1;

[0149] The projection of the first surface 1 a of the substrate 1 on the horizontal plane is located within the range of the projection of the second surface 1 b of the substrate 1 on the horizontal plane.

[0150] In this embodiment, the projection of the first surface 1a of the substrate 1 on the horizontal plane is smaller than the projection of the second surface 1b on the horizontal plane, that is, the substrate 1 adopts a layered design, and the position close to the fifth-generation double-speed synchronous dynamic random access memory (the second surface 1b) is relatively wide, and the position close to the fourth-generation double-speed synchronous dynamic random access memory (the first surface 1a) is relatively narrow. Because the size of the fifth-generation double-speed synchronous dynamic random access memory is larger than that of the fourth-generation double-speed synchronous dynamic random access memory, such a design can reduce the possibility of interference with surrounding electronic devices.

[0151] like Figures 6 to 10As shown, on the basis of any of the above embodiments, in one embodiment of the present invention, when the current device is a fourth-generation double rate synchronous dynamic random access memory and the device to be tested is a fifth-generation double rate synchronous dynamic random access memory, the fourth-generation double rate synchronous dynamic random access memory and the fifth-generation double rate synchronous dynamic random access memory include double rate address signals, double rate data signals, double rate clock signals, double rate data selection signals, double rate alarm signals, double rate reset signals, and double rate chip select signals, wherein the number of double rate address signals is 14, the number of double rate data signals is 8, the number of double rate clock signals is 2, the number of double rate data selection signals is 2, the number of double rate alarm signals is 1, the number of double rate reset signals is 1, and the number of double rate chip select signals is 1;

[0152] The signal interfaces of the double rate address signal, double rate data signal, double rate clock signal, double rate data select signal, double rate alarm signal, double rate reset signal and double rate chip select signal in the fifth generation double rate synchronous dynamic random access memory are connected to the signal interfaces of the double rate address signal, double rate data signal, double rate clock signal, double rate data select signal, double rate alarm signal, double rate reset signal and double rate chip select signal in the fourth generation double rate synchronous dynamic random access memory.

[0153] The 14 double rate address signals (DDR A) can be recorded as DDR A 00, DDR A 01, DDR A 02, …, DDR A 12, DDR A 13. The 8 double rate data signals (DDR DQ) can be recorded as DDR DQ 00, DDR DQ01, …, DDR DQ 06, DDR A07. The 2 double rate clock signals (DDR CLK) can be recorded as DDR CLK0 DP and DDR CLK0 DN. The 1 double rate alarm signal (DDR ALERT) can be recorded as DDR ALERT N. The 1 double rate reset signal (DDR RST) can be recorded as DDR RST N. The 1 double rate chip select signal (DDR CS0) can be recorded as DDR CS0 N.

[0154] Taking the double rate address signal as an example, the signal line connection of the same signal in the fourth generation double rate synchronous dynamic random access memory and the fifth generation double rate synchronous dynamic random access memory is explained. Figure 6 The fifth generation of double data rate synchronous dynamic random access memory DDR A 00 and Fig.10 The fourth generation of double data rate synchronous dynamic random access memory DDR A 00 connection, Figure 6 The fifth generation of double data rate synchronous dynamic random access memory DDR A 01 and Fig.10 The DDR A 01 connection in the fourth-generation double-data-rate synchronous dynamic random access memory, and so on.

[0155] It should be pointed out that some fourth-generation double-speed synchronous dynamic random access memory networks have no corresponding networks in the fifth-generation double-speed synchronous dynamic random access memory particles, such as ALE (Address Latch Enable) and CLE (Command Latch Enable), which are directly left floating without connecting to the network.

[0156] It should also be noted that since the power supply voltage of the fourth-generation double-rate synchronous dynamic random access memory is higher than that of the fifth-generation double-rate synchronous dynamic random access memory, it is necessary to use a voltage divider resistor to generate the power supply voltage required by the fifth-generation double-rate synchronous dynamic random access memory from the fourth-generation double-rate synchronous dynamic random access memory to provide power for the fifth-generation double-rate synchronous dynamic random access memory.

[0157] The schematic diagram of the power supply voltage required for the fifth generation double rate synchronous dynamic random access memory is shown in Figure 7 shown.

[0158] Figures 6 to 9 Located on the second surface 1b side of the substrate 1, Fig.10 Located on the first surface 1 a side of the substrate 1 .

[0159] Figure 7 and Figure 6 , Fig.10 The endpoints of the same label in are connected together. For example, Figure 6 P1V1 DRAM and Figure 7 The P1V1 DRAMs in the Figure 7 P2V5 DRAM and Fig.10 The P2V5 DRAMs in the are connected together.

[0160] Figure 6 and Figure 8 , Fig. 9 The endpoints with the same label in are connected together, for example Figure 6 DDR MIR0 and Figure 8 DDRMIR0 is connected together, Figure 6 DDR CA ODT0 and Figure 8 DDR CA ODT0 are connected together, Figure 6 DDR CAI and Figure 8DDR CAI is connected together, Fig. 9 DDR LBDQ0 and Figure 6 DDR LBDQ0 are connected together, Fig. 9 DDR LBDQS0 and Figure 6 DDR LBDQS0 are connected together.

[0161] In one embodiment of the present invention, interfaces of the same signal in a fourth-generation double data rate synchronous dynamic random access memory and a fifth-generation double data rate synchronous dynamic random access memory are connected by pin-to-pin connection, which has the following advantages: it can reduce additional circuit elements, simplify the design, and reduce costs; it can make the signal transmission path as short as possible, and can reduce the delay of signal transmission.

[0162] The present invention also provides a test system, which includes the test conversion component of any one of the above embodiments.

[0163] It can be understood that the test system further includes a target test circuit board, and the first test package array on the first surface of the test conversion component is electrically connected to the target test circuit board.

[0164] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0165] The test conversion component and the test system provided by the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A test conversion component, characterized in that: include: substrate; a first test package array located on a first surface of the substrate, for electrically connecting to a target test circuit board; The first test package array includes a plurality of first contacts; the target test circuit board is used to test the current device; A second test package array and peripheral circuits located on a second surface of the substrate, wherein the second test package array is used to be electrically connected to the device under test; The second test package array includes a plurality of second contacts, the peripheral circuit includes a circuit element, the circuit element is electrically connected to a signal network of the device under test that is different from the current device, and a signal line in the signal network is electrically connected to the second contact; The first surface and the second surface are two opposite surfaces of the substrate.

2. The test conversion component according to claim 1, characterized in that: When the current device is a fourth-generation double-rate synchronous dynamic random access memory and the device under test is a fifth-generation double-rate synchronous dynamic random access memory, the signal network includes: a command address mirror signal line, a command address on-chip terminal signal line and a command address signal flip signal line.

3. The test conversion component according to claim 2, characterized in that: The signal network includes a command address mirror signal line, and the circuit element includes a first pull-up resistor and a first pull-down resistor; A first end of the first pull-up resistor is connected to the command address mirror signal line, and a second end of the first pull-up resistor is connected to a power supply; A first end of the first pull-down resistor is connected to the command address mirror signal line, and a second end of the first pull-up resistor is grounded.

4. The test conversion component according to claim 2, characterized in that: The signal network includes a command address on-chip terminal signal line, and the circuit element includes a second pull-up resistor and a second pull-down resistor; A first end of the second pull-up resistor is connected to the command address on-chip terminal signal line, and a second end of the second pull-up resistor is connected to a power supply; A first end of the second pull-down resistor is connected to the command address on-chip terminal signal line, and a second end of the second pull-up resistor is grounded.

5. The test conversion component according to claim 2, characterized in that: The network includes a command address mirror signal line, and the circuit element includes a third pull-up resistor and a third pull-down resistor; A first end of the third pull-up resistor is connected to the command address mirror signal line, and a second end of the third pull-up resistor is connected to a power supply; A first end of the third pull-down resistor is connected to the command address mirror signal line, and a second end of the third pull-up resistor is grounded.

6. The test conversion component according to claim 2, characterized in that: Also includes: A loopback test point is provided at a side end of the second test package array.

7. The test conversion component according to claim 6, characterized in that: The loopback test points include a loopback data signal test point and a loopback data clock signal test point.

8. The test conversion component according to claim 2, characterized in that: The fourth-generation double rate synchronous dynamic random access memory and the fifth-generation double rate synchronous dynamic random access memory include double rate address signals, double rate data signals, double rate clock signals, double rate data strobe signals, double rate alarm signals, double rate reset signals, and double rate chip select signals, wherein the number of the double rate address signals is 14, the number of the double rate data signals is 8, the number of the double rate clock signals is 2, the number of the double rate data strobe signals is 2, the number of the double rate alarm signals is 1, the number of the double rate reset signals is 1, and the number of the double rate chip select signals is 1; The signal interfaces of the double rate address signal, the double rate data signal, the double rate clock signal, the double rate data select signal, the double rate alarm signal, the double rate reset signal and the double rate chip select signal in the fifth generation double rate synchronous dynamic random access memory are connected to the signal interfaces of the double rate address signal, the double rate data signal, the double rate clock signal, the double rate data select signal, the double rate alarm signal, the double rate reset signal and the double rate chip select signal in the fourth generation double rate synchronous dynamic random access memory.

9. The test conversion component according to any one of claims 1 to 8, characterized in that: A projection of the first surface of the substrate on a horizontal plane is located within a range of a projection of the second surface of the substrate on a horizontal plane.

10. A testing system, characterized in that: The method comprises a test conversion component as claimed in any one of claims 1 to 9.

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