Relay protection outlet control loop intelligent diagnosis device

Abstract

The invention provides an intelligent diagnosis device for a relay protection outlet control loop, which comprises a host and an acquisition box, the host communicates with the acquisition box through an optical Ethernet port communication circuit, the acquisition box is provided with a sub-controller and a plurality of strong current input quantity input circuits and weak current input quantity input circuits which are electrically connected with the sub-controller, and the strong current input quantity input circuits and the weak current input quantity input circuits are electrically connected with the sub-controller. The sub-controller is electrically connected with an optical B code receiving circuit and a power supply circuit, the host comprises a main controller, and a voltage acquisition sampling circuit and an electric B code transmitting and receiving circuit which are electrically connected with the main controller, and the acquisition box acquires various voltage signals of a relay protection outlet control loop and transmits the voltage signals to the host. And the host performs sampling display on various voltage signals by using the voltage sampling circuit. According to the invention, each input jump is collected and is compared according to a time sequence.

Description

Technical Field

[0001] The invention relates to the technical field, and in particular to an intelligent diagnosis device for a relay protection output control loop. Background Art

[0002] The tripping and closing circuit of the high-voltage circuit breaker is the final protection circuit in the power system control, so the monitoring of the tripping and closing circuit is very important. At present, there are roughly four monitoring methods for the tripping and closing circuit of the circuit breaker at home and abroad: direct monitoring using a simple and intuitive traffic light circuit; indirect monitoring using the normally closed contacts of the tripping and closing position relay in series to start the central signal; monitoring the integrity signal light of the tripping and closing circuit in the closed state; indirect monitoring using a high internal resistance relay in series with the tripping circuit. However, the above four methods can only monitor the on-off state of the circuit breaker tripping and closing circuit, and cannot perform jump comparison and time measurement of each input quantity. Therefore, when the cable fault causes abnormal current in the tripping and closing circuit, the fault point cannot be located, and the operation and maintenance personnel cannot be reminded to take remedial measures. Summary of the invention

[0003] The present invention solves the problem that the prior art can only monitor the on / off state of the circuit breaker tripping and closing circuit, and proposes an intelligent diagnosis device for a relay protection output control circuit, which collects the jumps of various input quantities and compares the jumps of various input quantities in a time sequence.

[0004] In order to achieve the above objectives, the following technical solutions are proposed: A relay protection outlet control circuit intelligent diagnosis device comprises a host and a collection box, wherein the host communicates with the collection box through an optical Ethernet port communication circuit, the collection box is provided with a sub-controller and a plurality of strong current binary input circuits and weak current binary input circuits electrically connected to the sub-controller, the sub-controller is electrically connected to an optical B code receiving circuit and a power supply circuit, the host comprises a main controller and a voltage collection sample circuit and an electrical B code transceiver circuit electrically connected to the main controller, the collection box collects various voltage signals of the relay protection outlet control circuit and transmits them to the host, and the host samples and displays various voltage signals using the voltage collection sample circuit.

[0005] The various voltage signals displayed by the host described in the present invention are used to assist on-site personnel in making intelligent judgments on the location and possible causes of control circuit defects, and to guide on-site defect elimination. At the same time, they play a teaching role in helping power practitioners identify and become proficient in secondary circuits, greatly saving time and human resources.

[0006] Preferably, the voltage acquisition sampling circuit includes a voltage divider resistor and a voltage follower, the input end of the voltage divider resistor is connected to an external interface, the output end of the voltage divider resistor is connected to the input end of the voltage follower, the output end of the voltage follower is connected to an ADC sampling chip, and the ADC sampling chip is connected to the main controller of the host through an isolation chip.

[0007] When on-site staff conduct maintenance, they will measure the ground potential at the test terminal at the key position of the control loop. Therefore, it is necessary to sample and quantify the potential of the test point. Taking into account various possible access situations and the actual ideal voltage range, the voltage input range is finally determined to be -250V~+250V, with a minimum resolution of 1V.

[0008] The present invention performs voltage division through a voltage-dividing resistor, and the voltage-dividing coefficient is 49:1, that is, when the input voltage is 250V, 5V is output after voltage division, and the output end of the voltage-dividing resistor is connected to a voltage follower (OP07 or others can be used) for buffering and input-output impedance conversion, and the output end of the voltage follower is linked to an ADC sampling chip (AD7606 or others can be used), and the FPGA of the host is connected to the isolation chip through the GPIO port, and the isolation chip is connected to the ADC to obtain the ADC sampling value.

[0009] Preferably, the external interface adopts an aviation plug or a 4mm red and black banana socket.

[0010] The host's external interface uses a 4mm red and black banana socket or aviation plug, where red represents the positive pole and black represents the negative pole. Use a multimeter probe or a wire with a clip to connect the banana socket to the test point.

[0011] Preferably, the interface of the high-current binary input circuit and the low-current binary input circuit adopts a 4mm red and black banana socket, and when the input ground voltage of the high-current binary input circuit is greater than 40V, the output is a high level; when the input ground voltage of the low-current binary input circuit is greater than 5V, the output is a high level.

[0012] In the high-voltage binary input circuit, the design requirement is to withstand a maximum DC voltage of 250V without burning the circuit. When the voltage of the binary input to the ground is greater than 40V, it is judged and output as a high level. The logic output of the high-voltage binary input circuit is connected to the FPGA (or CPLD, CPU, etc.) on the acquisition box side. The jump of the binary input potential is recorded and stored, and the recorded data is sent to the host side through wireless or wired communication so that the component side can view and measure the time. In the weak-voltage binary input circuit, it is required that when the voltage of the binary input to the ground is greater than 5V, it is judged and output as a high level. In terms of circuit principle, the weak-voltage binary input circuit should be similar to the strong-voltage binary input circuit, with only different circuit parameters.

[0013] Preferably, the high-voltage binary input circuit and the low-voltage binary input circuit both include a binary input pressure plate circuit and a binary input circuit, the binary input pressure plate circuit controls the on / off connection of the binary input circuit, and the binary input circuit performs binary input sampling.

[0014] Preferably, the binary input circuit comprises an input end and a common end, the input end connects the binary input pressure plate loop to a voltage regulator tube, a resistor is connected in series to the voltage regulator tube, the resistor is connected to the common end, and the resistor is connected to an optocoupler.

[0015] The specific circuit of the binary input circuit is as follows: the red end of the binary input is connected to a voltage regulator D, and then connected in series with a resistor R, and finally connected in series with an optocoupler to the common end of the binary input circuit.

[0016] The resistance R value of the high-voltage input circuit can be estimated as follows: The value of the voltage regulator D is about 38V, the optocoupler conduction current is 1mA, and the optocoupler conduction voltage drop is 2V. Then R = (110-38-2) / 1 = 70K, and the power P = 0.001*0.001*70000 = 0.07W.

[0017] The resistance R value of the high-voltage input circuit can be estimated as follows: The value of the voltage regulator D is about 3V, and other assumptions remain unchanged, R = (12-5) / 1 = 7K, power P = 0.001*0.001*7000 = 0.007W.

[0018] Preferably, the binary input pressure plate circuit includes a pressure plate switch, the pressure plate switch includes an upper end and a lower end, and the input end and the upper end of the binary input circuit are connected in parallel to the relay contact.

[0019] The sampling principle of the open-input pressure plate circuit is: when sampling the open-input quantity, the pressure plate is in the open state, the measuring point on the upper end of the pressure plate is in a suspended state, one end of the open-input circuit (red) is connected to the upper end of the pressure plate, and the other end (black) is connected to the common ground. When measuring the open-input quantity, close the relay contacts between the +110V power supply and the end point of the pressure plate (the contact closing time is generally tens of milliseconds, and it is generally disconnected at other times). At this time, the circuit loop is: +110V~relay contact~measuring point on the upper end of the pressure plate~open-input circuit red line~open-input identification circuit~open-input circuit black line~ground.

[0020] Preferably, the power supply circuit comprises a battery and a charge and discharge circuit, the battery is connected to a DC / DC module via the charge and discharge circuit, and the sub-controller is powered by the DC / DC module.

[0021] The acquisition box is an independent entity and has no power circuit connection with the host, so the acquisition box needs to have its own power supply.

[0022] Preferably, the battery is provided with 5 LEDs for displaying the remaining power. The battery pack has a designed capacity of 10000mAh, a platform voltage of 7.4V, and is expected to be usable for more than 12 hours by the collection box, and the remaining power is displayed by 5 LEDs.

[0023] Preferably, a downloader interface is provided in the acquisition box, and the FPGA program is downloaded through the downloader interface.

[0024] The beneficial effects of the present invention are: 1. Assist on-site staff to determine the location of control loop defects; 2. Intelligently analyze and judge the possible causes of failures; 3. Guide on-site maintenance personnel to quickly eliminate defects and ensure reliable operation of the power grid; 4. It plays a teaching role in helping power practitioners identify and master secondary circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a structural connection diagram of the present invention.

[0026] Figure 2 It is a schematic diagram of a voltage acquisition circuit of the present invention.

[0027] Figure 3 It is a schematic diagram of the open input pressure plate circuit of the present invention.

[0028] Figure 4 It is a schematic diagram of a binary input circuit of the present invention. DETAILED DESCRIPTION

[0029] Example: This embodiment proposes an intelligent diagnostic device for a relay protection export control circuit, which is composed of a host and a collection box. The host is improved from the DM5200 of Wuhan Kaimo Electric Co., Ltd. The collection box needs to be redeveloped, and the host and the collection box communicate through a 100M optical Ethernet port. The collection box is provided with a sub-controller, a plurality of strong current binary input circuits and weak current binary input circuits, the strong current binary input circuits and the weak current binary input circuits are electrically connected to the sub-controller, the sub-controller is electrically connected to a power supply circuit and an optical B code receiving circuit, the host includes a main controller, a voltage collection sample circuit and an electrical B code transceiver circuit, and the electrical B code transceiver circuit and the voltage collection sample circuit are electrically connected to the main controller. The acquisition box is provided with a sub-controller and several strong current input circuits and weak current input circuits electrically connected to the sub-controller, the sub-controller is electrically connected to an optical B code receiving circuit and a power supply circuit, the host includes a main controller and a voltage acquisition sample circuit and an electrical B code transceiver circuit electrically connected to the main controller, the acquisition box acquires various voltage signals of the relay protection export control circuit and transmits them to the host, and the host uses the voltage acquisition sample circuit to sample and display various voltage signals. The host mainly draws the PCB board on the original DM5200-AIN board of DM5200, and the PCB board content includes a voltage acquisition sample circuit and an electrical B code (RS-485) receiving / transmitting circuit. The main functions of the acquisition box include 25 strong current inputs, 6 weak current inputs, optical Ethernet port communication circuit, power management, sub-controller (FPGA, CPLD, single-chip microcomputer), optical B code receiving circuit and other six categories.

[0030] The acquisition box mainly includes 25-channel high-voltage input circuits, 6-channel low-voltage input circuits, optical Ethernet port communication circuits, power supply circuits, controllers (FPGA, CPLD, single-chip microcomputers) and optical B-code receiving circuits. The hardware block diagram of the acquisition box is as follows: Figure 1 As shown in the figure, the host side hardware modifies the voltage sampling circuit and retains the BM transceiver circuit in the original DM5200-AIN board, and the other parts can be deleted. The host side block diagram is as follows Figure 1 See Table 1 for the main hardware interfaces of the acquisition box and the host.

[0031] Table 1 Main hardware interfaces of tripping and closing circuit current monitor The interface features and indicators of the acquisition box and host are as follows: 1.1-channel DC voltage sampling input, minimum resolution 0.1V, measurement range -250V~+250V, this hardware function is on the host side.

[0032] 2. Add an electrical B code transceiver circuit on the host side, which is controlled by FPGA to receive or send, and uses RS-485 interface.

[0033] 3.25-way high-voltage input, can withstand a maximum voltage of 250V without damaging the circuit. When the input voltage is above 40V, it can be judged as a high level. 25 channels share a common terminal.

[0034] 4.6-way weak point binary input, when the binary input voltage is 5V, it can be judged as high level, and every 2 channels share a common terminal.

[0035] 5.1 100M optical Ethernet port, LC interface type, 62.5 / 125um multi-mode optical fiber, wavelength 1310nm, used for communication between the host and the acquisition box.

[0036] 6. Add one optical B code receiving circuit for the time synchronization of the acquisition box and for future product promotion.

[0037] 7. Battery and charging input interface, the battery uses the DM5200 battery pack of Wuhan Kaimo Electric Co., Ltd., which is a combination of 3 parallel and 2 series, with a designed capacity of 10000mAh and a platform voltage of 7.4V. It is expected to be used for more than 12 hours by the collection box, and the remaining power is displayed through 5 LEDs. The charging input interface is consistent with the DM5200 of Wuhan Kaimo Electric Co., Ltd., and the charging circuit is also consistent with the DM5200, using the same 13.4V / 4A power adapter.

[0038] When on-site staff conduct maintenance, they will measure the ground potential at the test terminal at the key position of the control loop. Therefore, it is necessary to sample and quantify the potential of the test point. Taking into account various possible access situations and the actual ideal voltage range, the voltage input range is finally determined to be -250V~+250V, with a minimum resolution of 1V.

[0039] The host external interface uses a 4mm red and black banana socket or aviation plug, where red represents the positive pole and black represents the negative pole. Use a multimeter probe or a wire with a clip to connect the banana socket to the test point.

[0040] Specific implementation: voltage is divided by a voltage-dividing resistor with a voltage-dividing coefficient of 49:1, that is, when the input voltage is 250V, the output is 5V after voltage division. The output end of the voltage-dividing resistor is connected to a voltage follower (OP07 or other) for buffering and input-output impedance conversion. The output end of the voltage follower is connected to an ADC sampling chip (AD7606 or other). The host's FPGA is connected to the isolation chip through the GPIO port, and the isolation chip is connected to the ADC to obtain the ADC sampling value. The voltage sampling diagram is as follows: Figure 2 shown.

[0041] On the acquisition box side, there are 25 channels of high-voltage input interfaces. Because there are certain requirements for the electrical isolation distance and the principle of ease of use must be met, a 4mm banana socket is used as the connector interface. Because a common terminal is grounded, only 26 banana sockets are actually needed.

[0042] In the high-voltage binary input circuit, the design requirement is to withstand a maximum DC voltage of 250V without burning the circuit. When the binary input voltage to ground is greater than 40V, it is judged and output as a high level. The logic output of the high-voltage binary input circuit is connected to the FPGA (or CPLD, CPU, etc.) on the acquisition box side. The jump of the binary input potential is recorded and stored, and the recorded data is sent to the host side through wireless or wired communication so that the component side can view and measure time.

[0043] The sampling principle of the binary input circuit is: when sampling binary input, the voltage plate of the voltage plate switch is open, the measuring point on the upper end of the voltage plate is in a suspended state, one end of the binary input circuit (red) is connected to the upper end of the voltage plate, and the other end (black) is connected to the common ground. When measuring binary input, close the relay contact between the +110V power supply and the upper end of the voltage plate (the closing time of the contact is generally tens of milliseconds, and it is usually disconnected). At this time, the circuit loop is: +110V~relay contact~measuring point on the upper end of the voltage plate~red wire of the binary input circuit~bind identification circuit~black wire of the binary input circuit~ground. The schematic diagram is as follows Figure 3 shown.

[0044] The specific circuit of the binary input circuit is as follows: the red end of the binary input is connected to a voltage regulator D, whose value is about 38V, and then connected in series with a resistor R, and finally connected in series with an optocoupler to the common end of the binary input circuit. The circuit diagram is as follows Figure 4 As shown, the value of resistance R can be estimated as follows: the optocoupler on-state current is 1mA, the optocoupler on-state voltage drop is 2V, then R = (110-38-2) / 1 = 70K, power P = 0.001*0.001*70000 = 0.07W.

[0045] Similarly, on the acquisition box side, 6 weak current binary input circuits are also required, and their functions are basically the same as those of the strong current binary input circuits. It is also planned to use 4mm banana sockets as interfaces. In the weak current binary input circuit, every two binary input circuits share a common grounding point, which is different from the common grounding point in the strong current binary input circuit. In the 6-channel weak current binary input circuit, 9 banana sockets are required.

[0046] In the weak current binary input circuit, when the voltage of the binary input to the ground is greater than 5V, it is judged and output as a high level. In terms of circuit principle, the weak current binary input circuit should be similar to the strong current binary input circuit, only the circuit parameters are different. The value of the voltage regulator D is about 3V, and other assumptions remain unchanged, R = (12-5) / 1 = 7K, and the power P = 0.001 * 0.001 * 7000 = 0.007W.

[0047] In the low-voltage input circuit, we also need to consider the possibility that the customer may mistakenly plug in the high-voltage input. Therefore, we need to make a protection circuit. We can add a 30V Zener diode or TVS diode at the entrance to clamp the input voltage.

[0048] 100M Ethernet port: The acquisition box and the host communicate via Ethernet port. It has strong interference capability and mature circuit design. Optical Ethernet port is preferred as the wired communication method.

[0049] Although the customer did not require time synchronization on the acquisition box side, in order to facilitate the future promotion of the product, an optical B code receiving circuit can be added.

[0050] The FPGA program download port on the acquisition box side is the same as the original BCST6400. Considering that the program is rarely upgraded or modified, the downloader interface is placed inside the acquisition box. The external optical Ethernet port also has the function of program upgrade.

[0051] The data acquisition box is an independent entity and has no power circuit connection with the host. Therefore, the data acquisition box needs to have its own power supply. Currently, the company uses more 18620 lithium batteries and has a more mature charging and discharging circuit.

[0052] The battery of the present invention uses the battery pack in DM5200, which is a combination of 3 parallel and 2 series. The design capacity of the battery pack is 10000mAh, the platform voltage is 7.4V, and it is expected that the collection box can be used for more than 12 hours, and the remaining power is displayed by 5 LEDs. The charging input interface is consistent with DM5200, and the charging circuit is also consistent with DM5200, using the same 13.4V / 4A power adapter. The charging and discharging circuit of the lithium battery can refer to DM5200.

[0053] When using the acquisition box for work, you need to know the remaining power of the acquisition box in order to estimate the remaining use time of the acquisition box. The specific method is that the FPGA on the acquisition box side reads the remaining power and / or battery voltage in the battery metering protection chip, and the FPGA drives 5 LEDs to indicate the remaining power. The relationship between the no-load voltage and the remaining power of a single lithium battery is shown in Table 2, and the relationship between the remaining power and the LED status is shown in Table 3.

[0054] Table 2 Relationship between no-load voltage and remaining capacity No-load voltage / V Remaining power / % 4.2 100 4.06 90 3.98 80 3.92 70 3.87 60 3.82 50 3.79 40 3.77 30 3.74 20 3.68 10 3.45 5 3 0 Table 3 Remaining power and LED status table Remaining power threshold LED Status Hysteresis range More than 80% LED1, LED2, LED3, LED4, LED5 are all on 10％ 60％-80％ LED1 is off, LED2, LED3, LED4, LED5 are on 10％ 40％-60％ LED1, LED2 off, LED3, LED4, LED5 on 10％ 20％-40％ LED1, LED2, LED3 are off, LED4, LED5 are on 10％ 10％-20％ LED1, LED2, LED3, LED4 are off, LED5 is on 10％ Below 10% LED5 is flashing 5％ Note: The hysteresis range refers to the state of the LED that displays the power from off to on. The hysteresis range needs to be added to the threshold to change the LED state, mainly to avoid the situation where the power is near the remaining power threshold, causing the LED to flicker. For example, taking the 80% threshold as an example, assuming that the remaining battery power drops from 81% to 79%, LED1 will go out. When the load becomes lighter, the remaining power collected may increase. At this time, if there is no threshold, LED1 will be repeatedly turned on and off. After setting the hysteresis range, the remaining power detection needs to reach 90% before the previously off LED1 will be lit. The other remaining power thresholds are similar.

[0055] The power requirements of the present invention are divided into the power requirements of the host side and the power requirements of the acquisition box side. The host side is improved by using the DM5200 platform. After the improvement, its power requirements are similar to the original platform. The power requirements of the acquisition box side are emphasized.

[0056] The power supply of the acquisition box side mainly comes from FPGA (or CPLD, CPU, etc.), 100M PHY, optical module, optical B code circuit, strong current digital input and weak current digital input circuit, etc. The following will introduce their power supply requirements in turn, among which the acquisition box side takes FPGA as the main control as an example.

[0057] The FPGA uses 5CEFA5U19. According to the Cyclone V data sheet, Table 4 lists the expected steady-state voltage values ​​of the Cyclone V device (excerpt). The power supply ramp must be strictly monotonically rising.

[0058] Table 4 FPGA power requirements As shown in Table 4, the power supplies required by FPGA are 1.1V, 2.5V, and 3.3V.

[0059] 100M PHY power requirements: According to the chip manual of DP83620, Table 5 lists the recommended operating conditions of the chip.

[0060] Table 5 100M PHY power requirements Symbol Data indicators Analog Supply Voltage(Vcc) 3.3Volts±0.3V I / O Supply Voltage(Vi / o) 3.3Volts±10% or 2.5Volts±5% Power Dissipation(PD)with VI / O=3.3V 290mW Power Dissipation(PD)with VI / O=2.5V 260mW As shown in Table 3, the 100M PHY can use 2.5V and 3.3V power supplies, and can also use a single 3.3V power supply. In the actual design, based on the principle of convenient power division, both Vcc and Vi / o power supplies use 3.3V.

[0061] 100M optical module power requirements: Refer to Table 5 and you can get the following data.

[0062] Table 5 Power requirements for 100M optical modules Symbol Parameter Min Type Max Unit VCC Supply Voltage 3.0 3.30 3.6 V ICC Transmitter Supply Current - 60 140 mA PDISS Transmitter Power Dissipation - 200 500 mW ICC Receiver Supply Current - 67 100 mA PDISS Receiver Power Dissipation - 220 360 mW From Table 4, we can see that the typical value of the power supply voltage of a 100M optical module is 3.3V.

[0063] Power supply requirement of binary input circuit: According to DM5200, the power supply required by the DI circuit is 3.3V and isolated 24V (generated by a 5V to 24V module). Based on this, it can be inferred that the power supply requirement of the improved binary input circuit is similar to that of the original binary input circuit, requiring 3.3V and 5V.

[0064] Overview of power supply requirements and selection of power supply chips: Through the description in the above sections, it can be determined that the power supply required in the present invention has 4 voltage levels, namely 1.1V, 2.5V, 3.3V and 5V, which can all be generated by DC-DC step-down chips, and the optional chip is TPS62130.

[0065] Referring to the DM5200 project, the FPGA power consumption is 1.148W. In this design, the FPGA logic is less than the FPGA, and the estimated power consumption is 0.8W-1W, totaling 1W.

[0066] Refer to the 100M PHY data sheet in Table 5, estimated power consumption: 0.29W, total 0.3W.

[0067] Refer to the optical module data sheet in Table 6 to estimate the power consumption of Avago 57E5: 0.5W + 0.36W = 0.86W.

[0068] Estimated total power consumption of the input circuit: 1.5W (including the loss of the isolation power module).

[0069] The power consumption of other parts is calculated as 1W.

[0070] Then: total power consumption P = 1 + 0.3 + 0.86 + 1.5 + 0.5 = 4.66W.

[0071] Based on the DC-DC conversion efficiency of 90%, the effective battery capacity of 10000mAh, and the battery platform voltage of 7.4V, the working time is approximately: T = 0.9*7.4*10 / 4.66 = 14.3 hours.

[0072] This working time also meets the previously estimated usage time.

[0073] On the acquisition box side, the main function is to trigger sampling of 25-channel high-voltage input circuits and 6-channel low-voltage input circuits, and send the input position information to the host side in real time through the optical Ethernet port in standard goose messages. The host side stores the recorded data until the recording time ends. The host side performs work such as parsing, viewing, and time measurement of the recorded data.

[0074] When the FPGA or other main control chip on the acquisition box side detects that the level of any single input input terminal jumps within a recording cycle, the moment of the jump is taken as the time zero point, and the single input sampling and recording are performed.

[0075] The host side can set two sampling time lengths, with the effective jump moment of monitoring as the time zero point, which are: 1. The time T1 before recording zero o'clock was recorded as 20mS in the meeting, but it was 1S in the document. Later, in the further communication, it was said that it could be hard-coded in the program as 20mS.

[0076] 2. The waveform recording records the time T2 after zero o'clock. The meeting mentioned 5S or 10S, which can be set by the host side program.

[0077] After the acquisition box is powered on, it immediately starts to collect the input position change information. If no valid position change information is collected, the FPGA on the acquisition box side sends the input level information at the standard GOOSE heartbeat message time interval (5S); when a valid trigger signal is generated, the FPGA on the acquisition box side sends a standard goose message through the optical network port at a time interval of 2ms-2ms-4ms-8ms. The host side takes the time when the jump information message is first received within a recording cycle as the time zero, and analyzes and records the level jump conditions of all the input circuits of the input quantity from T1 before zero to T2 after zero according to the received message time. A complete recording cycle is T1+T2. When the recording time ends, the host automatically saves it as a comtrade file.

[0078] During the recording process, the acquisition box sends standard goose messages in real time through the optical network port until the recording cycle ends. The FPGA on the host side receives these data and sends them to the CPU to save them as comtrade files. The CPU uses the parsed timestamp as the time axis and displays the input jump status on the display screen according to the time axis, so that users can compare the jumps of each input on the display screen and measure the time.

[0079] The complete workflow of the present invention is as follows: After the acquisition box is powered on, it immediately starts to collect the input position change information. If no valid position change information is collected, the FPGA on the acquisition box side sends the input level information at the standard GOOSE heartbeat message time interval (5S); when a valid trigger signal is generated, the FPGA on the acquisition box side sends a standard goose message through the optical network port at a time interval of 2ms-2ms-4ms-8ms. The host side takes the time of the first received jump information message in a recording cycle as the time zero, and analyzes and records the level jumps of all input circuits from T1 before zero to T2 after zero according to the received message time. A complete recording cycle is T1+T2. When the recording time ends, the host automatically saves it as a comtrade file. The CPU uses the received message time as the time axis and displays the input jump situation of the input on the display screen according to the time axis, so that the user can compare the jumps of each input on the display screen and measure the time.

Claims

1. An intelligent diagnostic device for a relay protection output control circuit, characterized in that: It includes a host and a collection box. The host communicates with the collection box through an optical Ethernet port communication circuit. The collection box is provided with a sub-controller and a plurality of strong current binary input circuits and weak current binary input circuits electrically connected to the sub-controller. The sub-controller is electrically connected to an optical B code receiving circuit and a power supply circuit. The host includes a main controller and a voltage collection sample circuit and an electrical B code transceiver circuit electrically connected to the main controller. The collection box collects various voltage signals of the relay protection outlet control circuit and transmits them to the host. The host uses the voltage collection sample circuit to sample and display various voltage signals.

2. The intelligent diagnostic device for a relay protection output control circuit according to claim 1 is characterized in that: The voltage sampling circuit includes a voltage divider resistor and a voltage follower. The input end of the voltage divider resistor is connected to an external interface, the output end of the voltage divider resistor is connected to the input end of the voltage follower, and the output end of the voltage follower is connected to an ADC sampling chip. The ADC sampling chip is connected to the main controller of the host through an isolation chip.

3. The intelligent diagnostic device for a relay protection output control circuit according to claim 2 is characterized in that: The external interface adopts an aviation plug or a 4mm red and black banana socket.

4. The intelligent diagnostic device for a relay protection output control circuit according to claim 1 is characterized in that: The interface of the high-voltage binary input circuit and the low-voltage binary input circuit adopts a 4mm red and black banana socket. When the input ground voltage of the high-voltage binary input circuit is greater than 40V, the output is a high level; when the input ground voltage of the low-voltage binary input circuit is greater than 5V, the output is a high level.

5. The intelligent diagnostic device for relay protection output control circuit according to claim 1 is characterized in that: The high-voltage binary input circuit and the low-voltage binary input circuit both include a binary input pressure plate loop and a binary input circuit. The binary input pressure plate loop controls the on / off connection of the binary input circuit, and the binary input circuit performs binary input sampling.

6. The intelligent diagnostic device for relay protection output control circuit according to claim 5 is characterized in that: The binary input circuit comprises an input end and a common end. The input end connects the binary input pressure plate loop with a voltage regulator tube. The voltage regulator tube is connected in series with a resistor. The resistor is connected to the common end. The resistor is connected to an optical coupler.

7. The intelligent diagnostic device for relay protection output control circuit according to claim 6 is characterized in that: The binary input pressure plate loop includes a pressure plate switch, the pressure plate switch includes an upper end and a lower end, and the input end and the upper end of the binary input circuit are connected in parallel to the relay contact.

8. An intelligent diagnostic device for a relay protection output control circuit according to any one of claims 1 to 7, characterized in that: The power supply circuit includes a battery and a charge and discharge circuit. The battery is connected to a DC / DC module via the charge and discharge circuit, and the sub-controller is powered by the DC / DC module.

9. The intelligent diagnostic device for relay protection output control circuit according to claim 8, characterized in that: The battery is provided with 5 LEDs for displaying the remaining power.

10. An intelligent diagnostic device for a relay protection output control circuit according to any one of claims 1 to 7, characterized in that: The acquisition box is provided with a downloader interface, through which the FPGA program is downloaded.

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