Low dropout regulator (LDO)

Abstract

The present disclosure relates to a low dropout regulator (LDO). An integrated circuit (1500) includes a first transistor (1550) coupled between a power input (VIN) and a power output (VOUT), the first transistor being an N-type transistor and having a first transistor control input (gate); a first amplifier stage (1510) having a reference input (VREF), a feedback input (VFB) coupled to the power output, and a first amplifier output (an output of the first amplifier stage 1510); a second amplifier stage (1520) having an amplifier input (connected to an output of the first amplifier stage (1510)) and a second amplifier output (connected to a gate of a transistor (1550)), the amplifier input coupled to the first amplifier output and the second amplifier output coupled to the first transistor control input; and a first bias circuit (1536) coupled to the first transistor control input, the first bias circuit having an electrical control input (connected to an output of a feedback circuit 1570) coupled to the power output (through the feedback circuit 1570).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to: (i) U.S. Provisional Application No. 63 / 590,548, filed on October 16, 2023, entitled “Split Biasing for Quiescent Current Reduction in Low Dropout (LDO) Regulator”; (ii) U.S. Provisional Application No. 63 / 590,564, filed on October 16, 2023, entitled “Dual-Loop Load Dependent Miller Compensation for Low Dropout (LDO) Regulator”; and (iii) U.S. Provisional Application No. 63 / 590,565, filed on October 16, 2023, entitled “Fast Load Transient Technique for Low Dropout (LDO) Regulator”. No. 63 / 590,581, entitled "LDO (Low-Dropout (LDO) regulator")", each of which is assigned to the present assignee and is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] The present disclosure relates to a low dropout (LDO) regulator. Background Art

[0004] A low dropout (LDO) regulator can be used to generate an output voltage from an input voltage (e.g., a supply voltage) and regulate the output voltage at a target value. An LDO regulator can provide a relatively stable load-independent output voltage that is close to the input voltage (and therefore has a low dropout voltage). For example, an LDO regulator can be used in mobile devices or other battery-powered electronic devices to maintain a target system voltage level independent of the battery's state of charge. LDO regulators can also be used in systems on chip (SOCs) for local on-chip voltage regulation.

[0005] An LDO regulator may have a relatively simple structure. For example, an LDO regulator may include a reference, a feedback amplifier that amplifies the difference between the reference and the regulator output (or a scaled-down version of the regulator output), and a transfer element (e.g., a transfer transistor) between the input voltage and the output voltage. The transfer element may be controlled by the output of the amplifier to achieve a target output voltage. Compared to other types of voltage regulators such as switching voltage regulators, LDO regulators may have fast transient response, low noise (e.g., no switching noise), simple design (including fewer components), and smaller device size (e.g., because no inductor or transformer is required and fewer components are used). However, LDO regulators may dissipate heat and may have relatively high losses and relatively low efficiency. It may also be challenging for LDO regulators to achieve good dynamic performance, stability, and power supply rejection ratio (PSRR) at both low and high load currents. Summary of the invention

[0006] This Summary is provided to introduce examples of the disclosed concepts in a simplified form that are further described below in the Detailed Description including the provided drawings.

[0007] According to certain aspects, a device may include: a first transistor coupled between a power input and a power output, the first transistor being an N-type transistor and having a first transistor control input; a first amplifier stage having a reference input, a feedback input, and a first amplifier output, the feedback input being coupled to the power output; a second amplifier stage having an amplifier input and a second amplifier output, the amplifier input being coupled to the first amplifier output, and the second amplifier output being coupled to the first transistor control input; and a first bias circuit coupled to the first transistor control input, the first bias circuit having an electrical control input coupled to the power output.

[0008] According to certain aspects, a device may include: a first transistor coupled between a power input and a power output, the first transistor being an N-type transistor and having a first transistor control input; a first amplifier stage having a reference input, a feedback input, and a first amplifier output, the feedback input being coupled to the power output; a second amplifier stage having an amplifier input and a second amplifier output, the amplifier input being coupled to the first amplifier output, and the second amplifier output being coupled to the first transistor control input; and a capacitor and a second transistor coupled in series between the first amplifier output and the first transistor control input, the second transistor having a second transistor control input electrically coupled to the power output and the first amplifier output.

[0009] According to certain aspects, a device may include: a transistor coupled between a power input and a power output, the transistor being an N-type transistor and having a transistor control input; an amplifier having a reference input, a feedback input, and an amplifier output, the feedback input being coupled to the power output; a buffer having a buffer input, a bias input, and a buffer output, the buffer input being coupled to the amplifier output; a level shifter having a level shifter input and a level shifter output, the level shifter input being coupled to the buffer output, and the level shifter output being coupled to the transistor control input; a first bias circuit coupled between the power input and the bias input of the buffer; and a second bias circuit coupled to the level shifter output and the transistor control input.

[0010] The foregoing summary of the invention has been summarized quite extensively in various features of the examples of the present disclosure so that the following detailed description can be better understood. Additional features and advantages of such examples will be described below. The present summary is neither intended to identify the key or essential features of the claimed subject matter nor to be used alone to determine the scope of the claimed subject matter. The subject matter should be understood by reference to the appropriate parts of the entire specification of the present disclosure, any or all drawings, and each claim. The foregoing and other features and examples will be described in more detail below in the following specification, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Illustrative examples are described in detail below with reference to the following figures.

[0012] Figure 1 is a schematic diagram of an example of a low dropout (LDO) regulator having an N-type field effect transistor (NFET) as a pass device.

[0013] Figure 2 is a schematic diagram of an example of an LDO regulator having an NFET as a pass device and including a dynamic bias circuit.

[0014] Figure 3 for Figure 2 Schematic diagram of an example of an LDO regulator.

[0015] Figure 4 is a schematic diagram of an example of an LDO regulator having an NFET as a pass device and including a separate bias circuit.

[0016] Figure 5 for Figure 4 Schematic diagram of an example of an LDO regulator.

[0017] Figure 6 is a schematic diagram of an example of an LDO regulator having an NFET as a pass device and including a separate bias circuit.

[0018] Fig. 7A and 7B Included are graphs showing examples of simulation results for LDO regulators with and without a dynamic bias circuit as described herein.

[0019] Fig. 8A and 8B Examples of simulation results for an LDO regulator with and without examples of a dynamic bias circuit as described herein are shown.

[0020] Fig. 9A and 9B Examples of simulation results for an LDO regulator with and without a split bias circuit as described herein are shown.

[0021] Fig.10 is a schematic diagram of an example of an LDO regulator having an NFET as a pass device and including an adjustable Miller compensation resistor.

[0022] Fig.11 for Fig.10 Schematic diagram of an example of an LDO regulator.

[0023] Fig.12 for Fig.10 and 11 Schematic diagram of an example of an LDO regulator.

[0024] Fig.13A and 13B is a graph showing examples of simulation results for an LDO regulator with and without examples of an adjustable Miller compensation resistor as described herein.

[0025] Fig.14A and 14B is a graph showing examples of simulation results for an LDO regulator with and without examples of an adjustable Miller compensation resistor as described herein.

[0026] Fig.15 is a schematic diagram of an example of an LDO regulator incorporating a combination of various techniques as described herein.

[0027] The drawings and the accompanying detailed description are provided to understand the features of the various examples and do not limit the scope of the appended claims. The examples illustrated in the drawings and described in the accompanying detailed description can be easily used as the basis for modifying or designing other examples within the scope of the appended claims. Those skilled in the art will easily recognize from the following description that alternative embodiments of the structures and methods described can be adopted without departing from the principles of the present disclosure or the benefits of the claims. Where possible, the same reference numerals can be used to refer to the same elements that are common in the drawings. Drawings are drawn to clearly illustrate the relevant elements or features and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0028] The present disclosure generally relates to low dropout (LDO) regulators. In some examples, the LDO regulator may include: (1) a feedback loop for controlling a dynamic bias circuit to improve load transient response; (2) a split bias circuit for providing a large bias current according to an input voltage and a relatively small bias current through a voltage boost circuit (e.g., a charge pump); (3) a feedback loop for load-dependent Miller compensation for controlling the resistance of a Miller compensation resistor using a voltage signal that tracks both the load current and the output voltage of a first amplifier stage, or any combination of these features, to achieve small device area, low quiescent current, fast response to load transients, low complexity, low current from a charge pump, high power supply rejection ratio, low output noise, and low sensitivity to variations in process and operating conditions.

[0029] The LDO regulator may include a transfer element (e.g., a transfer transistor) that receives an input voltage and provides an output voltage. The LDO regulator may also include an amplifier that compares the output voltage (or a scaled version thereof) with a reference voltage and generates a control signal for the transfer element based on the difference between the output voltage and the reference voltage. The LDO regulator may set a control signal based on the difference between the output voltage (or a scaled version thereof) and the reference voltage, thereby regulating the output voltage. The transfer element may include, for example, an NPN or PNP bipolar transistor, or an N-type or P-type field effect transistor (FET). The LDO regulator may generally perform a step-down voltage regulation operation in which the output voltage is lower than the input voltage. The voltage drop across the transfer element may be controlled by a control signal output by the amplifier to regulate the output voltage at a target value. For example, in an LDO regulator with an NFET transfer device, when the load current increases and the output voltage decreases, the difference between the output voltage and the target value increases, and therefore the amplifier may increase the gate voltage of the NFET transfer transistor to increase the drain current of the NFET transistor, which may increase the output voltage back to near the target value.

[0030] The amplifier of the LDO regulator may include, for example, a first amplifier stage and a second amplifier stage. The first amplifier stage may include a differential amplifier that may amplify the difference between a reference voltage and an output voltage (or a scaled-down version of the output voltage) of the LDO regulator. The second amplifier stage may include, for example, a buffer that may isolate the gate of the pass transistor from the output of the first amplifier stage, so that the pole at the gate of the pass transistor (e.g., a non-dominant pole) and the pole at the output of the first amplifier stage (e.g., a dominant pole) may be separated, and thus the LDO regulator may have a high unity gain frequency (UGF) and may be stable at higher frequencies for fast transient response. The large bias current of the second amplifier stage may increase the transconductance of the second amplifier stage, thereby pushing the pole at the gate of the pass transistor to a higher frequency to achieve fast dynamic / transient response and a high power supply rejection ratio (PSRR).

[0031] Therefore, compared to other types of voltage regulators such as switching voltage regulators, LDO regulators may have fast transient response, low noise (e.g., no switching noise), simple design (including fewer components), and smaller device size (e.g., because no inductive components are required and fewer components are used). However, in an LDO regulator, the pass transistor is always turned on during normal operation (e.g., steady-state operation), and because the pass transistor has a non-zero resistance, the pass transistor may consume power (e.g., convert some input power into heat). The control circuit (e.g., an amplifier) ​​may also conduct a quiescent current to regulate the output voltage (e.g., by charging or discharging the gate of the pass transistor). In some applications, the quiescent current may have a significant impact on the current efficiency (e.g., the ratio between the output current and the sum of the output current and the quiescent current). Therefore, some LDO regulators may have high quiescent current and low current efficiency. It may be difficult to design an LDO regulator with good dynamic performance, current efficiency, stability, and power supply rejection ratio (PSRR) at both low load currents and high load currents.

[0032] One way to reduce the quiescent current and improve the current efficiency of the LDO regulator is to reduce the bias current used to bias the second stage and / or the first stage of the amplifier and the current used to charge the gate capacitor of the pass transistor. For example, due to the higher mobility of most carriers (e.g., electrons), NFET pass transistors can have a smaller area than PFET pass transistors with similar current drive capability, and can therefore be used in LDO regulators to reduce the size of the LDO regulator. Smaller pass transistors can have smaller gate capacitance, and therefore the gate capacitor can be charged at a high rate and / or with a smaller current. Therefore, the quiescent current used to control the gate voltage of the pass transistor to set the output voltage can be reduced, and therefore the current efficiency of the LDO regulator can be improved. In addition, reducing the gate capacitance can help push the non-dominant pole at the gate of the pass transistor to a higher frequency, or the frequency of the non-dominant pole can be maintained with a reduced bias current.

[0033] However, in an LDO regulator based on an NFET pass transistor, a voltage boost circuit (e.g., a charge pump or a bootstrap circuit) may be included to charge the parasitic gate capacitor of the pass transistor and bias the second amplifier stage (e.g., a buffer) so that the voltage level at the gate of the pass transistor can be higher than the input voltage of the voltage regulator. Such an arrangement allows the voltage difference between the gate of the pass transistor and the output terminal (e.g., the source) to exceed a threshold, including when the output voltage is close to the input voltage, to maintain the pass transistor in an on state. In order to boost the output voltage, the input current of the charge pump may be several times the output current of the charge pump. In addition, the charge pump may consume power to operate, and thus may increase the quiescent current of the LDO regulator. For example, some charge pumps may have relatively low efficiency, such as less than 50%. Therefore, the charge pump may increase the quiescent power consumption. In addition, the size of the charge pump and / or the bias circuit may be larger to provide the bias current in order to improve the transient performance of the LDO regulator. Therefore, it may be desirable to reduce the bias current from the charge pump used to charge the gate capacitor and bias the second amplifier stage while achieving good load transient response performance.

[0034] In some examples, the LDO regulator may include an additional feedback loop (in addition to the feedback loop feeding the output voltage) to control a dynamic bias circuit to improve the load transient response of the LDO regulator. The dynamic bias circuit may consume no (or very little) quiescent current, and therefore may consume no power (or consume very little power) during steady-state operation of the LDO regulator, and therefore may not significantly increase the quiescent power consumption of the LDO regulator. When the output voltage is lower than the target output voltage, the dynamic bias circuit may be turned on to supply current to the gate of the pass transistor to pull up the gate voltage, and thus pull up the output voltage of the pass transistor (e.g., at the source). When the output voltage becomes higher than the target output voltage, the output voltage of the first amplifier stage and the control voltage of the second amplifier stage may increase, so that the current flowing from the gate of the pass transistor through the second amplifier stage to the ground may increase to discharge the gate capacitor, thereby reducing the output voltage at the pass transistor. The dynamic bias circuit may include a high pass filter (HPF), which may pass high frequency changes in the output voltage directly to the amplifier (e.g., not scaled down) to turn on the dynamic bias circuit. Therefore, the LDO regulator can have good load transient performance. The additional feedback loop can have low gain and high bandwidth to improve the load transient response, and has minimal or no effect on the stability of the main feedback loop of the LDO regulator. The dynamic bias circuit supplies zero current to the main feedback loop during steady state, and the additional feedback loop can have a low quiescent current, and therefore the additional circuit does not significantly increase the quiescent current during steady-state operation of the LDO regulator.

[0035] As described above, some LDO regulators can use a large bias current for the second amplifier stage to increase the transconductance of the second amplifier stage, thereby reducing the transconductance of the second amplifier stage and pushing the pole (e.g., non-dominant pole) at the gate of the pass transistor (and the output of the second amplifier stage) to high frequency to achieve fast dynamic response, high PSRR, and better stability. If all the bias current for the second amplifier stage is provided by the charge pump, the total quiescent current may increase significantly due to the voltage up-conversion and limited conversion efficiency of the charge pump. Therefore, the current efficiency of the LDO regulator may be low, and the area of ​​the charge pump used to provide the large bias current may need to be increased.

[0036] In some examples, the LDO regulator can use a split bias technique to provide a large bias current from the input voltage to a second amplifier stage that separates the gate of the transfer transistor from the output of the first amplifier stage, and a small bias current is provided to the gate of the level shifter and the transfer transistor through a voltage boost circuit (e.g., a charge pump or a bootstrap circuit). The large bias current from the input voltage to the second amplifier stage can increase the transconductance of the second amplifier stage, and thus increase the frequency of the non-dominant pole at the gate of the transfer transistor, thereby increasing the operating bandwidth and improving the transient response and PSRR performance of the LDO regulator. The level shifter can be driven by the output of the charge pump, and the output voltage of the second amplifier stage can be shifted to a higher level to drive the gate of the transfer transistor so that the output voltage of the LDO regulator can be closer to the input voltage. The level shifter can also help isolate the gate of the transfer transistor from the input voltage to reduce noise in the output voltage. In this way, the current supplied by the charge pump can be reduced, and the static power consumption and size of the LDO regulator can be reduced.

[0037] In some LDO regulators, Miller compensation can be used to improve the stability of the LDO regulator. A capacitor can be used in a Miller compensation circuit to increase the capacitance at the output of the first amplifier stage, the capacitor can have a high output impedance, and thus the dominant pole at the output of the first amplifier stage can have a low frequency and can be separated from the non-dominant pole at a higher frequency. The Miller compensation circuit can also include a resistor for moving the right half plane (RHP) zero to the left half plane (LHP), which can help eliminate the effects of the non-dominant pole, increase the unity gain frequency, and improve the phase margin. Under different operating conditions, the non-dominant pole can be at different frequencies. For example, when the load current is high, the transconductance of the transfer transistor can be high, and thus the non-dominant pole at the output of the LDO regulator can be moved to a higher frequency. When the load current is low, the transconductance of the transfer transistor can be low, and thus the non-dominant pole at the output of the LDO regulator can be moved to a lower frequency. Therefore, it may be desirable to move the LHP zero with a non-dominant pole, particularly when the load current is low, so as to improve the stability and unity gain frequency of the LDO regulator.

[0038] In some examples, a load-dependent Miller compensation loop using a current sensor, a current-to-voltage converter, and a voltage-controlled variable resistor can be used to track the load current, and the LHP zero is moved accordingly by tuning the resistance of the variable resistor in the compensation circuit. At high load currents, since the non-dominant pole can be moved to high frequencies and the unity gain frequency can be increased, the variable resistor can be controlled to reduce the resistance, thereby also moving the LHP zero to a higher frequency. At low load currents, the variable resistor can be controlled to increase the resistance, thereby moving the LHP zero to a lower frequency to eliminate the effect of the non-dominant pole at the output of the LDO regulator. However, this loop may conflict with the main feedback loop of the LDO regulator when adjusting the gate voltage of the pass transistor, and may therefore degrade the load transient response of the LDO regulator. In addition, the LHP zero may not be linearly proportional to the load current and may be sensitive to process, voltage, and temperature variations.

[0039] To overcome these problems in the load-dependent Miller compensation loop, the LDO regulator may include a variable Miller compensation resistor controlled based on the load current and the output voltage, and a load-dependent Miller compensation loop including two loops. The first loop may include a load current sensing circuit and a current-to-voltage conversion circuit to set a voltage that tracks the load current. The second loop may include an amplifier for setting a control voltage (e.g., gate voltage) of the Miller compensation resistor based on a difference between the output of the first amplifier stage (which may be associated with the output voltage of the LDO regulator) and the voltage set by the first loop to track the load current, so that the control voltage of the Miller compensation resistor can track both the load current and the output of the first amplifier stage (and thus the output voltage of the LDO regulator). Thus, the second loop can coordinate conflicts between the main feedback loop of the load-dependent Miller compensation loop and the opposite way in which the first loop controls the gate voltage of the pass transistor in response to a load transient, and thus can prevent the load-dependent Miller compensation loop and the main feedback loop from changing the gate voltage of the pass transistor in opposite directions, thereby improving load transient response. This technology can also provide a more accurate load-related zero, which can be proportional to the load current and is insensitive to variations in process and operating conditions, and can be implemented using native MOS devices, which can use fewer masks than low threshold voltage MOS devices, or share masks with other devices in a common process, thereby reducing mask costs.

[0040] In some examples, the LDO regulator may include various combinations of the techniques disclosed herein, including a dynamic bias circuit for output voltage control, a separate bias circuit for reducing charge pump current and / or increasing bias current directly according to input voltage, and an additional loop for load-dependent Miller compensation to control the resistance of the Miller compensation resistor using a voltage signal that tracks both the load current and the output voltage of the first amplifier stage (and thus the output voltage of the LDO regulator). Thus, the LDO regulator disclosed herein may have a small device area, low quiescent current, fast response to load transients, low complexity, low current from the charge pump, high PSRR, and low output noise, and may be less sensitive to variations in process and operating conditions.

[0041] Various features will be described below with reference to the drawings. The illustrated examples may not have all aspects or advantages shown. Aspects or advantages described in conjunction with a particular example are not necessarily limited to that example and may be practiced in any other example, even if not so illustrated or not explicitly described. In addition, the methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented in various other orders with more or fewer operations (e.g., including different serial or parallel executions of various operations).

[0042] Various examples are described herein. Although specific examples may illustrate various aspects of the features generally described above, examples may incorporate any combination generally described above (which are described in more detail in the examples below). For ease of reference, three-dimensional xyz axes are illustrated in some figures. Some cross-sectional views of various semiconductor devices herein may be general depictions for illustrating various aspects or concepts about such semiconductor devices. More specifically, some drain contact structures illustrated in the cross-sectional views may not necessarily accurately depict the structure of such drain contact contacts, except to the extent described herein. The description of these drain contact structures is to illustrate various aspects or concepts about those drain contact structures.

[0043] In the following description, for the purpose of explanation, specific details are set forth in order to provide a thorough understanding of the examples of the present disclosure. However, it will be apparent that various examples can be practiced without these specific details. For example, devices, systems, structures, assemblies, integrated circuits, and other components can be shown as components in block diagram form to avoid confusing the examples with unnecessary details. In other cases, well-known devices, processes, systems, structures, and techniques can be shown without the necessary details to avoid confusing the examples. The drawings and descriptions are not intended to be limiting. The terms and expressions that have been adopted in the present disclosure are used as descriptive and non-restrictive terms, and when using such terms and expressions, it is not intended to exclude any equivalents of the features or parts thereof shown and described. The word "example" is used herein to mean "serving as an example, example, or illustration". Any embodiment or design described herein as an "example" is not necessarily interpreted as being preferred or advantageous over other embodiments or designs.

[0044] A low dropout (LDO) regulator can be used in an electronic circuit (e.g., an integrated circuit) to provide a stable local output voltage that may be close to an input voltage. Compared to other types of voltage regulators, such as switching voltage regulators, LDO regulators can have fast transient response, no switching noise, simple design (including fewer components), and smaller device size (e.g., because no inductive components are used and fewer components are used). An LDO regulator can include an amplifier that amplifies the difference between a reference and a regulator output (or a scaled-down version of the regulator output), and a transfer element (e.g., a transfer transistor) located between the input voltage and the output voltage and controlled by the output of the amplifier. The transfer element can include, for example, an NPN or PNP bipolar transistor, or an NFET or PFET FET. The voltage drop across the transfer element can be controlled by the output of the amplifier to maintain the output at a target value. For example, in an LDO regulator with an NFET pass transistor, when the load current increases and therefore the output voltage decreases, the voltage error and therefore the amplifier output may increase, so that the control voltage (e.g., gate voltage) of the NFET pass transistor may increase, and therefore the drain current of the NFET pass transistor may increase and the output voltage may return to the target value.

[0045] As described above, in an LDO regulator, the transfer transistor may be always turned on (e.g., in a linear operating mode) during normal operation (e.g., steady-state operation), and may therefore consume power (e.g., due to the non-zero resistance of the transfer transistor) in order to regulate the output voltage, especially when the voltage drop across the transfer transistor is large and the output load current is high. In addition, the LDO regulator may consume quiescent current to control the transfer transistor (e.g., by charging or discharging the gate of the transfer transistor). In some applications, the quiescent current may have a significant impact on the current efficiency. Therefore, some LDO regulators may have high quiescent current and low current efficiency. It may be difficult to design an LDO regulator with good dynamic performance, efficiency, stability, and power supply rejection ratio (PSRR) at both low and high load currents.

[0046] One way to reduce the quiescent current and improve the current efficiency of the LDO regulator is to reduce the bias current used to bias the second stage and / or the first stage of the amplifier and the current used to charge the gate capacitor of the pass transistor. For example, due to the higher mobility of most carriers (e.g., electrons), NFET pass transistors can have a smaller area than PFET pass transistors with similar current drive capability, and can therefore be used in LDO regulators to reduce the size of the LDO regulator. Smaller pass transistors can have smaller gate capacitance, and therefore the gate capacitor can be charged at a high rate and / or with a smaller current. Therefore, the quiescent current used to control the gate voltage of the pass transistor to stabilize the output voltage can be reduced. In addition, reducing the gate capacitance can help push the non-dominant pole at the gate of the pass transistor to a higher frequency, or the frequency of the non-dominant pole can be maintained with a reduced bias current.

[0047] Figure 1 1 is a schematic diagram of an example of an LDO regulator 100. In the illustrated example, the LDO regulator 100 may include a pass transistor 150 and an amplifier, the pass transistor being an N-type transistor such as an NFET or an NPN, the amplifier may include a first amplifier stage 110 and a second amplifier stage 120. The second amplifier stage 120 may include an N-type transistor configured as a common source amplifier (as shown) or a common emitter amplifier. The LDO regulator 100 may also include: a Miller compensation circuit, which may include a resistor 122 and a capacitor 124; and an output feedback scaling circuit, which may include a resistor 160 and a resistor 162. The output feedback scaling circuit, the amplifier, and the Miller compensation circuit may form a main feedback loop for controlling the pass transistor 150.

[0048] The pass transistor 150 may include an NFET transistor having a voltage coupled to an input voltage V INThe LDO regulator 100 includes a drain, a source coupled to the voltage output port of the LDO regulator 100, and a gate coupled to the output of the second amplifier stage 120. Thus, the pass transistor 150 can be controlled by the amplifier to regulate the output voltage of the LDO regulator 100. Due to the higher mobility of most carriers (e.g., electrons), the NFET pass transistor 150 can have a smaller area than a PFET pass transistor with similar current drive capability, and thus the LDO regulator 100 with the NFET pass transistor 150 can have a smaller size than a PFET-based LDO regulator. The smaller pass transistor 150 can have a smaller gate capacitance, and thus the gate can be charged at a high rate and / or with a smaller current. The voltage level of the output voltage can depend on the input voltage V IN The voltage level at the gate (gate voltage V G ) and the threshold voltage V of the pass transistor 150 T When the voltage level at the gate is higher than the input voltage, for example, when the gate voltage V G With input voltage V IN The difference between them is greater than the threshold voltage V T , the pass transistor 150 is turned on, and the output voltage V OUT Can be close to the input voltage V IN .

[0049] In order to make the voltage level V at the gate of the pass transistor 150 G Greater than the input voltage V IN , a charge pump 140 or another voltage boost circuit (eg, a bootstrap circuit) may be used to generate a voltage higher than the input voltage V IN The output voltage V CP , and then the voltage V CP To set the gate voltage of the pass transistor 150. The charge pump 140 can receive the input voltage V IN input, and can store energy (e.g., using a capacitor) to provide a voltage higher than the input voltage V IN The output voltage V CP , but the output current of the charge pump 140 can be lower than the input current used to provide energy to the charge pump 140. For example, if the voltage conversion ratio of the charge pump is 4, then an input current greater than 4μA can be used to provide an output current of 1μA from the charge pump. The efficiency of the charge pump can be less than 100%, such as less than 50%, about 50%, about 60%, or at most about 90 to 95%. Therefore, an input current much greater than 4μA (e.g., 8mA if the efficiency of the charge pump is 50%) can be used to provide an output current of 1μA from the charge pump. As Figure 1As shown in FIG. 1 , the output voltage V of the charge pump 140 CP The charge pump 140 output may be used to drive a bias circuit 130 (eg, a current source) to set the voltage level at the gate of the pass transistor 150. The output of the charge pump 140 may also be used to bias the second amplifier stage 120, the output of which is coupled to the gate of the pass transistor 150.

[0050] The amplifier can be based on the feedback voltage V FB With reference voltage V REF The difference between them drives the pass transistor to regulate the output voltage V OUT The reference voltage can come from, for example, a bandgap voltage reference. The feedback voltage V FB Can be the output voltage V OUT The values ​​of resistors 160 and 162 can be selected to set the desired voltage divider ratio of the voltage divider formed by resistors 160 and 162 to produce the desired feedback voltage V FB The first amplifier stage 110 may include a differential amplifier that receives, for example, an input voltage V IN As the supply voltage, and can amplify the feedback voltage V FB With reference voltage V REF The output of the first amplifier stage 110 may be input to the second amplifier stage 120, which may perform a voltage level shift between the output of the first amplifier stage 110 and the gate of the transfer transistor 150. In the illustrated example, the second amplifier stage 120 may include a common source amplifier formed by NFET transistors. The gate of the NFET transistor of the second amplifier stage 120 may be coupled to the output of the first amplifier stage 110, the source of the NFET transistor may be coupled to ground, whereas the drain of the NFET transistor may be coupled to the bias circuit 130 and the gate of the transfer transistor 150. The second amplifier stage 120 may act as a buffer isolating the output of the first amplifier stage 110 from the gate of the transfer transistor 150, such that the pole at the gate of the transfer transistor 150 may be separated from the pole at the output of the first amplifier stage 110. Therefore, the LDO regulator 100 may be a pole separation based LDO regulator.

[0051] When the input voltage V IN When the load current at the output of the LDO regulator 100 changes and / or the load current at the output of the LDO regulator 100 changes, the output voltage V of the LDO regulator 100 OUT When the output voltage V OUTWhen the output voltage V is reduced to a level below the target output voltage, the output voltage of the first amplifier stage may decrease, the on-resistance and voltage drop of the NFET transistor of the second amplifier stage 120 may increase, and thus the voltage level at the gate of the pass transistor 150 may increase to pull up the output voltage V OUT When the output voltage V OUT Above the target output voltage, the output voltage of the first amplifier stage may increase, and the gate voltage and therefore the drain current of the NFET transistor of the second amplifier stage 120 may increase, so that the parasitic gate capacitor of the pass transistor 150 may be discharged more quickly through the NFET transistor of the second amplifier stage 120. As a result, the voltage level at the gate of the pass transistor 150 may decrease, thereby reducing the drain current of the pass transistor 150 and the output voltage V of the LDO regulator 100. OUT It is desirable that the LDO regulator can respond to changes in the output voltage as quickly as possible in order to reduce the variation in the output voltage.

[0052] In order to increase the unity gain frequency and load transient response performance while maintaining good phase margin and stability of the LDO regulator 100, the resistor 122 and capacitor 124 of the Miller compensation circuit can be connected in series between the output of the first amplifier stage 110 and the gate of the transfer transistor 150 (which is connected to the output of the second amplifier stage 120). The first amplifier stage 110 can have a high output impedance, and therefore due to the high impedance of the Miller compensation and the capacitor 124, the pole at the output of the first amplifier stage 110 can be a dominant pole at low frequencies. The second amplifier stage 120 can be biased at a high bias current, and therefore can have a high transconductance. The gate capacitance of the NFET transfer transistor 150 can be small. Therefore, the pole at the output of the second amplifier stage 120 and the gate of the transfer transistor 150 can be a non-dominant pole at a higher frequency. The separation of the dominant pole and the non-dominant pole can increase the unity gain frequency and the phase margin at the unity gain frequency. Additionally, resistor 122 of the Miller compensation circuit can be used to move the right half plane (RHP) zero to the left half plane and set the frequency of the left half plane (LHP) zero, which can help eliminate the effect of the pole, thereby increasing the unity gain frequency of the LDO regulator 100 and improving stability.

[0053] As described above, in order to increase the frequency of the non-dominant pole at the gate of the pass transistor 150 to obtain a fast transient response and a high PSRR, the second amplifier stage 120 may be biased at a high bias current to have a high transconductance. In the LDO regulator 100 based on the NFET pass transistor, the bias current may be provided from the charge pump 140, which may not have a high conversion efficiency, which may increase the quiescent current used to bias the second amplifier stage 120, and thus may reduce the current efficiency of the LDO regulator 100. For example, if the efficiency of the charge pump 140 is about 50%, and the voltage conversion ratio is about 4, an input current of about 8 μA may be used to provide an output current of 1 μA for biasing the second amplifier stage 120. Therefore, in the LDO regulator 100 based on the NFET pass transistor using the charge pump 140, the quiescent current may be significantly increased. Additionally, it may be necessary to increase the size of the charge pump 140 and / or the size of the bias circuit 130 (and therefore the overall size of the LDO regulator 100) to provide the bias current for achieving the desired transient performance of the LDO regulator. Therefore, it may be desirable to reduce the bias current from the charge pump 140 used to charge the gate capacitor and bias the second amplifier stage 120 while achieving good load transient response performance.

[0054] In some examples, the LDO regulator may include an additional feedback loop to control a dynamic bias circuit to improve the load transient response of the LDO regulator, wherein the dynamic bias circuit may consume no (or little) current, and thus may supply zero (or little) current to the main feedback loop during steady state, and the additional feedback loop may have a low quiescent current. Therefore, during steady-state operation of the LDO regulator, the additional feedback loop may not significantly increase the quiescent current. When the output voltage is lower than the target output voltage, the dynamic bias circuit may be turned on to supply current to the gate of the pass transistor to pull up the gate voltage, and thus pull up the output voltage of the pass transistor (e.g., at the source). When the output voltage is higher than the target output voltage, the output voltage of the first amplifier stage and the control voltage of the second amplifier stage may increase, so that the current flowing from the gate of the pass transistor through the second amplifier stage to the ground may increase to discharge the gate capacitor, thereby reducing the output voltage at the pass transistor. The dynamic bias circuit may include a high pass filter (HPF), which may pass high frequency changes in the output voltage directly to the amplifier (e.g., not scaled down) to turn on the dynamic bias circuit. Therefore, the LDO regulator may have good load transient performance.The additional feedback loop may have low gain and high bandwidth to improve the load transient response with minimal or no impact on the stability of the main feedback loop of the LDO regulator.

[0055] Figure 2Schematic diagram of an example of an NFET-based LDO regulator 200 including a dynamic bias circuit that can be adjusted based on the output level of the LDO regulator 200. The LDO regulator 200 can be similar to the LDO regulator 100 and can include an auxiliary feedback loop to improve load transient response. In the illustrated example, the LDO regulator 200 can include a pass transistor 250 and an amplifier, which can include a first amplifier stage 210 and a second amplifier stage 220. The LDO regulator 200 can also include: a Miller compensation circuit, which can include a resistor 222 and a capacitor 224; and an output feedback scaling circuit, which can include a resistor 260 and a resistor 262. The output feedback scaling circuit, the amplifier, and the Miller compensation circuit can form a main feedback loop for controlling the pass transistor 250.

[0056] The LDO regulator 200 may further include a charge pump 240 (or another voltage boosting circuit, such as a bootstrap circuit) and a bias circuit 230 (e.g., a current source) for driving the pass transistor 250 and the second amplifier stage 220. In addition, the LDO regulator 200 may include a feedback circuit 270 that can sense the output voltage V OUT And the dynamic bias circuit 232 is controlled to provide a dynamic bias current for charging the gate of the pass transistor 250 during the load transient, thereby improving the load transient response of the LDO regulator 200. The dynamic bias circuit 232 can be disabled during the steady-state operation of the LDO regulator 200, and thus may not significantly increase the power consumption of the LDO regulator 200.

[0057] Pass transistor 250 may have a voltage coupled to an input voltage V IN The drain of the LDO regulator 200 is coupled to the source of the voltage output port of the LDO regulator 200, and the gate is coupled to the output of the second amplifier stage 220. The pass transistor 250 can be an NFET transistor (or NPN) that can provide the desired current drive capability with a relatively small area on the die, and therefore can have a small parasitic gate capacitor that can be charged at a high rate and / or using a small current. In order to provide a voltage close to the input voltage V IN The output voltage V OUT , the voltage level at the gate of the pass transistor 250 may need to be higher than the input voltage V IN , because the voltage difference between the gate and the source (the output port of the LDO regulator 200) needs to be greater than the threshold voltage V of the pass transistor 250 T to turn on pass transistor 250. The higher voltage level at the gate can be supplied by charge pump 240 or another voltage boost circuit (e.g., a bootstrap circuit). Charge pump 240 can be supplied from input voltage V INReceives an input and can store energy (e.g., using a capacitor) to provide a voltage higher than the input voltage V IN The output voltage V CP .like Figure 2 As shown in FIG. 1 , the output voltage V of the charge pump 240 CP can be used to drive bias circuit 230 (e.g., a current source) to set the voltage level at the gate of pass transistor 250. The output of charge pump 240 can also be used to bias second amplifier stage 220, the output of which is coupled to the gate of pass transistor 250. As described above, charge pump 240 may have power losses, and may require an input current several times higher than the output current of charge pump 240 due to voltage up-conversion and power losses.

[0058] The amplifier can be based on the feedback voltage V FB With reference voltage V REF The difference between them drives the pass transistor 250 to regulate the output voltage V OUT . Reference voltage V FB The feedback voltage can be generated by, for example, a bandgap voltage reference or another reference voltage generating circuit. OUT The values ​​of resistors 260 and 262 may be selected based on the voltage levels of the reference voltage and the target output voltage to set a desired voltage division ratio of the voltage divider formed by resistors 260 and 262 .

[0059] The first amplifier stage 210 of the amplifier in the main feedback loop may include a differential amplifier that receives, for example, an input voltage V IN As the supply voltage, and can amplify the feedback voltage V FB With reference voltage V REF (or reference voltage V REF The output of the first amplifier stage 210 may be coupled to the input of the second amplifier stage 220, which may perform a voltage level shift between the output of the first amplifier stage 210 and the gate of the transfer transistor 250. In the illustrated example, the second amplifier stage 220 may include a common source amplifier formed by an NFET transistor. The gate of the NFET transistor may be coupled to the output of the first amplifier stage 210, the source of the NFET transistor may be coupled to ground, whereas the drain of the NFET transistor may be coupled to the bias circuit 230 and the gate of the transfer transistor 250. The second amplifier stage 220 may act as a buffer isolating the output of the first amplifier stage 210 from the gate of the transfer transistor 250, such that the pole at the gate of the transfer transistor 250 may be separated from the pole at the output of the first amplifier stage 210. Therefore, the LDO regulator 200 may be a pole separation based LDO regulator.

[0060] When the input voltage V IN changes and / or the load current at the output of the LDO regulator 200 changes, the output voltage V OUT When the output voltage V OUT When the output voltage of the first amplifier stage 210 is lower than the target output voltage, the output voltage of the first amplifier stage 210 may decrease, so that the gate voltage and drain current of the NFET transistor of the second amplifier stage 220 may decrease, and the voltage drop across the NFET transistor of the second amplifier stage 220 may increase. Therefore, the voltage level at the gate of the pass transistor 250 may increase to increase the drain current of the pass transistor 250, thereby pulling up the output voltage V OUT When the output voltage V OUT When the output voltage V is higher than the target output voltage, the output voltage of the first amplifier stage may increase, and thus the gate voltage and drain current of the NFET transistor of the second amplifier stage 220 may increase, so that the gate capacitor of the pass transistor 250 may be discharged through the NFET transistor of the second amplifier stage 220. Therefore, the voltage level at the gate of the pass transistor 250 may decrease, thereby reducing the drain current of the pass transistor 250 and the output voltage V OUT It is desirable that the LDO regulator 200 can respond to the change in the output voltage as quickly as possible in order to reduce the output voltage V OUT changes.

[0061] In order to increase the unity gain frequency and load transient response performance while maintaining good phase margin and stability of the LDO regulator 200, the resistor 222 and capacitor 224 of the Miller compensation circuit can be connected in series between the output of the first amplifier stage 210 and the gate of the transfer transistor 250 (and the output of the second amplifier stage 220). The first amplifier stage 210 can have a high output impedance, and therefore due to the high impedance of the Miller compensation circuit and the capacitor 224, the pole at the output of the first amplifier stage 210 can be a dominant pole at low frequencies. The second amplifier stage 220 can be biased at a high bias current, and therefore can have a high transconductance, and the gate capacitance of the NFET transfer transistor 250 can be small. Therefore, the pole at the output of the second amplifier stage 220 and the gate of the transfer transistor 250 can be a non-dominant pole at a higher frequency. The separation of the dominant pole and the non-dominant pole can increase the unity gain frequency and the phase margin at the unity gain frequency. Additionally, resistor 222 of the Miller compensation circuit can be used to move the RHP zero to the LHP and set the frequency of the LHP zero, which can help eliminate the effect of the pole, thereby increasing the unity gain frequency of the LDO regulator 200 and improving stability.

[0062] To further improve the fast transient response and PSRR and reduce the quiescent current when the LDO regulator 200 is operating in a steady state, the bias circuit for biasing the gate of the second amplifier stage 220 and the pass transistor 250 may include a bias circuit 230 and a dynamic bias circuit 232, wherein the bias circuit 230 may be active during both steady-state operation and transient operation of the LDO regulator 200, and the dynamic bias circuit 232 may be turned on when the output voltage of the LDO regulator 200 is lower than the target output voltage, and may be turned off under other operating conditions. The feedback circuit 270 may sense the output voltage V OUT The high frequency change of the LDO regulator 200 and the dynamic bias circuit 232 are controlled accordingly, so that when the output voltage of the LDO regulator 200 is lower than the target output voltage, the dynamic bias circuit 232 can be turned on to provide additional current to charge the gate capacitor and thus increase the voltage level at the gate of the pass transistor 250. Increasing the voltage level at the gate of the pass transistor 250 can increase the driving capability (e.g., drain current) of the pass transistor 250 and pull up the output voltage V OUT As described above, when the output voltage of the LDO regulator 200 is higher than the target output voltage, the voltage level at the gate of the NFET transistor of the common-source amplifier of the second amplifier stage 220 may increase, and the gate capacitor of the pass transistor 250 may be discharged through the NFET transistor to reduce the voltage level at the gate of the pass transistor 250, thereby reducing the drain current of the pass transistor 250 and the output voltage of the LDO regulator 200.

[0063] In this way, the bias current during steady-state operation can be reduced to reduce the quiescent current of the LDO regulator 200. During load transients or when the output voltage is otherwise below the target output voltage, the dynamic bias circuit can be turned on so that the total bias current can be higher to quickly pull up the gate voltage of the pass transistor 250, thereby improving the transient response. Therefore, the LDO regulator 200 can have a lower quiescent current without sacrificing load transient response performance. In some examples, a high-pass filter can be used to pass high-frequency changes directly to the feedback circuit 270 (e.g., without scaling down) to further improve transient response and PSRR, as described in more detail below.

[0064] Figure 3 is a schematic diagram of an example of an LDO regulator 300. The LDO regulator 300 may be Figure 2300. As LDO regulator 200, LDO regulator 300 may include an N-type pass transistor 350 (e.g., NFET or NPN) and an amplifier, which may include a first amplifier stage 310 and a second amplifier stage 320. LDO regulator 300 may also include an output feedback scaling circuit, which may include resistors 360 and 362. The amplifier and the output feedback scaling circuit may form a main feedback loop with the pass transistor 350 to regulate the output voltage V of the LDO regulator 300. OUT The LDO regulator 300 may further include a compensation circuit, which may include a resistor 322 and a capacitor 324. The compensation circuit may be a Miller compensation circuit to improve the stability of the amplifier and the main feedback loop. The LDO regulator 300 may further include a charge pump 340 and a bias circuit 330 (eg, a current source) for providing a bias current I BIAS (which may be a constant or relatively stable current) to bias or drive the pass transistor 350 and the second amplifier stage 320. The bias circuit 330 may be designed to provide a smaller bias current and may be smaller in size than the bias circuit 130 of the LDO regulator 100. These components may otherwise function in a manner similar to the corresponding components of the LDO regulator 200 described above, and therefore will not be described in detail.

[0065] LDO regulator 300 may include feedback circuit 370 and dynamic bias circuit 332 to improve transient response while reducing quiescent current during steady-state operation of LDO regulator 300. Feedback circuit 370 and dynamic bias circuit 332 may form an auxiliary feedback loop with pass transistor 350. Feedback circuit 370 may be an example of an implementation of feedback circuit 270 described above, and may sense output voltage V OUT The dynamic bias circuit 332 is controlled to provide a dynamic bias current for charging the gate of the pass transistor 350 during a load transient, thereby improving the load transient response of the LDO regulator 300 .

[0066] In the illustrated example, feedback circuit 370 may include amplifier 374, which may be a high bandwidth differential amplifier. Amplifier 374 may include a standard operational transconductance amplifier (OTA) and may be insensitive to variations in process and operating conditions. Amplifier 374 may have a low quiescent current (e.g., about 1 μA) and a small area. The input of amplifier 374 may include a reference voltage V provided by voltage divider 378. REF and the output voltage V provided by the voltage divider 376 OUTThe output voltage V provided by the high pass filter (HPF) 372 is OUT The voltage dividers 376 and 378 can be implemented using, for example, resistor dividers with a voltage divider ratio β. An example of an implementation of a high pass filter is a capacitor. The output of amplifier 374 can control dynamic bias circuit 332 to provide a dynamic bias current I DYN , to charge the node at the gate of the pass transistor 350 and the output (eg, drain of the NFET transistor) of the second amplifier stage 320. The dynamic bias circuit 332 may be a variable current source that may provide different amounts of current under different voltage control signals.

[0067] When the load of the LDO regulator 300 increases rapidly (eg, from less than or about 1 mA or 1 μA to several hundred mA in about 1 μs), the output voltage V OUT may drop temporarily because the LDO regulator 300 may need time to respond to the load change. The high-pass filter 372 can immediately reduce the output voltage V OUT The falling edge of is passed to the amplifier 374, which can then provide a higher output voltage signal to turn on the dynamic bias circuit 332, thereby providing or increasing the dynamic bias current I DYN , so that the voltage level V at the gate of the transfer transistor 350 G The increased voltage level V at the gate of the pass transistor 350 can be increased rapidly. G The voltage difference V between the gate and source of the pass transistor 350 can be increased GS , thereby increasing the drain current I of the pass transistor 350 D (or drain-to-source current I DS ) to supply higher load current and pull up the output voltage V OUT Due to the high bandwidth of amplifier 374, the auxiliary feedback loop can quickly respond to an output voltage drop to instantaneously pull up the output voltage.

[0068] In the steady-state operation or output voltage V OUT During the ramp-up period, the output of amplifier 374 may be low, and thus dynamic bias circuit 332 may not be disconnected, and thus may not provide dynamic bias current, so that second amplifier stage 320 may only receive bias current I from bias circuit 330. BIAS For example, when the load of the LDO regulator 300 decreases rapidly, the output voltage V OUT can temporarily increase the output voltage V OUTThe output voltage of the first amplifier stage 310 may be increased, which in turn may increase the drain current of the NFET transistor of the second amplifier stage 320 to discharge the gate capacitor of the pass transistor 350 more quickly, so that the voltage level V at the gate of the pass transistor 350 is G t may be reduced to reduce the drain current of pass transistor 350. Thus, when, for example, current is being drawn from the gate capacitor of pass transistor 350, feedback circuit 370 and dynamic bias circuit 332 may be disabled or otherwise inactive.

[0069] The auxiliary feedback loop formed by the feedback circuit 370 and the dynamic bias circuit 332 can have minimal or no effect on the stability of the main feedback loop for regulating the output voltage of the LDO regulator 300, and can further stabilize the output voltage level during fast transients and suppress power supply noise to achieve a higher power supply rejection ratio. As described above, the dynamic bias circuit 332 can be disconnected during steady-state operation of the LDO regulator 300, and the bias circuit 330 can be designed to provide a smaller bias current during steady-state operation of the LDO regulator 300 (e.g., compared to the bias circuit 130 of the LDO regulator 100). Therefore, during steady-state operation, the quiescent current of the LDO regulator 300 can be reduced without affecting the transient response performance of the LDO regulator 300.

[0070] As described above, a large bias current may be used to bias the second amplifier stage to push the non-dominant pole at the gate of the pass transistor to a higher frequency, thereby improving fast transient response and PSRR. For example, when the bias current of the second amplifier stage is low, the transconductance of the second amplifier stage may be low, and thus the non-dominant pole at the gate of the pass transistor may be moved to a lower frequency, which may reduce the stability and operating frequency range of the LDO regulator. The dynamic or adaptive biasing described above may be used to reduce the bias current from the charge pump, and thus reduce the total quiescent current during steady-state operation, and provide a small dynamic bias current (and thus a small gain at the output voltage V ) at relatively low loads. OUT However, if all bias currents for the gate of the second amplifier stage and the pass transistor are provided by the charge pump, the charge pump may need to support a relatively high dynamic bias current for heavy loads in order to quickly charge the gate capacitor of the pass transistor and pull up the output voltage of the LDO regulator. Therefore, the charge pump may need to have a large area in order to support the high total bias current for heavy loads. As described above, the charge pump may have low efficiency and may significantly increase the quiescent current of the LDO regulator. Therefore, it may be desirable to reduce the bias current supplied from the charge pump.

[0071] In some examples, to further reduce the quiescent current of the LDO regulator, the LDO regulator can use a split bias to provide a large bias current directly from the input voltage to the second amplifier stage, and provide a small bias current to the gate of the transfer transistor (and the level shifter of the second amplifier stage) through a charge pump. The large bias current from the input voltage to the second amplifier stage can increase the transconductance of the second amplifier stage, and thus increase the frequency of the non-dominant pole at the gate of the transfer transistor to increase the bandwidth and improve the transient and PSRR performance under both low and high loads. The level shifter (if used) can be driven by a small bias current from the charge pump, and the output voltage of the second amplifier stage can be shifted to a higher level to drive the gate of the transfer transistor so that the output voltage of the LDO regulator can be closer to the input voltage. The level shifter can also help isolate the gate of the transfer transistor from the input voltage to reduce noise in the output voltage, which may have been caused by noise in the input voltage. In this way, the quiescent current provided by the charge pump can be reduced because the charge pump may only need to provide a small bias current for level shifting and gate capacitor charging purposes, and thus the overall quiescent current of the LDO regulator can be reduced without negatively affecting the stability and transient response performance of the LDO regulator. In addition, the area of ​​the charge pump on the semiconductor die can be reduced because the area may only need to provide a relatively small bias current even when the load at the output of the LDO regulator is high.

[0072] Figure 4 Schematic diagram of an example of an NFET-based LDO regulator 400 including a split bias circuit. LDO regulator 400 may be an example of LDO regulators 200 and 300 or may be a portion thereof. As LDO regulators 200 and 300, LDO regulator 400 may include an N-type pass transistor 450 and an amplifier, which may include a first amplifier stage 410 and a second amplifier stage 420. LDO regulator 400 may also include an output feedback scaling circuit, which may include resistors 460 and 462. The amplifier, the output feedback scaling circuit, and the pass transistor 450 may form a main feedback loop for regulating the output voltage V of LDO regulator 400. OUT The LDO regulator 400 may further include a charge pump 440, which can increase the input voltage V IN Converted to a higher output voltage V CP .

[0073] Pass transistor 450 may have a voltage coupled to an input voltage V INThe gate of the LDO regulator 400 is connected to the current terminal (e.g., drain), the source coupled to the voltage output port of the LDO regulator 400, and the gate coupled to the output of the second amplifier stage 420. Thus, the pass transistor 450 can be controlled by the output of the amplifier. The pass transistor 450 can be an NFET transistor that can provide the desired current drive capability with a relatively small area on the semiconductor die, and therefore can have a relatively small parasitic gate capacitor that can be charged at a high rate and / or using a small current. The small gate capacitance can help push the non-dominant pole at the gate of the pass transistor 450 to a higher frequency, thereby improving stability and providing a fast transient response of the LDO regulator 400.

[0074] In order to provide a voltage close to the input voltage V IN The output voltage V OUT , the voltage level at the gate may need to be higher than the input voltage because the voltage difference between the gate and the source (the output of the LDO regulator 400) needs to be greater than the threshold voltage V of the pass transistor 450. T to turn on pass transistor 450. The higher voltage level at the gate may be supplied by charge pump 440. Charge pump 440 may be similar to charge pumps 140, 240, or 340 and may be supplied from an input voltage V IN Receives input and provides a higher output voltage V CP As described above, the charge pump 440 may have power losses, and may require an input current several times higher than the output current of the charge pump 440 due to voltage up-conversion and power losses.

[0075] The first amplifier stage 410 may include a differential amplifier that receives, for example, an input voltage V IN As the supply voltage, and can amplify the feedback voltage V FB With reference voltage V REF The first amplifier stage 410 may have a large output impedance, and thus the pole at the output of the first amplifier stage 410 may be the dominant pole at low frequencies. The output of the first amplifier stage 410 may be coupled to the input of the second amplifier stage 420, which may perform a voltage level shift between the output of the first amplifier stage 410 and the gate of the transfer transistor 450. In the illustrated example, the second amplifier stage 420 may include a buffer 422 and a level shifter 424. The buffer 422 may be powered by the input voltage, and may isolate the gate of the transfer transistor 450 from the first amplifier stage to achieve pole separation. The level shifter 424 may be powered by the charge pump 440, and may be used to shift the output voltage of the buffer 422 to a higher level to control the gate of the transfer transistor 450.

[0076] The LDO regulator 400 may further include a first bias circuit 432 (eg, a current source) for biasing the input voltage V IN Directly supplies bias current I to the second amplifier stage B1 and a second bias circuit 430 (eg, a current source) for providing a small bias current I from the charge pump 440 B2 To bias or drive the gates of the level shifter 424 and the pass transistor 450. The first bias circuit 432 can provide a large bias current I B1 To increase the transconductance of the buffer 422 for high loop bandwidth, the charge pump 440 and the second bias circuit 430 may only need to provide a small bias current for level shifting and gate capacitor charging purposes. Therefore, both the charge pump 440 and the second bias circuit 430 can use a smaller area on the semiconductor die, and the total quiescent current of the LDO regulator 400 can be reduced without sacrificing the stability and load transient response performance of the LDO regulator 400.

[0077] As described above, as the output voltage V OUT A scaled-down version of the feedback signal V FB The feedback signal V FB Can be compared with the reference voltage V REF is compared to determine the output voltage V OUT is at, above, or below the target output voltage. OUT Below the target output voltage, the output voltage of the first amplifier stage can increase, and thus the output voltage of buffer 422 and the level-shifted version of the output voltage of buffer 422 at the gate of pass transistor 450 can increase. Charge pump 440 and second bias circuit 430 can provide current for level-shifting and charging the gate capacitor of pass transistor 450 to a higher voltage level. The increase in gate voltage can increase the drain current of pass transistor 450, so that the output voltage V OUT can be pulled up. When the output voltage V OUT Above the target output voltage, the output voltage of the first amplifier stage can decrease, and thus the output voltage of buffer 422 and the level-shifted version of it at the gate of pass transistor 450 can also decrease. The reduction in gate voltage can reduce the drain current of pass transistor 450, so that the output voltage V OUT can be reduced. In this way, the output voltage V OUT Can be relatively stable.

[0078] Figure 5 For can be Figure 4Schematic diagram of an example of an LDO regulator 500 of an example of an LDO regulator 400. As LDO regulator 400, LDO regulator 500 can include an N-type pass transistor 550 and an amplifier, which can include a first amplifier stage 510 and a second amplifier stage 520, which can be examples of first amplifier stage 410 and second amplifier stage 420, respectively. LDO regulator 500 can also include an output feedback scaling circuit, which can include a voltage divider formed by resistor 560 and resistor 562. The amplifier, the output feedback scaling circuit, and the pass transistor 550 can form a main feedback loop for regulating the output voltage V of the LDO regulator 500. OUT The LDO regulator 500 may further include a charge pump 540, which can increase the input voltage V IN Converted to a higher output voltage V CP The charge pump 540 may be an example of the charge pump 440. The first amplifier stage 510 may be directly powered by the input voltage V IN powered by.

[0079] Figure 5 The second amplifier stage 520 shown in is an example of an implementation of the second amplifier stage 420. In the illustrated example, the second amplifier stage 520 can include an NFET transistor 522 in a common source configuration to implement the buffer 422. The second amplifier stage 520 can also include an NFET transistor 524 that can be configured to implement the level shifter 424. The gate of the NFET transistor 522 can be connected to the output of the first amplifier stage 510, the source of the NFET transistor 522 can be connected to ground, and the drain of the NFET transistor 522 can be connected to the first bias circuit 532 and the source of the NFET transistor 524. The gate of the NFET transistor 524 can be connected to the input voltage V IN or the output of charge pump 540, and the drain of NFET transistor 524 can be connected to the gate of second bias circuit 530 and pass transistor 550. Therefore, transistor 522 of first amplifier stage 510 and second amplifier stage 520 are both powered by the input voltage, while the gates of transistor 524 and pass transistor 550 can be biased or driven by the output of charge pump 540. Therefore, transistor 524 connects the gate of pass transistor to input voltage V INDomain isolation of the NFET transistor 524 and a feed-forward path for power supply noise cancellation can also be generated. For example, when there is noise on the input voltage, the gate of the NFET transistor 524 can receive the noisy input voltage, and the source of the NFET transistor 524 can also receive the noise signal through the first amplifier stage 510 and the NFET transistor 522, and thus the voltage difference between the gate and the source of the transistor 524 may not be affected by the noise in the input voltage. Therefore, the gate voltage of the pass transistor 550 may not be affected by the noise in the input voltage.

[0080] The second amplifier stage 520 may also include a compensation circuit including a resistor 526 and a capacitor 528. As described above (e.g., with respect to Figure 2 ), capacitor 528 can be used to form a pole at the output of the first amplifier stage 510, which can be the dominant pole at low frequencies due to the high output impedance of the first amplifier stage 510 and the Miller compensated capacitor 528. Resistor 526 of the Miller compensation circuit can be used to set the frequency of the LHP zero, which can help eliminate the effect of the pole, thereby increasing the unity gain frequency of the LDO regulator 500 and improving stability.

[0081] like Figure 5 As shown in FIG. 1 , the transistor 522 in the second amplifier stage 520 can be driven by the input voltage V IN Powered by the first bias circuit 532, the first bias circuit can provide a large current to the transistor 522 to increase the transconductance of the transistor 522, thereby setting a non-dominant pole at high frequencies. Therefore, the main feedback loop of the LDO regulator 500 can have a higher bandwidth for better transient response and higher PSRR. The transistor 522 in the second amplifier stage 520 can be partially biased by a current from the second bias circuit 530 through the transistor 524, where the current from the second bias circuit 530 can be small. The transistor 524 can be powered by a small current from the charge pump 540 through the second bias circuit 530 for level shifting. Therefore, this split biasing technique can allow the charge pump 540 to only bias the small bias current I B2 is provided to transistor 524 to shift the output voltage of transistor 522 to a higher level at the gate of pass transistor 550. Due to the small bias current I B2 , the area of ​​the charge pump 540 and the second bias circuit 530 on the semiconductor die can be small. Due to the small bias current from the charge pump 540, the total quiescent current of the LDO regulator 500 can also be reduced.

[0082] During operation of the LDO regulator 500, as the output voltage V OUT A scaled-down version of the feedback signal V FBThe feedback signal V FB can be compared with the reference voltage VREF to determine the output voltage V OUT is at, above, or below the target output voltage. OUT Below the target output voltage, the output voltage of the first amplifier stage can decrease, which can reduce the gate voltage of transistor 522, so that the drain current of transistor 522 can decrease and the voltage level at the drain of transistor 522 can increase. Therefore, the level-shifted version of the drain voltage of transistor 522 at the drain of transistor 524 and the gate of pass transistor 550 can also increase. Charge pump 540 and second bias circuit 530 can provide current to charge the gate capacitor of pass transistor 550 to a higher voltage level. The increase in the gate voltage of pass transistor 550 can increase the drain current of pass transistor 550, so that the output voltage V OUT can be pulled up. When the output voltage V OUT Above the target output voltage, the output voltage of the first amplifier stage can increase, which can increase the gate voltage of transistor 522, so that the drain current of transistor 522 can increase and the voltage level of the drain of transistor 522 can decrease. Therefore, the level-shifted version of the drain voltage of transistor 522 at the gate of pass transistor 550 can also decrease. The reduction in gate voltage can reduce the drain current of pass transistor 550, so that the output voltage V OUT can be reduced. In this way, the output voltage V OUT Can be relatively stable.

[0083] In some examples, the second bias circuit 530 can include: a static bias circuit configured to provide a predetermined bias current to the transistor 524; and a dynamic bias circuit configured to provide a variable dynamic bias current, which can be output-dependent to charge the gate capacitor of the pass transistor 550 during load transients, as described above with respect to, for example Figure 2 and 3 In some examples, the first bias circuit 532 may also include: a static bias circuit configured to provide a predetermined bias current to the transistor 522; and a dynamic bias circuit configured to provide a variable dynamic bias current, which may be output-dependent to provide a higher bias current to the transistor 522 during a load transient.

[0084] Figure 6Schematic diagram of an example of an LDO regulator 600 including separate bias circuits, wherein at least one bias circuit is adjustable based on the output level of the LDO regulator 600. The LDO regulator 600 may be an example of the LDO regulators 200, 300, 400, and 500, or may include the LDO regulators 200, 300, 400, and 500. In the illustrated example, the LDO regulator 600 may include an N-type pass transistor 650 and an amplifier, which may include a first amplifier stage 610 and a second amplifier stage. The second amplifier stage may include a common source amplifier formed by an NFET transistor 620, a Miller compensation circuit including a resistor 622 and a capacitor 624, and a level shifter formed by an NFET transistor 630 (which may or may not be considered part of the second amplifier stage). As described above, capacitor 624 can be used to form a pole at the output of first amplifier stage 610, which can be the dominant pole at low frequencies due to the high output impedance of first amplifier stage 610 and Miller compensated capacitor 624. Resistor 622 of the Miller compensation circuit can be used to set the frequency of the LHP zero, which can help cancel the effect of the pole, thereby increasing the unity gain frequency of LDO regulator 600 and improving stability.

[0085] LDO regulator 600 may also include an output feedback scaling circuit, which may include a voltage divider formed by resistor 660, resistor 662, and resistor 664. The amplifier, output feedback scaling circuit, and pass transistor 650 may form a main feedback loop for regulating the output voltage V of LDO regulator 600. OUT The LDO regulator 600 may further include a charge pump 640, which can increase the input voltage V IN Converted to a higher output voltage V CP The charge pump 640 may be an example of the charge pump 440. The first amplifier stage 610 may be directly powered by the input voltage V IN Transistor 620 (which may be Figure 4 The second amplifier stage 420 or buffer example) can be driven by the input voltage V IN and charge pump 640. Transistor 630 (or another level shifter) may be powered by charge pump 640. LDO regulator 600 may include other circuits for biasing the first and second amplifier stages, as well as circuits for sensing output voltage changes and controlling the bias circuit accordingly.

[0086] For example, LDO regulator 600 can include a feedback circuit (which can be an example of an implementation of feedback circuit 270 or 370), which can include a high-pass filter (e.g., capacitor 666), a first voltage divider (e.g., including resistors 662 and 664), a second voltage divider (e.g., including resistors 682 and 684), an auxiliary amplifier that can have a low gain but high bandwidth (e.g., including a current source 676 and transistors 672, 674, 678, and 680), and a voltage-to-current converter (e.g., including transistor 670). As illustrated, the output voltage V OUT The output voltage can be coupled to the gate of transistor 672 via capacitor 666 so that any high frequency changes in the output voltage can be coupled to one input of the high bandwidth, low gain auxiliary amplifier without being divided by the voltage divider. Thus, the feedback circuit may be more sensitive to high frequency changes in the output voltage. The output voltage can also be divided by resistor 660 and the sum of resistors 662 and 664 to produce a feedback voltage V for the first amplifier stage 610. FB The values ​​of resistors 660, 662, and 664 may be selected to divide the output voltage so that the auxiliary amplifier may be able to operate at low input voltages V IN (e.g., about 1.4V).

[0087] Feedback voltage V FB The feedback voltage V FB A portion of can be provided to the gate of transistor 672 through resistor 668. Therefore, the input signal at the gate of transistor 672 can be a DC level (which can be the output voltage V OUT The DC level of the output voltage V OUT The sum of the high frequency AC signals. Similarly, the reference voltage V REF The reference voltage V REF A portion of can be provided to another input of the auxiliary amplifier (e.g., the gate of transistor 674). The gates of transistors 678 and 680 are coupled together, and the sources of transistors 678 and 680 are also coupled together, so that the drain currents of transistors 678 and 680 can be the same. In a steady state, the voltage levels at the two inputs of the auxiliary amplifier can be the same, so that the drain currents of transistors 672 and 674 can be the same. When the voltage levels at the two inputs of the auxiliary amplifier are different, the drain currents of transistors 672 and 674 can be different. The difference in drain current through transistors 672 and 674 caused by the difference between the gate voltages of transistors 672 and 674 can follow through transistor 670. Therefore, a change in the drain current of transistor 670 can indicate the output voltage VOUT and can be used to control the bias current of the first bias circuit and the second bias circuit, as described in detail below.

[0088] The first bias circuit (which may be an example of an embodiment of the first bias circuit 532) may include a current source 654 and transistors 626, 628, 642, 644, and 648. The first bias circuit may be used to generate a bias current for driving transistor 620. The bias circuit generated by the first bias circuit may include a current source 654, transistors 642, and 644 (due to the same gate-source voltage V GS , which forms a first current mirror) and transistors 626 and 628 (due to the same V GS , which forms a second current mirror). For example, the current from the current source 654 can be mirrored to the transistors 626 and 620 through the first current mirror and the second current mirror. In addition, the bias current generated by the first bias circuit can include a dynamic bias current set by the transistors 670 and 648 (which form a third current mirror) and the transistors 626 and 628. For example, the current caused by the difference between the two input voltages of the auxiliary amplifier can be mirrored to the transistors 626 and 620 through the third current mirror and the second current mirror. The third current mirror can have a current ratio M that can be any desired value (e.g., 2, 4, 6, etc.), which can be achieved by, for example, making the channel width of the transistor 648 M times the channel width of the transistor 670. Therefore, the bias current generated by the first bias circuit and provided to the transistor 620 of the second amplifier stage can include a constant / static bias current and a variable / dynamic bias current, which can be controlled based on the output voltage of the LDO regulator to provide a fast transient response and improve PSRR. Both the constant static bias current and the variable dynamic bias current are derived from the input voltage V IN Instead of being provided from the charge pump 640, to improve current efficiency.

[0089] The second bias circuit (which may be an example of the second bias circuit 530) may include a current source 654 and transistors 632, 634, 636, 642, 646, and 652. The second bias circuit may be used to generate a bias current for driving transistor 630. The bias current generated by the second bias circuit may include a current source 654, transistors 642, and 646 (due to the same V GS, which forms a fourth current mirror), transistor 632, and transistors 634 and 636 (which form a fifth current mirror). For example, the current from the current source 654 can be mirrored to transistors 634 and 630 through the fourth current mirror and the fifth current mirror. In addition, the bias current generated by the second bias circuit can include a dynamic bias current set by transistors 670 and 652 (which form a sixth current mirror) and transistors 632, 634, and 636. For example, the drain current of transistor 670 caused by the difference between the two input voltages of the auxiliary amplifier can be mirrored to transistors 634 and 630 through the sixth current mirror and the fifth current mirror. The sixth current mirror can have a current ratio N that can be any desired value (e.g., 2, 4, 6, etc.), which can be achieved by, for example, making the channel width of transistor 652 N times the channel width of transistor 670. Therefore, the bias current generated by the second bias circuit and provided to the transistor 630 of the second amplifier stage can include a constant static bias current and a variable dynamic bias current, which can be dynamically controlled based on the output voltage of the LDO regulator to provide a fast transient response and improve PSRR. Both the constant static bias current and the variable dynamic bias current are provided from the charge pump 640 and can be small.

[0090] like Figure 6 As shown in FIG. 1 , the buffers (e.g., transistor 620) of the first amplifier stage 610 and the second amplifier stage are both powered by the input voltage, while the gates of the level shifter (e.g., transistor 630) and the pass transistor 650 can be powered by the output of the charge pump 640. Therefore, the level shifter (e.g., transistor 630) aligns the gate of the pass transistor 650 with the input voltage V IN domain isolation, and a feed-forward path for power supply noise cancellation can be generated. For example, when there is noise on the input voltage, the gate of NFET transistor 630 can receive the noisy input voltage, and the source of NFET transistor 630 can also receive the noise signal at the drain of transistor 626 (and the drain of transistor 620), and thus the voltage difference between the gate and source of transistor 630 may not be affected by the input voltage V IN Therefore, the drain of transistor 630 and thus the gate of pass transistor 650 may not be affected by the input voltage V IN The influence of noise in .

[0091] like Figure 6 As illustrated in and described above, the transistor 620 in the second amplifier stage can be mainly driven by the input voltage V INPower is supplied by a first bias circuit, which can provide a large current to transistor 620 to increase the transconductance of transistor 620, thereby setting a non-dominant pole at high frequency. Dynamic bias control based on the output voltage can further reduce the quiescent current during steady-state operation, and can also improve the transient response and PSRR of the LDO regulator 600. A high-pass filter in the feedback circuit for controlling the dynamic bias can make the feedback circuit more sensitive to fast transients or other high-frequency changes in the output voltage over the load and the entire output voltage range (even if the changes are relatively small compared to the DC level of the output voltage). Current mirrors with a current ratio greater than one (e.g., the third and sixth current mirrors) can further enable a larger dynamic bias current to quickly pull up the gate voltage of the transfer transistor. Therefore, the LDO regulator 600 can also have a higher bandwidth to obtain better transient response and improved power supply rejection ratio (PSRR).

[0092] In addition, since the charge pump 640 and the second bias circuit can provide relatively small currents to the gates of the transistor 630 (for level shifting) and the pass transistor 650 (for charging the gate capacitor), the area of ​​the charge pump 640 and the second bias circuit on the semiconductor die can be small. Due to the small current from the charge pump, the total quiescent current of the LDO regulator 600 can also be reduced.

[0093] Fig. 7A and 7B Contains graphs showing examples of simulation results for LDO regulators with and without a dynamic bias circuit as described herein. Fig. 7A In the example shown in Figure 1, the input voltage of the LDO regulator is V IN The target output voltage V OUT may be about 3.3V, the load capacitance may be about 1 μF, and the output load may change from about 1 mA to about 300 mA in about 1 μs, as shown by curve 702. The quiescent bias current used to charge the gate of the pass transistor may be less than about 6 μA.

[0094] exist Fig. 7A In the first example shown in FIG. 1 , the LDO regulator may be an LDO regulator without a feedback circuit including an auxiliary amplifier and a high-pass filter for dynamic bias control, such as Figure 1 . Curve 710 shows the voltage drop at the output of the LDO regulator when the load changes from about 1 mA to about 300 mA in about 1 μs. Curve 716 shows the bias current I used to charge the gate of the pass transistor of the LDO regulator during the load transient. G As shown by curves 710 and 716, during a fast load transient, the bias current IG may not increase, and the output voltage of the LDO regulator may drop by approximately ΔV OUT =76.54mV.

[0095] In a second example, the LDO regulator can be an LDO regulator with a feedback circuit that includes an auxiliary amplifier but does not include a high pass filter (e.g., HPF 372, such as capacitor 666) for dynamic bias control. Curve 712 shows the voltage drop at the output of the LDO regulator when the load changes from about 1 mA to about 300 mA in about 1 μs. Curve 718 shows the bias current I used to charge the gate of the pass transistor of the LDO regulator during a load transient. G As shown by curves 712 and 718, during a fast load transient, the bias current I G The current may increase by about 1μA, and the output voltage of the LDO regulator may drop by about ΔV OUT =61.17mV.

[0096] In a third example, the LDO regulator can be an LDO regulator with a feedback circuit that includes both an auxiliary amplifier and a high pass filter (e.g., capacitor 666) for dynamic bias control, such as LDO regulator 200, 300, or 600. Curve 714 shows the voltage drop at the output of the LDO regulator when the load changes from about 1 mA to about 300 mA in about 1 μs. Curve 720 shows the bias current I used to charge the gate of the pass transistor of the LDO regulator during the load transient. G As shown by curves 714 and 720, during fast load transients, the bias current I G The increase can be greater than about 3μA, and the output voltage of the LDO regulator can drop by about ΔV OUT =40.85 mV. Therefore, the LDO regulator with the feedback circuit disclosed herein can significantly reduce the voltage drop (e.g., from about 76.54 mV to about 40.85 mV or about 45%), and the HPF may also have a great impact on the voltage drop reduction (e.g., from about 61.17 mV to about 40.85 mV or about 33%).

[0097] exist Figure 7B In the example shown in Figure 1, the input voltage of the LDO regulator is V IN The target output voltage V OUTThe gate voltage of the pass transistor may be relatively low and may need to be increased by a large value in order to supply a load current of about 300 mA.

[0098] exist Figure 7B In the first example shown in FIG. 1 , the LDO regulator may be an LDO regulator without a feedback circuit including an auxiliary amplifier and a high-pass filter for dynamic bias control, such as Figure 1 . Curve 750 shows the voltage drop at the output of the LDO regulator when the load changes from about 1 μA to about 300 mA in about 1 μs. Curve 760 shows the bias current I used to charge the gate of the pass transistor of the LDO regulator during the load transient. G As shown by curves 750 and 760, during a fast load transient, the bias current I G may not increase, and the output voltage of the LDO regulator may drop by approximately ΔV OUT =175.19mV.

[0099] In a second example, the LDO regulator can be an LDO regulator with a feedback circuit that includes an auxiliary amplifier but does not include a high pass filter (e.g., HPF 372, such as capacitor 666) for dynamic bias control. Curve 752 shows the voltage drop at the output of the LDO regulator when the load changes from about 1 μA to about 300 mA in about 1 μs. Curve 758 shows the bias current I used to charge the gate of the pass transistor of the LDO regulator during a load transient. G As shown by curves 752 and 758, during a fast load transient, the bias current I G The current may increase by about 3μA, and the output voltage of the LDO regulator may drop by about ΔV OUT =111.22mV.

[0100] In a third example, the LDO regulator may be an LDO regulator with a feedback circuit that includes both an auxiliary amplifier and a high pass filter (e.g., HPF 372, such as capacitor 666) for dynamic bias control, such as LDO regulator 200 or 300. Curve 754 shows the voltage drop at the output of the LDO regulator when the load changes from about 1 μA to about 300 mA in about 1 μs. Curve 756 shows the bias current I used to charge the gate of the pass transistor of the LDO regulator during the load transient. G As shown by curves 754 and 756, during fast load transients, the bias current I G The increase can be greater than 7μA, and the output voltage of the LDO regulator can drop by about ΔV OUT =65.19 mV. Therefore, the LDO regulator with the feedback circuit disclosed herein can significantly reduce the voltage drop (e.g., from about 175.19 mV to about 65.19 mV or about 63%), and the HPF may also have a great impact on the voltage drop reduction (e.g., from about 111.22 mV to about 65.19 mV or about 40%).

[0101] Fig. 8A and 8B Examples of simulation results for LDO regulators with and without examples of dynamic bias circuits as described herein are shown. Fig. 8A In the example shown in Figure 1, the input voltage of the LDO regulator is V IN The target output voltage V OUT may be about 3.3V, the load capacitance may be about 1 μF, the output load may be about 50 mA, and the curve shows the power supply rejection ratio of different LDO regulators when the input voltage has noise of different frequencies. In a first example shown by curve 810, the LDO regulator may be an LDO regulator without a feedback circuit, wherein the feedback circuit includes an auxiliary amplifier and a high-pass filter for dynamic bias control, for example Figure 1 8. In a second example, shown by curve 812, the LDO regulator may be an LDO regulator with a feedback circuit that includes an auxiliary amplifier but does not include a high pass filter for dynamic bias control (e.g., HPF 372, such as capacitor 666). In a third example, shown by curve 814, the LDO regulator may be an LDO regulator with a feedback circuit that includes both an auxiliary amplifier and a high pass filter for dynamic bias control (e.g., HPF 372, such as capacitor 666), such as LDO regulator 200, 300, or 600. Fig. 8AIt is shown that the PSRR of an LDO regulator with a feedback circuit including an auxiliary amplifier and / or a high-pass filter can be improved at certain frequencies (eg, between tens of kilohertz and hundreds of kilohertz).

[0102] Figure 8B The magnitude (in dB) and phase (in degrees) of the loop gain of the main feedback loop of an LDO regulator with and without a dynamic bias circuit that can be adjusted based on the output level of the LDO regulator are shown. Figure 8B In the example shown in Figure 1, the input voltage of the LDO regulator is V IN The target output voltage V OUT It can be about 3.3V, the load capacitance can be about 1μF, and the output load can be about 0mA or 200mA. Curve 820 and curve 830 respectively show the loop gain magnitude and phase of the main feedback loop of the LDO regulator that does not have the dynamic bias circuit disclosed herein when the output load is about 0mA. Curve 822 and curve 832 respectively show the loop gain magnitude and phase of the main feedback loop of the LDO regulator that has the dynamic bias circuit disclosed herein when the output load is about 0mA. Curve 840 and curve 850 respectively show the loop gain magnitude and phase of the main feedback loop of the LDO regulator that does not have the dynamic bias circuit disclosed herein when the output load is about 200mA. Curve 842 and curve 852 respectively show the loop gain magnitude and phase of the main feedback loop of the LDO regulator that has the dynamic bias circuit disclosed herein when the output load is about 200mA. As Figure 8B As shown in Figure 2, the gain, unity-gain frequency, and phase margin of an LDO regulator can be improved as the output load increases. Figure 8B It is also shown that adding a dynamic bias circuit has minimal or no effect on the loop gain, phase margin, and stability of the main feedback loop of the LDO regulator.

[0103] Fig. 9A and 9B Examples of simulation results for LDO regulators with and without a split bias circuit as described herein are shown. In the illustrated example, the input voltage V IN The target output voltage V OUT It can be about 3.3V, and the output load can be about 50mA. Fig. 9A Curve 910 in shows the PSRR of an LDO regulator without bias separation, where all bias current for the second amplifier stage is provided by the charge pump. Fig. 9ACurve 912 in shows the PSRR of an LDO regulator (eg, LDO regulator 400 , 500 , or 600 ) with bias separation disclosed herein, where the bias current for the second amplifier stage can be provided primarily from the input voltage, and only a small portion of the bias current is provided by a charge pump. Fig. 9A It is shown that when bias splitting is used, the PSRR of the LDO regulator can be significantly improved at certain frequencies (e.g., about 11 dB at about 1 MHz). Without using bias splitting to achieve the same PSRR, if all bias current for the second amplifier stage is supplied from the charge pump, the total quiescent current and charge pump area may need to be significantly increased.

[0104] Fig. 9B An example of simulation results for the PSRR of an LDO regulator with split bias is shown. Curve 920 shows the PSRR of an LDO regulator without noise cancellation at the level shifter (e.g., transistor 524 or 630). Curve 922 shows the PSRR of an LDO regulator with noise cancellation at the level shifter, e.g., in response to a 1VAC signal to the gate of transistor 524 or 630 to cancel noise coupled to the source of transistor 524 or 630. Fig. 9B As shown in , by noise cancellation at the level shifter, the PSRR can be significantly improved at frequencies between tens of kilohertz and several MHz (eg, about 8.6 dB at about 100 KHz).

[0105] As described above, in an LDO regulator, Miller compensation can be used to perform pole separation and improve the stability of the LDO regulator. A capacitor can be used in a Miller compensation circuit to increase the capacitance at the output of the first amplifier stage, the capacitor can have a high output impedance, and thus the dominant pole at the output of the first amplifier stage can have a low frequency and can be separated from the non-dominant pole at a higher frequency. The Miller compensation circuit can also include a resistor for moving the right half plane (RHP) zero to the left half plane (LHP) to become an LHP zero, which can help eliminate the effects of the non-dominant pole, increase the unity gain frequency, and improve the phase margin. Under different operating conditions, the non-dominant pole can be at different frequencies. For example, when the load current is high, the transconductance of the transfer transistor can be high, and thus the non-dominant pole at the output of the LDO regulator can be moved to a higher frequency. When the load current is low, the transconductance of the transfer transistor can be low, and thus the non-dominant pole at the output of the LDO regulator can be moved to a lower frequency. Therefore, it may be desirable to move the LHP zero with a non-dominant pole, especially when the load current is low, in order to improve the stability and unity-gain frequency of the LDO regulator.

[0106] In some examples, a load-dependent Miller compensation loop using a current sensor, a current-to-voltage converter, and a voltage-controlled variable resistor can be used to track the load current, and the LHP zero is moved accordingly by tuning the resistance of the variable resistor in the compensation circuit. At high load currents, since the non-dominant pole can be moved to high frequencies and the unity gain frequency can be increased, the variable resistor can be controlled to reduce the resistance, thereby moving the LHP zero to a higher frequency. At low load currents, the variable resistor can be controlled to increase the resistance, thereby moving the LHP zero to a lower frequency to eliminate the effect of the non-dominant pole at the output of the LDO regulator. However, this loop may conflict with the main feedback loop of the LDO regulator when adjusting the gate voltage of the pass transistor, and thus may degrade the load transient response of the LDO regulator. For example, when the output voltage drops, the main feedback loop may increase the gate voltage of the pass transistor, but the second loop may decrease the gate voltage of the pass transistor. In addition, the frequency of the LHP zero set by the variable resistor may not be linearly proportional to the load current. Furthermore, the loop used to control the Miller compensation resistor may be susceptible to variations in process and operating conditions (eg, voltage and temperature).In some instances, a low threshold transistor may be required in order to support low input voltages.

[0107] In some examples, to overcome the above-mentioned problems in the load-dependent Miller compensation loop, the LDO regulator may include a variable Miller compensation resistor controlled based on the load current and the output voltage, and a load-dependent Miller compensation loop including two loops. The first loop may include a load current sensing circuit and a current-to-voltage conversion circuit to set a voltage that tracks the load current. The second loop may include an amplifier for setting a control voltage (e.g., gate voltage) of the Miller compensation resistor based on the difference between the output of the first amplifier stage (which may be associated with the output voltage of the LDO regulator) and the voltage set by the first loop to track the load current, so that the control voltage of the Miller compensation resistor can track both the load current and the output of the first amplifier stage (and thus the output voltage of the LDO regulator). Therefore, the second loop can coordinate the conflict between the main feedback loop of the load-dependent Miller compensation loop and the opposite way in which the first loop controls the gate voltage of the pass transistor in response to the load transient, and thus can prevent the load-dependent Miller compensation loop and the main feedback loop from changing the gate voltage of the pass transistor in opposite directions, thereby improving the load transient response. This technology can also provide a more accurate load-related zero, which can be proportional to the load current and is insensitive to variations in process and operating conditions, and can be implemented using native MOS devices, which can use fewer masks than low threshold voltage MOS devices, or share masks with other devices in a common process, thereby reducing mask costs.

[0108] Fig.10 1 is a schematic diagram of an example of an LDO regulator 1000 including an adjustable Miller compensation resistor. LDO regulator 1000 may be similar to LDO regulator 100 and may include an additional load-dependent Miller compensation loop that may move the RHP zero to the LHP to become the LHP zero and utilize a load-dependent non-dominant pole to move the LHP zero to improve the stability and unity gain frequency of the LDO regulator, especially when the load current is low. The load-dependent Miller compensation loop may include a feedback circuit 1070 that may sense the load current and generate a corresponding control signal to control a transistor for Miller compensation so that the resistance of the Miller compensation resistor may vary with the load current, thereby changing the frequency of the LHP zero, which may help eliminate the effect of the non-dominant pole.

[0109] In the illustrated example, the LDO regulator 1000 may include an N-type pass transistor 1050, an amplifier, which may include a first amplifier stage 1010 and a second amplifier stage 1020. The first amplifier stage 1010 may include a differential amplifier. The second amplifier stage 1020 may be implemented using, for example, an NFET transistor configured as a common source amplifier (or an NPN configured as a common emitter). The LDO regulator 1000 may also include a Miller compensation circuit, which may include a variable resistor 1022 (e.g., a transistor) and a capacitor 1024. The LDO regulator 1000 may further include an output feedback scaling circuit, which may include a resistor 1060 and a resistor 1062. The LDO regulator 1000 may further include a charge pump 1040 and a bias circuit 1030 (e.g., a current source) for driving the pass transistor 1050 and the second amplifier stage 1020. Additionally, the LDO regulator 1000 may include a feedback circuit 1070 that may sense a load current at the output of the LDO regulator 1000 and control the variable resistor 1022 accordingly to change the resistance of the variable resistor 1022 , thereby changing the frequency of the LHP zero according to the load current.

[0110] Pass transistor 1050 may have a voltage coupled to an input voltage V IN The drain of the LDO regulator 1000 is coupled to the source of the voltage output port of the LDO regulator 1000 and the gate is coupled to the output of the second amplifier stage 1020. Therefore, the pass transistor 1050 can be controlled by the amplifier based on the output voltage of the LDO regulator 1000. The pass transistor 1050 can be an NFET / NPN transistor that can provide the desired current drive capability in a relatively small area on the semiconductor die and can have a small parasitic gate capacitor that can be charged at a high rate and / or using a small current. In order to provide a voltage close to the input voltage VIN The output voltage V OUT , the voltage level at the gate of the pass transistor 1050 may need to be higher than the input voltage because the voltage difference between the gate and the source of the pass transistor 1050 needs to be greater than the threshold voltage V T In order to turn on the pass transistor 1050. The higher voltage level at the gate of the pass transistor 1050 can be supplied by the charge pump 1040 or another voltage boosting circuit (eg, a bootstrap circuit). The charge pump 1040 can be supplied from the input voltage V IN Receives an input and can store energy (e.g., using a capacitor) to provide a voltage higher than the input voltage V IN The output voltage V CP .like Fig.10 As shown in FIG. 1 , the output voltage V of the charge pump 1040 CP 1050. The charge pump 1040 may be used to drive a bias circuit 1030 (e.g., a current source) to set a voltage level at the gate of the pass transistor 1050. The output of the charge pump 1040 may also be used to bias the second amplifier stage 1020, the output of which is coupled to the gate of the pass transistor 1050. As described above, the charge pump 1040 may have power losses due to voltage up-conversion and power losses, and may require an input current that is several times higher than the output current of the charge pump 1040.

[0111] The amplifier can be based on the feedback voltage V FB With reference voltage V REF The difference between them drives the pass transistor 1050 to regulate the output voltage V OUT The reference voltage may come from, for example, a bandgap voltage reference or another reference voltage generating circuit. The feedback voltage V FB Can be the output voltage V OUT The values ​​of resistors 1060 and 1062 may be selected based on the voltage levels of the reference voltage and the target output voltage to set a desired voltage divider ratio of the voltage divider formed by resistors 1060 and 1062. The first amplifier stage 1010 may include a voltage divider formed by, for example, an input voltage V IN The differential amplifier is powered and can amplify the feedback voltage V FB With reference voltage V REFThe output of the first amplifier stage 1010 may be used as an input to the second amplifier stage 1020, which may perform a voltage level shift between the output of the first amplifier stage 1010 and the gate of the pass transistor 1050. In the illustrated example, the second amplifier stage 1020 may include a common source amplifier formed by an NFET transistor. The gate of the NFET transistor may be coupled to the output of the first amplifier stage 1010, the source of the NFET transistor may be coupled to ground, whereas the drain of the NFET transistor may be coupled to the bias circuit 1030 and the gate of the pass transistor 1050. The second amplifier stage 1020 may act as a buffer isolating the output of the first amplifier stage 1010 from the gate of the pass transistor 1050, such that the pole at the gate of the pass transistor 1050 may be separated from the pole at the output of the first amplifier stage 1010.

[0112] When the input voltage V IN changes and / or the load current at the output of the LDO regulator 1000 changes, the output voltage V OUT When the output voltage V OUT When the output voltage is below the target, the positive input of the first amplifier stage 1010 can be reduced, and thus the output voltage of the first amplifier stage and the gate voltage of the NFET transistor of the second amplifier stage 1020 can also be reduced, so that the drain current of the NFET transistor of the second amplifier stage 1020 can be reduced, and the voltage drop across the NFET transistor of the second amplifier stage 1020 can be increased. Therefore, the voltage level at the gate of the pass transistor 1050 can be increased, thereby increasing the drain current of the pass transistor 1050 to pull up the output voltage V OUT When the output voltage V OUT Above the target output voltage, the voltage level at the positive input of the first amplifier stage 1010 may increase, and thus the output voltage of the first amplifier stage 1010 and the gate voltage of the NFET transistor of the second amplifier stage 1020 may also increase. The higher gate voltage of the NFET transistor of the second amplifier stage 1020 may increase the drain current of the NFET transistor, so that the gate capacitor of the pass transistor 1050 may be discharged faster through the NFET transistor of the second amplifier stage 1020, and thus the voltage level at the gate of the pass transistor 1050 may decrease. The reduction in the gate voltage of the pass transistor 1050 may reduce the drain current of the pass transistor 1050, thereby reducing the output voltage V OUT .

[0113] In order to increase the unity gain frequency and load transient response performance while improving the phase margin and stability of the LDO regulator 1000, the variable resistor 1022 and the capacitor 1024 of the Miller compensation circuit can be connected in series between the output of the first amplifier stage 1010 and the gate of the pass transistor 1050 (and the output of the second amplifier stage 1020). The first amplifier stage 1010 can have a high output impedance, and therefore due to the high output impedance of the Miller compensation circuit and the capacitor 1024, the pole at the output of the first amplifier stage 1010 can be a dominant pole at low frequencies. The second amplifier stage 1020 can be biased at a high bias current, and therefore can have a high transconductance, and the gate capacitance of the NFET pass transistor 1050 can be small, so that the output of the second amplifier stage 1020 and the pole at the gate of the pass transistor 1050 can be a non-dominant pole at a higher frequency. In addition, the pole at the output of the LDO regulator 1000 can be another non-dominant pole, whose frequency can depend on the load current of the LDO regulator 1000. For example, when the load current is high, the transfer transistor 1050 can have a high transconductance, and thus the frequency of the non-dominant pole at the output of the LDO regulator 1000 can be high. When the load current is low, the transfer transistor 1050 can have a lower transconductance, and thus the frequency of the non-dominant pole at the output of the LDO regulator 1000 can be reduced. The separation of the dominant pole and the non-dominant pole can increase the unity gain frequency and the phase margin at the unity gain frequency. In addition, the variable resistor 1022 of the Miller compensation circuit can be used to set the frequency of the LHP zero to track the non-dominant pole (e.g., the non-dominant pole at the output of the LDO regulator 1000), which can help eliminate the influence of the non-dominant pole, thereby increasing the unity gain frequency of the LDO regulator 1000 and improving stability.

[0114] like Fig.10 As described in , the load-dependent Miller compensation loop may include a feedback circuit 1070 that can sense the load current and generate a corresponding control voltage signal to control the variable resistor 1022. The feedback circuit 1070 may also sense the output voltage of the first amplifier stage 1010 and generate a control voltage signal based in part on the output voltage of the first amplifier stage 1010. Thus, the load-dependent Miller compensation loop may include the following: Fig.10. The first loop (loop 1) may include a current sensing and current-to-voltage conversion circuit (e.g., part of feedback circuit 1070) to set a voltage level that tracks the load current. The second loop (loop 2) may include an amplifier (e.g., part of feedback circuit 1070) that sets a control voltage based on the difference between the output voltage of the first amplifier stage 1010 (which may depend on the output voltage of the LDO regulator 1000) and the voltage level set by the first loop based on the load current. The second loop may prevent the first loop and the main feedback loop from changing the gate voltage of the pass transistor 1050 in opposite directions, thereby improving load transient response.

[0115] Fig.11 For can be Fig.10 Schematic diagram of an example of an LDO regulator 1000 of an example of an LDO regulator 1100. As an LDO regulator 1000, the LDO regulator 1100 may include an N-type pass transistor 1150 (e.g., NFET or NPN) and an amplifier, which may include a first amplifier stage 1110 and a second amplifier stage 1120. The first amplifier stage 1110 may include a differential amplifier. The second amplifier stage 1120 may be implemented using, for example, an NFET transistor configured as a common source amplifier. The LDO regulator 1100 may also include an output feedback scaling circuit, which may include a voltage divider formed by a resistor 1160 and a resistor 1162. The amplifier, the output feedback scaling circuit, and the pass transistor 1150 may form a main feedback loop for regulating the output voltage V of the LDO regulator 1100. OUT The LDO regulator 1100 may further include a charge pump 1140 and a bias circuit 1130 (eg, a current source) for driving a pass transistor 1150 and a second amplifier stage 1120. These components may function in a manner similar to corresponding components of the LDO regulators 200, 300, or 1000 described above, for example, and thus are no longer described with respect to FIG. Fig.11 Detailed description.

[0116] As illustrated, the LDO regulator 1100 may also include a Miller compensation circuit, which may include a transistor 1122 and a capacitor 1124. The LDO regulator 1100 may further include an amplifier 1176 and transistors 1170, 1172, and 1174, which may be used to control the gate voltage of the transistor 1122 based on the output voltage and output load current of the LDO regulator 1100. The transistors 1170, 1172, and 1174 may be the gate voltage of the transistor 1122 described above. Fig.10 The amplifier 1176 may be part of the first loop (loop 1) of the load-dependent Miller compensation loop described above. Fig.10Part of the second loop (Loop 2) of the load-dependent Miller compensation loop is described.

[0117] In the first loop, the load current at the output of the LDO regulator 1100 can be sensed and mirrored from transistor 1170 to transistor 1172 and transistor 1174, so that the voltage level V at the source of transistor 1174 and the drain of transistor 1172 is C It can be a function of the load current. Because the gate of transistor 1122 is connected to the gate of transistor 1174, if the source of transistor 1122 and the source of transistor 1174 are also at the same voltage level, then the drain current of transistor 1174 can be mirrored to transistor 1122, so that the frequency of the LHP zero (after being moved from the RHP), which may depend on the operating conditions of transistor 1122, can be a function of the load current (e.g., a linear function). For example, when the load current is low, the current mirrored to transistor 1122 can be low, and thus the LHP zero can be at a lower frequency to eliminate the effect of the non-dominant pole at the lower frequency at the output of the LDO regulator 1100. When the load current is high, the current mirrored to transistor 1122 can be high, and thus the LHP zero can be at a higher frequency to eliminate the effect of the non-dominant pole at the higher frequency at the output of the LDO regulator 1100.

[0118] As described above, when the output voltage of the LDO regulator 1100 decreases due to, for example, an increase in load current, the output of the first amplifier stage 1110 of the main feedback loop may also decrease, so that the drain current of the NFET transistor of the second amplifier stage 1120 may decrease and the gate voltage of the pass transistor 1150 may increase, thereby increasing the load current and pulling up the output voltage. However, when the output of the first amplifier stage 1110 of the main feedback loop decreases, the drain current of the transistor 1122 may increase due to the larger V GS The gate voltage of the transfer transistor 1150 may increase due to the increase in current flowing through the transistor 1122 to charge the capacitor 1124 and discharge the gate capacitor of the transfer transistor 1150. Therefore, during the load transient, the main feedback loop and the first loop of the load-dependent Miller compensation loop may oppositely change the gate voltage of the transfer transistor 1150. This conflict may be reconciled by the second loop of the load-dependent Miller compensation loop, as described in detail below.

[0119] In the second loop, amplifier 1176 is used to adjust the gate voltages of transistors 1122 and 1174 and the source voltage of transistor 1174 based on the source voltage of transistor 1122 (e.g., the output voltage of the first amplifier stage 1110), so that the gate voltages of transistors 1122 and 1174 can track both the output voltage of the first amplifier stage 1110 (and therefore the output voltage of the LDO regulator 1100) and the source voltage of transistor 1174 (and therefore the load current), and the source voltage of transistor 1122 and the source voltage of transistor 1174 can be approximately equal. For example, if the output voltage of the first amplifier stage 1110 (and the output voltage of the LDO regulator 1100) decreases, the output voltage of the amplifier 1176 and therefore the gate voltage of the transistor 1174 may also decrease to reduce the source voltage of the transistor 1174 so that the source voltage of the transistor 1174 and the source voltage of the transistor 1122 may be approximately equal so that the sensed load current may be more accurately mirrored to the transistor 1122 through the transistor 1174. Thus, the drain current of the transistor 1122 may be similar to the drain current of the transistor 1174, even though there may be variations in the manufacturing process and operating conditions (e.g., operating voltage and temperature). Thus, the load-dependent LHP zero may be accurately set based on the load current (e.g., proportional to the load current). The second loop may also allow the use of a natural MOS device, which may use fewer masks than a low threshold voltage MOS device, or share masks with other devices in a common process, thereby reducing mask costs.

[0120] In addition, if Fig.11 , when the output voltage of the first amplifier stage 1110 (and the output voltage of the LDO regulator 1100) decreases, the output voltage of the amplifier 1176 and therefore the gate voltages of the transistors 1122 and 1174 may also decrease to reduce the drain current of the transistor 1122 so that the gate voltage of the transfer transistor 1150 may not decrease due to the discharge through the transistor 1122 (and the charging of the capacitor 1124). Therefore, the second loop can mitigate the undesirable effects of the first loop to improve the load transient response. For example, when the load current increases from a low value to a high value, the output voltage of the LDO regulator can decrease, which may cause the output voltage of the first amplifier stage 1110 and the output voltage of the amplifier 1176 to decrease. Therefore, the gate voltage of the transistor 1122 can decrease so that the drain current of the transistor 1122 can decrease, or the transistor 1122 can be turned off and may not draw current from the gates of the bias circuit 1130 and the transfer transistor 1150. Therefore, when the load increases and the output voltage decreases, the gate voltage of the pass transistor 1150 may not decrease through the first loop.

[0121] Fig.12 1 is a schematic diagram of an example of an LDO regulator 1200. The LDO regulator 1200 may be an example of the LDO regulator 1000 or 1100. As the LDO regulator 1100, the LDO regulator 1200 may include an N-type pass transistor 1250 (e.g., NFET or NPN) and an amplifier, which may include a first amplifier stage 1210 and a second amplifier stage 1220. The first amplifier stage 1210 may include a differential amplifier. The second amplifier stage 1220 may be implemented using, for example, an NFET transistor configured as a common source amplifier (or an NPN transistor configured as a common emitter amplifier). The LDO regulator 1200 may also include an output feedback scaling circuit, which may include a voltage divider formed by a resistor 1260 and a resistor 1262. The amplifier, the output feedback scaling circuit, and the pass transistor 1250 may form a main feedback loop for regulating the output voltage V of the LDO regulator 1200. OUT . The LDO regulator 1200 may further include a charge pump 1240 and a bias circuit 1230 (e.g., a current source) for driving a pass transistor 1250 and a second amplifier stage 1220. The LDO regulator 1200 may also include a Miller compensation circuit, which may include a transistor 1222 and a capacitor 1224. The LDO regulator 1200 may further include an amplifier 1276 and transistors 1270, 1272, and 1274, which may be used to control a gate voltage of transistor 1222 based on an output voltage and an output load current of the LDO regulator 1200. Transistors 1270, 1272, and 1274 may be as described above with respect to Fig.10 and 11 The amplifier 1276 may be part of the first loop (loop 1) of the load-dependent Miller compensation loop described above. Fig.10 and 11 The components may function in a similar manner to, for example, the corresponding components of the LDO regulator 1000 or 1100 described above, and therefore are no longer related to Fig.12 Detailed description.

[0122] Fig.12 An example of an implementation of amplifier 1276 is shown, which may be a differential amplifier including four transistors 1280, 1282, 1284, and 1286 without using a bias circuit. Fig.12 Transistors 1284 and 1286 are shown connected to the output of the charge pump via bias circuit 1230. In other examples, transistors 1284 and 1286 may be connected to an input voltage V INTransistor 1280 may have the same gate and source voltages as the NFET transistor of the second amplifier stage 1220, and may therefore have a drain current proportional to the drain current of the NFET transistor of the second amplifier stage 1220. Therefore, no additional bias current is required for amplifier 1276. The effective bias current for amplifier 1276 may depend on the size ratio between transistor 1280 and the NFET transistor of the second amplifier stage 1220.

[0123] Fig.12 Also shown is an example of an implementation of a load current sensing circuit that may include transistors 1252 and 1254 (which form a current mirror) and resistor 1256. Resistor 1256 may be connected to the source of pass transistor 1250 (the output of LDO regulator 1200) and the drain and gate of transistor 1252. The source of transistor 1252 may be connected to the gate of pass transistor 1250. Thus, the voltage across resistor 1256 and transistor 1252 may be equal to the voltage difference V between the gate and source of pass transistor 1250. GS , where the V of the pass transistor 1250 GS The V of the pass transistor 1250 may indicate the drain current of the pass transistor 1250. GS With the V of transistor 1252 GS (or V DS ) can be the voltage drop across resistor 1256. Therefore, the drain current of transistor 1252 can be equal to the V of pass transistor 1250. GS With the V of transistor 1252 GS The difference between the current and the load current divided by the resistance of resistor 1256 can therefore indicate the load current (or change in load current) of LDO regulator 1200. The drain current of transistor 1252 can then be mirrored to transistors 1254 and 1270, and ultimately to transistor 1222 through a pair of current mirrors formed by transistors 1270 and 1272 and a pair of current mirrors formed by transistors 1272 and 1222, as described above with respect to Fig.11 described.

[0124] Fig.13A and 13B Graphs showing examples of simulation results for LDO regulators with and without examples of adjustable Miller compensation resistors as described herein. Fig.13A and 13B In the example shown in Figure 1, the input voltage of the LDO regulator is V IN can be about 4.3V, and the target output voltage V OUTIt may be about 3.3 V. In a first example, the first LDO regulator may be similar to LDO regulators 1000, 1100, or 1200, but may not have the second loop of the load-dependent Miller compensation loop. In a second example, the second LDO regulator may be similar to LDO regulators 1000, 1100, or 1200, and may have both the first loop and the second loop of the load-dependent Miller compensation loop described above.

[0125] exist Fig.13A In the example shown in , the output load can be stepped from about 1 mA to about 300 mA in about 1 μs. Curve 1310 shows an example of the output voltage of the first LDO regulator. Curve 1320 shows the gate voltage of the Miller compensation resistor (e.g., variable resistor 1022, transistor 1122, or transistor 1122) of the first LDO regulator. Curve 1340 shows an example of the sensed load current of the first LDO regulator, which can be a portion of the load current of the first LDO regulator. Curve 1312 shows an example of the output voltage of the second LDO regulator. Curve 1330 shows the gate voltage of the Miller compensation resistor (e.g., variable resistor 1022, transistor 1122, or transistor 1122) of the second LDO regulator. Curve 1342 shows an example of the sensed load current of the second LDO regulator, which can be a portion of the load current of the second LDO regulator.

[0126] exist Fig. 13B In the example of simulation results shown in , the output load may include a series of short pulses with a period of about 60 μs and a pulse width of about 30 μs, as shown by curve 1360. Each pulse may include a rising edge of about 1 mA to about 300 mA and a falling edge of about 300 mA to about 1 mA. Curve 1350 shows the output voltage of the first LDO regulator, while curve 1352 shows the output voltage of the second LDO regulator.

[0127] As Fig.13A and 13B It is shown that in the second LDO regulator having a second loop of a load-dependent Miller compensation loop, the gate voltage of the Miller compensation resistor can better track the output voltage of the LDO regulator, and the well-regulated LHP zero can help improve the load transient response. For example, Fig. 13B It is shown that the undershoot of the output voltage of the second LDO regulator may be more than about 30% lower than the undershoot of the output voltage of the first LDO regulator, at least in part because the second loop may mitigate the undesirable change of the gate voltage of the pass transistor by the first loop, which may be opposite to the change of the gate voltage of the pass transistor by the main feedback loop.

[0128] Fig.14A and 14B Graphs showing examples of simulation results for LDO regulators with and without examples of adjustable Miller compensation resistors as described herein. Fig.14A and 14B In the example shown in Figure 1, the input voltage of the LDO regulator is V IN can be about 4.3V, and the target output voltage V OUT It may be about 3.3 V. In a first example, the first LDO regulator may be similar to LDO regulators 1000, 1100, or 1200, but may not have the second loop of the load-dependent Miller compensation loop. In a second example, the second LDO regulator may be similar to LDO regulators 1000, 1100, or 1200, and may have both the first loop and the second loop of the load-dependent Miller compensation loop described above.

[0129] exist Fig.14A In the example shown in , curve 1410 shows the magnitude of the small signal loop gain of the first LDO regulator. Curve 1420 shows the phase of the small signal loop gain of the first LDO regulator. Curve 1412 shows the magnitude of the small signal loop gain of the second LDO regulator. Curve 1422 shows the phase of the small signal loop gain of the second LDO regulator.

[0130] exist Fig. 14B In the example shown in , the output load may include a series of short pulses with a period of about 100 μs and a pulse width of about 50 μs, as shown by curve 1440. Each pulse may include a rising edge of about 1 mA to about 300 mA and a falling edge of about 300 mA to about 1 mA. Curve 1430 shows the output voltage of the first LDO regulator, while curve 1432 shows the output voltage of the second LDO regulator.

[0131] As described, the second LDO regulator having a second loop with a load-dependent Miller compensation loop can have similar small signal loop stability as the first LDO regulator, but can still improve load transient response compared to the first LDO regulator. Fig. 14B As described in , the undershoot of the output voltage of the second LDO regulator may be more than 40% lower than the undershoot of the output voltage of the first LDO regulator.

[0132] In some examples, the LDO regulator can implement two or more of the techniques disclosed herein, including a dynamic bias circuit for output voltage control, a separate bias circuit for reducing charge pump current, and an additional loop for load-dependent Miller compensation to control the resistance of a variable Miller compensation resistor using a voltage signal that tracks both the load current and the output voltage of the first amplifier stage. Thus, as described above and below, the LDO regulator disclosed herein can have a small device area, low quiescent current, fast response to load transients, low complexity, low current from the charge pump, high PSRR, and lower output noise, and can be less sensitive to variations in process and operating conditions.

[0133] Fig.15 1 is a schematic diagram of an example of an LDO regulator 1500 incorporating a combination of various techniques as described herein. The LDO regulator 1500 may include the above-described LDO regulators, such as Figures 10 to 12 The load-dependent Miller compensation loop described above may also include the above-described Figures 2 to 6 The described separate bias circuit can adjust the dynamic bias circuit. Fig.15 In the example illustrated in FIG. 1 , the LDO regulator 1500 may include a pass transistor 1550 and an amplifier, which may include a first amplifier stage 1510 and a second amplifier stage 1520. The first amplifier stage 1510 may include a differential amplifier. The second amplifier stage 1520 may use, for example, an NFET transistor configured as a common source amplifier (e.g., Figure 2 , 3 10 to 12) or may include an NFET transistor configured as a common source amplifier and level shifter (such as, for example Figures 4 to 6 15). LDO regulator 1500 may also include an output feedback scaling circuit, which may include a voltage divider formed by resistor 1560 and resistor 1562. The amplifier, output feedback scaling circuit, and pass transistor 1550 may form a main feedback loop for regulating the output voltage V of LDO regulator 1500. OUT The LDO regulator 1500 may further include a charge pump 1540 for driving the pass transistor 1550 and the second amplifier stage 1520 .

[0134] As illustrated, the LDO regulator 1500 may also include a Miller compensation circuit, which may include a variable resistor 1522 (e.g., implemented using a transistor) and a capacitor 1524. The LDO regulator 1500 may further include a feedback circuit 1580 and an amplifier 1586 for controlling the variable resistor 1522 based on the load current and the output of the first amplifier stage 1510. The feedback circuit 1580 may include a circuit configured to sense the load current of the LDO regulator 1500 (e.g., by sensing the V of the pass transistor 1550). GS ) of the current sensing circuit 1582, such as the above Fig.12 The feedback circuit 1580 may also include a current-to-voltage converter 1584 that may set a voltage that tracks the load current, as described above with respect to Fig.12 Amplifier 1586 can generate a control voltage for controlling variable resistor 1522 based on the output of first amplifier stage 1510 and a voltage that tracks the load current. In this way, the LHP zero of LDO regulator 1500 can be controlled by controlling the resistance of variable resistor 1522 based on the load current to track the non-dominant pole at the output of LDO regulator 1500. The resistance of variable resistor 1522 can also be controlled based on the output voltage to improve the load transient response and PSRR of LDO regulator 1500, as described above with respect to Fig.12 Also as described above, this technique may also be insensitive to variations in process and operating conditions, and may be implemented using native MOS devices, which may use fewer masks than low threshold voltage MOS devices, or share masks with other devices in a common process, thereby reducing mask costs.

[0135] The LDO regulator 1500 may also include a split bias circuit, which may include a first bias circuit 1530 and a second bias circuit 1532 for driving the second amplifier stage 1520, as described above with respect to, for example, Figures 4 to 6 As described above. The first bias circuit 1530 can be coupled to the input voltage and receive current from the input voltage. The second bias circuit 1532 can be coupled to the charge pump 1540 and receive current from the charge pump. In this way, the current supplied by the charge pump 1540 can be reduced, and the power consumption and size of the LDO regulator 1500 can be reduced. In addition, the first bias circuit 1530 can be designed to provide a large current to move the non-dominant pole at the gate of the pass transistor 1550 to a higher frequency, thereby increasing the unity gain frequency of the LDO regulator 1500 and improving stability and load transient response.

[0136] In some examples, the LDO regulator 1500 may also include a dynamic bias circuit that can provide a bias current based on the output voltage or load of the LDO regulator 1500, as described above with respect to, for example, Figure 2 , 3 and 6. For example, as described above with respect to Figure 6 As described, the dynamic bias circuit may include a third bias circuit 1534 and a fourth bias circuit 1536 that may be controlled by a feedback circuit 1570, wherein the third bias circuit 1534 may be coupled to an input voltage and receive current from the input voltage, and the fourth bias circuit 1536 may be coupled to a charge pump 1540 and receive current from the charge pump 1540. The third bias circuit 1534 and the fourth bias circuit 1536 may be disconnected during steady-state operation of the LDO regulator 1500, and may be turned on to provide more bias current when the output voltage decreases due to, for example, an increase in the load of the LDO regulator 1500. In this way, the load transient response and PSRR of the LDO regulator 1500 may be improved.

[0137] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0138] Additionally, in this specification, the statement "based on" means "based at least in part on." Thus, if X is based on Y, then X can vary as a function of at least a portion of Y and any number of other factors. If action X is "based on" Y, then action X can be based at least in part on at least a portion of Y.

[0139] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the described function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the described function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0140] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnections between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their ends.

[0141] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0142] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used in practice with little or no change to the rest of the circuitry. For example, field effect transistors ("FETs") (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs—e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0143] In the claims reference may be made to the control input of a transistor and its current terminals. In the case of a FET, the control input is the gate, and the current terminals are the drain and the source. In the case of a BJT, the control input is the base, and the current terminals are the collector and the emitter.

[0144] When a FET is “turned on” or “enabled” as used herein, it means that there is a conducting channel of the FET and the drain current I D (or drain-to-source current I DS ) can flow through the FET. When a FET is "off" or "disabled" in this article, it means that there is no conductive channel, so the drain current will not flow through the FET. However, an "off" FET can have current flowing through the body diode of the transistor.

[0145] The circuits described herein may be reconfigured to include additional or different components to provide functionality at least partially similar to functionality available before component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the displayed resistor. For example, a resistor or capacitor shown and described as a single component herein may actually be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described as a single component herein may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0146] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all features described as external to the integrated circuit may be included in the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0147] Use of the phrase "ground" in the foregoing description includes chassis ground, ground line ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification.

[0148] In this specification, unless otherwise specified, “about”, “approximately” or “substantially” preceding a parameter means within + / - 10% of the parameter, or if the parameter is zero, within a reasonable value range of about zero.

[0149] As used herein, the terms "and" and "or" may include multiple meanings, which are also expected to depend at least in part on the context in which such terms are used. Typically, "or", if used to associate a list (e.g., A, B, or C), is intended to represent A, B, and C (here in an inclusive sense), as well as A, B, or C (here in an exclusive sense). In addition, as used herein, the term "one or more" may be used to describe any feature, structure, or characteristic in a singular form, or may be used to describe a certain combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example, and the claimed subject matter is not limited to this example. In addition, if used to associate a list such as A, B, or C, the term "at least one of..." may be interpreted as meaning A, B, C, or a combination of A, B, and / or C, such as AB, AC, BC, AA, ABC, AAB, ACC, AABBCCC, etc.

[0150] Although various examples have been described in detail, it should be understood that various changes, substitutions and modifications can be made therein without departing from the scope defined by the appended claims. The devices, structures, materials and processes discussed above are examples. Various examples can omit, substitute or add various programs or components when appropriate. In addition, the features described about certain examples can be combined in various other examples. Different aspects and elements of examples can be combined in a similar manner. In addition, technology develops, and therefore, many elements are examples, which do not limit the scope of the present disclosure to those specific examples.

[0151] Specific details are given in the specification to provide a thorough understanding of the examples. However, examples can be practiced without these specific details. For example, well-known circuits, processes, systems, structures and techniques can be shown without unnecessary details to avoid confusing the examples. This description only provides examples and is not intended to limit the scope, applicability or configuration of the present invention. On the contrary, the foregoing description of the examples will provide a stimulating description for implementing various examples for those skilled in the art. Various changes can be made to the functions and arrangements of the elements without departing from the spirit and scope of the present disclosure. Within the scope of the claims, modifications may be made in the described examples, and other examples are possible.

Claims

1. A device comprising: A first transistor coupled between the power input and the power output, the first transistor being an N-type transistor and having a first transistor control input; a first amplifier stage having a reference input, a feedback input, and a first amplifier output, the feedback input being coupled to the power output; a second amplifier stage having an amplifier input coupled to the first amplifier output and a second amplifier output coupled to the first transistor control input; and A first bias circuit is coupled to the first transistor control input, the first bias circuit having an electrical control input coupled to the power output.

2. The apparatus of claim 1, wherein the second amplifier stage comprises a second transistor having a second transistor control input coupled to the amplifier input and a current input coupled to the second amplifier output.

3. The apparatus of claim 1 , further comprising a voltage boost circuit coupled to the power input and including a boosted voltage output, wherein the first bias circuit is coupled between the boosted voltage output and the first transistor control input.

4. The apparatus of claim 3, wherein the voltage boost circuit comprises at least one of a charge pump circuit or a bootstrap circuit.

5. The apparatus of claim 3, further comprising a second bias circuit coupled between the boosted voltage output and the second amplifier output.

6. The apparatus of claim 1, further comprising a feedback circuit electrically coupling the power output to the electrical control input of the first bias circuit.

7. The apparatus of claim 6, wherein the feedback circuit comprises: a negative feedback circuit having a negative input, a positive input coupled to the reference input, and a feedback output coupled to the electrical control input of the first bias circuit; and A high pass filter is coupled between the power output and the negative input.

8. The apparatus of claim 7, wherein: The negative feedback circuit includes a differential amplifier; and The high pass filter includes a capacitor.

9. The apparatus of claim 7, wherein the feedback circuit further comprises: a first voltage scaling circuit coupling the reference input to the positive input; and A second voltage scaling circuit couples the power output to the negative input.

10. The apparatus of claim 1, wherein the first bias circuit comprises a current mirror having a gain ratio greater than one.

11. The apparatus of claim 1, wherein: The second amplifier stage includes a buffer and a level shifter; The buffer comprises a buffer input, a buffer output and a bias input, the buffer input being coupled to the first amplifier output; The level shifter comprises a level shifter input coupled to the buffer output and a level shifter output coupled to the second amplifier output; and The apparatus further includes a second bias circuit coupled between the power input and the bias input of the buffer.

12. The apparatus of claim 11, wherein the level shifter comprises a second transistor coupled between the buffer output and the second amplifier output, the second transistor comprising a second transistor control input coupled to the power input.

13. The apparatus of claim 11, wherein the buffer comprises a second transistor having a second transistor control input coupled to the amplifier input and a current input coupled to the bias input.

14. The apparatus of claim 11, further comprising a feedback circuit coupled between the power output and a bias control input of the second bias circuit.

15. The apparatus of claim 14, wherein the second bias circuit comprises a current mirror having a gain ratio greater than one.

16. The apparatus of claim 1, further comprising a compensation circuit coupled between the first amplifier output and the second amplifier output, the compensation circuit comprising a capacitive element and a resistive element connected in series between the first amplifier output and the first transistor control input.

17. The apparatus of claim 16, wherein: The resistive element includes a second transistor having a second transistor control input coupled to the power output; and The apparatus further includes a feedback circuit coupling the power output to the second transistor control input.

18. The apparatus of claim 17, wherein the feedback circuit comprises: a current sensing circuit coupled to the power output; and A current-to-voltage conversion circuit is coupled between the current sensing circuit and the second transistor control input.

19. The apparatus of claim 18, wherein the current-to-voltage conversion circuit comprises: a third transistor having a current terminal coupled to the output of the current sensing circuit, the third transistor having a third transistor control input coupled to the second transistor control input; and a differential amplifier having a positive input coupled to the first amplifier output, a negative input coupled to the current terminal of the third transistor, and a third amplifier output coupled to the second transistor control input and the third transistor control input.

20. An apparatus comprising: A first transistor coupled between the power input and the power output, the first transistor being an N-type transistor and having a first transistor control input; a first amplifier stage having a reference input, a feedback input, and a first amplifier output, the feedback input being coupled to the power output; a second amplifier stage having an amplifier input coupled to the first amplifier output and a second amplifier output coupled to the first transistor control input; and A capacitor and a second transistor are coupled in series between the first amplifier output and the first transistor control input, the second transistor having a second transistor control input electrically coupled to the power output and the first amplifier output.

21. The apparatus of claim 20, further comprising a feedback circuit coupling the power output and the first amplifier output to the second transistor control input.

22. An apparatus comprising: a transistor coupled between the power input and the power output, the transistor being an N-type transistor and having a transistor control input; an amplifier having a reference input, a feedback input, and an amplifier output, the feedback input being coupled to the power output; a buffer having a buffer input, a bias input, and a buffer output, the buffer input being coupled to the amplifier output; a level shifter having a level shifter input coupled to the buffer output and a level shifter output coupled to the transistor control input; a first bias circuit coupled between the power input and the bias input of the buffer; and A second bias circuit is coupled to the level shifter output and the transistor control input.

23. The apparatus of claim 22, further comprising a voltage boost circuit coupled to the power input and including a boosted voltage output, wherein the second bias circuit is coupled between the boosted voltage output and the transistor control input.

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