A low-power linear voltage regulator circuit and a regulated power supply

Abstract

The present invention relates to a low-power linear voltage regulator circuit and a regulated power supply. Among them, the low-power linear voltage regulator circuit includes a depletion-type field-effect transistor with a startup threshold less than zero; a feedback circuit connected in series with the depletion-type field-effect transistor to form a first current branch for generating a feedback voltage according to the output voltage; a control circuit connected in series with the depletion-type field-effect transistor to form a second current branch for generating a startup voltage not less than the startup threshold according to the feedback voltage when the supply voltage drops to the output voltage, and then adjusting the output voltage to be stable according to the startup voltage. The two current branches adopted in the present invention can further reduce the quiescent current and meet the extremely low-power requirements. At the same time, a depletion-type field-effect transistor is used as the power transistor, which can still be normally turned on and operate when the supply voltage is as low as the output voltage. Therefore, in a scenario where the supply voltage is relatively low, a sufficiently high output voltage can be provided for the subsequent circuit to use.

Description

Technical Field

[0001] The present invention relates to the field of power supply circuits, and particularly to a low-power linear voltage regulator circuit and a regulated power supply. Background Art

[0002] For various electronic products with low-power standby requirements, a DC regulated power supply with a low quiescent current is usually required to supply power to the standby control circuit. The self-power consumption of the standby power supply directly affects the standby power consumption of the entire machine, so it is necessary to reduce its quiescent current as much as possible.

[0003] In the prior art, in order to meet low power consumption, the following deficiencies still exist in common voltage regulator circuits: (1) The circuit quiescent current is large: This voltage regulator uses three current branches. Although it can reduce power consumption, due to the large number of current branches, the current consumed by the circuit itself is large, making it difficult to further reduce the quiescent current and unable to meet the extreme low-power requirements. (2) The output voltage is limited: The voltage regulator in the prior art uses an enhancement-mode field-effect transistor (MOSFET) as the power transistor. Due to the characteristics of the enhancement-mode MOSFET, its output voltage can only reach the supply voltage minus the gate-source voltage of the power transistor (Vgs, about 1V). This limitation results in an inability to provide a high enough output voltage for the subsequent circuit in scenarios with a low supply voltage. (3) The dependence of the quiescent current on the supply voltage: In common standby power generation circuits, the quiescent current is proportional to the supply voltage. When the supply voltage has a large variation range, the quiescent current fluctuates accordingly, resulting in an inability to achieve stable and ultra-low standby power consumption across the entire supply voltage range.

[0004] In view of the above problems, the present invention aims to provide solutions to overcome these technical defects. Summary of the Invention

[0005] The present invention provides a low-power linear voltage regulator circuit and a regulated power supply to solve at least one of the above technical problems.

[0006] The technical solution of the present invention to solve the above technical problems is as follows: A low-power linear voltage regulator circuit includes:

[0007] A depletion-mode field-effect transistor, including an input terminal, an output terminal, and a control terminal. The input terminal is connected to the supply voltage, and the output terminal is used to output the output voltage; the depletion-mode field-effect transistor has a startup threshold, and the startup threshold is less than zero;

[0008] A feedback circuit, connected to the output terminal and in series with the depletion-mode field-effect transistor to form a first current branch, for generating a feedback voltage according to the output voltage;

[0009] A control circuit, connected to the depletion-mode field-effect transistor and the feedback circuit, forms a second current branch in series with the depletion-mode field-effect transistor, and is configured to generate a startup voltage not less than the startup threshold according to the feedback voltage when the supply voltage drops to the output voltage, and then regulate the output voltage to be stable according to the startup voltage.

[0010] Based on the above technical solution, the present invention can be further improved as follows.

[0011] Further, the feedback circuit includes a first resistor and a second resistor connected in series between the output terminal and the ground, and a feedback node located between the first resistor and the second resistor and connected to the control circuit;

[0012] The feedback voltage is generated by the first resistor and the second resistor and is fed back to the control circuit according to the voltage division ratio through the feedback node.

[0013] Further, the feedback circuit includes:

[0014] A clamping sub-circuit, connected to the output terminal, configured to perform a fixed voltage drop on the output voltage and generate a clamping current related to the output voltage;

[0015] A sampling sub-circuit, connected to the clamping sub-circuit and the control circuit, configured to sample the clamping current to generate the feedback voltage.

[0016] Further, the clamping sub-circuit includes a Zener diode; the sampling sub-circuit includes a sampling MOS transistor;

[0017] The cathode of the Zener diode is connected to the output terminal, and the anode of the Zener diode is connected to the drain of the sampling MOS transistor; the gate and drain of the sampling MOS transistor are short-circuited, and the gate is connected to the control circuit, and the source of the sampling MOS transistor is grounded.

[0018] Further, the clamping sub-circuit includes a MOS transistor cascade formed by a plurality of diodes connected in series, the gate and drain of the MOS transistor cascade are short-circuited, and the drain is connected to the output terminal, and the source is connected to the sampling sub-circuit;

[0019] The sampling sub-circuit includes a sampling MOS transistor, the drain of the sampling MOS transistor is connected to the source of the MOS transistor cascade, the gate and drain are short-circuited, and the gate is connected to the control circuit, and the source of the sampling MOS transistor is grounded.

[0020] Further, the control circuit includes:

[0021] A control sub - circuit, connected to the feedback circuit, for generating a pull - down current according to the feedback voltage and controlling the voltage of the control terminal of the depletion - type field - effect transistor;

[0022] A start - up voltage generation sub - circuit, connected to the control sub - circuit and the depletion - type field - effect transistor, for generating a start - up voltage not less than the start - up threshold according to the pull - down current when the supply voltage is as low as the output voltage, and controlling the output voltage to be stable according to the start - up voltage.

[0023] Furthermore, the control sub - circuit includes:

[0024] An enhancement - mode N - type field - effect transistor, whose gate is connected to the feedback circuit, whose source is grounded, and whose drain is connected to the start - up voltage generation sub - circuit.

[0025] Furthermore, the start - up voltage generation sub - circuit includes:

[0026] A pull - down resistor, one end is connected between the control terminal of the depletion - type field - effect transistor and the drain of the enhancement - mode N - type field - effect transistor, and the other end is connected to the output terminal of the depletion - type field - effect transistor, for generating a start - up voltage not less than the start - up threshold according to the pull - down current and the output voltage when the supply voltage is as low as the output voltage, and controlling the output voltage to be stable according to the start - up voltage.

[0027] Furthermore, the start - up voltage generation sub - circuit includes:

[0028] A pull - down resistor, one end is connected between the control terminal of the depletion - type field - effect transistor and the drain of the enhancement - mode N - type field - effect transistor, and the other end is connected to the input terminal of the depletion - type field - effect transistor, for generating a start - up voltage not less than the start - up threshold according to the pull - down current and the supply voltage when the supply voltage is as low as the output voltage, and controlling the output voltage to be stable according to the start - up voltage.

[0029] Based on the above - mentioned low - power linear voltage - regulating circuit, the present invention also provides a regulated power supply, which includes the above - mentioned low - power linear voltage - regulating circuit.

[0030] The beneficial effects of the present invention are as follows: In a low-power linear voltage regulator circuit and a regulated power supply of the present invention, only two current branches are required, namely, a first current branch formed by connecting a feedback circuit in series with a depletion-type field-effect transistor, and a second current branch formed by connecting a control circuit in series with a depletion-type field-effect transistor. Compared with the three current branches in the prior art, the use of two current branches in the present invention can further reduce the current consumed by the circuit itself, thereby further reducing the quiescent current and meeting the extremely low-power requirements. At the same time, the present invention uses a depletion-type field-effect transistor as a power transistor to support the low supply voltage requirement; since the startup threshold of the depletion-type field-effect transistor is less than zero, the depletion-type field-effect transistor can still be normally turned on and operated when the supply voltage is as low as the output voltage. Therefore, in scenarios where the supply voltage is relatively low, the present invention can also provide a sufficiently high output voltage for the subsequent-stage circuit to use. In addition, by using the feedback regulation of the feedback circuit and the control circuit, the present invention can effectively control the stability of the output voltage, and adjusting the feedback circuit can change the output voltage, so the load regulation rate is good. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 FIG. is a structural block diagram of a low-power linear voltage regulator circuit of the present invention;

[0032] Figure 2 FIG. is another structural block diagram of a low-power linear voltage regulator circuit of the present invention;

[0033] Figure 3 FIG. is a schematic diagram of a depletion-type field-effect transistor in a low-power linear voltage regulator circuit of the present invention;

[0034] Figure 4 FIG. is a schematic structural diagram of a feedback circuit in a low-power linear voltage regulator circuit of the present invention;

[0035] Figure 5 FIG. is a structural block diagram of a feedback circuit in a low-power linear voltage regulator circuit of the present invention;

[0036] Figure 6 is Figure 5 a specific schematic structural diagram of the feedback circuit in;

[0037] Figure 7 is Figure 5 another specific schematic structural diagram of the feedback circuit in;

[0038] Figure 8 FIG. is a structural block diagram of a control circuit in a low-power linear voltage regulator circuit of the present invention;

[0039] Figure 9 FIG. is another structural block diagram of a control circuit in a low-power linear voltage regulator circuit of the present invention;

[0040] Figure 10 isFigure 8 Schematic diagram of the specific structure of the control circuit;

[0041] Figure 11 is Figure 9 Schematic diagram of the specific structure of the control circuit;

[0042] Figure 12 The first circuit schematic diagram of a low-power linear voltage regulator circuit of the present invention;

[0043] Figure 13 The second circuit schematic diagram of a low-power linear voltage regulator circuit of the present invention;

[0044] Figure 14 The third circuit schematic diagram of a low-power linear voltage regulator circuit of the present invention;

[0045] Figure 15 The fourth circuit schematic diagram of a low-power linear voltage regulator circuit of the present invention. Specific embodiments

[0046] The principles and features of the present invention will be described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0047] As Figure 1 or Figure 2 shown, a low-power linear voltage regulator circuit includes:

[0048] A depletion-mode field-effect transistor 1, including an input terminal 11, an output terminal 12, and a control terminal 13. The input terminal 11 is connected to a supply voltage , and the output terminal 12 is used to output an output voltage . The depletion-mode field-effect transistor 1 has a startup threshold, and the startup threshold is less than zero;

[0049] A feedback circuit 2, connected to the output terminal 12 and in series with the depletion-mode field-effect transistor 1 to form a first current branch, for generating a feedback voltage according to the output voltage ; ;

[0050] A control circuit 3, connected to the output terminal 12 or the input terminal 11, the control terminal 13, and the feedback circuit 2 of the depletion-mode field-effect transistor 1, and in series with the depletion-mode field-effect transistor 1 to form a second current branch, for generating a startup voltage not less than the startup threshold according to the feedback voltage when the supply voltage is as low as the output voltage , and then adjusting the output voltage to be stable according to the startup voltage . stable.

[0051] Figure 1 In the low-power linear voltage regulator circuit shown, the control circuit 3 is connected to the output terminal 12; Figure 2 In the low-power linear voltage regulator circuit shown, the control circuit 3 is connected to the input terminal 11.

[0052] In a low-power linear voltage regulator circuit of the present invention, only two current branches are required, namely a first current branch formed by connecting the feedback circuit 2 and the depletion-type field-effect transistor 1 in series, and a second current branch formed by connecting the control circuit 3 and the depletion-type field-effect transistor 1 in series. Compared with the three current branches in the prior art, the two current branches adopted by the present invention can further reduce the current consumed by the circuit itself, thereby further reducing the static current, and further meeting the extreme low-power requirements. At the same time, the present invention uses the depletion-type field-effect transistor 1 as a power transistor to support a low supply voltage requirements; since the startup threshold of the depletion-type field-effect transistor 1 is less than zero, when the supply voltage is as low as the output voltage , the depletion-type field-effect transistor 1 can still be normally turned on and operate. Furthermore, in a scenario where the supply voltage is relatively low, the present invention can also provide a sufficiently high output voltage for the use of the subsequent-stage circuit. In addition, the present invention utilizes the feedback regulation of the feedback circuit 2 and the control circuit 3 to effectively control the stability of the output voltage ; moreover, by adjusting the feedback circuit 2, the output voltage can be changed, so the load regulation rate is good.

[0053] In some embodiments, as Figure 3 shown, the depletion-type field-effect transistor 1 is specifically a depletion-type N-channel field-effect transistor MDN, whose drain is the input terminal 11, whose source is the output terminal 12, and whose gate is the control terminal 13.

[0054] Specifically, the threshold voltage of the depletion-type N-channel field-effect transistor MDN is the startup threshold, and . Compared with the enhancement-type field-effect transistor, the threshold voltage of the depletion-type N-channel field-effect transistor MDN is less than zero, that is, when the gate-source voltage of the depletion-type N-channel field-effect transistor MDN, it can still maintain the conducting state. This characteristic enables the depletion-type N-channel field-effect transistor MDN to still operate when the supply voltage is as low as the output voltage . While the enhancement-type field-effect transistor is in the cut-off state (non-conducting) under the condition of the gate-source voltage , and the circuit cannot operate; therefore, in order to support a low supply voltage and enable a sufficiently high output voltage For use by the subsequent-stage circuit. The present invention preferably uses a depletion-type N-channel MOSFET MDN as a power transistor to provide an output voltage and a load current for a load connected to the output terminal 12. And load current.

[0055] In some embodiments, as Figure 4 shown, the feedback circuit 2 includes a first resistor R1 and a second resistor R2 connected in series between the output terminal 12 and the ground, and a feedback node located between the first resistor R1 and the second resistor R2 and connected to the control circuit 3; a feedback voltage is generated through the first resistor R1 and the second resistor R2 , and is fed back to the control circuit 3 through the feedback node according to the voltage division ratio.

[0056] Specifically, the first resistor R1 and the second resistor R2 form a voltage division structure, and the output voltage is fed back to the control circuit 3 according to the resistance ratio R2 / (R1+R2), providing a basis for the control circuit 3 to accurately adjust the output voltage to be stable. Stably.

[0057] If the accuracy requirement for the output voltage is not high, the feedback circuit 2 can also adopt the structure as Figure 5 shown.

[0058] In some other embodiments, as Figure 5 shown, the feedback circuit 2 includes:

[0059] A clamping sub-circuit 21, connected to the output terminal 12, for performing a fixed voltage drop on the output voltage , and generating a clamping current related to the output voltage ;

[0060] A sampling sub-circuit 22, connected to the clamping circuit 21 and the control circuit 3, for sampling the clamping current to generate the feedback voltage .

[0061] Specifically, the voltage drop of the clamping sub-circuit 21 is fixed, so the current flowing through the clamping circuit 21 changes with the output voltage ; the sampling sub-circuit 22 samples the clamping current flowing through the clamping sub-circuit 21 to obtain a sampling current, and converts the sampling current into a feedback voltage .

[0062] In some embodiments, as Figure 6As shown, the clamping sub - circuit 21 includes a Zener diode Dz, and the sampling sub - circuit 22 includes a sampling MOS transistor MS; the cathode of the Zener diode Dz is connected to the output terminal 12, and the anode of the Zener diode Dz is connected to the drain of the sampling MOS transistor MS; the gate and the drain of the sampling MOS transistor MS are short - circuited, and the gate is connected to the control circuit 3, and the source of the sampling MOS transistor MS is grounded.

[0063] Specifically, the clamping sub - circuit 21 uses a Zener diode Dz with a fixed voltage drop, and the sampling sub - circuit 22 uses a sampling MOS transistor MS as a current sampling transistor to sample the clamping current flowing through the Zener diode Dz. The voltage drop of the Zener diode Dz is weakly related to its own current, that is , where is the fixed voltage drop of the Zener diode Dz, is the threshold voltage of the Zener diode Dz, is the clamping current of the Zener diode Dz; therefore, it can be approximately considered that the output voltage is weakly related to the current of the Zener diode Dz; since the output voltage is approximately weakly related to the clamping current of the Zener diode Dz, therefore, if the accuracy requirement for the output voltage is not high, the feedback circuit 2 can adopt the structure as shown in Figure 6 .

[0064] In some other embodiments, as shown in Figure 7 , the clamping sub - circuit 21 includes a MOS transistor cascade M formed by a plurality of serially - connected diodes. The gate and the drain of the MOS transistor cascade M are short - circuited, and the drain is connected to the output terminal 12, and the source is connected to the sampling sub - circuit 22;

[0065] The sampling sub - circuit 22 includes a sampling MOS transistor MS. The drain of the sampling MOS transistor MS is connected to the source of the MOS transistor cascade M, the gate and the drain are short - circuited, and the gate is connected to the control circuit 3, and the source of the sampling MOS transistor MS is grounded.

[0066] Figure 7 In Figure 6 , a MOS transistor cascade M formed by a plurality of serially - connected diodes is used to replace the Zener diode Dz in , that is, the voltage drop is relatively fixed. The gate and the drain of the MOS transistor cascade M are short - circuited, which is a diode - connected MOS transistor. The I / V characteristic of the diode - connected MOS transistor is similar to that of a diode (the gate - drain terminal is the anode and the source terminal is the cathode); therefore, the voltage drop of the MOS transistor cascade M is also weakly related to its own clamping current, that is is the fixed voltage drop of the MOS transistor cascade M, is the threshold voltage of the MOS transistor cascade M, and is the clamping current of the MOS transistor cascade M; therefore, it can be approximately considered that the output voltage is weakly related to the clamping current of the MOS transistor cascade M ; since the output voltage is weakly related to the clamping current of the MOS transistor cascade M , if the accuracy requirement for the output voltage is not high, the feedback circuit 2 can also adopt the structure shown in Figure 7 .

[0067] In some embodiments, as shown in Figure 8 or Figure 9 , the control circuit 3 includes:

[0068] a control sub-circuit 31, connected to the feedback circuit 2, for generating a pull-down current according to the feedback voltage and controlling the voltage of the control terminal 13 of the depletion-type field-effect transistor 1;

[0069] a start-up voltage generation sub-circuit 32, connected to the control sub-circuit 31 and the depletion-type field-effect transistor 1, for generating a start-up voltage not less than the start-up threshold when the supply voltage is as low as the output voltage , and controlling the stability of the output voltage according to the start-up voltage . Stable.

[0070] Figure 8 In the control circuit 3 shown in Figure 9 , the start-up voltage generation sub-circuit 32 is connected to the output terminal 12;

[0071] In the control circuit 3 shown in , the start-up voltage generation sub-circuit 32 is connected to the input terminal 11. The control circuit 3 controls the output voltage according to the feedback voltage obtained by feeding back the output voltage by the feedback circuit 2, so as to ensure the stability of the output voltage . Specifically, when the output voltage is relatively high with respect to the target voltage, the feedback voltage obtained by the feedback circuit 2 feeding back the output voltage Less than zero, even the startup voltage decreases such that when the gate-source voltage of the depletion-mode N-type field-effect transistor MDN decreases, it can still maintain the conducting state. This characteristic enables the supply voltage to be as low as the output voltage while the depletion-mode N-type field-effect transistor MDN can still operate; due to the startup voltage generated by the startup voltage generation sub-circuit 32 decreases, that is, the gate voltage of the depletion-mode N-type field-effect transistor MDN decreases, thereby causing the gate-source voltage of the depletion-mode N-type field-effect transistor MDN to decrease, ultimately resulting in a decrease in the source-drain current of the depletion-mode N-type field-effect transistor MDN and thus causing the output voltage to decrease. When the output voltage is relatively low compared to the target voltage, the situation is opposite to when it is relatively high, which will not be elaborated here.

[0072] In some embodiments, as Figure 10 shown, the control sub-circuit 31 includes:

[0073] An enhancement-mode N-type field-effect transistor MN, whose gate is connected to the feedback circuit 2, whose source is grounded, and whose drain is connected to the startup voltage generation sub-circuit 32.

[0074] For Figure 8 the control circuit 3 shown, the startup voltage generation sub-circuit 32 includes:

[0075] A pull-down resistor Rpd, one end is connected between the control terminal 13 of the depletion-mode field-effect transistor 1 and the drain of the enhancement-mode N-type field-effect transistor MN, and the other end is connected to the output terminal 12 of the depletion-mode field-effect transistor 1, and is used to generate the startup voltage not less than the startup threshold according to the pull-down current and the output voltage when the supply voltage is as low as the output voltage and control the output voltage to be stable according to the startup voltage .

[0076] The enhancement-mode N-type field-effect transistor MN serves as a control transistor, which generates a pull-down current according to the magnitude of the gate voltage, and the gate voltage of the enhancement-mode N-type field-effect transistor MN is provided by the feedback of the output voltage by the feedback circuit 2. Therefore, the enhancement-mode N-type field-effect transistor MN generates a pull-down current according to the output voltage .

[0077] The pull-down resistor Rpd is connected between the control terminal 13 and the output terminal 12, that is, between the gate and source of the depletion-mode N-type field-effect transistor MDN, so that the static current of the low-power linear voltage regulator circuit of the present invention is independent of the supply voltage. Specifically, the static current is the current consumed by the circuit itself and not transferred to the load. The static current of the low-power linear voltage regulator circuit of the present invention consists of two parts. One is the current flowing to the feedback circuit 2, and the other is the current flowing to the control circuit 3. When the output voltage is stable, the current flowing to the feedback circuit 2 remains unchanged and is independent of the supply voltage ; the current flowing to the control circuit 3 is the current flowing through the pull-down resistor Rpd, which is equal to the gate-source voltage of the depletion-mode N-type field-effect transistor MDN divided by the pull-down resistor Rpd. The gate-source voltage of the depletion-mode N-type field-effect transistor MDN is only related to the current of the depletion-mode N-type field-effect transistor MDN, and the current of the depletion-mode N-type field-effect transistor MDN is independent of the supply voltage ; therefore, the current flowing to the control circuit 3 is also independent of the supply voltage ; the current of the feedback circuit 2 that is independent of the supply voltage plus the current of the control circuit 3 that is independent of the supply voltage results in a static current that is naturally also independent of the supply voltage ; therefore, when the supply voltage has a large variation range, the present invention can obtain a stable standby power consumption throughout the range. Therefore, when the supply voltage has a large variation range, the present invention can obtain a stable standby power consumption throughout the range.

[0078] For Figure 9 the control circuit 3 shown, when the variation range of the supply voltage is small and the load current is large, the start-up voltage generation sub-circuit 32 can also adopt the structure shown in Figure 11 to improve the maximum current capacity of the depletion-mode N-type field-effect transistor MDN.

[0079] In some other embodiments, as shown in Figure 11 , the start-up voltage generation sub-circuit 32 includes:

[0080] A pull-down resistor Rpd, one end is connected between the control terminal 13 of the depletion-type field-effect transistor 1 and the drain of the enhancement-type N-type field-effect transistor MN, and the other end is connected to the input terminal 11 of the depletion-type field-effect transistor 1, and is used to generate a start-up voltage not less than the start-up threshold according to the pull-down current and the output voltage when the supply voltage is as low as the output voltage , and control the stability of the output voltage according to the start-up voltage , and control the stability of the output voltage according to the start-up voltage .

[0081] In Figure 11 the structure shown, the pull-down resistor Rpd is connected between the gate and drain of the depletion-type N-channel MOSFET MDN. At this time, the current flowing through the pull-down resistor Rpd is equal to the difference between the supply voltage minus the startup voltage divided by the pull-down resistor Rpd. Therefore, the current flowing through the control circuit 3 is related to the supply voltage and further makes the static current also related to the supply voltage . Although the static current at this time is related to the supply voltage , it has been described above that the change range of the supply voltage is small. Therefore, the standby power consumption change that the invention can obtain in the whole range is also relatively small. Connecting the pull-down resistor Rpd between the gate and drain of the depletion-type N-channel MOSFET MDN can improve the maximum current capacity of the depletion-type N-channel MOSFET MDN, and thus the maximum driving ability is improved under the same device conditions.

[0082] The best low-power linear voltage regulator circuit composed of the above partial embodiments is as Figure 12 shown. At this time:

[0083] The source-drain current of the depletion-type N-channel MOSFET MDN is:

[0084] ; (1)

[0085] wherein, is a constant related to the characteristics of the depletion-type N-channel MOSFET MDN itself; is the gate-source voltage of the depletion-type N-channel MOSFET MDN, which is equal to ; Therefore, the source-drain current of the depletion-type N-channel MOSFET MDN can be deformed into the following expression:

[0086] ; (2)

[0087] The source-drain current of the depletion-type N-channel MOSFET MDN is the total current of the low-power linear voltage regulator circuit. After this current passes through the depletion-type N-channel MOSFET MDN, it is divided into three current branches. The first part flows to the load connected to the output terminal 12 and is called the load current; the second part flows to the first resistor R1 and the second resistor R2, and the third part flows to the pull-down resistor Rpd and the enhancement-type N-channel MOSFET MN; the current flowing to the first resistor R1 and the second resistor R2 and the current flowing to the pull-down resistor Rpd and the enhancement-type N-channel MOSFET MN are the power consumption of the circuit itself. Therefore, their sum is the static current; and there is the following relationship:

[0088] ; (3)

[0089] Wherein, represents the current flowing through the first resistor R1 and the second resistor R2; represents the current flowing through the pull-down resistor Rpd and the enhancement-mode N-type field-effect transistor MN; represents the load current; represents the total current of the low-power linear voltage regulator circuit; represents the static current, from which it can be seen that the static current is independent of the supply voltage .

[0090] The source-drain current of the enhancement-mode N-type field-effect transistor MN is:

[0091] ; (4)

[0092] Wherein, the source-drain current of the enhancement-mode N-type field-effect transistor MN is also the current flowing through the pull-down resistor Rpd ; is a constant related to the characteristics of the enhancement-mode N-type field-effect transistor MN itself; is the threshold voltage of the enhancement-mode N-type field-effect transistor MN; is the voltage across the second resistor R2, and

[0093] ; (5)

[0094] When the currents flowing through the first resistor R1 and the second resistor R2, the currents flowing through the pull-down resistor Rpd and the enhancement-mode N-type field-effect transistor MN, and the load current are all small, that is, when is satisfied, from equations (2) to (5), it can be deduced that:

[0095]

[0096] Combining equation (5) and equation (7), the output voltage can be deduced as:

[0097] ;

[0098] Combining equation (3), equation (5), equation (6) and equation (7), the static current can be deduced as:

[0099] .

[0100] From this, it can be seen thatFigure 10 The output voltage of the low-power linear voltage regulator circuit in is very stable, and the quiescent current is extremely small, and the quiescent current is also independent of the supply voltage . Additionally, by adjusting the resistance ratio of the first resistor R1 and the second resistor R2, the output voltage can be adjusted ; therefore, the output voltage of the present invention is adjustable and has a good load regulation rate.

[0101] In addition, as Figure 12 shown, there are fewer active devices in the low-power linear voltage regulator circuit of the present invention, only 2, so the circuit structure is very simple and the power consumption is extremely low.

[0102] If the requirement for the output voltage accuracy is not high, a low-power linear voltage regulator circuit as Figure 13 or as Figure 14 shown can be adopted.

[0103] In the Figure 13 shown low-power linear voltage regulator circuit, the size ratio of the sampling MOS transistor MS to the enhancement-mode N-type field-effect transistor MN is N:1, then:

[0104]

[0105] wherein, is the gate-source voltage of the enhancement-mode N-type field-effect transistor MN.

[0106] Under the conditions of load current , the current of the pull-down resistor Rpd, and a small N, that is, when is satisfied, according to equations (8) to (10), it can be deduced that:

[0107] ;

[0108] ;

[0109] From this, it can be seen that Figure 11 the output voltage of the low-power linear voltage regulator circuit in is very stable, the quiescent current is extremely small, and the quiescent current is also independent of the supply voltage . Additionally, by selecting a Zener diode Dz with different fixed voltage drops, the output voltage can be changed; therefore, the output voltage of the present invention is adjustable and has a good load regulation rate.

[0110] Figure 14 The low-power linear voltage regulator circuit shown is the same asFigure 13 The low-power linear voltage regulator circuit shown has the same properties, except that a MOS transistor cascade M formed by multiple series-connected diodes is used to replace Figure 13 the Zener diode Dz in . This will not be elaborated here in detail. Additionally, by selecting a MOS transistor cascade M formed by multiple series-connected diodes to obtain different fixed voltage drops, the output voltage can be changed ; therefore, the output voltage of the present invention

[0111] For a relatively small supply voltage variation range and a relatively large load current, a low-power linear voltage regulator circuit as shown in Figure 15 can be adopted. Among them, a pull-down resistor Rpd is connected between the gate and drain of the depletion-type N-channel MOSFET MDN to improve the maximum current capacity of the depletion-type N-channel MOSFET MDN.

[0112] In the Figure 15 low-power linear voltage regulator circuit shown, there are the following relationships:

[0113] ; (11)

[0114] ; (12)

[0115] ; (13)

[0116] Based on equations (11) to (13), it can be deduced that:

[0117]

[0118] Figure 15 the quiescent current in the low-power linear voltage regulator circuit shown is related to the supply voltage . Figure 15 The low-power linear voltage regulator circuit shown and Figure 12 the low-power linear voltage regulator circuit shown are compared. The difference is only that the quiescent current is related to the supply voltage ; although Figure 15 the quiescent current in the low-power linear voltage regulator circuit shown is not as stable as that in Figure 12 the low-power linear voltage regulator circuit shown, but when the supply voltage has a relatively small variation range, Figure 15 the variation range of the quiescent current in the low-power linear voltage regulator circuit shown is also relatively small, and it has a relatively stable standby power consumption compared with the prior art. Moreover, Figure 15 the maximum driving ability of the low-power linear voltage regulator circuit shown is improved under the same device conditions.

[0119] Based on the above low-power linear voltage regulator circuit, the present invention further provides a regulated power supply, which includes the low-power linear voltage regulator circuit as described above.

[0120] The regulated power supply of the present invention adopts the above low-power linear voltage regulator circuit. Therefore, the regulated power supply of the present invention has a low static current, meeting the extreme low-power requirements; at the same time, it supports low supply voltage requirements, and can provide a sufficiently high output voltage for the subsequent circuit to use even when the supply voltage is as low as the output voltage; in addition, it also has the advantage of good load regulation rate.

[0121] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A low-power linear voltage regulator circuit, characterized in that, Comprising: A depletion-mode field-effect transistor, including an input terminal, an output terminal, and a control terminal, wherein the input terminal is connected to a supply voltage, and the output terminal is used to output an output voltage; The depletion-mode field-effect transistor is provided with a startup threshold; A feedback circuit, connected to the output terminal and in series with the depletion-mode field-effect transistor to form a first current branch, for generating a feedback voltage according to the output voltage; A control circuit, connected to the depletion-mode field-effect transistor and the feedback circuit, and in series with the depletion-mode field-effect transistor to form a second current branch, for generating a startup voltage not less than the startup threshold according to the feedback voltage when the supply voltage drops to the output voltage, and then adjusting the output voltage to be stable according to the startup voltage; The control circuit includes: A control sub-circuit, connected to the feedback circuit, for generating a pull-down current according to the feedback voltage and controlling the voltage of the control terminal of the depletion-mode field-effect transistor; A startup voltage generation sub-circuit, connected to the control sub-circuit and the depletion-mode field-effect transistor, for generating the startup voltage not less than the startup threshold according to the pull-down current when the supply voltage is low to the output voltage, and controlling the output voltage to be stable according to the startup voltage; The control sub-circuit includes: An enhancement-mode N-type field-effect transistor, whose gate is connected to the feedback circuit, whose source is grounded, and whose drain is connected to the startup voltage generation sub-circuit.

2. The low-power linear voltage regulator circuit according to claim 1, wherein The feedback circuit includes a first resistor and a second resistor connected in series between the output terminal and the ground, and a feedback node; the feedback node is located between the first resistor and the second resistor and is connected to the control circuit; The feedback voltage is generated by the first resistor and the second resistor and fed back to the control circuit according to the voltage division ratio and through the feedback node.

3. The low-power linear voltage regulator circuit according to claim 1, wherein The feedback circuit includes: A clamping sub-circuit, connected to the output terminal, for performing a fixed voltage drop on the output voltage and generating a clamping current related to the output voltage; A sampling sub-circuit, connected to the clamping sub-circuit and the control circuit, for sampling the clamping current to generate the feedback voltage.

4. The low-power linear voltage regulator circuit according to claim 3, characterized in that, The clamping sub-circuit includes a Zener diode; the sampling sub-circuit includes a sampling MOS transistor; The cathode of the Zener diode is connected to the output terminal, the anode of the Zener diode is connected to the drain of the sampling MOS transistor; the gate and the drain of the sampling MOS transistor are short-circuited, and the gate is connected to the control circuit, and the source of the sampling MOS transistor is grounded.

5. The low-power linear voltage regulator circuit according to claim 3, wherein The clamping sub-circuit includes a MOS transistor cascade formed by a plurality of series-connected diodes, the gate and the drain of the MOS transistor cascade are short-circuited, and the drain is connected to the output terminal, and the source is connected to the sampling sub-circuit; The sampling sub-circuit includes a sampling MOS transistor, the drain of the sampling MOS transistor is connected to the source of the MOS transistor cascade, the gate and the drain are short-circuited, and the gate is connected to the control circuit, and the source of the sampling MOS transistor is grounded.

6. The low-power linear voltage regulator circuit according to claim 1, characterized in that The startup voltage generation sub-circuit includes: A pull-down resistor has one end connected between the control terminal of the depletion-mode field-effect transistor and the drain of the enhancement-mode N-type field-effect transistor, and the other end connected to the output terminal of the depletion-mode field-effect transistor. It is used to generate a start-up voltage not less than the start-up threshold according to the pull-down current and the output voltage when the supply voltage is as low as the output voltage, and control the stability of the output voltage according to the start-up voltage.

7. The low-power linear voltage regulator circuit according to claim 1, wherein The start-up voltage generation sub-circuit includes: A pull-down resistor has one end connected between the control terminal of the depletion-mode field-effect transistor and the drain of the enhancement-mode N-type field-effect transistor, and the other end connected to the input terminal of the depletion-mode field-effect transistor. It is used to generate a start-up voltage not less than the start-up threshold according to the pull-down current and the supply voltage when the supply voltage is as low as the output voltage, and control the stability of the output voltage according to the start-up voltage.

8. A regulated power supply, characterized in that, It includes the low-power linear voltage regulator circuit according to any one of claims 1 to 7.

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