A glitch-free switching method for multiple clock domains supporting dynamic clock switching

Abstract

The present invention discloses a multi-clock domain glitch-free switching method supporting dynamic clock switching, comprising the following steps: S1, a MUX multiplexer outputs a normally-on clk clock signal according to the switching status of each clock source, and sends the clk clock signal to the corresponding clock switching submodule; S2, in the clock switching submodule, a sel clock selection signal corresponding to the clk clock signal is output as a gating signal for the clk clock signal through an AND gate, a three-stage register, and a first-stage register, and a negated signal of the sel clock selection signal is output as a gating signal for the clock to be switched through an AND gate and a three-stage register; S3, the clk clock signal is turned off by the gating signal in a falling-edge-triggered manner, generating a feedback signal. After the clock to be switched receives the feedback signal, the clock to be switched is turned on by the gating signal, completing the switching. The method proposed by the present invention can be applied to the clock switching system of a low-power MCU and can realize multi-clock switching.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a multi-clock domain glitch-free switching method supporting dynamic clock switching. Background Art

[0002] MCUs, or microcontroller units, are highly integrated semiconductor chips widely used in modern electronic devices. The system clock source for an MCU typically includes an internal oscillator, an external crystal oscillator, and a phase-locked loop (PLL). The number of clock sources can range from three to five. To meet the MCU's low-power requirements, the high-speed clock must be switched to a low-speed clock before entering low-power mode, and inactive clock sources must be disabled to reduce power consumption. Before exiting low-power mode, the low-speed clock must be switched to a high-speed clock to meet the clock frequency requirements for normal system operation. MCUs must implement switching between multiple clocks. Implementing this using combinational logic muxes can generate clock signal glitches, seriously impacting system stability.

[0003] At present, the traditional clock glitch-free switching solution includes: a clock selection signal generating circuit, a synchronization circuit and a multiplexer. The clock selection signal generating circuit is used to generate multiple clock selection signals, and the synchronization circuit is used to synchronize the multiple clock selection signals. After processing, among any two adjacent clock selection signals, the falling edge of the previous clock selection signal is aligned with the rising edge of the next clock selection signal, the rising edge of each clock selection signal is aligned with the rising edge of its corresponding clock signal, and the falling edge of each clock selection signal is aligned with the falling edge of the next corresponding clock signal. Then, the multiplexer is used to select one output from the multiple input clock signals.

[0004] However, the current clock glitch-free switching solution has at least the following three problems:

[0005] 1) High power consumption: This glitch-free clock switching solution requires a clock selection signal generation circuit to generate multiple clock selection signals and a set of corresponding clock signals during clock switching, which results in high power consumption for the system.

[0006] 2) Low stability: This glitch-free clock switching solution requires the falling edge of the previous clock selection signal to be aligned with the rising edge of the next clock selection signal during clock switching. If a time delay occurs in the middle, the falling edge of the previous clock selection signal cannot be aligned with the rising edge of the next clock selection signal.

[0007] 3) Poor adaptability: This clock glitch-free switching solution can only switch the clock signals corresponding to two adjacent clock selection signals, and cannot switch any two clock signals. Summary of the Invention

[0008] In response to the above three problems, the purpose of the present invention is to propose a multi-clock domain glitch-free switching method that supports dynamic clock switching. Multi-clock switching can be achieved by cascading multiple clock switching sub-modules, which not only solves the need for MCU to switch more than two clocks, but also solves the problem of needing to shut down the clock source in low-power mode. At the same time, by generating a clock switching completion flag, the problem of shutting down the clock source before the clock switching is completed can be avoided.

[0009] This is achieved through the following technical solutions:

[0010] A multi-clock domain glitch-free switching method supporting dynamic clock switching includes the following steps: S1, generating multiple different clock signals through multiple clock sources, and inputting the multiple clock signals into a MUX multiplexer, wherein the MUX multiplexer outputs a corresponding clk clock signal according to the switching status of each clock source, and sends the output clk clock signal to the corresponding clock switching submodule; S2, in the clock switching submodule, the sel clock selection signal corresponding to the clk clock signal passes through an AND gate, a three-stage register, and a first-stage register, and outputs a negative signal of the sel clock selection signal, and uses the negative signal of the sel clock selection signal as the gate of the clk clock signal. Control signal, and then the negative signal of the sel clock selection signal is output as the gating signal of the clock to be switched through the AND gate and the three-level register; the clk clock signal is turned off by the gating signal to switch the clock signal; S3, when switching the clock signal, the clk clock signal is turned off by the gating signal in a falling edge triggered manner, and a feedback signal is generated, and the feedback signal is output to the clock to be switched. After the clock to be switched receives the feedback signal, it turns on the clock to be switched through the gating signal to complete the switching; at the same time, each clock switching sub-module adds a flag signal for turning on or off each corresponding clock signal. When any clock signal is not turned on, its corresponding clock enable signal is low.

[0011] The present invention proposes a multi-clock domain glitch-free switching method suitable for low-power MCUs and supporting dynamic clock switching. Multi-clock switching can be achieved by cascading multiple clock switching sub-modules, and the MCU system can be supported to shut down the non-running clock source to reduce power consumption after receiving the switching completion flag.

[0012] Preferably, in step S1, each clock source includes an oscillator, a crystal oscillator, and a phase-locked loop (PLL). The oscillator and crystal oscillator are used to generate clock signals, and the PLL is used to improve the stability and accuracy of the clock signals. The clock source can generate multiple high-precision, stable clock signals for the clock switching system.

[0013] Preferably, in step S1, a MUX multiplexer has multiple inputs and one output, and selects a corresponding clock signal from the multiple input clock signals for output based on the switching status of each clock source. The clock switching system uses a MUX multiplexer to select and output multiple clock signals, effectively managing the output of multiple clock signals and ensuring that the clock signal entering the clock switching submodule is always present, so that each clock switching submodule can complete clock switching normally.

[0014] Preferably, each binary code of the sel clock selection signal corresponds to a corresponding clock signal. The sel clock selection signal can enable the clock switching system to work stably and harmoniously.

[0015] Preferably, in step S2, the three-level register includes: a data register, a status register, and a control register. The three-level register can meet the transmission requirements of different clock signals and ensure the accuracy of clock signal transmission.

[0016] Preferably, in step S2, a gating signal is used to control the output of the clock signal. When the gating signal is high, the corresponding clock signal is output, and when the gating signal is low, the corresponding clock signal is not output. The gating signal can effectively control the output of the clock signal, so that the clock switching system can normally complete the switching of the clock signal.

[0017] Preferably, in step S3, the falling edge trigger is triggered when the clk clock signal changes from a high level to a low level, and when triggered, the clk clock signal generates a feedback signal. Generating the feedback signal by falling edge triggering solves the problem of needing to shut down the clock source in low power mode and avoids glitches generated during the switching process between the two clocks.

[0018] Preferably, in step S3, the sign of clock signal switching completion includes: the binary code of the sel clock selection signal changes and the gating signal of the clock to be switched becomes high. By adding the clock signal switching completion sign, the problem of shutting down the clock source before the clock signal switching is completed can be avoided.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The technical solution of the present invention can realize multi-clock switching by cascading multiple clock switching sub-modules, which not only solves the need for MCU to switch more than two clocks, but also solves the problem of needing to shut down the clock source in low-power mode, and avoids the generation of glitches between the two clocks during the switching process. At the same time, by generating a clock switching completion flag, it can avoid the problem of shutting down the clock source before the clock switching is completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A flowchart of a multi-clock domain glitch-free switching method supporting dynamic clock switching;

[0022] Figure 2 The schematic diagram of the clock switching submodule structure of a multi-clock domain glitch-free switching method that supports dynamic clock switching. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0024] like Figure 1 As shown in the figure, it is a flow chart of a multi-clock domain glitch-free switching method that supports dynamic clock switching. First, the MUX multiplexer outputs the clk clock signal according to the switching status of each clock source, and sends the clk clock signal to the corresponding clock switching sub-module; then, in the clock switching sub-module, the sel clock selection signal corresponding to the clk clock signal is output as the gating signal of the clk clock signal through the AND gate, the three-level register and the first-level register, and the negative signal of the sel clock selection signal is output as the gating signal of the clock to be switched through the AND gate and the three-level register; finally, the clk clock signal is turned off by the gating signal in a falling edge triggering manner, and a feedback signal is generated. After the clock to be switched receives the feedback signal, it turns on the clock to be switched through the gating signal to complete the clock switching.

[0025] The method specifically comprises the following steps:

[0026] S1. Multiple clock sources generate multiple different clock signals and input them into a MUX multiplexer. The MUX multiplexer has multiple inputs and one output. Based on the sel clock selection signal, which is composed of the switching signals of the clock sources, it selects a corresponding clock signal for output. Each binary code of the sel clock selection signal corresponds to a corresponding clock signal. The output clk clock signal is then sent to the corresponding clock switching submodule. Each clock source includes an oscillator, a crystal oscillator, and a phase-locked loop (PLL). Both oscillators and crystal oscillators are used to generate clock signals. The difference between them is that oscillators are on-chip clocks and generate clock signals with relatively low frequency accuracy and stability, while crystal oscillators are off-chip clocks and can generate highly accurate and stable clock signals. The PLL is used to improve the stability and accuracy of the clock signal. A MUX multiplexer is a logic circuit that selects one of multiple input signals as an output signal. In the present invention, the output clock signal is determined based on the binary code of the sel clock selection signal.

[0027] In this embodiment, in the method of the present invention, a clock source can generate multiple high-precision, stable clock signals for the clock switching system, and the clock switching system uses a MUX multiplexer to select and output multiple clock signals, which can effectively manage the output of multiple clock signals and ensure that they can be transmitted through a single output channel. At the same time, the sel clock selection signal can enable the clock switching system to work stably and coordinatedly, ensuring that the clock signal entering the clock switching sub-module must exist, so that each clock switching sub-module can complete the clock switching normally.

[0028] S2. In the clock switching submodule, the SEL clock selection signal corresponding to the CLK clock signal passes through an AND gate, a three-stage register, and a first-stage register, outputting a negated SEL clock selection signal. This negated SEL clock selection signal is then used as a gating signal for the CLK clock signal. The negated SEL clock selection signal then passes through an AND gate and a three-stage register to output a gating signal for the clock to be switched. The gating signal turns off the CLK clock signal, performing clock signal switching. The three-stage register includes a data register, a status register, and a control register. During transmission, the CLK clock signal passes through the control register, status register, and data register in sequence.

[0029] In this embodiment, the three-level register employed in the present invention can meet the transmission requirements of different clock signals, ensuring the accuracy and stability of clock signal transmission. A gating signal is used to control the output of the clock signal. When the gating signal is high, the corresponding clock signal is output; when the gating signal is low, the corresponding clock signal is not output. The gating signal effectively controls the output of the clock signal, allowing the clock switching system to properly complete clock signal switching.

[0030] S3. When switching the clock signal, the clk clock signal is turned off by the gating signal in a falling edge triggering manner, and a feedback signal is generated, and the feedback signal is output to the clock to be switched. After the clock to be switched receives the feedback signal, it turns on the clock to be switched by the gating signal to complete the switching; at the same time, each clock switching submodule adds a flag signal for turning on or off each corresponding clock signal. When any clock signal is not turned on, its corresponding clock enable signal is low. Among them, the falling edge trigger is triggered when the clk clock signal changes from a high level to a low level, and when triggered, the clk clock signal generates a feedback signal. Generating a feedback signal by falling edge triggering solves the problem of needing to turn off the clock source in low power mode, and avoids glitches between the two clocks during the switching process.

[0031] In this embodiment, the present invention achieves switching between multiple clock signals by cascading multiple clock switching submodules. Each clock switching submodule can switch between two clock signals, and the gating signal for each clock signal is controlled by a feedback signal generated by the falling edge of the other clock signal. This gating signal control by the other clock ensures the isolation of the two clock signals. Therefore, when switching between clock signals, the running clock signal is first shut down by the gating signal.

[0032] like Figure 2 The figure shows a schematic diagram of the clock switching submodule structure for a multi-clock domain glitch-free switching method that supports dynamic clock switching. The figure cascades two clock switching submodules, each consisting of an AND gate, an OR gate, and a three-stage register R. It also includes the switching circuit clk_a_switch for clk_a, the switching circuit clk_b_switch for clk_b, the switching circuit clk_o_switch for clk_o, and the switching circuit clk_c_switch for clk_c. The figure uses the three clock sources as an example. clk_a, clk_b, and clk_c are three different clock signals generated by these three clock sources. The generated clock signals are input into a MUX multiplexer, and the output clk clock signal is selected by the sel[1:0] clock selection signal. When the sel[1:0] clock selection signal is 2'b00, the clock signal selects clk_a; when the sel[1:0] clock selection signal is 2'b01, the clock signal selects clk_b; when the sel[1:0] clock selection signal is 2'b10, the clock signal selects clk_c. Among them, the clock switching system consists of two clock switching sub-modules. Sub-module 1 selects clk_a and clk_b according to the value of sel[0] and outputs clk_o. Its circuit formula can be simplified to clk_o=(~sel[0]&clk_a)|(sel[0]&clk_b). When sel[0] is 0, clk_a is selected, and when sel[0] is 1, clk_b is selected; sub-module 2 selects clk_o and clk_c according to the value of sel[1] and outputs clk_out. Its circuit formula can be simplified to clk_out=(~sel[1]&clk_o)|(sel[1]&clk_c). When sel[1] is 0, clk_o is selected, and when sel[1] is 1, clk_c is selected. At the same time, these two clock switching submodules add flag signals for turning the clock signal on or off, including: clk_a_on, clk_b_on and clk_c_on. When the corresponding clock signal is not turned on, the corresponding enable signal is low.

[0033] This embodiment of the present invention adds a clock signal switching completion flag to prevent the erroneous operation of shutting down the clock source before the clock signal switching is complete. This sign of clock signal switching completion includes a change in the binary encoding of the sel clock selection signal and a high level for the gate control signal of the clock to be switched. This added clock signal switching completion flag avoids the problem of shutting down the clock source before the clock signal switching is complete.

[0034] To sum up, the present invention can realize multi-clock switching by cascading multiple clock switching sub-modules, which not only solves the need for MCU to switch more than two clocks, but also solves the problem of needing to shut down the clock source in low-power mode, and avoids the generation of glitches between the two clocks during the switching process. At the same time, by generating a clock switching completion flag, it can avoid the problem of shutting down the clock source before the clock switching is completed, which is significantly progressive.

[0035] The above embodiments are only for illustrating the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A multi-clock domain glitch-free switching method supporting dynamic clock switching, characterized in that: The method comprises the following steps: S1. Generate multiple different clock signals through multiple clock sources and input the multiple clock signals into the MUX multiplexer. The MUX multiplexer outputs a corresponding clk clock signal according to the switching status of each clock source and sends the output clk clock signal to the corresponding clock switching submodule; S2. In the clock switching submodule, the sel clock selection signal corresponding to the clk clock signal passes through the AND gate, the three-stage register, and the first-stage register, and then outputs the negation signal of the sel clock selection signal, and uses the negation signal of the sel clock selection signal as the gating signal of the clk clock signal. The negation signal of the sel clock selection signal then passes through the AND gate and the three-stage register to output the gating signal of the clock to be switched; the clk clock signal is turned off by the gating signal to perform clock signal switching; Among them, two clock switching sub-modules are cascaded, and each clock switching sub-module consists of an AND gate, an OR gate and a three-level register R, and includes the switching circuit clk_a_switch of clk_a, the switching circuit clk_b_switch of clk_b, the switching circuit clk_o_switch of clk_o, and the switching circuit clk_c_switch of clk_c; sub-module 1 selects clk_a and clk_b according to the value of sel[0] and outputs clk_o, and sub-module 2 selects clk_o and clk_c according to the value of sel[1] and outputs clk_out; S3. When switching the clock signal, the clk clock signal is turned off by the gating signal in a falling-edge triggered manner, and a feedback signal is generated. The feedback signal is output to the clock to be switched. After the clock to be switched receives the feedback signal, it turns on the clock to be switched through the gating signal to complete the switching. At the same time, each clock switching sub-module adds a flag signal for turning on or off each corresponding clock signal. When any clock signal is not turned on, its corresponding clock enable signal is low.

2. The method for glitch-free multi-clock domain switching supporting dynamic clock switching according to claim 1, characterized in that: In step S1, each clock source includes: an oscillator, a crystal oscillator and a phase-locked loop; wherein the oscillator and the crystal oscillator are both used to generate a clock signal, and the phase-locked loop is used to improve the stability and accuracy of the clock signal.

3. The method for glitch-free multi-clock domain switching supporting dynamic clock switching according to claim 1, characterized in that: In step S1 , the MUX multiplexer has multiple input terminals and one output terminal, and selects a corresponding clock signal from multiple input clock signals for output according to the switching status of each clock source.

4. The method for glitch-free multi-clock domain switching supporting dynamic clock switching according to claim 3, characterized in that: Each binary code of the sel clock selection signal corresponds to a corresponding clock signal.

5. The method for glitch-free multi-clock domain switching supporting dynamic clock switching according to claim 1, wherein: In step S2, the three-level registers include: a data register, a status register and a control register.

6. The method for glitch-free multi-clock domain switching supporting dynamic clock switching according to claim 1, characterized in that: In step S2, the gating signal is used to control the output of the clock signal. When the gating signal is at a high level, the corresponding clock signal is output; when the gating signal is at a low level, the corresponding clock signal is not output.

7. The method for glitch-free multi-clock domain switching supporting dynamic clock switching according to claim 1, characterized in that: In step S3 , the falling edge trigger is triggered when the clk clock signal changes from a high level to a low level, and when triggered, the clk clock signal generates a feedback signal.

8. The method for glitch-free multi-clock domain switching supporting dynamic clock switching according to claim 1, wherein: In step S3, the signs indicating that the clock signal switching is completed include: the binary code of the sel clock selection signal changes and the gating signal of the clock to be switched becomes high level.

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