Memory performance optimization method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a memory performance optimization method and device, electronic equipment and a storage medium, and relates to the technical field of flash memories. The method comprises the steps of determining at least one target parallel event from a plurality of parallel events based on a preset erasing duration when an erasing instruction is received and an erasing operation is performed on a current super block, and executing the target parallel event. And judging whether the erasure of the current super block and the execution of the target parallel event are both completed or not. And if yes, sending a write-in instruction, and performing data write-in of the current super block. The response speed and performance of the storage device can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of flash memory technology, and in particular to a memory performance optimization method, device, electronic device and storage medium. Background Art

[0002] With the development of storage technology, flash storage media has gradually occupied the mainstream position in the market. Due to the characteristics of flash media, its basic reading unit is page, and the basic erasing unit is block. Most storage devices use super blocks for management. In flash memory, read, write, and erase commands can only be executed on one super block at a time. When the controller controls the flash memory to read, write, and erase the super block, the entire target block is in working state. In this process, the controller must wait for the erase operation to be completed before performing other subsequent tasks on the block. Other operations that need to access the block must wait, which leads to inefficiency and affects the data processing speed and performance of the storage device. Summary of the invention

[0003] The objectives of the present invention include, for example, providing a memory performance optimization method, device, electronic device and storage medium, which can at least partially solve the above-mentioned technical problems.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, an embodiment of the present invention provides a method for optimizing memory performance, the method comprising:

[0006] When receiving an erase instruction and performing an erase operation on the current super block, based on a preset erase duration, at least one target parallel event is determined from a plurality of parallel events, and the target parallel event is executed;

[0007] Determining whether erasure of the current super block and execution of the target parallel event are all completed;

[0008] If so, send a write instruction to write the data of the current super block.

[0009] Optionally, determining at least one target parallel event based on a preset erasure duration includes:

[0010] Respectively obtaining a preset execution time of each of the plurality of parallel events;

[0011] Combining the preset execution durations to obtain multiple combined durations;

[0012] The combined duration closest to the preset erasure duration among the combined durations is determined as the target combined duration, and the parallel event corresponding to the target combined duration is determined as the target parallel event.

[0013] Optionally, before receiving the erase instruction, the method further includes:

[0014] Get the L2P mapping table and the block erase amount corresponding to each super block;

[0015] The L2P mapping table and the block erase amount are stored in a memory.

[0016] Optionally, the target parallel event includes updating an L2P mapping table, and executing the target parallel event includes:

[0017] After confirming that the first super block data is full, the P2L mapping table of the first super block is loaded into the memory, and the L2P mapping table is updated according to the mapping relationship between the physical address and the logical address. The first super block is the super block that was last written.

[0018] Optionally, the target parallel event includes selecting a second super block, and executing the target parallel event includes:

[0019] Reading the erase amount of each block from the memory;

[0020] Based on a wear leveling algorithm, determining a super block with a minimum block erase amount from each of the super blocks according to the block erase amount;

[0021] The super block with the minimum block erase amount is used as the second super block; the second super block is the next super block to be erased.

[0022] Optionally, the method further comprises:

[0023] After the data writing of the current super block is completed, the second super block is determined to be a new current super block, and the newly determined current super block is erased when an erase instruction is received next time.

[0024] Optionally, the method further comprises:

[0025] If there are multiple parallel events, execute each of the parallel events in sequence according to a preset priority;

[0026] The determining whether the erasure of the current super block and the execution of the target parallel event are all completed further includes:

[0027] Obtaining an erase completion signal in real time and an execution completion signal corresponding to a parallel event with the lowest preset priority;

[0028] When the erase completion signal and the execution completion signal are respectively obtained, it is determined that the erasure of the current super block and the execution of the target parallel event are all completed. A memory performance optimization method.

[0029] In a second aspect, an embodiment of the present invention provides a memory performance optimization device, the memory performance optimization device comprising:

[0030] A target parallel event execution unit, configured to determine at least one target parallel event from a plurality of parallel events based on a preset erase duration and execute the target parallel event when receiving an erase instruction and performing an erase operation on a current super block;

[0031] A judging unit, used to judge whether the erasure of the current super block and the execution of the target parallel event are all completed;

[0032] The writing unit is used to send a writing instruction to write data into the current super block when the erasing of the current super block and the execution of the target parallel event are all completed.

[0033] In a third aspect, an embodiment of the present invention provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of any one of the above methods when executing the program.

[0034] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a computer program, and when the computer program is executed, the server where the computer-readable storage medium is located is controlled to implement the steps of any one of the above methods.

[0035] The beneficial effects of the embodiments of the present invention include, for example:

[0036] When the flash memory device erases the super block, the controller determines one or more parallel events for processing according to the preset erase duration, thereby making full use of the super block erase time to simultaneously process other parallel tasks unrelated to the flash memory I / 0 command without waiting for the erase operation to be completed, thereby improving the response speed and performance of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 A block diagram of an electronic device provided by an embodiment of the present invention;

[0039] Figure 2A schematic diagram of the steps of a memory performance optimization method provided by an embodiment of the present invention;

[0040] Figure 3 A flowchart of a memory performance optimization method provided by an embodiment of the present invention;

[0041] Figure 4 An architectural diagram of a memory performance optimization device provided in an embodiment of the present invention.

[0042] Icon: 100 - electronic device; 110 - memory; 120 - processor; 130 - communication module; 300 - memory performance optimization device; 301 - target parallel event execution unit; 302 - judgment unit; 303 - writing unit. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0044] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0046] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0047] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0048] In flash storage systems, a superblock is an important logical unit containing multiple pages or blocks, which is used to store management information, such as bad block mapping, erase counts, and logical to physical address mapping. The superblock is processed as a whole during the erase operation. At the same time, the redundant information or check data in the superblock ensures the integrity and reliability of the management information, thereby maintaining the long-term stable operation of the flash device.

[0049] In the prior art, due to the characteristics of flash memory media, one surface can only respond to one erase, write, or read command at a time. As a result, when the flash memory device is erasing the super block, the controller is in an idle state and needs to wait for the flash memory device to complete the erasing before proceeding to the next step. This wastes a lot of time and results in low efficiency of the entire processing flow.

[0050] Based on the above situation, the present invention provides a memory performance optimization method, device, electronic device and storage medium, which can effectively alleviate the above technical problems.

[0051] Please refer to Figure 1 , is a block diagram of an electronic device 100 provided by the present application. The electronic device 100 may be a device capable of performing data processing, which is not limited in this embodiment. The electronic device 100 includes a memory 110, a processor 120, and a communication module 130. The memory 110, the processor 120, and the communication module 130. Each component is electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses or signal lines.

[0052] The memory 110 is used to store programs or data. The memory 110 may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.

[0053] The processor 120 is used to read / write data or programs stored in the memory and execute corresponding functions.

[0054] The communication module 130 is used to establish a communication connection between the server and other communication terminals through the network, and to send and receive data through the network.

[0055] It should be understood that Figure 1 The structure shown is only a schematic diagram of the structure of the electronic device 100. The electronic device 100 may also include Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown. Figure 1The components shown in the figure can be implemented by hardware, software or a combination thereof. The electronic device 100 can be arranged in other devices or as an independent device.

[0056] Corresponding to the electronic device 100, an embodiment of the present invention provides a memory performance optimization method. The method includes: Figure 2 The following steps are shown:

[0057] Step S110: when receiving an erase instruction and performing an erase operation on the current super block, at least one target parallel event is determined from a plurality of parallel events based on a preset erase duration, and the target parallel event is executed.

[0058] Step S120: Determine whether the erasure of the current super block and the execution of the target parallel event are all completed.

[0059] Step S130: If yes, send a write instruction to write data into the current super block.

[0060] In step S110, when an erase instruction is received and an erase operation is performed on the current super block, at least one target parallel event is determined from multiple parallel events based on a preset erase duration, and the target parallel event is executed.

[0061] When the flash storage medium needs to be managed, the user can issue a corresponding erase instruction to the controller through the operation terminal. After receiving the erase instruction, the controller controls the flash device to erase the corresponding super block.

[0062] The parallel event can be an event that the controller can execute simultaneously when the flash memory device erases the super block. When the flash memory device starts to erase the current super block, at least one target parallel event can be determined from multiple parallel events according to a preset erase duration (i.e., the duration estimated by the staff for erasing). While the flash memory device erases the super block, the controller executes the target parallel event simultaneously.

[0063] Optionally, determining at least one target parallel event based on a preset erasure duration includes:

[0064] The preset execution duration of each of the plurality of parallel events is obtained respectively, and the preset execution durations are combined to obtain a plurality of combined durations.

[0065] The combined duration closest to the preset erasure duration among the combined durations is determined as the target combined duration, and the parallel event corresponding to the target combined duration is determined as the target parallel event.

[0066] As an optional implementation, an estimated preset execution duration may also be set for each parallel event. When determining the target parallel event, all parallel events are combined, and the preset execution durations corresponding to the parallel events in each combination are added together to obtain the combined duration. The combined duration that is closest to the preset erasure duration is determined as the target combined duration, and the corresponding parallel event is determined as the target parallel event. It should be noted that "close" here includes being equal to the preset erasure duration.

[0067] For example, if the preset erase duration is 2ms, there are three parallel events A, B, and C, corresponding to three preset execution durations j, k, and l respectively. The combination of A, B, and C includes the execution of three parallel events separately, as well as the combination of AB, ABC, BC, and AC, and the corresponding combination durations are j, k, l, jk, jkl, kl, and jl respectively. If the combination duration jl is closest to 2ms, A and C are determined as the target parallel events; if the combination duration k is closest to 2ms, B is determined as the target parallel event.

[0068] Optionally, before receiving the erase instruction, the method further includes:

[0069] Obtain the L2P mapping table and the block erase amount corresponding to each super block. Store the L2P mapping table and the block erase amount in a memory.

[0070] In order to enable the controller to handle other things while the flash memory device is being erased, the P2L mapping table corresponding to the last processed super block can be read from the flash memory device and stored in the memory before issuing the erase command. At the same time, the block erase amount of each super block in the flash memory device can also be read from the flash memory device and stored in the memory for backup.

[0071] Optionally, the target parallel event includes updating an L2P mapping table, and executing the target parallel event includes:

[0072] After confirming that the first super block data is full, the P2L mapping table of the first super block is loaded into the memory, and the L2P mapping table is updated according to the mapping relationship between the physical address and the logical address. The first super block is the super block that was last written.

[0073] After determining the target parallel event, the controller starts to execute the target parallel event. When the target parallel event is a mapping table update, the controller can call out from the P2L mapping table stored in the memory, establish a mapping relationship between the physical address and the logical address in the P2L mapping table, complete the conversion from the P2L mapping table to the L2P mapping table, and thus complete the update of the mapping table.

[0074] Optionally, the target parallel event includes selecting a second super block, and executing the target parallel event includes:

[0075] The erase amount of each block is read from the memory.

[0076] Based on a wear leveling algorithm, a super block with a minimum block erase amount is determined from each of the super blocks according to the block erase amount.

[0077] The super block with the minimum block erase amount is used as the second super block; the second super block is the next super block to be erased.

[0078] When the target parallel event is selected as the second super block, the controller reads the block erase amount corresponding to each super block from the memory, sorts the block erase amount through the wear leveling (WL) algorithm, and finds the super block with the smallest block erase amount. The super block is used as the second super block, that is, the super block used for the next flash memory device erase process.

[0079] In step S120, it is determined whether the erasure of the current super block and the execution of the target parallel event are all completed.

[0080] After the flash memory device completes erasing the current super block, it will feedback a signal to the controller, and each target parallel event will also generate a corresponding feedback signal after execution. The controller will determine that all are complete only when and if it receives a feedback signal that the target parallel event is complete and a feedback signal that the erasing of the current super block is complete. There is no need to determine the order of execution completion here.

[0081] Optionally, the method further includes: if there are multiple parallel events, executing each of the parallel events in sequence according to a preset priority.

[0082] The determining whether the erasure of the current super block and the execution of the target parallel event are all completed further includes: obtaining an erase completion signal in real time and obtaining an execution completion signal corresponding to a parallel event with the lowest preset priority. When the erase completion signal and the execution completion signal are respectively obtained, it is determined that the erasure of the current super block and the execution of the target parallel event are all completed.

[0083] If the target parallel event is determined to be one, then when the target parallel event is completed and the current super block is erased, the next step can be executed. When the target parallel event is determined to be multiple, the controller can execute each target parallel event according to the pre-set priority of parallel event processing from high to low. And obtain the erase completion signal and the execution completion signal corresponding to the parallel event with the lowest preset priority in real time. When the erase completion signal and the execution completion signal corresponding to the parallel event with the lowest preset priority are both obtained, it means that the erasure of the current super block and the execution of the target parallel event are all completed.

[0084] In step S130, if yes, a write instruction is sent to write the data of the current super block.

[0085] After the erasure of the current super block and the execution of the target parallel event are all completed, the next write operation can be performed. The controller sends a write instruction to the flash memory device to control the flash memory device to write to the current super block that has been erased, and finally completes the management of the file system.

[0086] Optionally, the method further comprises:

[0087] After the data writing of the current super block is completed, the second super block is determined to be a new current super block, and the newly determined current super block is erased when an erase instruction is received next time.

[0088] After the flash memory device completes writing the current super block, it feeds back a write completion signal to the controller, and the controller feeds back a signal to the control terminal based on the write completion signal, such as "modification completed", "deletion completed", etc. When the controller receives an erase request next time, it uses the second super block determined by the wear leveling algorithm as the new current super block and controls the flash memory device to erase it.

[0089] In order to better explain the solution of the present invention, the embodiment of the present invention also provides the following Figure 3 The flowchart shown illustrates this scheme.

[0090] See also Figure 3 The controller first obtains the mapping table and the block erase amount and other data from the flash memory device and stores them in the memory. When receiving the erase instruction, the flash memory device is controlled to erase the current super block. While the flash memory device is erasing the current super block, the controller determines at least one target parallel event to start executing, and reads the L2P mapping table and / or the block erase amount and other data from the memory during execution.

[0091] When the controller receives both the feedback signal indicating that the target parallel event processing is completed and the feedback signal indicating that the current super block is erased, the controller issues a write instruction to the flash memory device to control the flash memory device to write to the current super block.

[0092] After receiving the feedback signal of writing completion from the flash memory device, the controller uses the second super block determined when executing the target parallel event as the current super block, and controls the flash memory device to erase the super block when receiving an erase command next time.

[0093] Based on the same inventive concept, Figure 4 As shown, the embodiment of the present invention provides a memory performance optimization device 300, and the memory performance optimization device 300 includes:

[0094] The target parallel event execution unit 301 is used to determine at least one target parallel event from multiple parallel events based on a preset erase duration when receiving an erase instruction and performing an erase operation on the current super block, and execute the target parallel event.

[0095] The judging unit 302 is used to judge whether the erasure of the current super block and the execution of the target parallel event are all completed.

[0096] The writing unit 303 is used to send a writing instruction to write data into the current super block when the erasing of the current super block and the execution of the target parallel event are all completed.

[0097] Regarding the above-mentioned memory performance optimization device 300, the specific functions of each unit therein have been described in detail in the embodiment of the memory performance optimization method provided in this specification, and will not be elaborated here.

[0098] Based on the same inventive concept, an embodiment of the present invention specification provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above-mentioned memory performance optimization methods.

[0099] The present invention has at least the following beneficial effects:

[0100] 1. When erasing the super block, the controller determines one or more parallel events for processing according to the preset erasing duration, so as to make full use of the erasing time of the super block to process other tasks at the same time, thereby improving the response speed and performance of the storage device.

[0101] 2. The combined duration is obtained by combining the preset execution durations, and then the parallel events are determined based on the comparison between the combined duration and the preset erasure duration, so that the duration of the parallel events processed simultaneously within the erasure super time range is approximately consistent with the erasure duration, which is more reasonable.

[0102] In several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0103] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0104] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0105] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A memory performance optimization method, characterized in that: The method comprises: When receiving an erase instruction and performing an erase operation on the current super block, based on a preset erase duration, at least one target parallel event is determined from a plurality of parallel events, and the target parallel event is executed; Determining whether erasure of the current super block and execution of the target parallel event are all completed; If so, send a write instruction to write the data of the current super block.

2. The memory performance optimization method according to claim 1, characterized in that: The determining of at least one target parallel event based on the preset erasure duration includes: Respectively obtaining a preset execution time of each of the plurality of parallel events; Combining the preset execution durations to obtain multiple combined durations; The combined duration closest to the preset erasure duration among the combined durations is determined as the target combined duration, and the parallel event corresponding to the target combined duration is determined as the target parallel event.

3. The memory performance optimization method according to claim 1, characterized in that: Before receiving the erase instruction, the method further includes: Get the L2P mapping table and the block erase amount corresponding to each super block; The L2P mapping table and the block erase amount are stored in a memory.

4. The memory performance optimization method according to claim 3, characterized in that: The target parallel event includes an L2P mapping table update, and the executing the target parallel event includes: After confirming that the first super block data is full, the P2L mapping table of the first super block is loaded into the memory, and the L2P mapping table is updated according to the mapping relationship between the physical address and the logical address. The first super block is the super block that was last written.

5. The memory performance optimization method according to claim 3, characterized in that: The target parallel event includes selecting a second super block, and the executing the target parallel event includes: Reading the erase amount of each block from the memory; Based on a wear leveling algorithm, determining a super block with a minimum block erase amount from each of the super blocks according to the block erase amount; The super block with the minimum block erase amount is used as the second super block; the second super block is the next super block to be erased.

6. The memory performance optimization method according to claim 5, characterized in that: The method further comprises: After the data writing of the current super block is completed, the second super block is determined to be a new current super block, and the newly determined current super block is erased when an erase instruction is received next time.

7. The memory performance optimization method according to claim 1, characterized in that: The method further comprises: If there are multiple parallel events, execute each of the parallel events in sequence according to a preset priority; The determining whether the erasure of the current super block and the execution of the target parallel event are all completed further includes: Obtaining an erase completion signal in real time and an execution completion signal corresponding to a parallel event with the lowest preset priority; When the erase completion signal and the execution completion signal are respectively acquired, it is determined that the erasure of the current super block and the execution of the target parallel event are all completed.

8. A memory performance optimization device, characterized in that: The memory performance optimization device comprises: A target parallel event execution unit, configured to determine at least one target parallel event from a plurality of parallel events based on a preset erase duration and execute the target parallel event when receiving an erase instruction and performing an erase operation on a current super block; A judging unit, used to judge whether the erasure of the current super block and the execution of the target parallel event are all completed; The writing unit is used to send a writing instruction to write data into the current super block when the erasing of the current super block and the execution of the target parallel event are all completed.

9. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method according to any one of claims 1 to 7 when executing the program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a computer program, and when the computer program is executed, the server where the computer-readable storage medium is located is controlled to implement the steps of the method according to any one of claims 1 to 7.

Images