Data reading control method and memory storage device

Abstract

The invention provides a data reading control method and a memory storage device, which can improve the construction quality and efficiency of a sequence mapping table and improve the efficiency of the memory storage device. The data reading control method is used for a rewritable nonvolatile memory module. The data reading control method comprises the following steps: receiving a reading instruction and a first logic address interval corresponding to the reading instruction; judging whether a first sequence mapping table corresponding to the first logic address interval exists or not according to a state table; if the first sequence mapping table exists, executing a reading operation according to the first sequence mapping table; if the first sequence mapping table does not exist, the reading operation is executed according to a logic-to-physical address mapping table, and the first sequence mapping table is different from the logic-to-physical address mapping table.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a data reading control method and a memory storage device. Background Art

[0002] Smart phones, tablet computers and personal computers have grown rapidly in the past few years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are very suitable for being built into the various portable multimedia devices listed above because they are non-volatile, power-saving, small in size, and have no mechanical structure.

[0003] Generally speaking, one or more mapping tables are established and maintained in a memory storage device to record the mapping relationship between physical addresses and logical addresses. When a host system wants to read data from or write data to a rewritable non-volatile memory module, a memory management circuit (e.g., a memory controller) may, for example, look up the mapping table to obtain the physical address corresponding to the logical address to perform a data access operation on the rewritable non-volatile memory module. In a memory storage device, looking up or searching a mapping table is usually a relatively time-consuming and energy-consuming operation.

[0004] How to optimize the operation of searching the mapping table is a technical problem that needs to be solved urgently. Summary of the invention

[0005] An exemplary embodiment of the present invention provides a data read control method and a memory storage device, which can improve the performance of the memory storage device.

[0006] An exemplary embodiment of the present invention provides a data read control method for a rewritable non-volatile memory module. The data read control method comprises: receiving a read instruction and a first logical address interval corresponding to the read instruction; judging whether there is a first sequential mapping table corresponding to the first logical address interval according to a status table; if there is the first sequential mapping table, performing a read operation according to the first sequential mapping table; if there is no first sequential mapping table, performing the read operation according to a logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table.

[0007] In an exemplary embodiment of the present invention, the data reading control method further includes: constructing the state table; and constructing a plurality of sequential mapping tables, wherein the state table includes a plurality of state identifiers, the plurality of state identifiers respectively corresponding to a plurality of logical address intervals, and each of the state identifiers is used to characterize whether there is a sequential mapping table corresponding to the corresponding logical address interval, wherein the plurality of sequential mapping tables include the first sequential mapping table, and the plurality of logical address intervals include the first logical address interval.

[0008] In an exemplary embodiment of the present invention, the data reading control method further includes: when detecting that a trigger condition is reached when performing multiple read operations, traversing the status table to query multiple continuous segments; determining whether the multiple continuous segments meet a preset condition; if so, arranging the multiple continuous segments from large to small, and copying a second sequential mapping table corresponding to the first first number of continuous segments in the multiple continuous segments to a sequential mapping buffer memory, wherein the multiple sequential mapping tables include the second sequential mapping table.

[0009] In an exemplary embodiment of the present invention, the step of determining whether the plurality of continuous segments satisfy a preset condition comprises: determining whether the number of the plurality of continuous segments is within a preset interval; if the number is within the preset interval, determining whether the total number of status identifiers in the plurality of continuous segments is greater than a third number; if so, determining that the plurality of continuous segments satisfy the preset condition.

[0010] In an exemplary embodiment of the present invention, the step of determining whether the plurality of continuous segments satisfy a preset condition further includes: if the number is not within the preset interval, determining whether the number is greater than a preset number; if the number is greater than the preset number, determining whether the total number of status identifiers in a second number of continuous segments having more status identifiers among the plurality of continuous segments is greater than a third number; if so, determining that the plurality of continuous segments satisfy the preset condition.

[0011] In an exemplary embodiment of the present invention, the trigger condition is that the number of the plurality of read operations is greater than a preset value or the amount of read data corresponding to the plurality of read operations is greater than a preset amount of data.

[0012] In an exemplary embodiment of the present invention, the state identifier belonging to the first logical value among the multiple state identifiers is used to represent the existence of the sequential mapping table corresponding to the corresponding logical address interval, and the state identifier belonging to the second logical value among the multiple state identifiers is used to represent the non-existence of the sequential mapping table corresponding to the corresponding logical address interval.

[0013] In an exemplary embodiment of the present invention, each of the continuous segments includes continuous state identifiers, and the continuous state identifiers are at least two adjacent state identifiers among the plurality of state identifiers, wherein the at least two adjacent state identifiers are both the first logic value.

[0014] In an exemplary embodiment of the present invention, the step of traversing the state table to query the plurality of continuous segments includes: if the state identifier belonging to the second logic value is queried, not querying a subsequent fourth number of state identifiers.

[0015] In an exemplary embodiment of the present invention, the fourth number is associated with a logical address range corresponding to the continuous write operation.

[0016] In an exemplary embodiment of the present invention, the step of arranging the plurality of continuous segments from large to small includes: arranging the plurality of continuous segments from large to small according to the number of state identifiers included in the plurality of continuous segments.

[0017] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit includes a sequential mapping buffer memory. The connection interface unit is used to couple to a host system. The memory control circuit unit is used to receive a read instruction and its corresponding first logical address interval. The memory control circuit unit is also used to determine whether there is a first sequential mapping table corresponding to the first logical address interval according to a status table. If the first sequential mapping table exists, the memory control circuit unit is also used to perform a read operation according to the first sequential mapping table. If the first sequential mapping table does not exist, the memory control circuit unit is also used to perform the read operation according to a logical to physical address mapping table, wherein the first sequential mapping table is different from the logical to physical address mapping table.

[0018] In an exemplary embodiment of the present invention, the memory control circuit unit is also used to construct the state table and multiple sequential mapping tables, wherein the state table includes multiple state identifiers, and the multiple state identifiers respectively correspond to multiple logical address intervals, and each of the state identifiers is used to indicate whether there is a sequential mapping table corresponding to the corresponding logical address interval, wherein the multiple sequential mapping tables include the first sequential mapping table, and the multiple logical address intervals include the first logical address interval.

[0019] In an exemplary embodiment of the present invention, the memory control circuit unit is further used to detect that a trigger condition is reached when performing multiple read operations. The memory control circuit unit is further used to traverse the state table to query multiple continuous segments. The memory control circuit unit is further used to determine whether the multiple continuous segments meet a preset condition. If so, the memory control circuit unit is further used to arrange the multiple continuous segments from large to small, and copy the second sequential mapping table corresponding to the first first number of continuous segments in the multiple continuous segments to the sequential mapping buffer memory, wherein the multiple sequential mapping tables include the second sequential mapping table.

[0020] In an exemplary embodiment of the present invention, the memory control circuit unit is further used to determine whether the number of the plurality of continuous segments is within a preset interval. If the number is within the preset interval, the memory control circuit unit is further used to determine whether the total number of state identifiers in the plurality of continuous segments is greater than a third number. If so, the memory control circuit unit is further used to determine whether the plurality of continuous segments meet the preset condition.

[0021] In an exemplary embodiment of the present invention, if the number is not within the preset interval, the memory control circuit unit is further configured to determine whether the number is greater than a preset number. If the number is greater than the preset number, the memory control circuit unit is further configured to determine whether the total number of state identifiers in a second number of continuous segments having more state identifiers among the plurality of continuous segments is greater than the third number. If so, the memory control circuit unit is further configured to determine whether the plurality of continuous segments meet the preset condition.

[0022] In an exemplary embodiment of the present invention, if the state identifier belonging to the second logic value is found, the memory control circuit unit is further configured not to query a subsequent fourth number of state identifiers.

[0023] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to arrange the plurality of continuous segments in descending order according to the number of state identifiers included therein.

[0024] Based on the above, the present invention provides a data reading control method and a memory storage device, which can optimize the management mechanism for the sequential mapping table based on the continuity of the status table (that is, multiple consecutive segments in the status table), and perform reading operations according to the sequential mapping table to reduce the time required to load the mapping table, thereby improving the performance of the memory storage device.

[0025] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0027] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0028] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0029] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0030] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0031] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0032] Figure 7 is a schematic diagram of a state table and a sequence mapping table according to an exemplary embodiment of the present invention;

[0033] Figure 8 is a flow chart of a data reading control method according to an exemplary embodiment of the present invention;

[0034] Fig. 9 is a flow chart of a data reading control method according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0035] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0036] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used together with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0037] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0038] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be coupled to a system bus 110.

[0039] In an exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 via the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be coupled to the I / O device 12 via the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0040] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be coupled to the memory storage device 10 via a wired or wireless manner.

[0041] In an exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) or other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be coupled to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0042] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In one exemplary embodiment, the host system 11 is a vehicle-mounted system. In one exemplary embodiment, the memory storage device 10 and the host system 11 can each include Figure 3 A memory storage device 30 and a host system 31.

[0043] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0044] Please refer to Figure 3 , the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0045] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0046] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 41 , a memory control circuit unit 42 and a rewritable non-volatile memory module 43 .

[0047] The connection interface unit 41 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 41 and the memory control circuit unit 42 may be packaged in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42 .

[0048] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0049] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one storage cell), other flash memory modules, or other memory modules with the same characteristics.

[0050] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the critical voltage). Specifically, there is a charge capture layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge capture layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the critical voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in this memory cell.

[0051] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming cells, and these physical programming cells may constitute a plurality of physical cells. Specifically, the memory cells on the same word line may constitute one or more physical programming cells. If each memory cell can store more than 2 bits, the physical programming cells on the same word line may be classified into at least a lower physical programming cell and an upper physical programming cell. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming cell, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming cell. Generally speaking, in an MLC NAND flash memory, the write speed of the lower physical programming cell is greater than the write speed of the upper physical programming cell, and / or the reliability of the lower physical programming cell is higher than the reliability of the upper physical programming cell.

[0052] In one exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (for example, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of a physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical unit is the smallest unit of erasure. That is, each physical unit contains the minimum number of storage cells that are erased together. For example, the physical unit is a physical block.

[0053] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0054] Please refer to Figure 5 The memory control circuit unit 42 includes a memory management circuit 51 , a host interface 52 and a memory interface 53 .

[0055] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as writing, reading and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0056] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are recorded in the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

[0057] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of ​​the rewritable non-volatile memory module 43 (for example, a system area in the memory module dedicated to storing system data) in the form of code. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit will first execute the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Afterwards, the microprocessor unit will run these control instructions to perform operations such as writing, reading and erasing data.

[0058] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are coupled to the microcontroller. The storage unit management circuit is used to manage the storage unit or storage unit group of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may each include one or more codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0059] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited to this, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

[0060] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written to the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding command sequence. For example, these command sequences may include a write command sequence indicating writing data, a read command sequence indicating reading data, an erase command sequence indicating erasing data, and corresponding command sequences for indicating various memory operations (for example, changing a read voltage level or performing a garbage collection operation, etc.). These command sequences are, for example, generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These command sequences may include one or more signals, or data on a bus. These signals or data may include instruction codes or codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, etc. may be included.

[0061] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , a power management circuit 56 and a sequential mapping buffer memory 57 .

[0062] The error checking and correction circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Afterwards, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the error correcting code and / or error detecting code corresponding to the data will be read at the same time, and the error checking and correction circuit 54 will perform error checking and correction operations on the read data according to the error correcting code and / or error detecting code.

[0063] The buffer memory 55 is coupled to the memory management circuit 51 and used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and used to control the power of the memory storage device 10. The sequence mapping buffer memory 57 is coupled to the memory management circuit 51 and used to store a sequence mapping table.

[0064] In an exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0065] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0066] Please refer to Figure 6 , the memory management circuit 51 can logically group the physical units 610(0)-610(B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602. A physical unit refers to a virtual block (VB). A virtual block may include multiple physical programming units. For example, a virtual block may include one or more physical units.

[0067] The physical units 610(0)-610(A) in the storage area 601 are used to store user data (e.g. Figure 1 The user data of the host system 11 of the storage area 601). For example, the physical units 610(0)~610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A+1)~610(B) in the idle area 602 do not store data (such as valid data). For example, if a physical unit does not store valid data, this physical unit can be associated (or added) to the idle area 602. In addition, the physical units in the idle area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 602 to store the new data. In an exemplary embodiment, the idle area 602 is also called a free pool.

[0068] The memory management circuit 51 can configure the logical units 612(0)-612(C) to map the physical units 610(0)-610(A) in the storage area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units.

[0069] It should be noted that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it means that the data currently stored in this physical unit contains valid data. On the contrary, if a physical unit is not currently mapped by any logical unit, it means that the data currently stored in this physical unit does not contain any valid data.

[0070] The memory management circuit 51 may record management data describing the mapping relationship between the logical unit and the physical unit (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table. When the host system 11 wishes to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 may perform a data access operation on the memory storage device 10 according to the information in the logical-to-physical mapping table.

[0071] Figure 7 is a schematic diagram of a state table and a sequence mapping table according to an exemplary embodiment of the present invention.

[0072] Please refer to Figure 7 , the memory management circuit 51 may record the management information describing the mapping relationship between the logical address interval and the physical address interval in the sequential mapping table, and construct a state table PTE to manage the sequential mapping table. In an exemplary embodiment, the state table PTE may, for example, include multiple (for example, 512) state identifiers, and each state identifier corresponds to a logical address interval. For example, each state identifier corresponds to a logical address interval of 4kB. For example, the logical address interval includes the addresses of multiple logical units. For example, the physical address interval includes the addresses of multiple physical units.

[0073] In an exemplary embodiment, each state identifier is used to characterize whether there is a sequential mapping table corresponding to the logical address interval to which it corresponds. Specifically, multiple state identifiers may respectively belong to a first logical value (for example, a logical value of 1) or a second logical value (for example, a logical value of 0). For example, a state identifier belonging to a logical value of 1 is used to characterize that the logical address interval to which it corresponds has been mapped to one or more physical address intervals. In other words, a state identifier belonging to a logical value of 1 is used to characterize that there is a sequential mapping table corresponding to the logical address interval to which it corresponds. For example, a state identifier belonging to a logical value of 0 is used to characterize that the logical address interval to which it corresponds has not been mapped to a physical address interval. In other words, a state identifier belonging to a logical value of 0 is used to characterize that there is no sequential mapping table corresponding to the logical address interval to which it corresponds.

[0074] In an exemplary embodiment, the memory management circuit 51 may perform a read operation on the memory storage device 10 according to the sequential mapping table or the above-mentioned logical-to-physical mapping table. Specifically, when the host system 11 wants to read data from the memory storage device 10, the memory management circuit 51 may receive a read instruction and its corresponding logical address interval (also referred to as the first logical address interval). The memory management circuit 51 may determine whether there is a sequential mapping table corresponding to the first logical address interval (also referred to as the first sequential mapping table) according to the status table PTE.

[0075] In an exemplary embodiment, it is assumed that the first logical address interval corresponds to the fifth state identifier in the state table PTE. Figure 7 As shown, the fifth state flag belongs to the first logic value (ie, logic value 1), which indicates that there is a first sequential mapping table M1 corresponding to the first logical address interval. Therefore, the memory management circuit 51 can perform a read operation according to the first sequential mapping table M1.

[0076] Specifically, the sequential mapping table M1 includes but is not limited to the starting logical address Addr-1, the length L, and the starting physical address Addr-phy. The starting logical address Addr-1 is the starting address of the logical address interval included in the sequential mapping table M1. The length L is the length of the logical address interval included in the sequential mapping table M1. The starting physical address Addr-phy is the starting address of the physical address interval corresponding to the logical address interval. Figure 7As shown, the starting logical address Addr-1 is 4 and the length L is 3. Since the first logical address interval corresponds to the 5th state identifier in the state table PTE (that is, the first logical address interval is the 5th logical address interval represented by the state table PTE) and the starting logical address Addr-1 is 4 (that is, the starting address of the logical address interval included in the sequential mapping table M1 is the starting address of the 4th logical address interval), the memory management circuit 51 can calculate that the difference between the starting address (that is, the starting address of the 4th logical address interval) and the starting address of the currently requested logical address interval (that is, the 5th logical address interval) (also called the offset) is 1 (that is, the length of 1 logical address interval). Afterwards, the memory management circuit 51 can obtain the physical address of the physical address interval to which the first logical address interval is mapped according to the starting physical address Addr-phy, the length L and the offset, and complete the read operation accordingly.

[0077] In an exemplary embodiment, it is assumed that the first logical address interval corresponds to the fourth state identifier in the state table PTE. Figure 7 As shown, the fourth state flag belongs to the second logic value (ie, logic value 0), which indicates that there is no first sequence mapping table corresponding to the first logical address interval. Therefore, the memory management circuit 51 needs to perform a read operation according to the above logic-to-physical mapping table.

[0078] It should be noted that, since the logic-to-physical mapping table is used to record the mapping relationship between each logical unit and the physical unit, and the sequential mapping table only includes the following information: the starting physical address Addr-phy, the length L and the starting physical address Addr-phy, and only these information can be used to represent the mapping relationship between the logical address interval and the physical address interval, therefore, compared with the sequential mapping table, the logic-to-physical mapping table needs to occupy more storage space. Furthermore, the loading time of the logic-to-physical mapping table is also longer than the loading time of .

[0079] It is worth mentioning that if the write data from the host system 11 is discontinuous data, a logical unit corresponding to the write data may be mapped to multiple physical units. In this case, when the host system 11 wants to read the data belonging to this logical unit, the memory management circuit 51 needs to load different logical to physical mapping tables multiple times to perform the read operation, which will cause the reading speed to slow down and seriously affect the performance of the memory storage device 10.

[0080] Accordingly, the memory management circuit 51 of the present invention can determine whether to use a logic-to-physical mapping table or a sequential mapping table to perform a read operation through the status table PTE, which can speed up the execution efficiency of the read operation and thus improve the performance of the memory storage device 10.

[0081] Figure 8 is a flow chart of a data reading control method according to an exemplary embodiment of the present invention.

[0082] Please refer to Figure 8 In step S801, the memory management circuit 51 detects that a trigger condition is reached when executing a plurality of read operations. In an exemplary embodiment, the read operation may be, for example, a continuous read operation or a random read operation. In an exemplary embodiment, the trigger condition is that the number of the plurality of read operations is greater than a preset value. In an exemplary embodiment, the trigger condition is that the amount of read data corresponding to the plurality of read operations is greater than a preset amount of data. The values ​​of the preset value and the preset amount of data may be designed according to actual needs, and the present invention is not limited thereto.

[0083] In step S802, the memory management circuit 51 may traverse the state table PTE to query multiple continuous segments. In an exemplary embodiment, the memory management circuit 51 may check multiple state identifiers in the state table PTE to query multiple continuous segments. Specifically, each continuous segment includes a continuous state identifier, and the continuous state identifier is at least two adjacent state identifiers in the multiple state identifiers in the state table PTE, wherein at least two adjacent state identifiers are both the first logic value (that is, logic value 1). For example, if Figure 7 As shown, the first three state identifiers in the state table PTE are all logical values ​​1, so these three state identifiers form a continuous segment.

[0084] In an exemplary embodiment, when the memory management circuit 51 queries the state flag belonging to the second logic value (i.e., logic value 0), the memory management circuit 51 may not query the subsequent fourth number (e.g., 64) of state flags. In an exemplary embodiment, the fourth number is associated with the logical address interval corresponding to the continuous write operation.

[0085] Generally speaking, the logical address interval corresponding to the continuous write operation is in units of 512kB, so when the memory management circuit 51 searches for the continuous segment, the search unit each time needs to be smaller than 512kB (e.g., 256kB). Therefore, the fourth number can be defined as 256kB (i.e., 64 state flags).

[0086] For example, if Figure 7As shown, the fourth state identifier in the state table PTE is a logical value of 0, and the memory management circuit 51 may not query the 64 state identifiers after this state identifier. Further explanation, the fourth state identifier is a logical value of 0, which means that there is no sequential mapping table corresponding to the logical address interval corresponding to the fourth state identifier. In other words, the logical address interval corresponding to the fourth state identifier is not mapped to the physical address interval, so the logical address intervals corresponding to the 64 state identifiers after the fourth state identifier should mostly correspond to discontinuous physical addresses. In other words, the probability that these 64 state identifiers have continuous segments is small, so these 64 state identifiers can be omitted to quickly query the next continuous segment and increase the speed of traversing the state table PTE.

[0087] After traversing the state table PTE, the memory management circuit 51 may continue to determine whether the multiple continuous segments meet the preset conditions. For example, the memory management circuit 51 may continue to execute step 803 and / or step 803 to determine whether the multiple continuous segments meet the preset conditions. For example, the memory management circuit 51 may continue to execute step 803 and / or step 807 and / or step 807 to determine whether the multiple continuous segments meet the preset conditions.

[0088] In step S803, the memory management circuit 51 may determine whether the number of the plurality of continuous segments is within a preset interval. In an exemplary embodiment, the preset interval may be, for example, 4 to 8. The range of the preset interval may be designed according to actual needs, and the present invention is not limited thereto. If the number of the plurality of continuous segments is within the preset interval, the process proceeds to step S804. On the contrary, if the number of the plurality of continuous segments is not within the preset interval, the process proceeds to step S807.

[0089] In step S804 , the memory management circuit 51 may determine whether the total number of status identifiers in the plurality of consecutive segments is greater than a third number (eg, 128, where 128 status identifiers are 512 kB).

[0090] In an exemplary embodiment, assuming that the number of the plurality of continuous segments is 8, the memory management circuit 51 may determine whether the total number of status flags in the 8 continuous segments is greater than 128. The value of the third number may be designed according to actual needs, and the present invention is not limited thereto.

[0091] If the total number of status identifiers in multiple consecutive segments is not greater than 128, then end Figure 8 Specifically, when the total number of state identifiers in multiple consecutive segments is not greater than 128, it means that the state table PTE is in a highly random state, and the use of a sequential mapping table to record the mapping relationship between the logical address interval and the physical address interval is of limited benefit. Therefore, if the total number of state identifiers in multiple consecutive segments is not greater than 128, then end Figure 8The data reading control method is not used anymore and this state table PTE is no longer used.

[0092] On the contrary, if the total number of status identifiers in the 8 consecutive segments is greater than 128, the process proceeds to step S805.

[0093] In step S805 , the memory management circuit 51 may determine whether a plurality of consecutive segments satisfy a preset condition.

[0094] In step S806, the memory management circuit 51 may arrange the plurality of continuous segments from large to small, and copy the sequence mapping table corresponding to the first first number (e.g., first 4) of the plurality of continuous segments (also referred to as the second sequence mapping table) to the sequence mapping buffer memory 57. In an exemplary embodiment, the memory management circuit 51 may arrange the plurality of continuous segments from large to small according to the number of state identifiers included therein. Thereafter, the memory management circuit 51 may copy the second sequence mapping table corresponding to the first 4 continuous segments with the most state identifiers in the state table PTE to the sequence mapping buffer memory 57. Accordingly, the memory management circuit 51 may construct a high-quality (e.g., corresponding to multiple logical address intervals) sequence mapping table according to all the sequence mapping tables corresponding to the first 4 continuous segments (i.e., all the second sequence mapping tables), thereby improving the performance of the memory storage device 10.

[0095] Accordingly, the memory management circuit 51 can pre-read the data that may be needed into the buffer memory 55 according to the information in all the sequential mapping tables corresponding to the previous 4 consecutive segments, so as to improve the performance of the memory storage device 10. In addition, the method of copying the previous 4 consecutive segments to the sequential mapping buffer memory 57 can avoid the time of loading the sequential mapping table when performing subsequent data access operations, and can reduce the situation of loading different logical to physical mapping tables multiple times, which can improve the data access speed of the memory storage device 10.

[0096] On the other hand, if the number of the plurality of continuous segments is not within the preset range (i.e., 4 to 8), in step S807, the memory management circuit 51 may determine whether the number of the plurality of continuous segments is greater than the preset number (e.g., 4). The value of the preset number may be designed according to actual needs, and the present invention is not limited thereto. If the number of the plurality of continuous segments is not greater than 4, then the process ends. Figure 8 Specifically, when the number of the plurality of continuous segments is not greater than 4, it indicates that the state table PTE is in a highly random state, so the state table PTE is no longer used.

[0097] On the contrary, if the number of the plurality of continuous segments is greater than 4, the process proceeds to step S808.

[0098] In step S808, the memory management circuit 51 may determine whether the total number of state identifiers in a second number of continuous segments (for example, the first 8) with more state identifiers among the plurality of continuous segments is greater than a third number (i.e., 128). In an exemplary embodiment, assuming that the number of continuous segments is 10, the memory management circuit 51 may select 8 continuous segments with more state identifiers from the 10 continuous segments, and determine whether the total number of state identifiers in the 8 continuous segments is greater than 128. If the total number of nodes in the 8 continuous segments is not greater than 128, it means that the state table PTE is a highly random state, and the process ends. Figure 8 The data reading control method is not used anymore and this state table PTE is no longer used.

[0099] On the contrary, if the total number of status flags in the 8 consecutive segments is greater than 128, the memory management circuit 51 can continue to complete step S805 and step S806. The implementation details of step S805 and step S806 have been described in detail above and will not be repeated here.

[0100] According to the above, the memory management circuit 51 can optimize the management mechanism for the sequential mapping table based on the continuity of the status table PTE to construct a high-quality (eg, corresponding to multiple logical address intervals) sequential mapping table, thereby improving the performance of the memory storage device 10.

[0101] Fig. 9 is a flow chart of a memory management method according to an exemplary embodiment of the present invention. Fig. 9 . In step S901, a read instruction and its corresponding first logical address interval are received. In step S902, it is determined whether there is a first sequential mapping table corresponding to the first logical address interval according to the status table. In step S903, if there is a first sequential mapping table, a read operation is performed according to the first sequential mapping table. In step S904, if there is no first sequential mapping table, a read operation is performed according to a logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table.

[0102] However, Fig. 9 The steps in the above are described in detail, so we will not repeat them here. It is worth noting that Fig. 9 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Fig. 9 The method can be used in combination with the above embodiments or can be used alone, and the present invention is not limited thereto.

[0103] In summary, the data reading control method and memory storage device proposed in the exemplary embodiments of the present invention can optimize the management mechanism for the sequential mapping table based on the continuity of the state table, and use the sequential mapping table to perform the reading operation, which can speed up the execution efficiency of the reading operation, thereby improving the performance of the memory storage device 10.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data reading control method, characterized in that: For a rewritable non-volatile memory module, the data reading control method includes: Receiving a read instruction and a first logical address interval corresponding thereto; Determining whether there is a first sequence mapping table corresponding to the first logical address interval according to the status table; If the first sequence mapping table exists, performing a read operation according to the first sequence mapping table; If the first sequential mapping table does not exist, the read operation is performed according to a logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table.

2. The data reading control method according to claim 1, further comprising: Constructing the state table; as well as Build multiple sequential mapping tables, The state table includes a plurality of state identifiers, each of which corresponds to a plurality of logical address intervals, and each state identifier is used to indicate whether there is a sequential mapping table corresponding to the corresponding logical address interval. The multiple sequential mapping tables include the first sequential mapping table, and the multiple logical address intervals include the first logical address interval.

3. The data reading control method according to claim 2, further comprising: detecting that a trigger condition is reached when performing multiple read operations, traversing the state table to query multiple consecutive segments; Determining whether the plurality of continuous segments meet a preset condition; If so, the plurality of continuous segments are arranged from large to small, and the second sequential mapping tables corresponding to the first first number of continuous segments among the plurality of continuous segments are copied to the sequential mapping buffer memory, wherein the plurality of sequential mapping tables include the second sequential mapping table.

4. The data reading control method according to claim 3, wherein the step of determining whether the plurality of continuous segments meet a preset condition comprises: Determining whether the number of the plurality of continuous segments is within a preset range; If the number is within the preset interval, determining whether the total number of status identifiers in the plurality of consecutive segments is greater than a third number; If so, it is determined that the multiple continuous segments meet the preset condition.

5. The data reading control method according to claim 4, wherein the step of determining whether the plurality of continuous segments meet a preset condition further comprises: If the number is not within the preset range, determining whether the number is greater than a preset number; If the number is greater than the preset number, determining whether the total number of state identifiers in a second number of continuous segments including more state identifiers among the plurality of continuous segments is greater than the third number; If so, it is determined that the multiple continuous segments meet the preset condition. 6 . The data reading control method according to claim 3 , wherein the trigger condition is that the number of the plurality of reading operations is greater than a preset value or the amount of read data corresponding to the plurality of reading operations is greater than a preset amount of data.

7. The data reading control method according to claim 3, wherein The state identifier of the first logic value among the plurality of state identifiers is used to indicate that there is the sequence mapping table corresponding to the corresponding logical address interval. The state identifier of the second logic value among the multiple state identifiers is used to indicate that there is no sequential mapping table corresponding to the corresponding logical address interval.

8. The data reading control method according to claim 7, wherein each of the continuous segments comprises continuous state identifiers, and the continuous state identifiers are at least two adjacent state identifiers among the plurality of state identifiers, wherein the at least two adjacent state identifiers are both the first logic value.

9. The data reading control method according to claim 7, wherein the step of traversing the state table to query the plurality of continuous segments comprises: If the state identifier belonging to the second logic value is queried, the subsequent fourth number of state identifiers are not queried. 10 . The data read control method according to claim 9 , wherein the fourth number is associated with a logical address interval corresponding to a continuous write operation.

11. The data reading control method according to claim 3, wherein the step of arranging the plurality of continuous segments from large to small comprises: The multiple continuous segments are arranged from large to small according to the number of state identifiers included in them.

12. A memory storage device, characterized in that: include: A connection interface unit for coupling to a host system; Rewritable non-volatile memory module; as well as A memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module and includes a sequential mapping buffer memory. The memory control circuit unit is used to: Receiving a read instruction and a first logical address interval corresponding thereto; Determining whether there is a first sequence mapping table corresponding to the first logical address interval according to the status table; If the first sequence mapping table exists, performing a read operation according to the first sequence mapping table; If the first sequential mapping table does not exist, the read operation is performed according to a logical-to-physical address mapping table, wherein the first sequential mapping table is different from the logical-to-physical address mapping table.

13. The memory storage device according to claim 12, wherein the memory control circuit unit is further configured to: constructing the state table; and Build multiple sequential mapping tables, The state table includes a plurality of state identifiers, each of which corresponds to a plurality of logical address intervals, and each state identifier is used to indicate whether there is a sequential mapping table corresponding to the corresponding logical address interval. The multiple sequential mapping tables include the first sequential mapping table, and the multiple logical address intervals include the first logical address interval.

14. The memory storage device according to claim 13, wherein the memory control circuit unit is further configured to: detecting that a trigger condition is reached when performing multiple read operations, traversing the state table to query multiple consecutive segments; Determining whether the plurality of continuous segments meet a preset condition; If so, the plurality of continuous segments are arranged from large to small, and the second sequential mapping tables corresponding to the first first number of continuous segments among the plurality of continuous segments are copied to the sequential mapping buffer memory, wherein the plurality of sequential mapping tables include the second sequential mapping table.

15. The memory storage device according to claim 14, wherein the memory control circuit unit is further configured to: Determining whether the number of the plurality of continuous segments is within a preset range; If the number is within the preset interval, determining whether the total number of status identifiers in the plurality of consecutive segments is greater than a third number; If so, it is determined that the multiple continuous segments meet the preset condition.

16. The memory storage device according to claim 15, wherein the memory control circuit unit is further configured to: If the number is not within the preset range, determining whether the number is greater than a preset number; If the number is greater than the preset number, determining whether the total number of state identifiers in a second number of continuous segments including more state identifiers among the plurality of continuous segments is greater than the third number; If so, it is determined that the multiple continuous segments meet the preset condition. 17 . The memory storage device according to claim 14 , wherein the trigger condition is that the number of the plurality of read operations is greater than a preset value or the amount of read data corresponding to the plurality of read operations is greater than a preset amount of data.

18. The memory storage device of claim 14, wherein The state identifier of the first logic value among the plurality of state identifiers is used to indicate that there is the sequence mapping table corresponding to the corresponding logical address interval. The state identifier of the second logic value among the multiple state identifiers is used to indicate that there is no sequential mapping table corresponding to the corresponding logical address interval. 19 . The memory storage device according to claim 18 , wherein each of the continuous segments comprises continuous state identifiers, and the continuous state identifiers are at least two adjacent state identifiers among the plurality of state identifiers, wherein the at least two adjacent state identifiers are both the first logic value.

20. The memory storage device according to claim 18, wherein the memory control circuit unit is further configured to: If the state identifier belonging to the second logic value is queried, the subsequent fourth number of state identifiers are not queried.

21. The memory storage device of claim 20, wherein the fourth number is associated with a logical address interval corresponding to consecutive write operations.

22. The memory storage device according to claim 14, wherein the memory control circuit unit is further configured to: The multiple continuous segments are arranged from large to small according to the number of state identifiers included in them.

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