Software and hardware collaborative memory access operation optimization method and device, equipment and medium

Abstract

The invention discloses a software and hardware collaborative memory access operation optimization method and device, equipment and a medium, and relates to the technical field of computers, and the method comprises the following steps: traversing an operation type of a target memory reading operation corresponding to a current memory reading operation code in a target code; if the operation type is a non-direct addressing mode, executing the cache query instruction to replace the target memory reading operation; if the mode is the direct addressing mode, calculating a reuse distance corresponding to the current memory reading operation code, and judging whether the reuse distance is greater than a preset distance threshold; if yes, executing a preset direct memory access instruction to replace the target memory reading operation, and if not, executing a target cache instruction to replace the target memory reading operation; and continuing to traverse the codes until all the memory reading operation codes in the target codes are traversed. Therefore, cache pollution can be reduced by combining a memory access instruction optimization method of software and hardware.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device, equipment and medium for optimizing software and hardware collaborative memory access operations. Background Art

[0002] Currently, there are two main solutions to the cache pollution problem: hardware optimization and software optimization. However, the hardware optimization solution has to maintain a large prediction table or cache block counter every time a memory access instruction is executed, resulting in large delays and area overhead. At the same time, due to the lack of overall understanding of the program code structure and the limitation of hardware resources, the replacement strategy of the hardware optimization solution can only be based on local analysis of several recently executed instructions. Software-based methods, due to the lack of specific state information of instructions at runtime, are not ideal when faced with irregular indirect addressing memory access patterns and conditional memory access patterns caused by branch instructions. Summary of the invention

[0003] In view of this, the purpose of the present invention is to provide a method, device, equipment and medium for optimizing software and hardware collaborative memory access operations, which reasonably combines software and hardware memory access instruction optimization methods. Compared with the traditional hardware cache bypass solution, the reuse distance index is used to judge whether the instruction will be reused in the short term after being loaded into the cache, thereby reducing the overhead of dynamic judgment of these instructions during execution and the potential risk of contaminating the cache; compared with pure software solutions, for memory access modes that are not suitable for code analysis, the reuse count record module is queried and maintained during execution to determine whether cache bypass should be performed, and the judgment result is more accurate and efficient. The specific scheme is as follows:

[0004] In a first aspect, the present application discloses a method for optimizing software and hardware collaborative memory access operations, comprising:

[0005] Traversing the current memory read operation code in the target code, and determining the operation type of the target memory read operation corresponding to the current memory read operation code;

[0006] If the operation type is a non-direct addressing mode, replacing the target memory read operation by executing a cache query instruction;

[0007] If the operation type is a direct addressing mode, then calculating a reuse distance corresponding to the current memory read operation code, and determining whether the reuse distance is greater than a preset distance threshold;

[0008] If the reuse distance is greater than the preset distance threshold, the target memory read operation is replaced by executing a preset direct memory access instruction; if the reuse distance is not greater than the preset distance threshold, the target memory read operation is replaced by executing a target cache instruction;

[0009] Jump to the step of traversing the current memory read operation code in the target code to use the next memory read operation code as the current memory read operation code until all the memory read operation codes in the target code are traversed.

[0010] Optionally, traversing the current memory read operation code in the target code and determining the operation type of the target memory read operation corresponding to the current memory read operation code includes:

[0011] The target code is sequentially traversed to take the memory read operation code that first appears in the target code as the current memory read operation code, and the current memory operation code is analyzed to determine the operation type of the target memory read operation corresponding to the current memory operation code.

[0012] Optionally, if the operation type is a non-direct addressing mode, executing a cache query instruction to replace the target memory read operation includes:

[0013] If the operation type is a non-direct addressing mode, executing a cache query instruction to query the number of hardware reuses, and determining whether to save the current array to be stored to a preset cache according to the number of hardware reuses;

[0014] If the hardware reuse count is greater than a preset hardware reuse count threshold, the array to be stored is directly processed; if the hardware reuse count is not greater than the preset hardware reuse count threshold, the array to be stored is saved to a preset cache.

[0015] Optionally, if the operation type is a direct addressing mode, calculating the reuse distance corresponding to the current memory read operation code includes:

[0016] If the operation type is direct addressing mode, the next memory read operation code in the target code is traversed, and the data access amount between the current memory read operation code and the next memory read operation code is used as the reuse distance corresponding to the current memory read operation code.

[0017] Optionally, if the reuse distance is greater than the preset distance threshold, replacing the target memory read operation by executing a preset direct memory access instruction includes:

[0018] If the reuse distance is greater than the preset distance threshold, the target memory read operation is replaced by a preset direct memory access instruction, and the array to be deleted in the preset cache is deleted, so that the array to be stored is directly stored in the preset cache through the direct memory access instruction.

[0019] Optionally, if the reuse distance is not greater than the preset distance threshold, executing a target cache instruction to replace the target memory read operation includes:

[0020] If the reuse distance is not greater than the preset distance threshold, a target cache instruction is generated, and the target memory read operation is replaced by executing the target cache instruction; the target cache instruction is used to skip the judgment of the data amount of the array to be stored and directly store the array to be stored in the preset cache.

[0021] Optionally, the step of jumping to the current memory read operation code in the traversal target code to use the next memory read operation code as the current memory read operation code until all memory read operation codes in the target code are traversed, includes:

[0022] Jump to the step of traversing the current memory read operation code in the target code to determine the next memory read operation code in the target code, and use the next memory read operation code as the current memory read operation code;

[0023] Determine whether the current memory read operation code is the last memory read operation code in the target code. If the current memory read operation code is the last memory read operation code in the target code, then end the memory access operation optimization after the memory access operation corresponding to the current memory read operation code ends.

[0024] In a second aspect, the present application discloses a software-hardware collaborative memory access operation optimization device, comprising:

[0025] A code traversal module, used to traverse the current memory read operation code in the target code, and determine the operation type of the target memory read operation corresponding to the current memory read operation code;

[0026] A first instruction replacement module, configured to replace the target memory read operation by executing a cache query instruction if the operation type is a non-direct addressing mode;

[0027] A reuse distance calculation module, configured to calculate a reuse distance corresponding to the current memory read operation code if the operation type is a direct addressing mode, and determine whether the reuse distance is greater than a preset distance threshold;

[0028] A second instruction replacement module, configured to replace the target memory read operation by executing a preset direct memory access instruction if the reuse distance is greater than the preset distance threshold, and to replace the target memory read operation by executing a target cache instruction if the reuse distance is not greater than the preset distance threshold;

[0029] A step jump module is used to jump to the step of traversing the current memory read operation code in the target code to use the next memory read operation code as the current memory read operation code until all the memory read operation codes in the target code are traversed.

[0030] In a third aspect, the present application discloses an electronic device, comprising:

[0031] Memory, used to store computer programs;

[0032] The processor is used to execute the computer program to implement the aforementioned software and hardware collaborative memory access operation optimization method.

[0033] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the aforementioned software-hardware collaborative memory access operation optimization method.

[0034] In the present application, the current memory read operation code in the target code can be traversed, and the operation type of the target memory read operation corresponding to the current memory read operation code can be determined; if the operation type is a non-direct addressing mode, the target memory read operation is replaced by executing a cache query instruction; if the operation type is a direct addressing mode, the reuse distance corresponding to the current memory read operation code is calculated, and it is determined whether the reuse distance is greater than a preset distance threshold; if the reuse distance is greater than the preset distance threshold, the target memory read operation is replaced by executing a preset direct memory access instruction, and if the reuse distance is not greater than the preset distance threshold, the target memory read operation is replaced by executing a target cache instruction; jump to the step of traversing the current memory read operation code in the target code to use the next memory read operation code as the current memory read operation code until all memory read operation codes in the target code are traversed. It can be seen that, through the method of the present application, the memory read operation code in the target code can be traversed. If the operation type of the current memory read operation code is a non-direct addressing mode, the target memory read operation is replaced by executing a cache query instruction. If it is a direct addressing mode, the reuse distance is calculated, and then it is determined whether the reuse distance is greater than the preset distance threshold. If it is greater, the target memory read operation is replaced by executing a preset direct memory access instruction. If it is not greater, the target memory read operation is replaced by executing a target cache instruction, and then the traversal is continued until all the memory read operation codes in the target code are traversed. In this way, the method of the present application reasonably combines the software and hardware memory access instruction optimization methods. Compared with the traditional hardware cache bypass solution, for regular memory access read operations, this method uses the reuse distance indicator to determine whether the instruction will be reused in a short period of time after being loaded into the cache, thereby reducing the overhead of dynamic judgment of this part of the instructions during execution and the potential risk of contaminating the cache. At the same time, compared with the pure software solution, for non-direct addressing modes that are not suitable for code analysis, the cache bypass is determined by executing a cache query instruction, and the judgment result is more accurate and efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0036] Figure 1 A flowchart of a method for optimizing software and hardware collaborative memory access operations disclosed in this application;

[0037] Figure 2 A processing timing diagram of a method for optimizing software and hardware collaborative memory access operations disclosed in this application;

[0038] Figure 3 This is a diagram of a software and hardware collaborative memory access operation optimization component architecture disclosed in this application;

[0039] Figure 4 A schematic diagram of the structure of a software-hardware collaborative memory access operation optimization device disclosed in this application;

[0040] Figure 5 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] In the prior art, there are two main types of solutions to the cache pollution problem: hardware optimization and software optimization. However, the hardware optimization solution has to maintain a large prediction table or cache block counter each time a memory access instruction is executed, resulting in large delays and area overhead. The software solution lacks specific status information of the instruction at runtime, and is not ideal when faced with irregular indirect addressing memory access modes and conditional memory access modes caused by branch instructions.

[0043] In order to overcome the above-mentioned technical problems, the present application discloses a method, device, equipment and medium for optimizing software and hardware collaborative memory access operations, which can combine software and hardware memory access instruction optimization methods to reduce cache pollution. For non-direct addressing modes that are not suitable for code analysis, it is determined whether cache bypass should be performed by executing cache query instructions.

[0044] See also Figure 1 As shown, an embodiment of the present invention discloses a method for optimizing software and hardware collaborative memory access operations, including:

[0045] Step S11, traverse the current memory read operation code in the target code, and determine the operation type of the target memory read operation corresponding to the current memory read operation code.

[0046] In this embodiment, the target code that needs to be optimized for memory access operation can be traversed to determine the memory read operation code in the target code, and determine the operation type corresponding to the target memory read operation in the memory read operation code. Specifically, Figure 2As shown, it is necessary to sequentially traverse the target code and determine the memory read operation code that appears for the first time in the target code, and then use the memory read operation code that appears for the first time as the current memory read operation code, and then analyze the current memory read operation code to determine the operation type of the memory read operation corresponding to the current memory read operation code based on the obtained analysis results. It should be noted that there may be two types of operation types of the memory read operation corresponding to the current memory read operation code, one is a direct addressing mode, and the other is an indirect addressing mode. In this way, the target code can be traversed and the operation type corresponding to the memory read operation code in the target code can be accurately determined, thereby improving the accuracy of the optimization of software and hardware collaborative memory access operations.

[0047] Step S12: If the operation type is a non-direct addressing mode, the target memory read operation is replaced by executing a cache query instruction.

[0048] In this embodiment, if the operation type corresponding to the memory read operation code is a non-direct addressing mode, it is necessary to replace the target memory read operation by executing a cache query instruction. Specifically, if the operation type of the memory read operation is a non-direct addressing mode, such as an indirect addressing mode, an unbalanced addressing mode, etc., then due to the lack of specific state information of the instruction at runtime, the effect is not good when facing irregular indirect addressing memory access modes and conditional memory access modes caused by branch instructions. Therefore, a cache query instruction can be used to execute the cache query instruction to query the number of hardware reuse times, and determine whether to save the current array to be stored to the preset cache based on the number of hardware reuse times. Specifically, a cache query instruction can be used to instruct the processor to query and maintain the hardware reuse count recording module during execution, and determine the hardware reuse count based on the query result. If the hardware reuse count is greater than the preset hardware reuse count threshold, the array to be stored is directly processed; if the hardware reuse count is not greater than the preset hardware reuse count threshold, the array to be stored is saved to the preset cache. In this way, compared with pure software solutions, for memory access patterns that are not suitable for code analysis, by querying and maintaining the reuse count record module during execution to determine whether cache bypass should be performed, the judgment result is more accurate and efficient.

[0049] Step S13: If the operation type is the direct addressing mode, then calculate the reuse distance corresponding to the current memory read operation code, and determine whether the reuse distance is greater than a preset distance threshold.

[0050] In this embodiment, if the operation type is a direct addressing mode, it is necessary to calculate the reuse distance corresponding to the current memory read operation code. Specifically, the direct addressing mode includes a constant direct addressing mode and an incremental direct addressing mode, and the reuse distance refers to the number of different data elements accessed between two consecutive accesses to the same data element. Therefore, it is necessary to traverse the next memory read operation code in the target code, and use the data access amount between the current memory read operation code and the next memory read operation code as the reuse distance corresponding to the current memory read operation code. Specifically, in the calculation process of the reuse distance, it is necessary to search downward according to the order of code execution until the next memory read operation is found and the same address is accessed. At this time, the reuse distance is equal to the number of iterative loops between the two multiplied by the amount of data searched in each loop. It should be noted that due to the existence of pointers, pointers need to be aliased during the search process to determine whether two different pointers point to the same place.

[0051] Step S14: if the reuse distance is greater than the preset distance threshold, the target memory read operation is replaced by executing a preset direct memory access instruction; if the reuse distance is not greater than the preset distance threshold, the target memory read operation is replaced by executing a target cache instruction.

[0052] In this embodiment, if the reuse distance is greater than the preset distance threshold, it can be considered that the amount of data in the array to be stored is too large and exceeds the capacity of the preset cache. If the array to be stored is cached at this time, it will cause the cached array to be replaced before the next reuse. Therefore, the target memory read operation can be replaced with a preset direct memory access instruction, and the array to be deleted with the least number of accesses and the earliest access in the preset cache is deleted, so that the array to be stored is directly stored in the preset cache through the direct memory access instruction. It should be noted that the distance threshold changes with the different cache sizes in the processor.

[0053] In another scenario, if the reuse distance is not greater than the preset distance threshold, it can be considered that the array to be stored currently accessed and read will gain benefits in a short time after being placed in the preset cache, so a target cache instruction can be generated, and the target memory read operation can be replaced by the target cache instruction to skip the data volume judgment of the array to be stored, and directly store the array to be stored in the preset cache. In this way, for different reuse distance scenarios, corresponding implementation plans can be matched, and the reuse distance indicator can be used to determine whether the instruction will be reused in a short time after being loaded into the cache, thereby reducing the overhead of dynamic judgment of these instructions during execution and the potential risk of polluting the cache.

[0054] Step S15, jump to the step of traversing the current memory read operation code in the target code, so as to use the next memory read operation code as the current memory read operation code, until all the memory read operation codes in the target code are traversed.

[0055] In this embodiment, Figure 2 As shown, it is necessary to jump to the step of traversing the current memory read operation code in the target code, and then judge the next memory read operation code, and then use the next memory read operation code as the current memory read operation code. If the current memory read operation code is the last memory read operation code in the target code, then after the memory access operation corresponding to the current memory read operation code is completed, the memory access operation optimization is ended.

[0056] It can be seen that, through the method of the present application, the memory read operation code in the target code can be traversed. If the operation type of the current memory read operation code is a non-direct addressing mode, the target memory read operation is replaced by executing a cache query instruction. If it is a direct addressing mode, the reuse distance is calculated, and then it is determined whether the reuse distance is greater than the preset distance threshold. If it is greater, the target memory read operation is replaced by executing a preset direct memory access instruction. If it is not greater, the target memory read operation is replaced by executing a target cache instruction, and then the traversal is continued until all the memory read operation codes in the target code are traversed. In this way, the method of the present application reasonably combines the software and hardware memory access instruction optimization methods. Compared with the traditional hardware cache bypass solution, for regular memory access read operations, this method uses the reuse distance indicator to determine whether the instruction will be reused in a short period of time after being loaded into the cache, thereby reducing the overhead of dynamic judgment of this part of the instructions during execution and the potential risk of contaminating the cache. At the same time, compared with the pure software solution, for non-direct addressing modes that are not suitable for code analysis, the cache bypass is determined by executing a cache query instruction, and the judgment result is more accurate and efficient.

[0057] like Figure 3 The figure shows a software-hardware collaborative memory access instruction optimization component disclosed in the present application, including two parts: a software part and a hardware part. Among them, the memory is used to store compiled and optimized binary instructions, such as cache query instructions, preset direct memory access instructions, and target cache instructions, and is also used to save the data required for program operation. Depending on the type of optimized memory access instruction, the memory will send the data to different places. If it is a preset direct memory access instruction, the memory unit directly sends the data to the operation unit; if it is a target cache instruction, the data is sent to the preset cache. If it is a cache query instruction, the reuse count recording module is used to query and determine the flow of data.

[0058] Among them, the reuse count recording module is located inside the processor, and multiple storage items are used to store the reuse of different memory access operations. Each storage item has two parts. The first step part stores the program counter of the instruction. The program counter storage in this application adopts 32-bit binary. The same instruction in the loop may have multiple memory accesses during the execution process. The address of the memory access may be different each time it is executed, but the corresponding memory access mode is unified. The second part of each storage item stores the number of executions of the memory access instruction. Its upper limit needs to be set according to the scale of the specific program. It can be set as a 32-bit binary number here. When the reuse count recording module detects a memory read request, it searches for the program counter of the current read request in the storage item. If it is not found, a new storage item is added to store the program counter of the current read request and initialized to 0. At the same time, the data of the memory access is directly sent to the operation unit. If the number of newly added storage items exceeds the resource limit, the storage item with the least number of accesses and the earliest access is deleted, and then a new storage item is added. If the storage item is found, the number of accesses to the storage item corresponding to the instruction is increased by 1. And according to the found execution times, it is determined whether it is greater than the threshold. If it is greater than the threshold, the data is sent to the cache. If it is less than the threshold, the data is directly sent to the operation unit. If the access times exceed the representation range of the 32-bit binary number, the access times bits are kept at the maximum representation range unchanged.

[0059] The preset cache can store data during program execution and provide the data to the operation unit. The operation unit accepts operands from corresponding positions according to instruction requirements and performs corresponding operation types.

[0060] See also Figure 4 As shown, the embodiment of the present invention discloses a software and hardware collaborative memory access operation optimization device, comprising:

[0061] A code traversal module 11 is used to traverse the current memory read operation code in the target code and determine the operation type of the target memory read operation corresponding to the current memory read operation code;

[0062] A first instruction replacement module 12 is used for replacing the target memory read operation by executing a cache query instruction if the operation type is a non-direct addressing mode;

[0063] A reuse distance calculation module 13, for calculating the reuse distance corresponding to the current memory read operation code if the operation type is a direct addressing mode, and determining whether the reuse distance is greater than a preset distance threshold;

[0064] A second instruction replacement module 14 is configured to replace the target memory read operation by executing a preset direct memory access instruction if the reuse distance is greater than the preset distance threshold, and to replace the target memory read operation by executing a target cache instruction if the reuse distance is not greater than the preset distance threshold;

[0065] The step jump module 15 is used to jump to the step of traversing the current memory read operation code in the target code to use the next memory read operation code as the current memory read operation code until all the memory read operation codes in the target code are traversed.

[0066] In this embodiment, the current memory read operation code in the target code can be traversed, and the operation type of the target memory read operation corresponding to the current memory read operation code can be determined; if the operation type is a non-direct addressing mode, the target memory read operation is replaced by executing a cache query instruction; if the operation type is a direct addressing mode, the reuse distance corresponding to the current memory read operation code is calculated, and it is determined whether the reuse distance is greater than a preset distance threshold; if the reuse distance is greater than the preset distance threshold, the target memory read operation is replaced by executing a preset direct memory access instruction, and if the reuse distance is not greater than the preset distance threshold, the target memory read operation is replaced by executing a target cache instruction; jump to the step of traversing the current memory read operation code in the target code to use the next memory read operation code as the current memory read operation code until all memory read operation codes in the target code are traversed. It can be seen that, through the method of the present application, the memory read operation code in the target code can be traversed. If the operation type of the current memory read operation code is a non-direct addressing mode, the target memory read operation is replaced by executing a cache query instruction. If it is a direct addressing mode, the reuse distance is calculated, and then it is determined whether the reuse distance is greater than the preset distance threshold. If it is greater, the target memory read operation is replaced by executing a preset direct memory access instruction. If it is not greater, the target memory read operation is replaced by executing a target cache instruction, and then the traversal is continued until all the memory read operation codes in the target code are traversed. In this way, the method of the present application reasonably combines the software and hardware memory access instruction optimization methods. Compared with the traditional hardware cache bypass solution, for regular memory access read operations, this method uses the reuse distance indicator to determine whether the instruction will be reused in a short period of time after being loaded into the cache, thereby reducing the overhead of dynamic judgment of this part of the instructions during execution and the potential risk of contaminating the cache. At the same time, compared with the pure software solution, for non-direct addressing modes that are not suitable for code analysis, the cache bypass is determined by executing a cache query instruction, and the judgment result is more accurate and efficient.

[0067] In some embodiments, the code traversal module 11 may specifically include:

[0068] A code traversal unit is used to sequentially traverse the target code to take the memory read operation code that appears for the first time in the target code as the current memory read operation code, and analyze the current memory operation code to determine the operation type of the target memory read operation corresponding to the current memory operation code.

[0069] In some embodiments, the first instruction replacement module 12 may specifically include:

[0070] A reuse count query unit, configured to execute a cache query instruction to query a hardware reuse count if the operation type is a non-direct addressing mode, and determine whether to save the current array to be stored to a preset cache according to the hardware reuse count;

[0071] The first cache unit is used to directly perform operation processing on the array to be stored if the hardware reuse times are greater than a preset hardware reuse times threshold, and to save the array to be stored to a preset cache if the hardware reuse times are not greater than the preset hardware reuse times threshold.

[0072] In some embodiments, the reuse distance calculation module 13 may specifically include:

[0073] A reuse distance calculation unit is used to traverse the next memory read operation code in the target code if the operation type is a direct addressing mode, and use the data access amount between the current memory read operation code and the next memory read operation code as the reuse distance corresponding to the current memory read operation code.

[0074] In some embodiments, the second instruction replacement module 14 may specifically include:

[0075] The second cache unit is used to replace the target memory read operation with a preset direct memory access instruction if the reuse distance is greater than the preset distance threshold, and delete the array to be deleted in the preset cache, so as to directly store the array to be stored in the preset cache through the direct memory access instruction.

[0076] In some embodiments, the second instruction replacement module 14 may specifically include:

[0077] The third cache unit is used to generate a target cache instruction if the reuse distance is not greater than the preset distance threshold, and replace the target memory read operation by executing the target cache instruction; the target cache instruction is used to skip the judgment of the data amount of the array to be stored, and directly store the array to be stored in the preset cache.

[0078] In some embodiments, the step jump module 15 may specifically include:

[0079] a step jump unit, used to jump to the step of traversing the current memory read operation code in the target code to determine the next memory read operation code in the target code, and use the next memory read operation code as the current memory read operation code;

[0080] A code judgment unit is used to judge whether the current memory read operation code is the last memory read operation code in the target code. If the current memory read operation code is the last memory read operation code in the target code, the memory access operation optimization is terminated after the memory access operation corresponding to the current memory read operation code is completed.

[0081] Furthermore, the present application also discloses an electronic device. Figure 5 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0082] Figure 5 A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the software and hardware collaborative memory access operation optimization method disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0083] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0084] In addition, the memory 22 as a carrier for resource storage may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage method may be temporary storage or permanent storage.

[0085] The operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, and can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the software and hardware collaborative memory access operation optimization method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include computer programs that can be used to complete other specific tasks.

[0086] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the aforementioned software-hardware collaborative memory access operation optimization method is implemented. The specific steps of the method can refer to the corresponding contents disclosed in the aforementioned embodiments, and will not be repeated here.

[0087] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0088] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0089] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0090] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0091] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for optimizing software and hardware collaborative memory access operations, characterized in that: include: Traversing the current memory read operation code in the target code, and determining the operation type of the target memory read operation corresponding to the current memory read operation code; If the operation type is a non-direct addressing mode, replacing the target memory read operation by executing a cache query instruction; If the operation type is a direct addressing mode, then calculating a reuse distance corresponding to the current memory read operation code, and determining whether the reuse distance is greater than a preset distance threshold; If the reuse distance is greater than the preset distance threshold, the target memory read operation is replaced by executing a preset direct memory access instruction; if the reuse distance is not greater than the preset distance threshold, the target memory read operation is replaced by executing a target cache instruction; Jump to the step of traversing the current memory read operation code in the target code to use the next memory read operation code as the current memory read operation code until all the memory read operation codes in the target code are traversed.

2. The method for optimizing software and hardware collaborative memory access operations according to claim 1, characterized in that: The traversing the current memory read operation code in the target code and determining the operation type of the target memory read operation corresponding to the current memory read operation code includes: The target code is sequentially traversed to take the memory read operation code that first appears in the target code as the current memory read operation code, and the current memory operation code is analyzed to determine the operation type of the target memory read operation corresponding to the current memory operation code.

3. The method for optimizing software and hardware collaborative memory access operations according to claim 1, characterized in that: If the operation type is a non-direct addressing mode, executing a cache query instruction to replace the target memory read operation includes: If the operation type is a non-direct addressing mode, executing a cache query instruction to query the number of hardware reuses, and determining whether to save the current array to be stored to a preset cache according to the number of hardware reuses; If the hardware reuse count is greater than a preset hardware reuse count threshold, the array to be stored is directly processed; if the hardware reuse count is not greater than the preset hardware reuse count threshold, the array to be stored is saved to a preset cache.

4. The method for optimizing software and hardware collaborative memory access operations according to claim 1, characterized in that: If the operation type is a direct addressing mode, calculating the reuse distance corresponding to the current memory read operation code includes: If the operation type is direct addressing mode, the next memory read operation code in the target code is traversed, and the data access amount between the current memory read operation code and the next memory read operation code is used as the reuse distance corresponding to the current memory read operation code.

5. The method for optimizing software and hardware collaborative memory access operations according to claim 3, characterized in that: If the reuse distance is greater than the preset distance threshold, replacing the target memory read operation by executing a preset direct memory access instruction includes: If the reuse distance is greater than the preset distance threshold, the target memory read operation is replaced by a preset direct memory access instruction, and the array to be deleted in the preset cache is deleted, so that the array to be stored is directly stored in the preset cache through the direct memory access instruction.

6. The method for optimizing software and hardware collaborative memory access operations according to claim 5, characterized in that: If the reuse distance is not greater than the preset distance threshold, executing a target cache instruction to replace the target memory read operation includes: If the reuse distance is not greater than the preset distance threshold, a target cache instruction is generated, and the target memory read operation is replaced by executing the target cache instruction; the target cache instruction is used to skip the judgment of the data amount of the array to be stored and directly store the array to be stored in the preset cache.

7. The method for optimizing software and hardware collaborative memory access operations according to any one of claims 1 to 6, characterized in that: The step of jumping to the current memory read operation code in the traversal target code, so as to use the next memory read operation code as the current memory read operation code, until all memory read operation codes in the target code are traversed, includes: Jump to the step of traversing the current memory read operation code in the target code to determine the next memory read operation code in the target code, and use the next memory read operation code as the current memory read operation code; Determine whether the current memory read operation code is the last memory read operation code in the target code. If the current memory read operation code is the last memory read operation code in the target code, then end the memory access operation optimization after the memory access operation corresponding to the current memory read operation code ends.

8. A software and hardware collaborative memory access operation optimization device, characterized in that: include: A code traversal module, used to traverse the current memory read operation code in the target code, and determine the operation type of the target memory read operation corresponding to the current memory read operation code; A first instruction replacement module, configured to replace the target memory read operation by executing a cache query instruction if the operation type is a non-direct addressing mode; A reuse distance calculation module, configured to calculate a reuse distance corresponding to the current memory read operation code if the operation type is a direct addressing mode, and determine whether the reuse distance is greater than a preset distance threshold; A second instruction replacement module, configured to replace the target memory read operation by executing a preset direct memory access instruction if the reuse distance is greater than the preset distance threshold, and to replace the target memory read operation by executing a target cache instruction if the reuse distance is not greater than the preset distance threshold; A step jump module is used to jump to the step of traversing the current memory read operation code in the target code to use the next memory read operation code as the current memory read operation code until all the memory read operation codes in the target code are traversed.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor is used to execute the computer program to implement the software and hardware collaborative memory access operation optimization method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store a computer program, wherein when the computer program is executed by a processor, the method for optimizing software and hardware collaborative memory access operations as described in any one of claims 1 to 7 is implemented.

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