Multi-clock domain chip debugging method and device, electronic equipment, medium and program

Abstract

The embodiment of the invention discloses a multi-clock domain chip debugging method and device, electronic equipment, a medium and a program, and the method comprises the steps: monitoring the current data state of debugging data of each target to-be-debugged chip in real time; under the condition that it is determined that the debugging data meet at least one piece of cross debugging signal triggering configuration information according to the current data state of each piece of debugging data, the debugging data of a target clock domain are sent to an upper computer for software debugging; wherein the cross debugging signal triggering configuration information is generated by debugging output data configuration of a plurality of different clock domains. According to the technical scheme of the embodiment of the invention, asynchronous capture of debugging signals of multiple clock domains can be supported, so that the debugging efficiency of a multi-clock domain chip is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of chip debugging technology, and in particular to a multi-clock domain chip debugging method, device, electronic equipment, medium and program. Background Art

[0002] With the continuous evolution of integrated circuit technology, the scale of chip design has grown exponentially. At the same time, the architecture of chips has also developed in a more complex direction, and the application of multi-clock domain architecture has become more and more common. Therefore, higher requirements are also placed on chip verification and debugging.

[0003] At present, when debugging multi-clock domain chips, a dedicated debug chip is usually used to receive debug data from multiple chips. This method solves the problem that a single debug cannot capture debug data from multiple chips, and realizes the parallel and synchronous capture of debug data between multiple clock domain chips. In large-scale multi-clock domain designs, it is often necessary to capture debug signals from different clock domains. However, the existing technology cannot effectively capture debug signals from different clock domains. Summary of the invention

[0004] The embodiments of the present invention provide a multi-clock domain chip debugging method, device, electronic device, medium and program, which can support asynchronous capture of multiple clock domain debugging signals, thereby improving the debugging efficiency of the multi-clock domain chip.

[0005] According to one aspect of the present invention, a multi-clock domain chip debugging method is provided, which is applied to debugging a chip, and includes:

[0006] Real-time monitoring of the current data status of the debugging data of each target chip to be debugged;

[0007] When it is determined according to the current data state of each of the debugging data that the debugging data satisfies at least one cross debugging signal triggering configuration information, the debugging data of the target clock domain is sent to the host computer for software debugging;

[0008] The cross-debugging signal triggering configuration information is generated by configuring debug output data of a plurality of different clock domains.

[0009] According to another aspect of the present invention, a debug trigger module is provided, which is configured in a debug chip, and the debug trigger module is used to:

[0010] Real-time monitoring of the current data status of the debugging data of each target chip to be debugged;

[0011] When it is determined according to the current data state of each of the debugging data that the debugging data satisfies at least one cross debugging signal triggering configuration information, the debugging data of the target clock domain is sent to the host computer for software debugging;

[0012] The cross-debugging signal triggering configuration information is generated by configuring debug output data of a plurality of different clock domains.

[0013] According to another aspect of the present invention, a multi-clock domain chip debugging device is provided, which is configured on a debugging chip and includes:

[0014] The current data status monitoring module is used to monitor the current data status of the debugging data of each target chip to be debugged in real time;

[0015] A debugging data sending module, for sending the debugging data of the target clock domain to the host computer for software debugging when it is determined that the debugging data satisfies at least one cross debugging signal triggering configuration information according to the current data state of each debugging data;

[0016] The cross-debugging signal triggering configuration information is generated by configuring debug output data of a plurality of different clock domains.

[0017] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0018] at least one processor; and

[0019] a memory communicatively connected to the at least one processor; wherein,

[0020] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the multi-clock domain chip debugging method described in any embodiment of the present invention.

[0021] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the multi-clock domain chip debugging method described in any embodiment of the present invention when executed.

[0022] According to another aspect of the present invention, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the multi-clock domain chip debugging method according to any embodiment of the present invention is implemented.

[0023] In the embodiment of the present invention, the debugging chip monitors the current data status of the debugging data of each target chip to be debugged in real time, and determines whether the debugging data satisfies at least one cross debugging signal trigger configuration information according to the current data status of each debugging data. Further, when it is determined that the debugging data satisfies at least one cross debugging signal trigger configuration information according to the current data status of each debugging data, the debugging data of the target clock domain is sent to the host computer for software debugging, which solves the problem that the prior art cannot realize the capture of debugging signals from different clock domains, and can support the asynchronous capture of debugging signals of multiple clock domains, thereby improving the debugging efficiency of multi-clock domain chips.

[0024] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 This is a flowchart of a multi-clock domain chip debugging method provided by Embodiment 1 of the present invention;

[0027] Figure 2 This is a flow chart of a multi-clock domain chip debugging method provided by Embodiment 2 of the present invention;

[0028] Figure 3 It is a schematic diagram of a flow chart of triggering judgment of a single clock domain by a debugging chip provided in the second embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of a flow chart of a debug chip implementing cross-triggering judgment provided by the second embodiment of the present invention;

[0030] Figure 5 This is a block diagram of a multi-clock domain parallel deep debugging system provided by Embodiment 2 of the present invention;

[0031] Figure 6 is a schematic diagram of a debugging trigger module provided in Embodiment 3 of the present invention;

[0032] Figure 7 is a schematic diagram of a multi-clock domain chip debugging device provided by a fourth embodiment of the present invention;

[0033] Figure 8This is a schematic diagram of the structure of an electronic device provided in Embodiment 5 of the present invention. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "original", "target", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] Embodiment 1

[0037] Figure 1 This is a flowchart of a multi-clock domain chip debugging method provided by the first embodiment of the present invention. This embodiment is applicable to the case of asynchronously capturing debugging data of chips in different clock domains. The method can be executed by a multi-clock domain chip debugging device, which can be implemented by software and / or hardware, and can generally be integrated in an electronic device. The electronic device can be a terminal device or a server device. As long as it can execute the multi-clock domain chip debugging method, the embodiment of the present invention does not limit the specific device type of the electronic device. Accordingly, if Figure 1 As shown, the method includes the following operations:

[0038] S110 , monitoring the current data status of the debugging data of each target chip to be debugged in real time.

[0039] The target chip to be debugged may be a chip that needs to be debugged during the system development process. The debugging data may be various status and operation information obtained from the target chip to be debugged. Exemplarily, the debugging data may include but is not limited to register data, memory content, peripheral status, and debugging tracking data, etc. The embodiment of the present invention does not limit the specific content included in the debugging data. The register data may be key information of the program running stored in the register. The memory content may be the content stored in the memory inside the chip. The peripheral status may be the status information of the peripheral of the target chip to be debugged with a peripheral interface. The debugging tracking data may be information such as the program execution path and instruction execution order recorded in the debugging tracking module built into the chip. The current data status may be the real-time operation status of the debugging data of the target chip to be debugged.

[0040] In an embodiment of the present invention, in order to realize the debugging of multi-clock domain chips, the current data status of the debugging data of each target chip to be debugged can be monitored in real time, and then it can be determined whether each debugging data satisfies the cross debugging signal triggering configuration information according to the current data status of each debugging data.

[0041] S120. When it is determined according to the current data status of each of the debugging data that the debugging data satisfies at least one cross-debugging signal triggering configuration information, the debugging data of the target clock domain is sent to the host computer for software debugging; wherein the cross-debugging signal triggering configuration information is generated by the debugging output data configuration of multiple different clock domains.

[0042] Among them, the cross-debugging signal trigger configuration information can be the configuration information used to set and control the debug signal trigger signal during the debugging process. The cross-debugging signal trigger configuration information can be generated by the debug output data configuration of multiple different clock domains, that is, the cross-debugging signal trigger configuration information can be obtained by performing logical operations based on the debug output data of multiple different clock domains. The debug output data of different clock domains can be the relevant information of the debug data when the debug data of different clock domains meets a specific trigger signal. The host computer can be a specific computer system, which can be used to receive the debug data of the target clock domain sent by the debug chip, and parse the debug data according to the storage signal table, and store the debug data into a general signal data waveform file for in-depth analysis of the debug data of the multi-clock domain target chip to be debugged. The so-called storage signal table can be a data structure for recording and storing signal related information. The storage table can include but is not limited to the signal name, signal type, signal source and destination, and signal parameters, etc. The embodiment of the present invention does not limit the specific content included in the storage signal table.

[0043] Accordingly, after obtaining the current data status of the debug data of each target chip to be debugged through real-time monitoring, it is possible to determine whether the debug data satisfies the cross-debug signal trigger configuration information according to the current data status of each debug data. Exemplarily, assuming that the trigger signal of clock domain A is A1, the trigger signal of clock domain B is B1, and the debugging purpose is to check the debug data of clock domain C when the debug data of clock domain A satisfies the trigger signal A1 and the debug data of clock domain B satisfies the trigger signal B1. Therefore, the cross-debug signal trigger configuration information can be that when clock domain A and clock domain B simultaneously meet a specific trigger signal, the debug data of clock domain C is captured. Further, in the case of determining that the debug data satisfies at least one cross-debug signal trigger configuration information, the debug data of the target clock domain can be sent to the host computer via the high-speed host computer port for software debugging.

[0044] In the embodiment of the present invention, the debugging chip monitors the current data status of the debugging data of each target chip to be debugged in real time, and determines whether the debugging data satisfies at least one cross debugging signal trigger configuration information according to the current data status of each debugging data. Further, when it is determined that the debugging data satisfies at least one cross debugging signal trigger configuration information according to the current data status of each debugging data, the debugging data of the target clock domain is sent to the host computer for software debugging, which solves the problem that the prior art cannot realize the capture of debugging signals from different clock domains, and can support the asynchronous capture of debugging signals of multiple clock domains, thereby improving the debugging efficiency of multi-clock domain chips.

[0045] Embodiment 2

[0046] Figure 2 1 is a flowchart of a multi-clock domain chip debugging method provided by Embodiment 2 of the present invention. This embodiment is specific based on the above embodiment. In this embodiment, multiple specific optional implementation methods are provided for real-time monitoring of the current data state of the debugging data of each target chip to be debugged and determining that the debugging data satisfies at least one cross debugging signal trigger configuration information according to the current data state of each debugging data. Accordingly, Figure 2 As shown, the method of this embodiment may include:

[0047] S210: Receive serial debugging data packets sent by the target chips to be debugged in multiple different clock domains.

[0048] The serial debugging data packet may be a data packet composed of debugging data generated by target chips to be debugged in different clock domains in a serial manner.

[0049] In the embodiment of the present invention, the debugging chip can receive serial debugging data packets sent by multiple target to-be-debugged chips in different clock domains through a high-speed channel.

[0050] In an optional embodiment of the present invention, a serial debugging data packet can be generated by converting the original debugging data packet sent by each of the target chips to be debugged; wherein: the original debugging data can include a data packet header, data content and a data packet tail; the data packet header can include a data encoding mode, a data channel number, a data timestamp and a data length.

[0051] The original debug data packet may be a data packet in which the debug data of different target chips to be debugged are encapsulated into a specific format. The original debug data packet may include but is not limited to a data packet header, data content, and a data packet tail. The data packet header may include but is not limited to a data encoding mode, a data channel number, a data timestamp, and a data length. The original debug data packet may be converted into a serial debug data packet by a parallel-to-serial conversion module in the target chip to be debugged.

[0052] Specifically, after receiving the original debug data packets sent by each target chip to be debugged, the debug chip can convert the original debug data packets from different data sources to obtain a debug data packet in a serial format, i.e., a serial debug data packet. It can be understood that a serial debug data packet is a data packet that performs data generation and reception processing in a serial manner.

[0053] S220: Convert the serial debugging data packet into a parallel debugging data packet.

[0054] The parallel debugging data packet may be generated by converting the serial debugging data packet.

[0055] Accordingly, after receiving serial debugging data packets sent by multiple target chips to be debugged in different clock domains, the debugging chip can convert the serial data packets into parallel debugging data packets through the parallel-serial conversion module inside the debugging chip, so as to facilitate decentralized processing and storage of debugging data of multiple target chips to be debugged. It can be understood that parallel debugging data packets are multiple data packets that process each debugging data packet in parallel.

[0056] S230 , aligning and grouping the parallel debugging data packets of each clock domain based on the clock domain.

[0057] Accordingly, after converting the serial debug data packets into parallel debug data packets, the debug chip can first group the parallel debug data packets in different clock domains according to the clock domains, for example, they can be divided into clock domain group A, clock domain group B, and clock domain group C. Furthermore, the parallel debug data packets in the same clock domain can be aligned according to the time sequence of their generation, so as to observe the changes of the data in the clock domain over time, thereby improving the debugging efficiency of the multi-clock domain chip.

[0058] S240: Store the aligned and grouped parallel debugging data packets into an external memory module.

[0059] The external memory module may be an external storage device connected to the debug data. The external memory module may be used to receive the aligned grouped parallel debug data packets sent by the debug chip, or to read back the stored parallel debug data packets to the debug chip. The debug data of each target chip to be debugged is stored in the external memory module, and when the trigger signal of the debug data is met, the debug data is read back from the external memory module, which can increase the storage depth of the debug data and provide richer data basis for in-depth analysis of the operating status of the target chip to be debugged.

[0060] Correspondingly, after the parallel debugging data packets of each clock domain are aligned and grouped based on the clock domain, the aligned and grouped parallel debugging data packets can be stored in the external memory module.

[0061] In an optional embodiment of the present invention, storing the aligned grouped parallel debug data packets into an external memory module may include: determining a target clock domain of the aligned grouped parallel debug data packets; allocating a target storage space to each of the target clock domains in the storage space of the external memory module; and storing one or more groups of parallel debug data packets in the target clock domain into the same address segment of the target storage space.

[0062] The target clock domain may be the clock domain to which the parallel debugging data packet belongs. The target storage space may be the storage space in the external memory module for storing the parallel debugging data packet of the target clock domain.

[0063] In an embodiment of the present invention, in order to store the aligned grouped parallel debug data packets into an external memory module, the target clock domain of the aligned grouped parallel debug data packets can be first determined. Furthermore, a target storage space can be allocated to each target clock domain in the storage space of the external memory module, so that one or more groups of parallel debug data packets in the target clock domain can be stored in the same address segment of the target storage space.

[0064] S250 , monitoring the current data status of the debugging data of each target chip to be debugged in real time.

[0065] In an optional embodiment of the present invention, before the real-time monitoring of the current data status of the debugging data of each target chip to be debugged, it can also include: determining the cross debugging strategy of different clock domains; configuring the cross debugging signal trigger configuration information according to the cross debugging strategy of different clock domains.

[0066] Among them, the cross-debugging strategy can be that when a specific event occurs in one or more clock domains, the debug data capture of other clock domains can be triggered. The cross-debugging strategy of different clock domains can effectively analyze and manage the debug data of different clock domains in a multi-clock domain system, thereby improving the accuracy and efficiency of debugging.

[0067] In an embodiment of the present invention, before real-time monitoring of the current data status of the debugging data of each target chip to be debugged, the cross debugging strategies of different clock domains can be first determined, and then the cross debugging signal triggering configuration information can be configured according to the cross debugging strategies of different clock domains. It is understandable that there can be one or more cross debugging strategies for different clock domains, and therefore, there can also be one or more cross debugging signal triggering configuration information configured according to the cross debugging strategies of different clock domains.

[0068] In a specific example, the cross-debugging strategy for different clock domains is to check the debug data of clock domain C when the debug data of clock domain A meets the trigger signal A1 and the debug data of clock domain B meets the trigger signal B1. Therefore, the cross-debugging signal trigger configuration information can be to capture the debug data of clock domain C when clock domain A and clock domain B simultaneously meet a specific trigger signal.

[0069] S260 , comparing the current data states of the debugging data according to the trigger signals of the clock domains to obtain the trigger judgment results of the clock domains.

[0070] The trigger signal may be a signal for starting or activating a certain time, process or operation. It is understandable that the trigger signal may be preset for each clock domain. The trigger judgment result may be a conclusion obtained after evaluating the current data state of the debugging data according to the preset trigger signal during the debugging process.

[0071] In an embodiment of the present invention, after the trigger signal is pre-set for each clock domain, the current data state of each debug data can be compared according to the trigger signal of each clock domain, so as to obtain the trigger judgment result of each clock domain. It should be noted that when the current data state of each debug data is compared according to the trigger signal of each clock domain, and it is determined that the current data state of each debug data meets the trigger signal of each clock domain, the storage position of the debug data that meets the trigger signal in each clock domain is recorded, and then, when the debug output data of each clock domain meets at least one cross debug signal trigger configuration information, the debug data at the corresponding position in the target clock domain can be sent to the host computer according to the storage position.

[0072] S270 . Determine debug output data of each of the clock domains according to the conditional truth table and the trigger judgment result.

[0073] The conditional truth table may be used to store expected output results of the target chip to be debugged under all possible input combinations.

[0074] Correspondingly, after the trigger judgment result of each clock domain is obtained, the debug output data of each clock domain can be determined according to the condition truth table and the trigger judgment result.

[0075] Figure 3 FIG. 1 is a flow chart of a debugging chip triggering a single clock domain according to the second embodiment of the present invention. Figure 3 As shown, the trigger module of a single clock domain may include a trigger signal selection module matrix, a conditional comparison module compare and a conditional truth table module lut. When performing a trigger judgment in a single clock domain, a specific signal may be selected as a trigger signal through the trigger signal selection module. Further, the current data state of the debug data of the clock domain may be compared according to the trigger signal to obtain the trigger judgment result of the clock domain, and then the corresponding debug output data trigger_out may be searched from the conditional truth table module according to the trigger judgment result, so as to obtain the debug output data of the clock domain.

[0076] S280. When the debug output data of each of the clock domains hits at least one cross debug signal trigger configuration information, determine that the debug data satisfies at least one cross debug signal trigger configuration information.

[0077] Accordingly, after determining the debug output data of each clock domain, it can be determined whether the debug output data of each clock domain hits the cross debug signal trigger configuration information according to the cross debug signal trigger configuration information. Further, when the debug output data of each clock domain hits at least one cross debug signal trigger configuration information, it can be determined that the debug data satisfies at least one cross debug signal trigger configuration information.

[0078] Figure 4 FIG. 1 is a flow chart of a debug chip implementing cross triggering judgment according to the second embodiment of the present invention. Figure 4 As shown, after obtaining the debug output data of each clock domain, a multiplexer can be used to perform a logical operation on the multiple debug output data to determine the cross debug signal trigger configuration information. For example, when clock domain A and clock domain B simultaneously meet the corresponding trigger signal, the debug data of clock domain C can be captured, that is, the debug output data of clock domain A and the debug output data of clock domain B are logically ANDed. Furthermore, the debug information of the target clock domain can be determined according to the cross debug signal trigger configuration information, and the debug information can be sent to the host computer for software debugging.

[0079] S290, sending the debugging data of the target clock domain to the host computer for software debugging.

[0080] In the embodiment of the present invention, the serial debug data packets from each target chip to be debugged are received by the debug chip, and converted into parallel debug data packets. Furthermore, the debug chip aligns and groups the parallel debug data packets of each clock domain based on the clock domain, and stores the aligned and grouped parallel debug data packets in an external memory module. The debug chip can also monitor the current data status of the debug data of each target chip to be debugged in real time, so that when it is determined that the debug data meets at least one cross-debug signal trigger configuration information according to the current data status of each debug data, the debug data of the target clock domain can be read back from the external memory module to the debug chip and the debug data of the target clock domain can be sent to the host computer for software debugging, which solves the problem that the prior art cannot realize the capture of debug signals from different clock domains, and can support the asynchronous capture of debug signals of multiple clock domains, thereby improving the debugging efficiency of multi-clock domain chips.

[0081] Specific application scenarios

[0082] In order to more clearly describe the technical solution provided by the embodiment of the present invention, the embodiment of the present invention provides a multi-clock domain parallel deep debugging system. Figure 5 is a block diagram of a multi-clock domain parallel deep debugging system provided by Embodiment 2 of the present invention. In a specific example, Figure 5 As shown, the multi-clock domain parallel deep debugging system may include multiple target chips to be debugged, debugging chips, external memory modules and a host computer.

[0083] Step 1: Aggregate the internal signals of each target chip to be debugged into a bus signal, and encapsulate the bus signal into a specific communication packet format as an original debug data packet. Further, the original debug data packet can be converted into a serial debug data packet, so that the serial debug data packet can be sent to the debug chip.

[0084] Step 2: The debug chip receives serial debug data packets from each target debug chip and converts them into parallel debug data packets. Furthermore, the parallel debug data packets can be grouped according to the clock domain, and the parallel debug data packets of each clock domain can be aligned, so that the aligned parallel debug data can be stored in the external memory module.

[0085] Step 3: The debug chip can also trigger the configuration information according to the configuration cross debug signal, and monitor the current data status of the debug data of each target chip to be debugged in real time. Further, when it is determined according to the current data status of each debug data that the debug data satisfies at least one cross debug signal trigger configuration information, the debug data of the target clock domain can be read back from the external memory module to the debug chip, and the debug data can be sent to the host computer for software debugging.

[0086] Step 4: After receiving the debugging data from the debugging chip, the host computer can parse the debugging data according to the storage signal table, and store the parsed debugging data into a general signal data waveform file.

[0087] In the embodiment of the present invention, each target chip to be debugged encapsulates the debug data into an original debug data packet of a specific format, and converts the original debug data packet into a serial data packet and sends it to the debug chip. Further, the debug chip can receive the serial debug data packet from each target chip to be debugged, and convert it into a parallel debug data packet. Further, the debug chip uses the clock domain as a reference, aligns and groups the parallel debug data packets of each clock domain, and stores the aligned and grouped parallel debug data packets in an external memory module. The debug chip can also monitor the current data state of the debug data of each target chip to be debugged in real time, so that when it is determined that the debug data meets at least one cross-debug signal trigger configuration information according to the current data state of each debug data, the debug data of the target clock domain can be read back from the external memory module to the debug chip and the debug data of the target clock domain can be sent to the host computer for software debugging, solving the problem that the prior art cannot realize the capture of debug signals from different clock domains, and can support the asynchronous capture of debug signals of multiple clock domains, thereby improving the debugging efficiency of multi-clock domain chips.

[0088] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information are in compliance with the relevant laws and regulations and do not violate public order and good morals.

[0089] It should be noted that any arrangement and combination of the technical features in the above embodiments also falls within the protection scope of the present invention.

[0090] Embodiment 3

[0091] Figure 6 is a schematic diagram of a debugging trigger module provided in Embodiment 3 of the present invention, such as Figure 6As shown, the debug trigger module 310 is configured on the debug chip 300, and the debug trigger module 310 is specifically used for: real-time monitoring of the current data status of the debug data of each target chip to be debugged; when it is determined according to the current data status of each debug data that the debug data satisfies at least one cross-debug signal trigger configuration information, the debug data of the target clock domain is sent to the host computer for software debugging; wherein the cross-debug signal trigger configuration information is generated by the debug output data configuration of multiple different clock domains.

[0092] Optionally, the debug trigger module 310 is also used to: compare the current data status of each of the debug data according to the trigger signal of each of the clock domains to obtain a trigger judgment result of each of the clock domains; determine the debug output data of each of the clock domains according to the conditional truth table and the trigger judgment result; and when the debug output data of each of the clock domains hits at least one cross-debug signal trigger configuration information, determine that the debug data satisfies at least one cross-debug signal trigger configuration information.

[0093] Optionally, the debugging chip 300 is further used to: determine cross debugging strategies for different clock domains; and configure the cross debugging signal triggering configuration information according to the cross debugging strategies for different clock domains.

[0094] Optionally, the debug chip 300 is also used to: receive serial debug data packets sent by the target chip to be debugged in multiple different clock domains; convert the serial debug data packets into parallel debug data packets; align and group the parallel debug data packets of each clock domain based on the clock domain; and store the aligned and grouped parallel debug data packets in an external memory module.

[0095] Optionally, the debug chip 300 is also used to: determine the target clock domain of the parallel debug data packets after the alignment grouping; allocate target storage space to each of the target clock domains in the storage space of the external memory module; and store one or more groups of parallel debug data packets in the target clock domain into the same address segment of the target storage space.

[0096] Optionally, the serial debug data packet is generated by converting the original debug data packet sent by each target chip to be debugged; wherein: the original debug data packet includes a data packet header, data content and a data packet tail; the data packet header includes a data encoding mode, a data channel number, a data timestamp and a data length.

[0097] In the embodiment of the present invention, the debugging chip monitors the current data status of the debugging data of each target chip to be debugged in real time, and determines whether the debugging data satisfies at least one cross debugging signal trigger configuration information according to the current data status of each debugging data. Further, when it is determined that the debugging data satisfies at least one cross debugging signal trigger configuration information according to the current data status of each debugging data, the debugging data of the target clock domain is sent to the host computer for software debugging, which solves the problem that the prior art cannot realize the capture of debugging signals from different clock domains, and can support the asynchronous capture of debugging signals of multiple clock domains, thereby improving the debugging efficiency of multi-clock domain chips.

[0098] Embodiment 4

[0099] Figure 7 is a schematic diagram of a multi-clock domain chip debugging device provided by a fourth embodiment of the present invention, such as Figure 7 As shown, the device is configured on a debugging chip, and the device includes: a current data status monitoring module 410 and a debugging data sending module 420, wherein:

[0100] The current data status monitoring module 410 is used to monitor the current data status of the debugging data of each target chip to be debugged in real time;

[0101] The debugging data sending module 420 is used to send the debugging data of the target clock domain to the host computer for software debugging when it is determined that the debugging data satisfies at least one cross debugging signal triggering configuration information according to the current data state of each debugging data;

[0102] The cross-debugging signal triggering configuration information is generated by configuring debug output data of a plurality of different clock domains.

[0103] In the embodiment of the present invention, the debugging chip monitors the current data status of the debugging data of each target chip to be debugged in real time, and determines whether the debugging data satisfies at least one cross debugging signal trigger configuration information according to the current data status of each debugging data. Further, when it is determined that the debugging data satisfies at least one cross debugging signal trigger configuration information according to the current data status of each debugging data, the debugging data of the target clock domain is sent to the host computer for software debugging, which solves the problem that the prior art cannot realize the capture of debugging signals from different clock domains, and can support the asynchronous capture of debugging signals of multiple clock domains, thereby improving the debugging efficiency of multi-clock domain chips.

[0104] Optionally, the debug data sending module 420 is specifically used to: compare the current data status of each debug data according to the trigger signal of each clock domain to obtain the trigger judgment result of each clock domain; determine the debug output data of each clock domain according to the conditional truth table and the trigger judgment result; when the debug output data of each clock domain hits at least one cross-debug signal trigger configuration information, determine that the debug data satisfies at least one cross-debug signal trigger configuration information.

[0105] Optionally, the above-mentioned device may further include a trigger signal configuration module, which is specifically used to: determine the cross debugging strategies of different clock domains; and configure the cross debugging signal trigger configuration information according to the cross debugging strategies of different clock domains.

[0106] Optionally, the above-mentioned device may also include a debugging data receiving module, which is specifically used to: receive serial debugging data packets sent by the target chip to be debugged in multiple different clock domains; convert the serial debugging data packets into parallel debugging data packets; align and group the parallel debugging data packets of each clock domain based on the clock domain; and store the aligned and grouped parallel debugging data packets in an external memory module.

[0107] Optionally, the debug data receiving module is also used to: determine the target clock domain of the parallel debug data packets after the alignment grouping; allocate target storage space to each of the target clock domains in the storage space of the external memory module; and store one or more groups of parallel debug data packets in the target clock domain into the same address segment of the target storage space.

[0108] Optionally, the serial debug data packet can be generated by converting the original debug data packet sent by each of the target chips to be debugged; wherein: the original debug data packet can include a data packet header, data content and a data packet tail; the data packet header can include a data encoding mode, a data channel number, a data timestamp and a data length.

[0109] The above-mentioned multi-clock domain chip debugging device can execute the multi-clock domain chip debugging method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method. For technical details not described in detail in this embodiment, please refer to the multi-clock domain chip debugging method provided by any embodiment of the present invention.

[0110] Since the multi-clock domain chip debugging device introduced above is a device that can execute the multi-clock domain chip debugging method in the embodiment of the present invention, based on the multi-clock domain chip debugging method introduced in the embodiment of the present invention, the technical personnel in this field can understand the specific implementation of the multi-clock domain chip debugging device of this embodiment and its various variations, so how the multi-clock domain chip debugging device implements the multi-clock domain chip debugging method in the embodiment of the present invention is not introduced in detail here. As long as the technical personnel in this field implement the device adopted by the multi-clock domain chip debugging method in the embodiment of the present invention, it belongs to the scope of protection of this application.

[0111] Embodiment 5

[0112] Figure 8 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0113] like Figure 8 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0114] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0115] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as a multi-clock domain chip debugging method.

[0116] In some embodiments, the multi-clock domain chip debugging method can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the multi-clock domain chip debugging method described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to execute the multi-clock domain chip debugging method in any other appropriate manner (for example, by means of firmware).

[0117] Optionally, a multi-clock domain chip debugging method, applied to debugging chips, may include: real-time monitoring of the current data status of the debugging data of each target chip to be debugged; when it is determined according to the current data status of each debugging data that the debugging data satisfies at least one cross-debugging signal triggering configuration information, sending the debugging data of the target clock domain to a host computer for software debugging; wherein the cross-debugging signal triggering configuration information is generated by the debugging output data configuration of multiple different clock domains.

[0118] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0119] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0120] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0121] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0122] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0123] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0124] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0125] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A multi-clock domain chip debugging method, characterized in that: Used to debug chips, including: Real-time monitoring of the current data status of the debugging data of each target chip to be debugged; When it is determined according to the current data state of each of the debugging data that the debugging data satisfies at least one cross debugging signal triggering configuration information, the debugging data of the target clock domain is sent to the host computer for software debugging; The cross-debugging signal triggering configuration information is generated by configuring debug output data of a plurality of different clock domains.

2. The method according to claim 1, characterized in that The determining, according to the current data state of each of the debugging data, that the debugging data satisfies at least one cross debugging signal triggering configuration information comprises: Comparing the current data states of the debugging data according to the trigger signals of the clock domains to obtain the trigger judgment results of the clock domains; Determine the debug output data of each of the clock domains according to the conditional truth table and the trigger judgment result; When the debug output data of each of the clock domains hits at least one cross debug signal trigger configuration information, it is determined that the debug data satisfies at least one cross debug signal trigger configuration information.

3. The method according to claim 1, characterized in that: Before the real-time monitoring of the current data status of the debugging data of each target chip to be debugged, the method further includes: Determine cross-debugging strategies for different clock domains; The cross debugging signal triggering configuration information is configured according to the cross debugging strategies of the different clock domains.

4. The method according to claim 1, characterized in that: Before the real-time monitoring of the current data status of the debugging data of each target chip to be debugged, the method further includes: Receiving serial debugging data packets sent by the target chips to be debugged in multiple different clock domains; Converting the serial debug data packet into a parallel debug data packet; Based on the clock domain, the parallel debugging data packets of each clock domain are aligned and grouped; The aligned grouped parallel debug data packets are stored in an external memory block.

5. The method according to claim 4, characterized in that The step of storing the aligned grouped parallel debugging data packets into an external memory module comprises: Determine the target clock domain of the aligned grouped parallel debugging data packets; Allocating a target storage space for each of the target clock domains in the storage space of the external memory module; One or more groups of parallel debugging data packets in the target clock domain are stored in the same address segment of the target storage space.

6. The method according to claim 4, characterized in that The serial debugging data packet is generated by converting the original debugging data packet sent by each of the target chips to be debugged; wherein: The original debugging data packet includes a data packet header, data content and a data packet tail; the data packet header includes a data encoding mode, a data channel number, a data timestamp and a data length.

7. A debugging trigger module, characterized in that: Configured in the debug chip, the debug trigger module is used to: Real-time monitoring of the current data status of the debugging data of each target chip to be debugged; When it is determined according to the current data state of each of the debugging data that the debugging data satisfies at least one cross debugging signal triggering configuration information, the debugging data of the target clock domain is sent to the host computer for software debugging; The cross-debugging signal triggering configuration information is generated by configuring debug output data of a plurality of different clock domains.

8. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the multi-clock domain chip debugging method described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the multi-clock domain chip debugging method described in any one of claims 1-6 when executed.

10. A computer program product comprising a computer program / instructions, wherein: When the computer program / instruction is executed by a processor, the multi-clock domain chip debugging method described in any one of claims 1-6 is implemented.

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