Memory testing method and device and terminal equipment

Abstract

The embodiment of the invention provides a memory testing method and device and terminal equipment. The method comprises the steps that a memory test request is obtained, the memory test request comprises a memory identifier of at least one memory to be tested and test parameters, and the at least one memory is arranged in a server; according to the test parameters, performing test processing on the at least one memory to obtain a first test result; and according to the first test result, adjusting the at least one memory to obtain an adjustment parameter, and according to the adjustment parameter and the test parameter, testing the at least one memory to obtain a target test result. And the memory test optimization efficiency is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a memory testing method, apparatus, and terminal device. Background Art

[0002] Currently, enterprises can process business data through servers. In order to make the server suitable for processing large amounts of data, the memory performance of the server is tested before using the server.

[0003] In actual application, the memory performance of the server can be tested through the automated testing tool in the terminal device to obtain the test results. The staff optimizes the memory according to the test results to improve the memory performance. In the above process, since the memory is optimized manually according to the test results, the efficiency of memory test optimization is low. Summary of the invention

[0004] Embodiments of the present application provide a memory testing method, apparatus, and terminal device to solve the problem of low efficiency of memory testing optimization.

[0005] In a first aspect, an embodiment of the present application provides a memory testing method, comprising:

[0006] Obtain a memory test request, the memory test request including a memory identifier of at least one memory to be tested and a test parameter, the at least one memory being set in a server;

[0007] According to the test parameters, test the at least one memory to obtain a first test result;

[0008] According to the first test result, the at least one memory is adjusted to obtain an adjustment parameter, and according to the adjustment parameter and the test parameter, the at least one memory is tested to obtain a target test result.

[0009] In the embodiment of the present application, the terminal device can automatically optimize at least one memory according to the first test result and test the optimized memory, thereby avoiding the situation where the memory is optimized manually according to the test result, and improving the efficiency of memory test optimization.

[0010] In a possible implementation manner, the first test result includes a first memory bandwidth, a target memory bandwidth, a bandwidth efficiency, and a cross-core bandwidth set; and according to the first test result, adjusting the at least one memory to obtain an adjustment parameter includes:

[0011] Get preset bandwidth efficiency;

[0012] If the bandwidth efficiency is less than or equal to the preset bandwidth efficiency, acquiring memory plug-in information, where the memory plug-in information is used to indicate at least one memory channel and the number of memories plugged into each memory channel;

[0013] According to the memory insertion information, the at least one memory is adjusted to obtain the adjustment parameter.

[0014] In the embodiment of the present application, when the bandwidth efficiency is less than or equal to the preset bandwidth efficiency, the memory can be automatically adjusted to obtain better memory performance.

[0015] In a possible implementation, adjusting the at least one memory according to the memory insertion information and the at least one first thread to obtain the adjustment parameter includes:

[0016] Acquire at least one processing core and at least one first thread, wherein the server further comprises a central processing unit (CPU), and the CPU comprises at least one processing core;

[0017] If the memory insertion information is used to indicate that there is a memory channel that is not inserted with a memory, the at least one processing core and the at least one first thread perform adjustment processing on the at least one memory to obtain the adjustment parameter;

[0018] If the memory insertion information is used to indicate that the number of memories inserted in the memory channel is greater than a preset value, a memory channel in which the number of memories inserted is greater than the preset value is determined as a candidate memory channel, at least one memory inserted in the candidate memory channel is determined as a candidate memory, and adjustment processing is performed on the at least one candidate memory according to the at least one processing core and the at least one first thread to obtain the adjustment parameter;

[0019] The adjustment parameter is used to indicate the relationship between each memory and the at least one processing core, and the target number of the at least one first thread.

[0020] In the embodiment of the present application, the adjustment method corresponding to the memory can be determined according to the memory insertion information, thereby improving the accuracy of memory performance optimization.

[0021] In a possible implementation, performing adjustment processing on the at least one memory according to the at least one processing core and the at least one first thread to obtain the adjustment parameter includes:

[0022] For any memory, determine the processing core corresponding to the memory;

[0023] Binding the memory and a processing core corresponding to the memory to obtain a memory adjustment parameter corresponding to the memory;

[0024] Determining a target number of the at least one first thread as a number of the at least one memory;

[0025] Determining the adjustment parameter includes the memory adjustment parameter corresponding to each memory and the target quantity.

[0026] In an embodiment of the present application, when there is a memory channel without a memory inserted, each memory can be bound to the corresponding processing core. At the same time, the target number of at least one first thread is determined. In this way, the memory can access the memory corresponding to the processing core through the corresponding first thread. Avoid the situation where the memory first accesses the memory corresponding to the non-processing core or the empty memory through the first thread, and then accesses the memory corresponding to the processing core, resulting in access delay. The memory bandwidth is improved, thereby improving the memory performance.

[0027] In a possible implementation, performing adjustment processing on the at least one candidate memory according to the at least one processing core and the at least one first thread to obtain the adjustment parameter includes:

[0028] Determine an intermediate memory and at least one non-intermediate memory in the at least one to-be-selected memory, wherein the intermediate memory has a corresponding processing core, and the non-intermediate memory does not have a corresponding processing core;

[0029] For any non-intermediate memory, the non-intermediate memory is bound to a processing core corresponding to the intermediate memory to obtain an adjustment parameter corresponding to the non-intermediate memory;

[0030] Determining the adjustment parameter includes the memory adjustment parameter corresponding to each non-intermediate memory and the target quantity.

[0031] In an embodiment of the present application, when the number of memories inserted in a memory channel is greater than a preset value, each non-intermediate memory can be bound to a processing core corresponding to the intermediate memory, and the target number of at least one first thread is determined to be the number of at least one memory channel. In this way, the memory can access the memory corresponding to the processing core through the corresponding first thread. Avoid the situation where the memory randomly accesses any memory through the first thread, resulting in access delay. The memory bandwidth is improved, thereby improving the memory performance.

[0032] In a possible implementation, testing the at least one memory according to the adjustment parameter and the test parameter to obtain a target test result includes:

[0033] Determining a target thread corresponding to each processing core according to the adjustment parameter;

[0034] According to the test parameters, each processing core is controlled to run a corresponding target thread to obtain the target test result, wherein the target test result includes a second memory bandwidth, a target memory bandwidth, a bandwidth efficiency, a cross-core bandwidth set, and an adjusted bandwidth ratio.

[0035] In the embodiment of the present application, the optimized memory is tested to obtain a target test result. The target test result can indicate the degree of optimization, and the user can accurately obtain relevant information about the memory performance through the target test result, saving manpower and improving the user experience.

[0036] In a second aspect, an embodiment of the present application provides a memory testing device, the device comprising:

[0037] An acquisition module, used for acquiring a memory test request, wherein the memory test request includes a memory identifier of at least one memory to be tested and a test parameter;

[0038] A first processing module, configured to perform a test process on the at least one memory according to the test parameters to obtain a first test result;

[0039] The second processing module adjusts the at least one memory according to the first test result to obtain adjustment parameters, and tests the at least one memory according to the adjustment parameters and the test parameters to obtain target test results, wherein the adjustment parameters are used to indicate the relationship between each memory and the first thread and the processing core.

[0040] In a possible implementation manner, the second processing module is used to:

[0041] Get preset bandwidth efficiency;

[0042] If the bandwidth efficiency is less than or equal to the preset bandwidth efficiency, acquiring memory plug-in information, where the memory plug-in information is used to indicate at least one memory channel and the number of memories plugged into each memory channel;

[0043] According to the memory insertion information and the at least one first thread, the at least one memory is adjusted to obtain the adjustment parameter.

[0044] In a possible implementation manner, the second processing module is used to:

[0045] Acquire at least one processing core and at least one first thread, wherein the server further comprises a central processing unit (CPU), and the CPU comprises at least one processing core;

[0046] If the memory insertion information is used to indicate that there is a memory channel without a memory inserted, adjusting the at least one memory according to the at least one processing core and the at least one first thread to obtain the adjustment parameter;

[0047] If the memory insertion information is used to indicate that the number of memories inserted in the memory channel is greater than a preset value, a memory channel in which the number of memories inserted is greater than the preset value is determined as a candidate memory channel, at least one memory inserted in the candidate memory channel is determined as a candidate memory, and adjustment processing is performed on the at least one candidate memory according to the at least one processing core and the at least one first thread to obtain the adjustment parameter;

[0048] The adjustment parameter is used to indicate the relationship between each memory and the at least one processing core, and the target number of the at least one first thread.

[0049] In a possible implementation manner, the second processing module is used to:

[0050] For any memory, determine the processing core corresponding to the memory;

[0051] Binding the memory and a processing core corresponding to the memory to obtain a memory adjustment parameter corresponding to the memory;

[0052] Determining a target number of the at least one first thread as a number of the at least one memory;

[0053] Determining the adjustment parameter includes the memory adjustment parameter corresponding to each memory and the target quantity.

[0054] In a possible implementation manner, the second processing module is used to:

[0055] Determine an intermediate memory and at least one non-intermediate memory in the at least one to-be-selected memory, wherein the intermediate memory has a corresponding processing core, and the non-intermediate memory does not have a corresponding processing core;

[0056] For any non-intermediate memory, the non-intermediate memory is bound to a processing core corresponding to the intermediate memory to obtain an adjustment parameter corresponding to the non-intermediate memory;

[0057] determining a target number of the at least one first thread to be the number of the at least one memory channel;

[0058] Determining the adjustment parameter includes the memory adjustment parameter corresponding to each non-intermediate memory and the target quantity.

[0059] In a possible implementation manner, the second processing module is used to:

[0060] Determining a target thread corresponding to each processing core according to the adjustment parameter;

[0061] According to the test parameters, each processing core is controlled to run a corresponding target thread to obtain the target test result, wherein the target test result includes a second memory bandwidth, a target memory bandwidth, a bandwidth efficiency, a cross-core bandwidth set, and an adjusted bandwidth ratio.

[0062] In a third aspect, an embodiment of the present application provides a terminal device, including:

[0063] at least one processor; and

[0064] a memory communicatively connected to the at least one processor; wherein,

[0065] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform any method described in the first aspect.

[0066] In a fourth aspect, an embodiment of the present application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute any one of the methods described in the first aspect.

[0067] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, which implements any method in the first aspect when executed by a processor.

[0068] The memory testing method, device and terminal device provided in the embodiments of the present application can adjust at least one memory of the server according to the first test result to obtain the test result after testing at least one memory of the server. Then, according to the adjustment parameters and the test parameters, the at least one memory is tested to obtain the target test result. In the above process, the terminal device can automatically optimize at least one memory and test the optimized memory according to the first test result. This avoids the situation where the memory is optimized manually according to the test results, thereby improving the efficiency of memory test optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0070] Figure 1 A schematic diagram of an application scenario provided by an embodiment of the present application;

[0071] Figure 2 A flowchart of a memory testing method provided in an embodiment of the present application;

[0072] Figure 3 A schematic diagram of a process for obtaining a memory test request provided in an embodiment of the present application;

[0073] Figure 4 A flowchart of another memory testing method provided in an embodiment of the present application;

[0074] Figure 5 A schematic diagram of the memory test process provided by an embodiment of the present application;

[0075] Figure 6 A schematic diagram of the structure of a memory testing device provided in an embodiment of the present application;

[0076] Figure 7 A schematic diagram of the structure of a terminal device provided in an embodiment of the present application.

[0077] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0078] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0079] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0080] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0081] For ease of understanding, below, combined Figure 1 , the application scenarios to which the embodiments of the present application are applicable are described.

[0082] Figure 1 This is a schematic diagram of an application scenario provided by an embodiment of the present application. Figure 1 , including a terminal device 101 and a server 102. The terminal device 101 is provided with a test tool, and a user can test the memory performance of the server 101 through the test tool of the terminal device 101 to obtain a test result. And according to the test result, the memory of the server 101 is manually optimized to improve the memory performance.

[0083] In the above process, since the memory is optimized manually according to the test results, the efficiency of memory test optimization is low.

[0084] In an embodiment of the present application, after testing at least one memory of the server to obtain a test result, at least one memory can be adjusted according to the first test result to obtain an adjustment parameter. Then, at least one memory is tested according to the adjustment parameter and the test parameter to obtain a target test result. In the above process, the terminal device can automatically optimize at least one memory and test the optimized memory according to the first test result. This avoids the situation where the memory is optimized manually according to the test results, thereby improving the efficiency of memory test optimization.

[0085] The method shown in the present application is described below through specific embodiments. It should be noted that the following embodiments can exist independently or in combination with each other, and the same or similar contents will not be described repeatedly in different embodiments.

[0086] Figure 2 A flowchart of a memory testing method provided in an embodiment of the present application. Figure 2 , the method may include:

[0087] S201. Obtain a memory test request.

[0088] The execution subject of the embodiment of the present application may be a terminal device, or a memory test device arranged in the terminal device. The memory test device may be implemented by software, or by a combination of software and hardware. The terminal device may be a computer.

[0089] The memory test request includes a memory identifier of at least one memory to be tested and a test parameter, and the at least one memory is set in the server.

[0090] The memory is set in the server, and the memory may be a storage device, for example, a random-access memory (RAM).

[0091] The server also includes a central processing unit (CPU), and the CPU includes at least one processing core.

[0092] The test parameters are used to indicate the configuration information corresponding to each processing core in the server. The test parameters can be represented in the form of a matrix, and each element in the matrix can be the configuration information corresponding to the processing core.

[0093] The test parameter may be determined according to the total capacity of at least one memory in the server. If the total capacity of at least one memory is less than the preset capacity, the test parameter may be determined to be the first preset parameter. If the total capacity of at least one memory is greater than or equal to the preset capacity, the test parameter may be determined to be the second preset parameter.

[0094] If the test parameter is expressed in the form of a matrix, it can be determined that when the total capacity of at least one memory is less than the preset capacity, the first preset parameter can be a smaller matrix. When the total capacity of at least one memory is greater than or equal to the preset capacity, the first preset parameter can be a larger matrix.

[0095] The preset capacity can be set in advance and stored in the preset storage space of the terminal device. For example, the preset capacity can be 8G.

[0096] Next, combine Figure 3 , describes the process of obtaining a memory test request. Figure 3 A schematic diagram of the process of obtaining a memory test request provided in an embodiment of the present application. Figure 3 , including interface 301 and interface 302. Interface 301 and interface 302 may be interfaces provided by the terminal device. Referring to interface 301, the user clicks the icon corresponding to the test tool in the main page of the terminal device, and the terminal device displays the operation page in response to the user's click operation. The operation page includes a drop-down selection menu corresponding to the memory and a text input box.

[0097] Please refer to interface 302. In the drop-down selection menu corresponding to the memory, determine that the memory is memory A, and click the confirmation icon. The terminal device responds to the user's input selection operation, and at least one memory corresponding to memory A includes memory A1, memory A2, and memory A3. The terminal device determines that the total memory capacity is less than the preset capacity of 8G, and then it can determine that the test parameter is parameter A. Therefore, the terminal device obtains a memory test request including parameter A, memory A1, memory A2, and memory A3.

[0098] S202: Perform test processing on at least one memory according to the test parameters to obtain a first test result.

[0099] The first test result includes a first memory bandwidth, a target memory bandwidth, a bandwidth efficiency, and a cross-core bandwidth set.

[0100] After the terminal device obtains the test parameters, it generates a test execution file according to the test parameters. According to the test execution file, a multi-threaded test is performed, that is, the first thread corresponding to each memory performs the memory access test of the processing core and the cross-processing core to obtain the first test result.

[0101] The core binding instruction can be used to determine the processing core corresponding to each memory access and the processing core corresponding to other memory accesses (i.e., cross-processing core access).

[0102] The first memory bandwidth is the actual test bandwidth of the memory during the test, and the target memory bandwidth is the theoretical bandwidth.

[0103] The target memory bandwidth may be a product of a memory frequency, a number of memory channels, and a preset number, wherein the preset number may be 8.

[0104] The bandwidth efficiency may be a ratio of the first memory bandwidth to the target memory bandwidth.

[0105] The cross-core bandwidth set is used to indicate the bandwidth required for each processing core to access the memory corresponding to other processing cores. The cross-core bandwidth set can be represented by a matrix, where each element in the matrix is ​​the bandwidth required for a processing core to access the memory corresponding to other processing cores.

[0106] S203. According to the first test result, adjust at least one memory to obtain adjustment parameters, and according to the adjustment parameters and the test parameters, test at least one memory to obtain a target test result.

[0107] At least one memory may be adjusted according to the first test result to obtain an adjustment parameter in the following manner: obtaining a preset bandwidth efficiency; determining at least one first thread according to the first test result; if the bandwidth efficiency is less than or equal to the preset bandwidth efficiency, obtaining memory insertion information, the memory insertion information being used to indicate at least one memory channel and the number of memories inserted in each memory channel; and adjusting at least one memory corresponding row according to the memory insertion information and the at least one first thread to obtain an adjustment parameter.

[0108] The preset bandwidth efficiency may be set in advance and stored in a preset storage space of the terminal device. For example, the preset bandwidth efficiency may be 0.6.

[0109] When the bandwidth efficiency is less than or equal to the preset bandwidth efficiency, the memory can be automatically adjusted to obtain better memory performance.

[0110] Each memory can execute a test script through a corresponding first thread to perform a memory performance test. Therefore, at least one first thread and a memory corresponding to each first thread can be determined according to the first test result.

[0111] For example, according to the above example, the first thread corresponding to each memory may be determined as shown in Table 1:

[0112] Table 1

[0113]

[0114] According to the memory insertion information, it can be determined whether the memory corresponding to each processing core has been accessed across processing cores during the test. This can optimize such memory and avoid the situation where the memory corresponding to each processing core is accessed across processing cores during formal use, resulting in a long processing time.

[0115] For example, the processing core corresponding to memory A1 is processing core A1. When memory A1 is tested through the first thread, data needs to be obtained from memory A1. Since the first thread corresponding to memory A1 is not bound to processing core A1, memory A1 may first access processing core A2 or processing core A3 through the first thread, and then access processing core A1 if the corresponding data cannot be obtained from processing core A2 or processing core A3. In this way, the memory access speed is slowed down, resulting in poor memory performance. At this time, the first thread corresponding to memory A1 can be bound to processing core A1. After binding, when processing core A1 is tested again, it will give priority to accessing memory A1 and obtaining data from memory A1 when obtaining data through the first thread. In this way, the memory access speed can be improved, thereby improving memory performance.

[0116] The memory test method provided in the embodiment of the present application obtains a memory test request. According to the test parameters, at least one memory is tested and processed to obtain a first test result. According to the first test result, at least one memory is adjusted to obtain adjustment parameters, and according to the adjustment parameters and the test parameters, at least one memory is tested and processed to obtain a target test result. In the above process, the terminal device can automatically optimize at least one memory and test the optimized memory according to the first test result. This avoids the situation where the memory is optimized manually according to the test results, thereby improving the efficiency of memory test optimization.

[0117] Based on any of the above embodiments, Figure 4 , the detailed process of memory testing is explained.

[0118] Figure 4 A flowchart of another memory testing method provided in an embodiment of the present application. Figure 4 , the method comprising:

[0119] S401: Obtain a memory test request.

[0120] It should be noted that the execution process of S401 can refer to S201 and will not be repeated here.

[0121] S402: Perform test processing on at least one memory according to the test parameters to obtain a first test result.

[0122] It should be noted that the execution process of S402 can refer to S202 and will not be repeated here.

[0123] S403: Obtain at least one first thread and a preset bandwidth efficiency.

[0124] For example, assume that the memory test request obtained by the terminal device includes parameter B, memory B1, memory B2, and memory B3. The terminal device tests memory B1, memory B2, and memory B3 according to parameter B, and obtains a first test result as shown in Table 2:

[0125] Table 2

[0126]

[0127] The preset bandwidth efficiency obtained by the terminal device is 0.6.

[0128] S404: If the bandwidth efficiency is less than or equal to the preset bandwidth efficiency, obtain memory plug-in information.

[0129] The memory insertion information is used to indicate at least one memory channel and the number of memories inserted in each memory channel.

[0130] If the memory type of the memory is a dual-inline-memory-module (DIMM) type, the memory insertion information may be determined according to the number of DIMMs of the memory.

[0131] For example, according to the above example, it is determined that the bandwidth efficiency is less than the preset bandwidth efficiency. At this time, the terminal device obtains the memory plug-in information as shown in Table 3:

[0132] Table 3

[0133]

[0134] Optionally, if the bandwidth efficiency is greater than the preset bandwidth efficiency, the user can also determine whether to perform adjustment processing according to the settings, and test the memory after the adjustment processing.

[0135] S405: Acquire at least one processing core.

[0136] The server also includes a central processing unit (CPU), and the CPU includes at least one processing core.

[0137] For example, the terminal device may obtain at least one processing core as shown in Table 4:

[0138] Table 4

[0139]

[0140] S406: If the memory insertion information indicates that there is a memory channel without any memory inserted, adjusting the at least one memory according to the at least one processing core and the at least one first thread to obtain an adjustment parameter.

[0141] The adjustment parameter is used to indicate the relationship between each memory and at least one processing core, and the target number of at least one first thread.

[0142] At least one memory can be adjusted based on at least one processing core and the at least one first thread to obtain adjustment parameters in the following manner: for any memory, determine the processing core corresponding to the memory; bind the first thread corresponding to the memory and the processing core corresponding to the memory to obtain memory adjustment parameters corresponding to the memory; determine the target number of the at least one first thread to be the number of at least one memory; determine that the adjustment parameters include the memory adjustment parameters and the target number corresponding to each memory.

[0143] When there is a memory channel without a memory inserted, each memory can be bound to the corresponding processing core. At the same time, the target number of at least one first thread is determined. In this way, the memory can access the memory corresponding to the processing core through the corresponding first thread. Avoid the situation where the memory first accesses the memory corresponding to the non-processing core or the empty memory through the first thread, and then accesses the memory corresponding to the processing core, resulting in access delay. The memory bandwidth is improved, thereby improving the memory performance.

[0144] If the memory type of the memory is a DIMM type, when the number of inserted memories is less than 1DPC (1 DIMM PerChannel), it can be determined that the memory insertion information is used to indicate that there is a memory channel that has no memory inserted. Among them, 1DPC is used to indicate that there is 1 DIMM slot per channel.

[0145] For example, according to Table 3 above, it can be determined that there is a memory channel 2 that is not plugged with a memory. For the memory B1 shown in Table 4, the processing core corresponding to the memory B1 is determined to be the processing core B1. The terminal device performs binding processing on the memory B1 and the processing core B1, and obtains that the processing core whose memory adjustment parameter corresponding to the memory B1 is the memory B1 is the processing core B1. For the memory B2 shown in Table 4, it is determined that the processing core corresponding to the memory B2 is the processing core B2. The terminal device performs binding processing on the memory B2 and the processing core B2, and obtains that the processing core whose memory adjustment parameter corresponding to the memory B2 is the memory B2 is the processing core B2. For the memory B3 shown in Table 4, it is determined that the processing core corresponding to the memory B3 is the processing core B3. The terminal device performs binding processing on the memory B3 and the processing core B3, and obtains that the processing core whose memory adjustment parameter corresponding to the memory B3 is the memory B3 is the processing core B3. The terminal device determines that at least one memory includes memory B1, memory B2, and memory B3, and then it can be determined that the target number of at least one first thread is 3. The adjustment parameters can be specifically shown in Table 5:

[0146] Table 5

[0147]

[0148] In this way, when the processing core of the server accesses the memory through the first thread, it will preferentially access the memory corresponding to the processing core, and avoid preferentially accessing the memory corresponding to a non-processing core or empty memory (memory channel 2 is not equipped with memory).

[0149] S407: If the memory insertion information indicates that the number of memories inserted into the memory channel is greater than a preset value, determine the memory channel whose number of memories inserted is greater than the preset value as a candidate memory channel, and determine at least one memory inserted into the candidate memory channel as a candidate memory.

[0150] The preset value may be 1. If the memory type of the memory is a DIMM type, when the number of inserted memories is greater than 1DPC, it may be determined that the memory insertion information is used to indicate that the number of inserted memories in the memory channel is greater than the preset value.

[0151] In actual use, when the memory insertion information is used to indicate that the number of memories inserted into a memory channel is greater than a preset value, it indicates that at least one memory is inserted into each memory channel. There is no situation where there is no memory channel without a memory inserted and there is a memory channel with a number of memories inserted that is greater than a preset value.

[0152] For example, assuming that the terminal device obtains memory plug-in information, the specific information may be as shown in Table 6:

[0153] Table 6

[0154]

[0155] According to Table 6, it is determined that the number of memories inserted in memory channel 2 is greater than the preset value 1. Therefore, the terminal device determines memory channel 2 as the memory channel to be selected, and determines memory B4 and memory B5 as the memory to be selected.

[0156] S408: According to the at least one processing core and the at least one first thread, perform adjustment processing on at least one candidate memory to obtain an adjustment parameter.

[0157] At least one candidate memory can be adjusted and processed to obtain adjustment parameters in the following manner: determine an intermediate memory and at least one non-intermediate memory in the at least one candidate memory, the intermediate memory has a corresponding processing core, and the non-intermediate memory does not have a corresponding processing core; for any non-intermediate memory, bind the non-intermediate memory to the processing core corresponding to the intermediate memory to obtain the adjustment parameters corresponding to the non-intermediate memory; determine the target number of at least one first thread to be the number of at least one memory channel; determine the adjustment parameters include the memory adjustment parameters and the target number corresponding to each non-intermediate memory.

[0158] When the number of memories plugged into a memory channel is greater than a preset value, it can be determined that there are multiple memories plugged into the memory channel. At this time, there are remaining memories in the multiple memories, and when the processing core corresponding to the remaining memories accesses the memory through the corresponding first thread, it may randomly access any memory. This results in increased memory access latency and reduced memory performance. Therefore, multiple memories are bound to the corresponding processing cores respectively, and the target number of at least one first thread is determined to be the number of at least one memory channel.

[0159] When the number of memories inserted in the memory channels is greater than the preset value, each non-intermediate memory can be bound to the processing core corresponding to the intermediate memory, and the target number of at least one first thread is determined to be the number of at least one memory channel. In this way, the memory can access the memory corresponding to the processing core through the corresponding first thread. Avoid the situation where the memory randomly accesses any memory through the first thread, resulting in access delay. The memory bandwidth is improved, thereby improving the memory performance.

[0160] For example, according to the above example, the memory to be selected is determined to be memory B4 and memory B5. For memory B4, the first thread of memory B4 is determined to be thread B4, and the processing core corresponding to memory B4 is processing core B4. Thread B4 and processing core B4 are in a binding relationship. Therefore, it can be determined that the intermediate memory is memory B4, and the non-intermediate memory is memory B5. The terminal device binds memory B5 and processing core B4 to obtain the memory adjustment parameter corresponding to memory B5, that is, the processing core corresponding to memory B5 is processing core B4. According to Table 6 above, the terminal device determines that the number of at least one memory channel is 4, and then the target number can be determined to be 4. At least one first thread includes thread B1 to thread B4. The adjustment parameters can be specifically shown in Table 7:

[0161] Table 7

[0162]

[0163] S409: Perform test processing on at least one memory according to the adjustment parameters and the test parameters to obtain a target test result.

[0164] At least one memory can be tested and processed according to the adjustment parameters and the test parameters to obtain the target test results in the following manner: according to the adjustment parameters, the target thread corresponding to each processing core is determined; according to the test parameters, each processing core is controlled to run the corresponding target thread to obtain the target test results, and the target test results include the second memory bandwidth, the target memory bandwidth, the bandwidth efficiency, the cross-core bandwidth set, and the adjusted bandwidth ratio.

[0165] The second memory bandwidth is the actual test bandwidth of the memory during the test.

[0166] The bandwidth adjustment ratio is used to indicate the ratio of bandwidth increase before and after adjustment. Bandwidth adjustment ratio = (second memory bandwidth - first memory bandwidth) / second memory bandwidth

[0167] Test the optimized memory to get the target test result. The target test result can indicate the degree of optimization. Users can accurately obtain relevant information about memory performance through the target test result, saving manpower and improving user experience.

[0168] For example, according to the adjustment parameters shown in Table 7 above, it is determined that the target thread corresponding to the processing core B1 is thread B1, the target thread corresponding to the processing core B2 is thread B2, the target thread corresponding to the processing core B3 is thread B3, and the target thread corresponding to the processing core B4 is thread B4. According to the test parameters, each processing core is controlled to run the corresponding target thread to obtain the target test result. The target test result can be specifically shown in Table 8:

[0169] Table 8

[0170]

[0171] During the two tests, the memory monitoring module can be used to determine the real-time changes in data such as memory bandwidth. The test results can be compared with the monitoring data of the memory monitoring module to avoid a large gap between the test results and the monitoring data of the memory monitoring module, which may lead to errors in the test.

[0172] After obtaining the target test result, the target test result can be displayed through the terminal device. Alternatively, the target test result is sent to a preset device. The preset device can be a terminal device used by the user.

[0173] After obtaining the target test results, users can determine whether the hardware link of the memory in the server meets the design based on the target test results. If not, feedback the problem and assist in hardware problem improvement. If it meets the design, exit this test optimization.

[0174] CPUs and CPU metal dies (DIEs) are connected via buses. Different memory access paths will result in different memory bandwidths and delays. Therefore, the principle of short delay and large bandwidth can be followed to determine whether the hardware link design meets the CPU theoretical design specifications and provide a design reliability description.

[0175] The memory test method provided in the embodiment of the present application obtains a memory test request. According to the test parameters, at least one memory is tested and processed to obtain a first test result. At least one first thread and a preset bandwidth efficiency are obtained. If the bandwidth efficiency is less than or equal to the preset bandwidth efficiency, memory plug-in information is obtained. At least one processing core is obtained. If the memory plug-in information is used to indicate that there is a memory channel without a memory plugged in, at least one memory is adjusted and processed according to at least one processing core and at least one first thread to obtain an adjustment parameter. If the memory plug-in information is used to indicate that there is a memory channel with a number of plugged memories greater than a preset value, a memory channel with a number of plugged memories greater than the preset value is determined as a candidate memory channel, and at least one memory plugged in the candidate memory channel is determined as a candidate memory. And at least one candidate memory is adjusted and processed according to at least one processing core and at least one first thread to obtain an adjustment parameter. According to the adjustment parameter and the test parameter, at least one memory is tested and processed to obtain a target test result. In the above process, the terminal device can automatically optimize at least one memory according to the first test result and test the optimized memory. It avoids the situation where the memory is optimized manually according to the test result, and improves the efficiency of memory test optimization.

[0176] Based on any of the above embodiments, Figure 5 , the memory testing process is illustrated with examples.

[0177] Figure 5 A schematic diagram of the memory test process provided by the embodiment of the present application. Figure 5 , including a terminal device 501 and a server 502. The terminal device 501 can be a computer, and a test and tuning tool is set in the terminal device 501. The server 502 is provided with a memory and a CPU, and the CPU includes at least one processing core. The user inputs the memory through the test and tuning tool of the terminal device 501. The terminal device 501 responds to the user's input selection operation and obtains a memory test request including parameters C, memory C1, memory C2, and memory C3. The test and tuning tool of the terminal device 501 tests and processes at least one memory through the server 502 according to the test parameters, and obtains a first test result, which can be specifically shown in Table 9:

[0178] Table 9

[0179]

[0180] The test and tuning tool of the terminal device 501 determines that the bandwidth efficiency is less than or equal to the preset bandwidth efficiency 0.6, and then the memory plug-in information can be obtained as shown in Table 10:

[0181] Table 10

[0182]

[0183] The test and tuning tool of the terminal device 501 may obtain the first thread and the processing core corresponding to each memory as shown in Table 11:

[0184] Table 11

[0185]

[0186] The test and tuning tool of the terminal device 501 determines that the plug-in information shown in Table 10 is used to indicate that the number of memory channels plugged in is greater than the preset value 1, and determines that the selected channel is memory channel 2, and at least one selected memory is memory C2 and memory C3. The test tool of the terminal device 501 determines that there is a binding relationship between memory C2, thread C2 and processing core C2. Therefore, it is determined that the first memory is memory C2, and the second memory is memory C3. As shown in Table 11, the test and tuning tool of the terminal device 501 determines to bind memory C3, thread C2 and processing core C2 to obtain the memory adjustment parameters corresponding to memory C3. The test and tuning tool of the terminal device 501 determines that the number of at least one memory is 3, and then the target number of at least one first thread can be determined to be 3. The at least one first thread includes thread C1, thread C2 and thread C3 shown in Table 11. The test and tuning tool of the terminal device 501 determines that the adjustment parameters can be specifically as shown in Table 12:

[0187] Table 12

[0188]

[0189] The test tuning tool of the terminal device 501 determines that the target thread corresponding to the processing core C1 is thread C1, the target thread corresponding to the processing core C2 is thread C2, and the target thread corresponding to the processing core C3 is thread C3 according to the adjustment parameters shown in Table 12. The test tuning tool of the terminal device 501 controls each processing core to run the corresponding target thread according to the test parameters and the adjustment parameters shown in Table 12, and the obtained target test results can be specifically shown in Table 13:

[0190] Table 13

[0191]

[0192] The test tuning tool of the terminal device 501 displays the target test results shown in Table 13. The user can perform subsequent operations according to the target test results.

[0193] The memory test process provided in the embodiment of the present application obtains a memory test request. According to the test parameters, at least one memory is tested and processed to obtain a first test result. The first thread corresponding to each memory and the preset bandwidth efficiency are obtained. If the bandwidth efficiency is less than or equal to the preset bandwidth efficiency, the memory insertion information is obtained. The processing core corresponding to each memory is obtained. If the memory insertion information is used to indicate that there is a memory channel without a memory inserted, the first thread corresponding to at least one memory is adjusted according to the first thread corresponding to each memory and the processing core corresponding to each memory to obtain an adjustment parameter. If the memory insertion information is used to indicate that there is a memory channel with a number of inserted memories greater than the preset value, the memory channel with a number of inserted memories greater than the preset value is determined as a candidate memory channel, and at least one memory inserted in the candidate memory channel is determined as a candidate memory. The first thread corresponding to at least one candidate memory is adjusted to obtain an adjustment parameter. According to the adjustment parameter and the test parameter, at least one memory is tested and processed to obtain a target test result. In the above process, the terminal device can automatically optimize at least one memory according to the first test result and test the optimized memory. It avoids the situation where the memory is optimized manually according to the test results, and improves the efficiency of memory test optimization.

[0194] Figure 6 This is a schematic diagram of the structure of the memory test device provided in the embodiment of the present application. Figure 6 , the memory testing device 10 may include:

[0195] An acquisition module 11 is used to acquire a memory test request, wherein the memory test request includes a memory identifier of at least one memory to be tested and a test parameter;

[0196] A first processing module 12, configured to perform a test process on the at least one memory according to the test parameters to obtain a first test result;

[0197] The second processing module 13 adjusts the at least one memory according to the first test result to obtain adjustment parameters, and tests the at least one memory according to the adjustment parameters and the test parameters to obtain target test results, wherein the adjustment parameters are used to indicate the relationship between each memory and the first thread and the processing core.

[0198] In a possible implementation manner, the second processing module 13 is used to:

[0199] Get preset bandwidth efficiency;

[0200] Determine at least one first thread according to the first test result;

[0201] If the bandwidth efficiency is less than or equal to the preset bandwidth efficiency, acquiring memory plug-in information, where the memory plug-in information is used to indicate at least one memory channel and the number of memories plugged into each memory channel;

[0202] According to the memory insertion information and the at least one first thread, the at least one memory is adjusted to obtain the adjustment parameter.

[0203] In a possible implementation manner, the second processing module 13 is used to:

[0204] Acquire at least one processing core, the server further comprising a central processing unit (CPU), the CPU comprising at least one processing core;

[0205] If the memory insertion information is used to indicate that there is a memory channel without a memory inserted, adjusting the at least one memory according to the at least one processing core and the at least one first thread to obtain the adjustment parameter;

[0206] If the memory insertion information is used to indicate that the number of memories inserted in the memory channel is greater than a preset value, a memory channel in which the number of memories inserted is greater than the preset value is determined as a candidate memory channel, at least one memory inserted in the candidate memory channel is determined as a candidate memory, and adjustment processing is performed on the at least one candidate memory according to the at least one processing core and the at least one first thread to obtain the adjustment parameter;

[0207] The adjustment parameter is used to indicate the relationship between each memory and at least one processing core, and the target number of the at least one first thread.

[0208] In a possible implementation manner, the second processing module 13 is used to:

[0209] For any memory, determine a first thread corresponding to the memory and a processing core corresponding to the memory;

[0210] Binding the memory and a processing core corresponding to the memory to obtain a memory adjustment parameter corresponding to the memory;

[0211] Determining a target number of the at least one first thread as a number of the at least one memory;

[0212] Determining the adjustment parameter includes the memory adjustment parameter corresponding to each memory and the target quantity.

[0213] In a possible implementation manner, the second processing module 13 is used to:

[0214] Determine an intermediate memory and at least one non-intermediate memory in the at least one to-be-selected memory, wherein the intermediate memory has a corresponding processing core, and the non-intermediate memory does not have a corresponding processing core;

[0215] For any non-intermediate memory, the non-intermediate memory is bound to a processing core corresponding to the intermediate memory to obtain an adjustment parameter corresponding to the non-intermediate memory;

[0216] determining a target number of the at least one first thread to be the number of the at least one memory channel;

[0217] Determining the adjustment parameter includes the memory adjustment parameter corresponding to each non-intermediate memory and the target quantity.

[0218] In a possible implementation manner, the second processing module 13 is used to:

[0219] Determining a target thread corresponding to each processing core according to the adjustment parameter;

[0220] According to the test parameters, each processing core is controlled to run a corresponding target thread to obtain the target test result, wherein the target test result includes a second memory bandwidth, a target memory bandwidth, a bandwidth efficiency, a cross-core bandwidth set, and an adjusted bandwidth ratio.

[0221] The memory testing device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0222] Figure 7 This is a schematic diagram of the structure of the terminal device provided in the embodiment of the present application. Figure 7 The terminal device 20 may include: a memory 21 and a processor 22. Exemplarily, the memory 21 and the processor 22 are interconnected via a bus 23.

[0223] The memory 21 is used to store program instructions;

[0224] The processor 22 is used to execute the program instructions stored in the memory, so as to enable the terminal device 20 to execute the method shown in the above method embodiment.

[0225] The terminal device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0226] An embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the above method.

[0227] The embodiment of the present application may also provide a computer program product, including a computer program, which can implement the above method when executed by a processor.

[0228] All or part of the steps of the above-mentioned method embodiments can be completed by hardware related to program instructions. The above-mentioned program can be stored in a readable memory. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the above-mentioned memory (storage medium) includes: read-only memory (ROM), random access memory (RAM), flash memory, hard disk, solid state drive, magnetic tape, floppy disk, optical disc and any combination thereof.

[0229] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processing unit of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0230] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0231] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0232] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

[0233] In the present application, the term "include" and its variations may refer to non-restrictive inclusion; the term "or" and its variations may refer to "and / or". The terms "first", "second", etc. in the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In the present application, "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previously associated objects are in an "or" relationship.

Claims

1. A memory testing method, characterized in that: include: Obtain a memory test request, the memory test request including a memory identifier of at least one memory to be tested and a test parameter, the at least one memory being set in a server; According to the test parameters, test the at least one memory to obtain a first test result; According to the first test result, the at least one memory is adjusted to obtain an adjustment parameter, and according to the adjustment parameter and the test parameter, the at least one memory is tested to obtain a target test result.

2. The method according to claim 1, characterized in that: The first test result includes a first memory bandwidth, a target memory bandwidth, a bandwidth efficiency, and a cross-core bandwidth set; and according to the first test result, the at least one memory is adjusted to obtain an adjustment parameter, including: Get preset bandwidth efficiency; Determine at least one first thread according to the first test result; If the bandwidth efficiency is less than or equal to the preset bandwidth efficiency, acquiring memory plug-in information, where the memory plug-in information is used to indicate at least one memory channel and the number of memories plugged into each memory channel; According to the memory insertion information and the at least one first thread, the at least one memory is adjusted to obtain the adjustment parameter.

3. The method according to claim 2, characterized in that According to the memory insertion information and the at least one first thread, adjusting the at least one memory to obtain the adjustment parameter includes: Acquire at least one processing core, the server further comprising a central processing unit (CPU), the CPU comprising at least one processing core; If the memory insertion information is used to indicate that there is a memory channel without a memory inserted, adjusting the at least one memory according to the at least one processing core and the at least one first thread to obtain the adjustment parameter; If the memory insertion information is used to indicate that the number of memories inserted in the memory channel is greater than a preset value, a memory channel in which the number of memories inserted is greater than the preset value is determined as a candidate memory channel, at least one memory inserted in the candidate memory channel is determined as a candidate memory, and adjustment processing is performed on the at least one candidate memory according to the at least one processing core and the at least one first thread to obtain the adjustment parameter; The adjustment parameter is used to indicate the relationship between each memory and the at least one processing core, and the target number of the at least one first thread.

4. The method according to claim 3, characterized in that According to the at least one processing core and the at least one first thread, adjusting the at least one memory to obtain the adjustment parameter includes: For any memory, determine the processing core corresponding to the memory; Binding the memory and a processing core corresponding to the memory to obtain a memory adjustment parameter corresponding to the memory; Determining a target number of the at least one first thread as a number of the at least one memory; Determining the adjustment parameter includes the memory adjustment parameter corresponding to each memory and the target quantity.

5. The method according to claim 3, characterized in that: According to the at least one processing core and the at least one first thread, adjusting the at least one to-be-selected memory to obtain the adjustment parameter includes: Determine an intermediate memory and at least one non-intermediate memory in the at least one to-be-selected memory, wherein the intermediate memory has a corresponding processing core, and the non-intermediate memory does not have a corresponding processing core; For any non-intermediate memory, the non-intermediate memory is bound to a processing core corresponding to the intermediate memory to obtain an adjustment parameter corresponding to the non-intermediate memory; determining a target number of the at least one first thread to be the number of the at least one memory channel; Determining the adjustment parameter includes the memory adjustment parameter corresponding to each non-intermediate memory and the target quantity.

6. The method according to any one of claims 1 to 5, characterized in that: The step of testing the at least one memory according to the adjustment parameter and the test parameter to obtain a target test result includes: Determining a target thread corresponding to each processing core according to the adjustment parameter; According to the test parameters, each processing core is controlled to run a corresponding target thread to obtain the target test result, wherein the target test result includes a second memory bandwidth, a target memory bandwidth, a bandwidth efficiency, a cross-core bandwidth set, and an adjusted bandwidth ratio.

7. A memory testing device, characterized in that: The device comprises: An acquisition module, used for acquiring a memory test request, wherein the memory test request includes a memory identifier of at least one memory to be tested and a test parameter; A first processing module, configured to perform a test process on the at least one memory according to the test parameters to obtain a first test result; The second processing module adjusts the at least one memory according to the first test result to obtain adjustment parameters, and tests the at least one memory according to the adjustment parameters and the test parameters to obtain target test results, wherein the adjustment parameters are used to indicate the relationship between each memory and the first thread and the processing core.

8. A terminal device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: in, The computer instructions are used to make a computer execute the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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