Read-write function test method and device of storage chip, equipment and storage medium

Abstract

The invention discloses a read-write function test method and device for a storage chip, electronic equipment and a computer readable storage medium, and the method comprises the steps: obtaining a test requirement, input by a user, of a to-be-tested storage chip, the test requirements at least comprise the following information: storage unit matrix parameters and data writing mode requirements of the to-be-tested storage chip; embedding the test requirement into a preset cue word template to obtain a test cue word; inputting the test cue word into a trained test case generation model to obtain a target test case; and calling the target test case to execute a read-write function test process. According to the scheme, the test case can be automatically generated according to the test requirements, various test scenes can be quickly adapted, the time and the economic cost for manually compiling the test case are remarkably reduced, and the test efficiency is greatly improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of memory chips, and in particular to a method for testing the read and write functions of a memory chip, a device for testing the read and write functions, an electronic device, and a computer-readable storage medium. Background Art

[0002] The read and write function test of memory chips is a key link to ensure their performance and reliability. By writing data to the chip and reading and verifying, the integrity and consistency of data storage can be effectively detected. Generally, the read and write function test of memory chips covers multiple test scenarios to comprehensively evaluate their performance under different conditions. For example, in the basic function test scenario, technicians will write data to the chip in a specific data pattern and perform read verification to detect problems such as short circuits, open circuits, and short circuits of adjacent cells in the storage unit; in the performance test scenario, by simulating actual application scenarios (such as sequential read and write and random read and write tests), the chip's performance in processing large data streams and random I / O requests is evaluated; in the durability test scenario, repeated writes and high-temperature data retention tests are used to verify the chip's data consistency after multiple write operations and its ability to retain data in a high-temperature environment; in the stability test scenario, extreme conditions such as power failures and temperature cycles are simulated to detect the chip's reliability in a complex environment.

[0003] Since different types of memory chips differ in specifications and performance indicators, technicians need to design and write corresponding test cases based on the characteristics of each chip. In addition, the testing of each chip involves multiple scenarios (such as high load, low power consumption, extreme temperature, etc.), and each scenario requires customized test cases, which further increases the workload. The test case writing process is not only time-consuming, but also highly dependent on the professional capabilities of technicians, resulting in high testing costs. With the rapid development of memory chip technology, testing requirements are becoming increasingly complex. How to improve the efficiency of test case writing and reduce testing costs has become a technical problem that the industry needs to solve urgently. Summary of the invention

[0004] The embodiments of the present application provide a read-write function test method, a read-write function test device, an electronic device and a computer-readable storage medium for a storage chip, aiming to automatically generate test cases according to test requirements to quickly respond to various test scenarios, reduce the time and cost of manually writing test cases, and improve test efficiency.

[0005] In a first aspect, an embodiment of the present application provides a method for testing the read and write functions of a memory chip, the method comprising: Acquire the test requirements of the memory chip to be tested input by the user, wherein the test requirements at least include the following information: memory cell matrix parameters and data writing mode requirements of the memory chip to be tested; Embedding the test requirement into a preset prompt word template to obtain a test prompt word; Input the test prompt words into a trained test case generation model to obtain a target test case; The target test case is called to execute a read-write function test process, wherein the read-write test process includes: writing data to the memory chip to be tested, reading data from the memory chip to be tested according to the memory cell matrix parameters and the data writing mode requirements, and generating a test report based on the comparison results of the written data and the read data.

[0006] In the above scheme, the test requirements of the memory chip to be tested input by the user will be embedded in the preset prompt word template, and the test prompt words including the storage unit matrix parameters and the data write mode requirements will be generated. Then, the test prompt words are input into the pre-trained test case generation model, and the model will automatically generate the corresponding target test case according to the storage unit matrix parameters and the data write mode requirements, so as to realize the automatic generation of the test case. By calling the generated target test case, the read-write function test process can be automatically executed, specifically including: according to the storage unit matrix parameters and the data write mode requirements, write data to the memory chip to be tested, then read data from the chip, and finally generate a test report by comparing the results of writing data and reading data. Based on the scheme of the embodiment of the present application, test cases can be automatically generated according to the test requirements, quickly adapt to various test scenarios, significantly reduce the time and economic cost of manually writing test cases, thereby greatly improving the test efficiency.

[0007] In a possible implementation manner of the first aspect, inputting the test prompt word into a trained test case generation model to obtain a target test case includes: The test prompt word is input into a trained test case generation model, so that the test case generation model generates a storage chip definition according to the storage cell matrix parameters, generates a write function and a read verification function according to the data write mode requirements, and generates the target test case according to the storage chip definition, the target write function and the target read verification function, wherein the write function and the read verification function both call the storage chip definition, the write function is used to perform a write data operation, and the read verification function is used to verify whether the data written to the storage chip meets the expected value, and outputs the verification result.

[0008] In a possible implementation of the first aspect, the prompt word template includes: a write function template and a read verification function template corresponding to a preset data write mode; The step of generating a write function and a read verification function according to the data write mode requirement includes: Selecting a target write function template from the write function templates according to the data write mode requirement, and selecting a target read verification function template from the read verification function templates; Generate the write function according to the target write function template; The read verification function is generated according to the target read verification function template.

[0009] In a possible implementation manner of the first aspect, the preset data writing mode includes at least one of the following: an all-0 mode, an all-1 mode, and a checkerboard mode.

[0010] In a possible implementation manner of the first aspect, the test requirement further includes the following information: test report requirements; the step of inputting the test prompt word into a trained test case generation model to obtain a target test case includes: The test prompt word is input into a trained test case generation model, so that the test case generation model generates a storage chip definition according to the storage cell matrix parameters, generates a write function and a read verification function according to the data write mode requirements, and generates an output test result function according to the test report requirements, wherein the write function and the read verification function both call the storage chip definition, the write function is used to perform a write data operation, and the read verification function is used to verify whether the data written to the storage chip meets the expected value, and outputs the verification result; the output test result function is used to call the verification result output by the read verification function, and output the test report according to the verification result and the test report requirements.

[0011] In a possible implementation manner of the first aspect, the test requirement further includes the following information: test environment conditions; the step of inputting the test prompt words into a trained test case generation model to obtain a target test case includes: The test prompt word is input into a trained test case generation model, so that the test case generation model generates a storage chip definition according to the storage cell matrix parameters, generates an initialization test environment function according to the test environment conditions, generates a write function and a read verification function according to the data write mode requirements, and generates the target test case according to the storage chip definition, the initialization test environment function, the target write function and the target read verification function, wherein the initialization test environment function is used to control the test equipment hardware so that the test environment meets the test environment conditions, the write function and the read verification function both call the storage chip definition, the write function is used to perform a write data operation, and the read verification function is used to verify whether the data written to the storage chip meets the expected value, and outputs the verification result.

[0012] In a possible implementation of the first aspect, the prompt word template includes: an initialization test environment function template; and generating the initialization test environment function according to the test environment condition includes: The environment condition parameters in the initialization test environment function template are set according to the test environment conditions to obtain the initialization test environment function.

[0013] In a second aspect, an embodiment of the present application provides a read / write function test device for a memory chip, the device comprising: An acquisition module, used for acquiring the test requirements of the memory chip to be tested input by the user, wherein the test requirements at least include the following information: memory cell matrix parameters and data writing mode requirements of the memory chip to be tested; A prompt word generation module, used for embedding the test requirements into a preset prompt word template to obtain a test prompt word; A test case generation module, used for inputting the test prompt words into a trained test case generation model to obtain a target test case; A test module is used to call the target test case to execute a read and write function test process, wherein the read and write test process includes: writing data to the memory chip to be tested and reading data from the memory chip to be tested according to the storage cell matrix parameters and the data writing mode requirements, and generating a test report based on the comparison results of the written data and the read data.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, the electronic device comprising: at least one processor; at least one memory for storing at least one program; At least one program is executed by at least one of the processors to implement the method described in the first aspect.

[0015] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to execute the method described in the first aspect above.

[0016] The solutions provided in the second to fourth aspects are used to implement or cooperate with the method provided in the first aspect, and thus can achieve the same or corresponding beneficial effects as the first aspect, and will not be described in detail here.

[0017] It should be understood that the above general description and the following detailed description are merely exemplary and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of an implementation environment of a method for testing the read and write functions of a memory chip provided in an embodiment of the present application; Figure 2 A flowchart of a method for testing the read and write functions of a memory chip provided in an embodiment of the present application; Figure 3 A schematic diagram of a test prompt word provided in an embodiment of the present application; Figure 4 A schematic diagram of the structure of a read-write function test device for a memory chip provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical methods and advantages of this application more clear, the following is a further detailed description of this application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain this application and are not used to limit this application.

[0021] It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order from that in the flowchart. In the description of the specification, claims and the above-mentioned drawings, "at least one" means one or more, and the meaning of multiple (or multiple) is more than two. Greater than, less than, and exceeding are understood to exclude the number itself, and above, below, and within are understood to include the number itself. If there is a description of "first", "second", etc., it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the order of the technical features indicated.

[0022] In the embodiments of the present application, "and / or" describes the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B may represent the situation where A exists alone, A and B exist at the same time, or B exists alone. A and B may be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, at least one of a, b, and c may represent: a exists alone, b exists alone, c exists alone, a and b exist at the same time, a and c exist at the same time, b and c exist at the same time, or a, b, and c exist at the same time, wherein a, b, and c may be single or multiple.

[0023] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0024] The embodiments of the present application provide a method for testing the read and write functions of a storage chip, a device for testing the read and write functions of a storage chip, an electronic device, a computer program product, and a computer-readable storage medium, which are intended to automatically generate test cases according to test requirements to quickly respond to various test scenarios, reduce the time and cost of manually writing test cases, and improve test efficiency.

[0025] The following first explains the terms involved in the embodiments of the present application.

[0026] Memory chip: Memory chip is a core semiconductor device used for data storage in electronic devices, mainly recording binary information through charge or transistor state. Memory cell is the smallest physical unit in the memory chip that can store a single binary bit (0 or 1). The memory chip usually uses a matrix structure to organize the memory cells. The memory cells are arranged in an array in rows and columns. Each cell corresponds to a unique coordinate and is physically located by a row address decoder and a column address decoder. When the CPU initiates an access request, it first sends the row address and activates the corresponding row line through the row address select signal (RAS#). All cells in the row are connected to the column line; then the column address is sent, and the column decoder is triggered by the column address select signal (CAS#) to screen out the target cell to complete the read and write operation.

[0027] All 0 mode: A data writing mode for memory chip testing, which writes 0 to all memory cells of the memory chip, and then reads and verifies whether the content of each memory cell is 0. It can be used to detect fixed faults of the memory, that is, whether the memory cell can correctly store and read the value 0.

[0028] All 1 mode: A data writing mode for memory chip testing, which writes 1 to all memory cells of the memory chip, and then reads and verifies whether the content of each memory cell is 1. Similar to the all 0 mode, it is used to detect fixed faults of the memory, that is, whether the memory cell can correctly store and read the value of 1.

[0029] Checkerboard mode: A data writing mode for memory chip testing, in which 0 and 1 are written to the memory cells of the memory chip in a checkerboard manner, that is, different values ​​are written to adjacent memory cells to form a chessboard-like pattern. It is used to detect fixed faults, address decoding faults, and short circuit faults of adjacent bits of memory. This mode can more effectively detect faults between adjacent cells in the memory.

[0030] Prompt: Prompt is an instruction or guiding information input to the language model. It can guide the model to output results in the direction expected by the user. By using examples to standardize the output format and using clear instructions to constrain the direction of result generation, the output results can be more in line with specific needs, improve the pertinence and accuracy of the output results, and allow the model to better serve different scenarios and tasks.

[0031] Test Case: A test case is the basic unit in software or hardware testing, used to verify whether a specific function or behavior meets expectations. In memory chip testing, the purpose of the test case is to detect the function, performance, and reliability of the memory chip through specific data patterns and operation steps.

[0032] Language model: A language model is an AI system that predicts text sequences through probabilistic modeling. Its core is to learn the association rules between words. Modern language models based on deep learning (such as GPT and BERT) use the Transformer architecture to capture long-distance semantic dependencies through the self-attention mechanism. Training is divided into two stages: the pre-training stage learns general language representations (such as predicting mask words or the next sentence) on massive texts, and the fine-tuning stage optimizes parameters for specific tasks. The model processes text through a decoder (autoregressive generation) or an encoder (semantic understanding), supporting tasks such as machine translation, question answering, and code generation.

[0033] The following introduces the implementation environment of the read and write function testing method of the storage chip provided in the embodiment of the present application.

[0034] See also Figure 1, is a schematic diagram of an implementation environment of the read-write function test method of the memory chip provided in the embodiment of the present application. Figure 1 As shown, the implementation environment of the read-write function test method of the memory chip includes a memory chip test device (Memory Tester) and a server. Among them, the memory chip test device is used to receive the test requirements of the memory chip to be tested input by the user, and then send the test requirements to the server. A pre-trained test case generation model is deployed in the server. After the server receives the test requirements, it outputs the corresponding target test case based on the test requirements through the test case generation model, and returns it to the memory chip test device. The memory chip test device calls the target test case to automatically execute the read-write function test process, which specifically includes: writing data to the memory chip to be tested according to the storage unit matrix parameters and data writing mode requirements, and then reading data from the chip, and finally generating a test report by comparing the results of writing data and reading data.

[0035] Exemplarily, the memory chip test equipment is used as the core hardware platform of the test environment, and the specific structure may be as follows: Main control module: Integrates FPGA or ASIC controller, responsible for executing test algorithms, timing control and signal generation.

[0036] Channel resource module: provides multi-channel parallel testing capabilities, supports interface protocols such as DDR4 / DDR5, LPDDR, and NAND Flash, and supports channel expansion to achieve multi-chip synchronous testing.

[0037] Parametric Measurement Unit (PMU): Tests static parameters (standby current, leakage current) and dynamic parameters (read and write voltage tolerance, signal integrity) to ensure compliance with JEDEC standards.

[0038] Logic analyzer and bit error rate tester: capture data bus signals in real time, analyze eye diagrams, jitter and other indicators, and detect high-speed interface signal attenuation.

[0039] Environmental simulation module: integrated temperature control system (-40℃ to 150℃) and voltage disturbance device to simulate extreme conditions to verify chip stability.

[0040] Input module: Equipped with multi-modal interactive hardware (such as physical buttons, touch screen, voice commands and remote API interface), users can input test requirements through interactive hardware, and integrate barcode / RFID scanner to realize fast entry of chip information.

[0041] Display module: mainly used to display test results. It can adopt a multi-screen collaborative architecture. The main screen displays the signal waveform eye diagram, storage unit heat map and 3D error distribution model in real time, and the auxiliary screen presents the timing parameter curve and protocol decoding data. The test report can be exported as a visual chart (histogram, trend line) or standard document (PDF / CSV) with one click.

[0042] Exemplarily, the server may be one or more. When there are multiple servers, there are at least two servers for providing different services, and / or there are at least two servers for providing the same service, such as providing the same service in a load balancing manner, which is not limited in the embodiments of the present application. Among them, the above-mentioned server may be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. The server can also become a node of the blockchain.

[0043] In the embodiment of the present application, the storage chip testing device and the server may be directly or indirectly connected via wired communication or wireless communication, and the present application does not impose any limitation on this.

[0044] It should be noted that the implementation environment of the embodiments of the present application includes but is not limited to Figure 1 shown.

[0045] The following is an introduction to the read and write function testing method of the storage chip provided in the embodiment of the present application.

[0046] See also Figure 2 , is a flow chart of a method for testing the read and write functions of a memory chip provided in an embodiment of the present application. The method for testing the read and write functions includes the following steps S101-S104, which are described in detail below.

[0047] Step S101 : obtaining test requirements of a memory chip to be tested input by a user, where the test requirements at least include the following information: memory cell matrix parameters and data writing mode requirements of the memory chip to be tested.

[0048] Exemplarily, the test requirements input by the user are used to clarify the test scenario information of the memory chip to be tested, including the following key contents: (1) parameters of the memory chip to be tested, such as memory cell matrix parameters (such as 1024×1024), which are used to indicate the organization form of the memory cell matrix in the memory chip; (2) data writing mode, which is used to describe the mode of writing data to the memory chip during the test, such as all-0 mode, all-1 mode, and checkerboard mode.

[0049] Exemplarily, the test requirements may be input through an input module integrated in the storage chip test device (such as a physical button, a touch screen, a voice command, and a remote API interface).

[0050] Step S102: embed the test requirement into a preset prompt word template to obtain a test prompt word.

[0051] Exemplarily, the prompt word template may include at least one of the following: Test requirements: Test requirements for embedding user input; Processing prompt information: Processing prompt information required by the test; Test case examples: used to visually display the style and structure of test cases to ensure the standardization and accuracy of test case generation; Function template: includes some functions that may be used in test cases, such as chip definition function template, initialization test environment function template, write function template, read verification function template, output test result function template, etc.

[0052] In the embodiment of the present application, the test prompt words are used to guide the test case generation model to generate valid target test cases. Specifically, the test prompt words are used to clarify the test tasks and tell the model the tasks to be completed, such as "Please output the test cases based on the above test requirements", and provide context, including chip type, test write data mode, test report requirements and other detailed information.

[0053] Please refer to Figure 3 , is a schematic diagram of a test prompt word provided in an embodiment of the present application. Figure 3 The test prompts shown include: test requirements, processing prompts, test case examples, and function templates. Figure 3 In the example, the test requirements include the memory chip model, memory chip capacity (i.e., memory cell matrix parameters), test mode, and output test report requirements, among which the test mode gives the data writing mode requirement "checkerboard mode". The processing prompt message "Please output test cases based on the above test requirements" is used to indicate that the task that the test case generation model needs to perform is to output test cases based on the information required by the test. The test case example intuitively displays the target format and semantic specifications through structured instances, so that the model can accurately capture standardized elements, avoid format deviations and logical omissions, and ensure that the generated test cases can well inherit the style and comment format of the test case examples to ensure code readability. The function template contains a variety of function templates. The function template has a built-in parameterized code framework, which supports the model to quickly adapt the function skeleton according to the test requirements. The code in the test case can be generated by simply replacing the key variables in the template (such as the memory chip capacity).

[0054] Step S103: input the test prompt words into the trained test case generation model to obtain the target test case.

[0055] In the embodiment of the present application, the test case generation model can convert natural language prompts into high-precision, executable test cases, significantly improving test development efficiency and protocol coverage completeness.

[0056] For example, Figure 3 After the test prompt words shown are input into the test case generation model, the model can first parse the constraint information in the test requirements through the semantic understanding engine, deeply couple the standardized logical framework in the test case example (chip parameter definition-data mode writing-verification and error location-structured report output), follow the hierarchical and progressive code generation path, ensure the logical coherence between code levels without jumps, and strictly refer to the interface specifications and code style of the function template (such as parameterized encapsulation and exception handling nesting), which not only ensures the executable nature of the generated code (avoiding syntax / semantic errors), but also improves readability through comment insertion and modular splitting, and realizes the precise conversion from natural language description to industrial-grade test scripts.

[0057] Step S104, calling the target test case to execute the read and write function test process, wherein the read and write test process includes: writing data to the memory chip to be tested, reading data from the memory chip to be tested according to the storage cell matrix parameters and the data writing mode requirements, and generating a test report according to the comparison results of the written data and the read data.

[0058] In the embodiment of the present application, the test requirements of the memory chip to be tested input by the user will be embedded in the preset prompt word template, and the test prompt words including the storage unit matrix parameters and the data write mode requirements will be generated. Then, the test prompt words are input into the pre-trained test case generation model, and the model will automatically generate the corresponding target test case according to the storage unit matrix parameters and the data write mode requirements, so as to realize the automatic generation of the test case. By calling the generated target test case, the read-write function test process can be automatically executed, specifically including: according to the storage unit matrix parameters and the data write mode requirements, write data to the memory chip to be tested, then read data from the chip, and finally generate a test report by comparing the results of writing data and reading data. Based on the scheme of the embodiment of the present application, test cases can be automatically generated according to the test requirements, quickly adapt to various test scenarios, significantly reduce the time and economic cost of manually writing test cases, thereby greatly improving test efficiency.

[0059] In a possible implementation of the present application, a test prompt word is input into a trained test case generation model to obtain a target test case, which specifically includes the following steps: the test prompt word is input into the trained test case generation model so that the test case generation model generates a storage chip definition according to the storage cell matrix parameters, generates a write function and a read verification function according to the data write mode requirements, and generates a target test case according to the storage chip definition, the target write function and the target read verification function, wherein the write function and the read verification function both call the storage chip definition, the write function is used to perform a write data operation, and the read verification function is used to verify whether the data written to the storage chip meets the expected value, and outputs the verification result.

[0060] It can be understood that in order to realize the read and write test functions, the target test case includes storage chip definition, write function and read verification function. The write function and read verification function can call the variables in the storage chip definition so that the write data operation and read verification operation can adapt to the test requirements in the test prompt words.

[0061] In a possible implementation of the present application, the prompt word template includes: a write function template and a read verification function template corresponding to a preset data write mode. Exemplarily, the preset data write mode includes at least one of the following: all-0 mode, all-1 mode, checkerboard mode. That is to say, the prompt word template may include: all-0 mode write function template, all-0 mode read verification function template, all-1 mode write function template, all-1 mode read verification function template, checkerboard mode write function template, checkerboard mode read verification function template.

[0062] In a possible implementation of the present application, a write function and a read verification function are generated according to data write mode requirements, specifically including the following steps S301-S303: Step S301: selecting a target write function template from the write function templates according to the data write mode requirements, and selecting a target read verification function template from the read verification function templates; Step S302, generating a write function according to a target write function template; Step S303: Generate a read verification function according to the target read verification function template.

[0063] For example, in a scenario where the test requirements explicitly require the use of a checkerboard pattern to write data and verify the accuracy of memory chips, the test case generation model will execute the following optimization logic: First, based on the standardized framework of the test case example, the checkerboard pattern write function template and the checkerboard pattern read verification function template are selected as the basic templates; then, the storage cell matrix parameters provided in the test requirements are parsed, and the key variables in the template are replaced, such as replacing the "MEMORY_SIZE" variable in the template with 1024×1024, and the final test case is generated through the function template rewriting mechanism.

[0064] In a possible implementation of the present application, the test requirements also include the following information: test report requirements; the target test case includes: an output test result function, the output test result function is used to call the verification result output by the target reading verification function, and output the test report according to the verification result and test report requirements.

[0065] In a possible implementation of the present application, a test prompt word is input into a trained test case generation model to obtain a target test case, which specifically includes the following steps: the test prompt word is input into the trained test case generation model so that the test case generation model generates a storage chip definition according to the storage cell matrix parameters, generates a write function and a read verification function according to the data write mode requirements, and generates an output test result function according to the test report requirements, wherein the write function and the read verification function both call the storage chip definition, the write function is used to perform the write data operation, and the read verification function is used to verify whether the data written to the storage chip meets the expected value, and outputs the verification result; the output test result function is used to call the verification result output by the read verification function, and output the test report according to the verification result and the test report requirements.

[0066] Exemplarily, when the test requirements also include test report requirements, the test case generation model generates an output test result function based on the test report requirements. The output test result function calls the verification result output by the target reading verification function, and transforms the verification result according to the test report requirements to generate and output a test report.

[0067] In specific implementation, the test case generation model generates an output test result function based on the test report requirements, which can be achieved through the following steps: rewriting the output test result function provided by the test prompt word based on the test report requirements to obtain the output test result function.

[0068] In a possible implementation of the present application, the test requirements also include the following information: test environment conditions; the target test case includes: an initialization test environment function, the initialization test environment function is used to control the test equipment hardware so that the test environment meets the test environment conditions.

[0069] In a possible implementation of the present application, a test prompt word is input into a trained test case generation model to obtain a target test case, which specifically includes the following steps: the test prompt word is input into the trained test case generation model so that the test case generation model generates a storage chip definition according to the storage cell matrix parameters, generates an initialization test environment function according to the test environment conditions, generates a write function and a read verification function according to the data write mode requirements, and generates a target test case according to the storage chip definition, the initialization test environment function, the target write function and the target read verification function, wherein the initialization test environment function is used to control the test equipment hardware so that the test environment meets the test environment conditions, the write function and the read verification function both call the storage chip definition, the write function is used to perform a write data operation, and the read verification function is used to verify whether the data written to the storage chip meets the expected value, and outputs the verification result.

[0070] In a possible implementation of the present application, the prompt word template includes: an initialization test environment function template. Generating an initialization test environment function according to the test environment conditions specifically includes: setting the environment condition parameters in the initialization test environment function template according to the test environment conditions to obtain an initialization test environment function It can be understood that by configuring the initialization test environment function in the target test case, the configuration of the chip test environment conditions can be achieved.

[0071] For example, in the durability test scenario, the test requirements include: the chip operates at a rated voltage of 3.3V, in a high temperature environment of 100°C, and repeatedly writes data in a checkerboard pattern 1,000 times to verify data consistency. In specific implementation, the test cases can be constructed layer by layer through the initialization test environment function, the checkerboard pattern write function, the read verification function, the repeated write test function and the output test result function; the voltage variable in the initialization test environment function is set to 3.3V, and the temperature variable is set to 100℃, so as to use the initialization test environment function to control the environmental simulation module of the test equipment and implement the test environment adjustment; the chip size variable "MEMORY_SIZE" in the checkerboard pattern write function and the read verification function is set to the capacity of the current chip to be tested (such as 1024); the repeated write count variable in the repeated write test function is set to 1000, and the repeated write test function is used to repeatedly call the checkerboard pattern write function and the read verification function 1000 times to repeatedly write the checkerboard pattern data 1000 times, and verify the data consistency after each data write; the output test result function is used to output the results of the durability test, and its output content and output format can be defined in the test requirements.

[0072] In a possible implementation of the present application, the test case generation model is a language model. The language model may be a pre-trained language model, and then the pre-trained language model is fine-tuned so that the language model can adapt to the memory chip test case generation task.

[0073] Fine-tuning the language model can be achieved by following the steps below: (1) Construct training set and validation set: (1.1) Data collection: Collect data related to memory chip testing, including chip functional description, parameter specifications, existing test cases, etc. These data can be obtained from chip design documents, test case libraries written by test engineers, chip verification reports, etc. (1.2) Data preprocessing and annotation: (1.2.1) Preprocessing: Convert the test requirements (chip parameters and test modes) into natural language descriptions, standardize the test cases, and form standard test cases; (1.2.2) Build input-output mapping: Input sample: natural language statement containing chip parameters and test patterns; Output sample: standard test case; (1.2.3) Data enhancement: Expand data diversity through parameter perturbation, mode combination, etc.; (1.3) Dataset division: A stratified sampling strategy is used to divide the training set and validation set into a 7:3 ratio to maintain the distribution consistency of various test modes; (2) Model iterative optimization (2.1) Forward propagation: Input the input samples in the training set into the language model to obtain the predicted test cases output by the model; (2.2) Loss calculation: Use contrastive learning loss function to calculate the loss value of the predicted test case and the standard test case; (2.3) Back propagation: Calculate the gradient based on the loss value and optimize the model weights by back propagating the gradient; Repeat the above (2.1)-(2.3) until the model converges; (3) Model evaluation: Evaluate the performance of the model through the validation set, use appropriate evaluation indicators (such as accuracy, recall, etc.) to measure the quality of the model-generated test cases, and adjust the training parameters and model structure based on the evaluation results.

[0074] See also Figure 4 The present application also provides a device for testing the read and write functions of a memory chip, the device comprising: An acquisition module is used to acquire the test requirements of the memory chip to be tested input by the user, where the test requirements at least include the following information: memory cell matrix parameters and data writing mode requirements of the memory chip to be tested; A prompt word generation module is used to embed the test requirements into a preset prompt word template to obtain a test prompt word; A test case generation module is used to input the test prompt words into the trained test case generation model to obtain the target test case; The test module is used to call the target test case to execute the read and write function test process, wherein the read and write test process includes: writing data to the memory chip to be tested and reading data from the memory chip to be tested according to the storage cell matrix parameters and data writing mode requirements, and generating a test report based on the comparison results of the written data and the read data.

[0075] It should be noted that the information interaction, execution process, etc. between the above-mentioned modules / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0076] It should be noted that the device described in the embodiments of the present application is only schematic. For example, the division of units is only a logical function division. There may be other division methods in specific implementation scenarios. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some communication interface, device or unit, which can be electrical, mechanical or other forms.

[0077] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0078] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0079] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a processor-executable non-volatile computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium.

[0080] The method provided in the embodiment of the present application can automatically generate test cases according to test requirements, and has the following advantages: Improve efficiency: Automatically generating test cases can quickly respond to new test scenarios, reduce manual writing time, and improve testing efficiency.

[0081] Enhanced coverage: Automation tools can generate more test cases, covering more code paths and boundary conditions, and reducing omissions.

[0082] Reduce human errors: Automatic generation avoids errors in manual writing and improves the accuracy of test cases.

[0083] Support continuous integration: Automatically generated test cases can be quickly integrated into the CI / CD pipeline to ensure timely testing after each code change.

[0084] Cost savings: In the long run, automation reduces manpower input and reduces testing costs.

[0085] Adapt to changes: When requirements or code change frequently, automatic generation can quickly adjust test cases to maintain the timeliness of the test.

[0086] Support for complex scenarios: Automation tools can generate test cases for complex scenarios, covering situations that are difficult to simulate manually.

[0087] Improve maintainability: The automatically generated test cases have a consistent structure, making them easier to maintain and update.

[0088] Promote standardization: Test cases generated by automation tools follow unified standards, improving the consistency of the testing process.

[0089] In short, automatic generation of test cases can significantly improve test efficiency, coverage, and accuracy, while reducing costs and supporting continuous integration and complex scenario testing.

[0090] See also Figure 5 The embodiment of the present application further provides an electronic device, the electronic device 1100 comprising: at least one processor 1101; At least one memory 1102, used to store at least one program; At least one program is executed by at least one of the processors 1101 to implement the method described in any of the foregoing embodiments.

[0091] An embodiment of the present application also provides a computer program product, including a computer program or computer instructions, wherein the computer program or the computer instructions are stored in a computer-readable storage medium, a processor of an electronic device reads the computer program or the computer instructions from the computer-readable storage medium, and the processor executes the computer program or the computer instructions, so that the electronic device executes the method described in any of the aforementioned embodiments.

[0092] An embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the method described in any of the aforementioned embodiments.

[0093] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0094] In addition, the processor may include a central processing unit (CPU), a baseband processor, a digital signal processor (DSP), a microprocessor unit (MPU), a microcontroller unit (MCU), a graphics processor (GPU), a field programmable gate array (FPGA), an artificial intelligence processor (AI processor) or a neural network processor (NPU) One or more combinations thereof.

[0095] It should also be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0096] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When a computer instruction or computer program is loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instruction can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instruction can be transmitted from a website site, a computer, a server or a data center by wired or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or a data center containing one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0097] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0098] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0099] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0100] The unit described as a separate component may or may not be physically separated, and the component displayed as a unit may or may not be a physical unit, that is, it may be located in one place, or it may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, the functional units in each embodiment of the present application may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit. If the above functions are implemented in the form of software functional units and sold or used as independent products, they may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions for a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory, a random access memory, a disk or an optical disk.

[0101] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present application. These equivalent deformations or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A method for testing the read and write functions of a memory chip, characterized in that: The method comprises: Acquire the test requirements of the memory chip to be tested input by the user, wherein the test requirements at least include the following information: memory cell matrix parameters and data writing mode requirements of the memory chip to be tested; Embedding the test requirement into a preset prompt word template to obtain a test prompt word; Input the test prompt words into the trained test case generation model to obtain the target test case; The target test case is called to execute a read-write function test process, wherein the read-write test process includes: writing data to the memory chip to be tested, reading data from the memory chip to be tested according to the memory cell matrix parameters and the data writing mode requirements, and generating a test report based on the comparison results of the written data and the read data.

2. The method according to claim 1, characterized in that The step of inputting the test prompt words into a trained test case generation model to obtain a target test case comprises: The test prompt word is input into a trained test case generation model, so that the test case generation model generates a storage chip definition according to the storage cell matrix parameters, generates a write function and a read verification function according to the data write mode requirements, and generates the target test case according to the storage chip definition, the target write function and the target read verification function, wherein the write function and the read verification function both call the storage chip definition, the write function is used to perform a write data operation, and the read verification function is used to verify whether the data written to the storage chip meets the expected value, and outputs the verification result.

3. The method according to claim 2, characterized in that The prompt word template includes: a writing function template and a reading verification function template corresponding to a preset data writing mode; The step of generating a write function and a read verification function according to the data write mode requirement includes: Selecting a target write function template from the write function templates according to the data write mode requirement, and selecting a target read verification function template from the read verification function templates; Generate the write function according to the target write function template; The read verification function is generated according to the target read verification function template.

4. The method according to claim 3, characterized in that The preset data writing mode includes at least one of the following: all-0 mode, all-1 mode, and checkerboard mode.

5. The method according to claim 1, characterized in that The test requirements also include the following information: test report requirements; The step of inputting the test prompt words into a trained test case generation model to obtain a target test case comprises: The test prompt word is input into a trained test case generation model, so that the test case generation model generates a storage chip definition according to the storage cell matrix parameters, generates a write function and a read verification function according to the data write mode requirements, and generates an output test result function according to the test report requirements, wherein the write function and the read verification function both call the storage chip definition, the write function is used to perform a write data operation, and the read verification function is used to verify whether the data written to the storage chip meets the expected value, and outputs the verification result; the output test result function is used to call the verification result output by the read verification function, and output the test report according to the verification result and the test report requirements.

6. The method according to claim 1, characterized in that The test requirements also include the following information: test environment conditions; The step of inputting the test prompt words into a trained test case generation model to obtain a target test case comprises: The test prompt word is input into a trained test case generation model, so that the test case generation model generates a storage chip definition according to the storage cell matrix parameters, generates an initialization test environment function according to the test environment conditions, generates a write function and a read verification function according to the data write mode requirements, and generates the target test case according to the storage chip definition, the initialization test environment function, the target write function and the target read verification function, wherein the initialization test environment function is used to control the test equipment hardware so that the test environment meets the test environment conditions, the write function and the read verification function both call the storage chip definition, the write function is used to perform a write data operation, and the read verification function is used to verify whether the data written to the storage chip meets the expected value, and outputs the verification result.

7. The method according to claim 6, characterized in that The prompt word template includes: an initialization test environment function template; the initialization test environment function generated according to the test environment condition includes: The environment condition parameters in the initialization test environment function template are set according to the test environment conditions to obtain the initialization test environment function.

8. A read-write function test device for a memory chip, characterized in that: The device comprises: An acquisition module, used for acquiring the test requirements of the memory chip to be tested input by the user, wherein the test requirements at least include the following information: memory cell matrix parameters and data writing mode requirements of the memory chip to be tested; A prompt word generation module, used for embedding the test requirements into a preset prompt word template to obtain a test prompt word; A test case generation module, used for inputting the test prompt words into a trained test case generation model to obtain a target test case; A test module is used to call the target test case to execute a read and write function test process, wherein the read and write test process includes: writing data to the memory chip to be tested and reading data from the memory chip to be tested according to the storage cell matrix parameters and the data writing mode requirements, and generating a test report based on the comparison results of the written data and the read data.

9. An electronic device, characterized in that: include: at least one processor; at least one memory for storing at least one program; At least one program is executed by at least one of the processors to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute: the method according to any one of claims 1 to 7.

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