Memory system, operating method, electronic device, and computer readable storage medium

Abstract

The invention provides a memory system, an operation method, electronic equipment and a computer readable storage medium. The memory system comprises a memory device and a memory controller coupled with the memory device, the memory device includes a plurality of first sub-regions storing mapping data; the memory controller is coupled with a host; the host comprises a plurality of second sub-regions corresponding to the plurality of first sub-regions; the mapping data comprises a mapping relation from a logic address to a physical address; the ranges of logic addresses of the mapping data stored in the first sub-region and the second sub-region which correspond to each other are the same; the memory controller is configured to: divide the first sub-region into a plurality of data units; when the mapping data in the data unit is changed, marking the data unit; and determining whether to trigger updating of mapping data in a second sub-region corresponding to the first sub-region or not based on the number of the marked data units in the first sub-region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory system and operating method, an electronic device, and a computer-readable storage medium. Background Art

[0002] With the rapid development of data storage technology, more and more data storage systems appear in electronic devices used by people, such as Secure Digital Memory Card (SD card), Universal Flash Storage (UFS), Solid State Drives (SSD), etc. In order to further optimize the performance of the memory system, how to achieve random reading and improve reading efficiency has become a problem that needs to be solved urgently. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a memory system and operating method, an electronic device, and a computer-readable storage medium to solve at least one problem existing in the prior art.

[0004] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a memory system, the memory system comprising a memory device and a memory controller coupled to the memory device; the memory device comprising a plurality of first sub-regions storing mapping data; the memory controller is coupled to a host; the host comprises a plurality of second sub-regions corresponding to the plurality of first sub-regions; the mapping data comprises a mapping relationship from a logical address to a physical address; the logical address range of the mapping data stored in the first sub-region and the second sub-region corresponding to each other is the same; the memory controller is configured as follows:

[0006] Dividing the first sub-area into a plurality of data units;

[0007] When the mapping data in the data unit changes, marking the data unit;

[0008] Whether to trigger updating of mapping data in the second sub-region corresponding to the first sub-region is determined based on the number of marked data units in the first sub-region.

[0009] In an optional implementation manner, the memory controller is specifically configured as follows:

[0010] Establishing a bitmap of the first sub-region, wherein a bit in the bitmap corresponds to a data unit in the first sub-region, so as to divide the first sub-region into a plurality of data units;

[0011] When a physical address corresponding to at least one logical address in the data unit changes, a bit corresponding to the data unit is marked in the bitmap to mark the data unit.

[0012] In an optional implementation manner, the memory controller is specifically configured as follows:

[0013] When the number of the marked data units in the first sub-region is greater than or equal to an update threshold, determining to trigger an update of mapping data in the second sub-region corresponding to the first sub-region;

[0014] When the number of the marked data units in the first sub-region is less than the update threshold, it is determined not to trigger the update of the mapping data in the second sub-region corresponding to the first sub-region.

[0015] In an optional implementation, the memory controller is further configured to:

[0016] Receive read command packet;

[0017] When the read command packet includes mapping data in the second sub-region, acquiring the number of the marked data units in the first sub-region corresponding to the second sub-region;

[0018] In response to determining that an update of mapping data in the second sub-region corresponding to the first sub-region is triggered, a message recommending an update of the second sub-region is sent.

[0019] In an optional implementation, the memory controller is further configured to:

[0020] When the logical address of the mapping data in the read command packet is within the logical address range of the mapping data stored in the marked data unit, acquiring a physical address corresponding to the logical address from the first sub-area and performing a read operation;

[0021] When the logical address of the mapping data in the read command packet is not within the logical address range of the mapping data stored in the marked data unit, a read operation is performed based on the physical address in the read command packet.

[0022] In an optional implementation, the memory controller is further configured to:

[0023] In response to determining to update the mapping data in the second sub-region, the mapping data stored in the first sub-region corresponding to the second sub-region is sent.

[0024] In an optional implementation manner, the number of the data units in the first sub-area ranges from 8 to 1024; and the ratio of the update threshold to the number of the data units in the first sub-area ranges from 25% to 75%.

[0025] In a second aspect, an embodiment of the present disclosure provides an operating method of a memory system, including:

[0026] dividing a first sub-region storing mapping data in the memory device into a plurality of data units;

[0027] When mapping data in the data unit changes, marking the data unit; the mapping data includes a mapping relationship from a logical address to a physical address;

[0028] Based on the number of marked data units in the first sub-area, determine whether to trigger the update of mapping data in the second sub-area corresponding to the first sub-area in the host; the logical address range of the mapping data stored in the first sub-area and the second sub-area corresponding to each other is the same.

[0029] In an optional implementation, dividing the first sub-region storing the mapping data in the memory device into a plurality of data units and marking the data units comprises:

[0030] Establishing a bitmap of the first sub-region, wherein a bit in the bitmap corresponds to a data unit in the first sub-region, so as to divide the first sub-region into a plurality of data units;

[0031] When a physical address corresponding to at least one logical address in the data unit changes, a bit corresponding to the data unit is marked in the bitmap to mark the data unit.

[0032] In an optional implementation, the determining whether to trigger updating of mapping data in a second sub-area corresponding to the first sub-area in the host based on the number of marked data units in the first sub-area includes:

[0033] When the number of the marked data units in the first sub-region is greater than or equal to an update threshold, determining to trigger an update of mapping data in the second sub-region corresponding to the first sub-region;

[0034] When the number of the marked data units in the first sub-region is less than the update threshold, it is determined not to trigger the update of the mapping data in the second sub-region corresponding to the first sub-region.

[0035] In an optional implementation, the operation method further includes:

[0036] Receive read command packet;

[0037] When the read command packet includes mapping data in the second sub-region, acquiring the number of the marked data units in the first sub-region corresponding to the second sub-region;

[0038] In response to determining that an update of mapping data in the second sub-region corresponding to the first sub-region is triggered, a message recommending an update of the second sub-region is sent.

[0039] In an optional implementation, the operation method further includes:

[0040] When the logical address of the mapping data in the read command packet is within the logical address range of the mapping data stored in the marked data unit, acquiring a physical address corresponding to the logical address from the first sub-area and performing a read operation;

[0041] When the logical address of the mapping data in the read command packet is not within the logical address range of the mapping data stored in the marked data unit, a read operation is performed based on the physical address in the read command packet.

[0042] In an optional implementation, the operation method further includes:

[0043] In response to determining to update the mapping data in the second sub-region, the mapping data stored in the first sub-region corresponding to the second sub-region is sent.

[0044] In a third aspect, an embodiment of the present disclosure provides an electronic device, the electronic device comprising a memory system and a host coupled to the memory system; the memory system comprising a memory device and a memory controller coupled to the memory device; the memory device comprising a plurality of first sub-regions storing mapping data; the host comprising a host controller and a plurality of second sub-regions corresponding to the plurality of first sub-regions; the mapping data comprising a mapping relationship from a logical address to a physical address; the first sub-region and the second sub-region corresponding to each other storing the same range of logical addresses of the mapping data; the memory controller being configured as follows:

[0045] Dividing the first sub-area into a plurality of data units;

[0046] When the mapping data in the data unit changes, marking the data unit;

[0047] determining whether to trigger updating of mapping data in the second sub-region corresponding to the first sub-region based on the number of marked data units in the first sub-region;

[0048] In response to determining that an update of mapping data in the second sub-region corresponding to the first sub-region is triggered, sending a message recommending an update of the second sub-region;

[0049] The host controller is configured to:

[0050] A message recommending updating the second sub-area is received, and it is determined whether to update mapping data in the second sub-area.

[0051] In an optional implementation manner, the memory controller is specifically configured as follows:

[0052] Establishing a bitmap of the first sub-region, wherein a bit in the bitmap corresponds to a data unit in the first sub-region, so as to divide the first sub-region into a plurality of data units;

[0053] When a physical address corresponding to at least one logical address in the data unit changes, a bit corresponding to the data unit is marked in the bitmap to mark the data unit.

[0054] In an optional implementation manner, the memory controller is specifically configured as follows:

[0055] When the number of the marked data units in the first sub-region is greater than or equal to an update threshold, determining to trigger an update of mapping data in the second sub-region corresponding to the first sub-region;

[0056] When the number of the marked data units in the first sub-region is less than the update threshold, it is determined not to trigger the update of the mapping data in the second sub-region corresponding to the first sub-region.

[0057] In an optional implementation, the host controller is further configured to:

[0058] Sending a read command packet to the memory controller;

[0059] The memory controller is further configured to:

[0060] The read command packet is received, and when the read command packet includes mapping data in the second sub-region, the number of the marked data units in the first sub-region corresponding to the second sub-region is acquired.

[0061] In an optional implementation, the memory controller is further configured to:

[0062] In response to the host controller determining to update the mapping data in the second sub-area, sending the mapping data stored in the first sub-area corresponding to the second sub-area;

[0063] The host controller is further configured to:

[0064] The mapping data stored in the first sub-region is received, and the mapping data in the second sub-region corresponding to the first sub-region is updated.

[0065] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the operating method described in any of the above embodiments is performed.

[0066] In the technical solution provided by the embodiment of the present disclosure, the memory device of the memory system includes a first sub-region for storing mapping data, and the host includes a second sub-region for storing mapping data. The first sub-region and the second sub-region correspond to each other one by one, and the range of logical addresses of the mapping data stored in the first sub-region and the second sub-region corresponding to each other is the same. The memory controller can divide the first sub-region into multiple data units by establishing a bitmap, and mark the validity of the mapping data in the bitmap in units of data units, and determine whether to trigger the update of the mapping data of the second sub-region corresponding to the first sub-region based on the number of marked data units. On the one hand, the memory controller can mark the validity of the mapping data in units of smaller granularity, thereby improving the accuracy of validity management; on the other hand, the memory controller can adjust the frequency of updating the second sub-region by setting an update threshold, so as to balance the degree of occupation of system resources and the degree of influence on the performance of random read operations, so as to achieve the purpose of improving the overall performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 A schematic diagram of an exemplary system having a memory system provided for an embodiment of the present disclosure;

[0068] Figure 2 A schematic diagram of an exemplary memory card having a memory system provided for an embodiment of the present disclosure;

[0069] Figure 3 A schematic diagram of an exemplary solid state drive having a memory system provided for an embodiment of the present disclosure;

[0070] Figure 4 A schematic diagram of an exemplary memory device including peripheral circuits provided for an embodiment of the present disclosure;

[0071] Figure 5 A cross-sectional schematic diagram of a memory array including memory strings provided for an embodiment of the present disclosure;

[0072] Figure 6 A schematic diagram of an exemplary memory device including a memory array and peripheral circuits provided for an embodiment of the present disclosure;

[0073] Figure 7 A schematic diagram of a system including a host and a memory system provided for an embodiment of the present disclosure;

[0074] Figure 8 A schematic diagram of a bitmap provided for a specific example of the present disclosure;

[0075] Fig. 9 A schematic diagram of a framework flow of a read operation provided for a specific example of the present disclosure;

[0076] Fig.10 A schematic diagram of a framework flow of effectiveness management operations provided for a specific example of the present disclosure;

[0077] Fig.11 A flowchart of an operating method of a memory system provided for a specific example of the present disclosure. DETAILED DESCRIPTION

[0078] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0079] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0080] In the drawings, like reference numerals refer to like elements throughout.

[0081] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0082] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0083] The memory system in the embodiments of the present disclosure includes but is not limited to a memory system including a three-dimensional NAND memory. For ease of understanding, the memory system provided by the present disclosure is described by taking the memory system including a three-dimensional NAND memory as an example.

[0084] Figure 1 Schematic diagram of an exemplary system with a memory system provided for an embodiment of the present disclosure. In the embodiment of the present disclosure, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1As shown in , the system 100 may include a host device 101 and a memory system 102, and the memory system 102 may include one or more memory devices 103 and a memory controller 104. The host device 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host device 101 may be configured to send data to the memory system 102 or receive data from the memory system 102.

[0085] In some embodiments, the memory controller 104 is coupled to the memory device 103 and the host device 101, and is configured to control the memory device 103. The memory controller 104 can manage the data stored in the memory device 103 and communicate with the host device 101. In some embodiments, the memory controller 104 is designed to operate in a low duty cycle environment, such as in a secure digital card, a compact flash card (Compact Flash Card, CFC), a universal serial bus (Universal Serial BUS, USB) flash drive, or in other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In other embodiments, the memory controller 104 is designed to operate in a high duty cycle environment, such as a solid state drive or an embedded multimedia card (EmbeddedMulti-MediaCard, eMMC).

[0086] In some embodiments, the memory controller 104 and the one or more memory devices 103 may be integrated into various types of storage devices, that is, the memory system 102 may be implemented and packaged into different types of terminal electronic products.

[0087] In such Figure 2 In one example shown in , the memory controller 104 and the single memory device 103 can be integrated into the memory card 201. The memory card 201 can be a compact flash card, a smart media card (Smart Media Card, SMC), a memory stick (Memory Stick, MS), a multimedia card (Multi-Media Card, MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card, such as Mini SD card, Micro SD card, SDHC card, etc., or a universal flash card. The memory card 201 can also include a device that connects the memory card 201 to a host device (e.g., Figure 1The host device 101 in the embodiment of the present invention is coupled to the memory card connector 202. Figure 3 In another example shown in , the memory controller 104 and the plurality of memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include a processor that connects the SSD 203 to a host device (eg, Figure 1 In some embodiments, the storage capacity and / or operating speed of SSD203 is greater than the storage capacity and / or operating speed of memory card 201.

[0088] Figure 4 A circuit diagram of an exemplary memory device 300 including peripheral circuits provided for an embodiment of the present disclosure. The memory device 300 may be Figure 1 300 is an example of a memory device 103 in FIG. The memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301. The memory array 301 is taken as a three-dimensional NAND type memory array for illustration, wherein the memory cells 305 are NAND memory cells, and the memory cells 305 are provided in the form of an array of memory strings 304, each memory string 304 extending vertically above a substrate (not shown). In some embodiments, each memory string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 305. Each memory cell 305 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0089] In some embodiments, each memory cell 305 is a single level cell (SLC) having two possible memory states and thus can store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, for example, a multi-level cell (MLC) storing two bits per cell, a triple level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0090] like Figure 4As shown in , each memory string 304 may include a bottom select transistor (BST) 307 at its source terminal and a top select transistor (TST) 306 at its drain terminal. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory string 304 during read and program operations. In some embodiments, the sources of the memory strings 304 in the same memory block 303 may be coupled through a common source line (CSL) 310. In other words, all memory strings 304 in the same memory block 303 have a common source (Array Common Source, ACS). According to some embodiments, the top select transistor 306 of each memory string 304 is coupled to a corresponding bit line (BL) 311, and data can be read or written from the bit line 311 via an output bus (not shown). In some embodiments, each memory string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the upper selection tube 306) or a deselection voltage (e.g., 0V) to the corresponding upper selection tube 306 through one or more top selection lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the lower selection tube 307) or a deselection voltage (e.g., 0V) to the corresponding lower selection tube 307 through one or more bottom selection lines (BSL) 309.

[0091] like Figure 4 As shown in , the memory string 304 can be organized into a plurality of memory blocks 303, each of which can have a common source line 310. In some embodiments, each memory block 303 is a basic data unit for an erase operation, that is, all memory cells 305 on the same memory block 303 are erased at the same time. In order to erase the memory cells 305 in a selected memory block, a common source line 310 coupled to the selected memory block and the unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage. It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 305 of adjacent memory strings 304 can be coupled by word lines 312, which select which row of memory cells 305 is affected by a read or programming operation.

[0092] Figure 5 A cross-sectional schematic diagram of a memory array including memory strings provided in an embodiment of the present disclosure. Figure 5As shown, the memory array may include a stacked structure 400, which includes a plurality of gate layers 401 and a plurality of insulating layers 402 that are alternately stacked in sequence, and a channel structure 403 that vertically penetrates the gate layers 401 and the insulating layers 402. The gate layers 401 and the insulating layers 402 may be alternately stacked, and two adjacent gate layers 401 are separated by an insulating layer 402. The number of memory cells included in the memory array is mainly related to the number of pairs of gate layers 401 and insulating layers 402 in the stacked structure 400.

[0093] The constituent material of the gate layer 401 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 401 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 401 includes a doped polysilicon layer. Multiple gate layers 401 surround a channel structure 403 to form a memory string. The gate layer 401 at the top of the stacked structure 400 can extend laterally as an upper selection gate line, the gate layer 401 at the bottom of the stacked structure 400 can extend laterally as a lower selection gate line, and the gate layer 401 extending laterally between the upper selection gate line and the lower selection gate line can serve as a word line layer.

[0094] In some embodiments, the stacked structure 400 may be disposed on a substrate 404. The substrate 404 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0095] It should be noted that, in some other embodiments, the memory array may only include the stacked structure 400 but not a substrate, and the present disclosure does not limit whether the memory array includes a substrate.

[0096] In some embodiments, the channel structure 403 includes a functional layer, a channel layer, and an insulating filling layer. In some embodiments, the channel layer includes silicon, for example, polycrystalline silicon. In some embodiments, the functional layer is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge capture / storage layer"), and a barrier layer. The channel structure 403 may have a cylindrical shape (e.g., a column shape). According to some embodiments, the channel layer, the tunneling layer, the storage layer, and the barrier layer are radially arranged in this order from the center of the column toward the outer surface of the column. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the functional layer may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0097] Return to reference Figure 4 , the peripheral circuit 302 may be coupled to the memory array 301 through the bit line 311, the word line 312, the common source line 310, the lower selection line 309, and the upper selection line 308. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for applying a voltage signal and / or a current signal to each target memory cell 305 through the bit line 311, the word line 312, the common source line 310, the lower selection line 309, and the upper selection line 308, and sensing a voltage signal and / or a current signal from each target memory cell 305 to implement the operation of the memory array 301. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor technology. For example, Figure 6 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 501, a column decoder / bit line driver 502, a row decoder / word line driver 503, a voltage generator 504, a control logic unit 505, a register 506, a flash memory interface 507, and a data bus 508. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 6 Additional peripheral circuits not shown.

[0098] The page buffer / sense amplifier 501 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to a control signal from the control logic unit 505. In one example, the page buffer / sense amplifier 501 can store a page of programming data (write data) to be programmed into the memory array 301. In another example, the page buffer / sense amplifier 501 can perform a programming verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer / sense amplifier 501 can also sense a low-power signal from a bit line representing a data bit stored in a memory cell, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 502 can be configured to be controlled by the control logic unit 505, and select one or more memory strings by applying a bit line voltage generated from the voltage generator 504.

[0099] The row decoder / word line driver 503 may be configured to be controlled by the control logic unit 505, and select / deselect a memory block of the memory array 301 and select / deselect a word line of the memory block. The row decoder / word line driver 508 may also be configured to drive a word line using a word line voltage generated from the voltage generator 504. In some embodiments, the row decoder / word line driver 503 may also select / deselect and drive a lower selection line and an upper selection line. As described in detail below, the row decoder / word line driver 503 is configured to perform a programming operation on a memory cell coupled to (one or more) selected word lines. The voltage generator 504 may be configured to be controlled by the control logic unit 505, and generate a word line voltage (e.g., a read voltage, a programming voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 301.

[0100] The control logic unit 505 may be coupled to each peripheral circuit described above, and is configured to control the operation of each peripheral circuit. The register 506 may be coupled to the control logic unit 505, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The flash memory interface 507 may be coupled to the control logic unit 505, and act as a control buffer to buffer control commands received from a host-side device (not shown) and relay them to the control logic unit 505, and to buffer status information received from the control logic unit 505 and relay them to the memory controller. The flash memory interface 507 may also be coupled to the column decoder / bit line driver 502 via the data bus 508, and act as a data I / O interface and a data buffer to buffer data and relay them to the memory array 301 or relay or buffer data from the memory array 301.

[0101] Figure 7 A schematic diagram of a system including a host and a memory system provided in an embodiment of the present disclosure is shown in FIG. Figure 7 As shown, the memory system 600 includes a memory controller 601 and a memory device 602. The memory controller 601 is used to control the memory device 602 to perform read and write operations. Here, the memory controller 601 and the memory device 602 can be coupled in any suitable manner. The memory controller 601 includes a control unit 605, a data buffer 607, a host I / F interface 606, a memory I / F interface 609, etc. The memory device 602 may include Figures 4 to 6 The three-dimensional NAND type memory shown.

[0102] In some embodiments, the host I / F interface 606 outputs commands, valid data (write data), etc. received from the host 700 to the internal bus 610, and sends valid data (read data) read from the memory device 602, responses from the control unit 605, etc. to the host 700. The memory I / F interface 609 controls the process of writing data, etc. to the memory device 602 and the process of reading data from the memory device 602 based on the instructions of the control unit 605. The control unit 605 controls the memory system 600 as a whole, and the control unit 605 is, for example, a central processing unit, a microprocessor unit (MPU), etc. When the control unit 605 receives a command from the host 700 via the host I / F interface 606, it performs control according to the command. For example, the control unit 605 instructs the memory I / F interface 609 to write data to the memory device 602 according to the command from the host 700. In addition, the control unit 605 instructs the memory I / F interface 609 to read data from the memory device 602 according to the command from the host 700.

[0103] In some embodiments, the memory controller 601 is configured to perform mapping management on the data stored in the memory device 602. Specifically, the memory controller can update and maintain a logical address to physical address (Logical address To Physical address, L2P) mapping table, i.e., an L2P table. Each L2P entry in the L2P table can represent a mapping relationship between a logical address and a physical address. When the host 700 sends a read command including a logical address to the memory controller 601, the memory controller 601 can obtain the corresponding physical address based on the L2P table and the logical address in the read command, and read the data from the memory device 602 according to the physical address and send it to the host 700.

[0104] In some embodiments, the memory controller 601 includes a data buffer 607, which may include but is not limited to a static random access memory (SRAM). At the same time, the memory system 600 also includes a memory for storing the L2P table, such as a dynamic random access memory (DRAM). The memory controller 601 can quickly obtain the L2P table from the DRAM, thereby achieving higher reading efficiency.

[0105] In other embodiments, DRAM may not be set as a cache space in the memory system 600 due to considerations of package size, power consumption, and cost. In this case, since the storage space in the memory controller 601 is limited, the memory controller 601 is configured to store the L2P table, which is a secondary mapping table and occupies a large storage space, in the mapping data storage area 603 of the memory device 602, and only store the primary mapping table, which occupies a small storage space, in the data buffer 607. When the memory controller 601 receives a read command packet including a read command and a logical address, the memory controller 601 may obtain the storage location of the L2P table to be used in the memory device 602 according to the primary mapping table, and read the part of the L2P table to be used from the memory device 602, and then obtain the physical address according to the logical address and the read part of the L2P table and perform a read operation, that is, two read operations are required to read the data, resulting in low efficiency of the read operation, especially for random read operations, one random read operation may require a large number of L2P tables to be read from the memory device 602, resulting in poor performance of the random read operation.

[0106] In some embodiments, continue to refer to Figure 7 In order to solve the problems of low read operation efficiency and poor random read operation performance in the above embodiments, a system architecture including a host performance booster (HPB) 701 is proposed. Specifically, part of the storage space in the host 700 can be divided into the host performance booster 701 as a cache space for mapping data, and the memory controller 601 can send part of the mapping data to the host 700, and the host 700 can cache the mapping data in the host performance booster 701. Here, the mapping data includes an L2P table. Therefore, the host 700 can send an HPB read command packet to the memory system 600 to read data. The HPB read command packet can include the physical address of the data to be read by the host 700, and the physical address can be obtained according to the mapping data cached in the host performance booster 701. The memory controller 601 can directly read the data from the memory device 602 according to the physical address in the HPB read command packet, without reading the mapping data from the memory device 602, thereby effectively improving the efficiency of the read operation and improving the performance of the random read operation.

[0107] However, after the memory system 600 performs background operations such as garbage collection, the mapping relationship between the logical address and the physical address may change and the mapping data needs to be updated. When the mapping data stored in the memory device 602 and cached in the host performance enhancer 701 is updated, the mapping data stored in the host performance enhancer 701 will become invalid. Therefore, the mapping data in the host performance enhancer 701 also needs to be updated. When the mapping data in the host performance enhancer 701 is updated frequently, it may have a negative impact on the performance of the system. When the mapping data cannot be updated in time, the HPB read operation cannot be performed, thereby reducing the performance of random read operations. Therefore, it is necessary to optimize the update trigger mechanism of the mapping data in the host performance enhancer to improve the overall performance of the system. In this regard, the present disclosure proposes the following implementation methods.

[0108] The present disclosure provides a memory system. Figure 7 As shown, the memory system 600 includes a memory device 602 and a memory controller 601 coupled to the memory device 602, and the memory controller 601 is coupled to the host 700; the memory device 602 includes a plurality of first sub-areas 604 for storing mapping data, and the host 700 includes a plurality of second sub-areas 702 corresponding to the plurality of first sub-areas 604.

[0109] It should be noted that, under the HPB system architecture, the logical address space can be divided into multiple HPB areas, each HPB area can be divided into multiple HPB sub-areas, each HPB sub-area stores multiple L2P entries, and the mapping data can be cached in the host performance enhancer 701 in units of HPB sub-areas. The HPB sub-areas that have been cached in the host performance enhancer 701 are activated HPB sub-areas.

[0110] In the embodiment of the present disclosure, the first sub-region 604 is an activated HPB sub-region in the memory device 602, that is, the first sub-region 604 may be only a part of the mapped data storage region 603, and the mapped data storage region 603 also includes an unactivated HPB sub-region. The mapping data in the second sub-region 702 in the host performance enhancer 701 corresponds to the mapping data in the activated HPB sub-region, that is, the first sub-region 604 and the second sub-region 702 correspond one-to-one, and the logical address range of the mapping data stored in the first sub-region 604 and the second sub-region 702 corresponding to each other is the same.

[0111] It should be noted that Figure 7 The numbers of the first sub-regions 604 and the second sub-regions 702 shown in FIG. 7 are only examples, and the present disclosure does not limit the specific numbers of the first sub-regions 604 and the second sub-regions 702 .

[0112] In the embodiment of the present disclosure, the mapping data includes a mapping relationship from a logical address to a physical address. The logical address may be a logical block address (LBA), and the physical address may be a physical block address (PBA). The physical block address of the data corresponds to the location of the storage block where the data is located in the memory device 602.

[0113] In some embodiments, the memory controller 601 is configured to: divide the first sub-region 604 into multiple data units; mark the data unit when the mapping data in the data unit changes; and determine whether to trigger an update of the mapping data in the second sub-region 702 corresponding to the first sub-region 604 based on the number of marked data units in the first sub-region 604.

[0114] In some embodiments, the memory controller 601 is specifically configured to: establish a bit map of the first sub-region 604, where a bit in the bit map corresponds to a data unit in the first sub-region 604, so as to divide the first sub-region 604 into a plurality of data units.

[0115] In some embodiments, Figure 7 As shown, the data buffer 607 in the memory controller 601 may include a bitmap storage area 608 , and the bitmap of the first sub-area 604 may be stored in the bitmap storage area 608 in the data buffer 607 .

[0116] In some specific examples, the number of data units in a first sub-region 604 ranges from 8 to 1024.

[0117] Figure 8 A bitmap provided for a specific example of the present disclosure, such as Figure 8 As shown, a bitmap of a first sub-region 604 may include 32 bits, and one bit corresponds to one data unit, so that a first sub-region 604 may be divided into 32 data units.

[0118] In some specific examples, each data unit in the first sub-area 604 has the same size, that is, the first sub-area 604 can be equally divided into a plurality of data units, and the size of the mapped data storage space of each data unit is the same.

[0119] In a specific example, when the size of the first sub-region 604 is 16 MB and one first sub-region 604 is divided into 32 data units, the size of each data unit is 512 KB.

[0120] In some embodiments, the mapping data includes multiple L2P entries, and each L2P entry has the same size. After the first sub-region 604 is equally divided into multiple data units, the number of L2P entries in each data unit is the same, and for the L2P entries in the first sub-region 604, the logical addresses are continuous. Therefore, the range of the logical address of the mapping data in each data unit can be determined based on the starting logical address of the mapping data in the first sub-region 604 and the number of L2P entries in each data unit. When the physical address corresponding to the logical address in an L2P entry changes, the first sub-region 604 and the data unit to which the L2P entry belongs can be determined based on the logical address in the L2P entry.

[0121] In some embodiments, when the mapping data in the first sub-area 604 is cached in the host performance enhancer 701, the memory controller 601 may set each bit position in the bitmap of the first sub-area 604 to 0, indicating that the mapping data in the first sub-area 604 is the same as the mapping data in the second sub-area 702, and the mapping data in the second sub-area 702 is valid. In this case, when the host 700 sends an HPB read command packet including a physical address according to the mapping data in the second sub-area 702, the memory controller 601 may directly read data from the memory device 602 according to the physical address in the HPB read command packet, that is, may perform an HPB read operation.

[0122] It is understandable that the memory controller 601 can perform background operations of changing mapping data without a request from the host 700. For example, the memory controller 601 can perform background operations such as garbage collection operations, data migration operations of the SLC buffer, read recovery operations, and wear leveling operations without a request from the host 700. Among them, the garbage collection operation can be an operation of moving valid data stored in a sacrifice block (containing valid data and invalid data) to a free block as a target block and erasing the sacrifice block; the data migration operation of the SLC buffer can be an operation of migrating data stored in an SLC block in the memory device 602 and writing it to an MLC block, a TLC block, or a QLC block; the read recovery operation can be an operation of rewriting data of a storage block whose threshold voltage distribution has deteriorated due to repeated read operations to another storage block; and the wear leveling operation can be an operation of moving data between storage blocks in the memory device 602 to achieve uniform use of storage blocks. The above-mentioned background operations will all change the physical address of the data. After the physical address of the data is changed, the mapping relationship between the logical address and the physical address will also change accordingly. If the logical address is within the logical address range of the mapping data in the first sub-area 604, the mapping data in the first sub-area 604 needs to be updated. In this case, the mapping data in the first sub-area 604 and the corresponding mapping data in the second sub-area 702 will no longer be the same. Specifically, the physical address corresponding to the same logical address will be different, causing the mapping data in the second sub-area 702 to become invalid.

[0123] In some embodiments, the memory controller 601 is specifically configured to: when the physical address corresponding to at least one logical address in the data unit changes, mark the bit corresponding to the data unit in the bitmap to mark the data unit. Specifically, when the physical address corresponding to a logical address changes, the memory controller 601 can first determine the data unit to which the L2P entry corresponding to the logical address belongs, and flip the bit corresponding to the data unit in the bitmap, such as from 0 to 1, to mark the data unit. In this case, when the host 700 sends an HPB read command packet including mapping data according to the mapping data in the second sub-area 702, if the logical address of the mapping data in the HPB read command packet is within the logical address range of the mapping data stored in the marked data unit, the mapping data is invalid, and the memory controller 601 needs to obtain the mapping data from the first sub-area 604 to obtain the physical address corresponding to the logical address, and perform a read operation, that is, perform a normal read operation.

[0124] In a specific example, if Figure 8As shown, in the bitmap of the first sub-area 604, the bits corresponding to data unit 5 and data unit 7 are 1, and the bits corresponding to other data units are 0, indicating that data unit 5 and data unit 7 are marked due to changes in mapping data. When the read command packet includes mapping data stored in the second sub-area 702, and the logical address of the mapping data is within the logical address range of the mapping data in the marked data unit 5 and data unit 7, the mapping data in the read command packet is invalid, and the memory controller 601 needs to perform a normal read operation; and when the logical address of the mapping data is within the logical address range of the mapping data of other unmarked data units, the mapping data in the read command packet is valid, and the memory controller 601 can perform an HPB read operation.

[0125] In some other embodiments, "1" may be used in the bitmap to indicate that the mapping data of the data unit corresponding to the bit position has not changed, and "0" may be used to indicate that the data unit corresponding to the bit position has been marked due to a change in the mapping data.

[0126] In some specific examples, the memory controller 601 is configured to perform the following Fig. 9 Specifically, the memory controller 601 is configured to: execute step S1001 to receive a read command packet. Here, the read command packet may include a read command and address information of the data, and the read command may include a normal read command and an HPB read command. When the read command is a normal read command, the address information of the data only includes the logical address of the data, and when the read command is an HPB read command, the address information of the data may include the mapping data stored in the second sub-area 702, that is, the address information of the data includes both the logical address of the data and the physical address of the data.

[0127] The memory controller 601 is further configured to: execute step S1002 to determine whether the read command in the read command packet is a normal read command; if the read command is a normal read command, execute step S1007 to perform a normal read operation; if the read command is not a normal read command, execute step S1003 to determine whether the read command is a HPB read command; if the read command is a HPB read command, execute step S1004 to obtain mapping data in the read command packet.

[0128] The memory controller 601 is further configured to: execute step S1005 to determine whether the mapping data is valid, and the specific process may include: determining whether the logical address of the mapping data is within the range of the logical address of the mapping data stored in the marked data unit. When the logical address of the mapping data in the read command packet is within the range of the logical address of the mapping data stored in the marked data unit, the physical address corresponding to the logical address of the mapping data in the first sub-area 604 may have changed, and the mapping data is invalid, then execute step S1007 to perform a normal read operation, that is, obtain the physical address corresponding to the logical address in the read command packet from the first sub-area 604 and perform a read operation; when the logical address of the mapping data in the read command packet is not within the range of the logical address of the mapping data stored in the marked data unit, the mapping data is valid, then execute step S1008 to perform an HPB read operation, that is, perform a read operation based on the physical address in the read command packet.

[0129] In the disclosed embodiment, the mapping data is judged to be invalid only when the logical address of the mapping data in the HPB read command packet is within the logical address range of the mapping data stored in the marked data unit, that is, for multiple data units in a first sub-area 604, the marking of one or more data units does not affect the validity of the mapping data in other unmarked data units.

[0130] In a specific example, the memory controller 601 is configured to perform the following Fig.10 Specifically, the memory controller 601 is configured to: execute step S2001 to receive a read command packet; execute step S2002 to determine whether the read command includes the mapping data stored in the second sub-area 702, and when the read command packet includes the mapping data stored in the second sub-area 702, execute step S2003 to obtain the number of marked data units in the first sub-area 604 corresponding to the second sub-area 702.

[0131] Here, when the read command packet received by the memory controller 601 includes mapping data in the second sub-region 702, that is, when the read command packet is an HPB read command packet, the memory controller 601 can calculate the number of marked data units in the first sub-region 604 corresponding to the second sub-region 702. For example, the number of marked data units in the first sub-region 604 can be obtained by calculating the number of "1"s in the bitmap of the first sub-region 604.

[0132] The memory controller 601 is also configured to: execute step S2004, compare the number of marked data units in the first sub-area 604 with a pre-set update threshold, and when the number of marked data units in the first sub-area 604 is greater than or equal to the update threshold, determine to trigger the update of the mapping data in the second sub-area 702 corresponding to the first sub-area 604, and execute step S2005 to send a message recommending the update of the second sub-area 702; when the number of marked data units in the first sub-area 604 is less than the update threshold, determine not to trigger the update of the mapping data in the second sub-area 702 corresponding to the first sub-area 604.

[0133] In some embodiments, the memory controller 601 is further configured to: in response to determining to update the mapping data in the second sub-region 702 , send the mapping data stored in the first sub-region 604 corresponding to the second sub-region 702 .

[0134] In some specific examples, in response to determining to trigger an update of the mapping data in the second sub-region 702 corresponding to the first sub-region 604, the memory controller 601 may send a message recommending the update of the second sub-region 702 to the host 700 in the response information of the read command, and in response to the host 700 determining to update the mapping data in the second sub-region 702, the memory controller 601 may read the mapping data in the first sub-region 604 corresponding to the second sub-region 702 from the memory device 602 and send it to the host 700, while resetting each bit in the bitmap of the first sub-region 604.

[0135] It is understandable that a first sub-region 604 includes a large number of mapping relationships between logical addresses and physical addresses. If the validity of the mapping data is marked in units of the first sub-region 604, once the physical address corresponding to a logical address changes, the entire first sub-region 604 will be marked, resulting in all mapping data in the second sub-region 702 corresponding to the first sub-region 604 being invalid. In addition, if the update of the mapping data of the second sub-region 702 corresponding to the first sub-region 604 is triggered as long as the first sub-region 604 is marked, the update frequency will be too high, occupying more system resources, thereby having a negative impact on the overall performance of the system; and if the update frequency is reduced, the second sub-region 702 will not be updated in time, and a large amount of mapping data in the second sub-region 702 will not be used because the corresponding first sub-region 604 is marked as invalid, that is, the HPB read operation cannot be performed, thereby resulting in reduced performance of random read operations.

[0136] In the embodiment of the present disclosure, the memory controller 601 is configured to mark the first sub-region 604 in units of data units, and when the number of marked data units in the first sub-region 604 reaches or exceeds the update threshold, the update of the second sub-region 702 is triggered. In this case, even if some data units in the first sub-region 604 are marked and the mapping data of the second sub-region 702 corresponding to the first sub-region 604 is not immediately updated, the mapping data in the second sub-region 702 that does not fall within the logical address range of the marked data unit is still valid, so that the impact on the HPB read operation can be reduced while controlling the update frequency, and the degree of reduction in random read operation performance can be reduced while avoiding occupying too many system resources.

[0137] In some specific examples, the ratio of the update threshold to the number of data units in the first sub-region 604 ranges from 25% to 75%. For example, when the first sub-region 604 is divided into 32 data units, the update threshold can range from 8 to 24.

[0138] In the embodiment of the present disclosure, the memory controller 601 is further configured to adjust the number of data units and the update threshold in the first sub-region 604 according to the resource configuration of the system, so as to improve the flexibility of the HPB sub-region validity management.

[0139] In a specific example, when the system has sufficient resources to manage the validity of the HPB sub-region, the number of data units in the first sub-region 604 can be increased, so that the validity of the mapped data can be marked in units of smaller granularity, thereby improving the accuracy of validity management. When the system resources are insufficient, the number of data units in the first sub-region 604 can be reduced, thereby reducing the size of the bitmap of the first sub-region 604 and reducing the resources required to maintain the bitmap.

[0140] In another specific example, when the number of data units in the first sub-region 604 remains unchanged, when the system has sufficient resources to manage the validity of the HPB sub-region, the update threshold can be reduced to increase the update frequency, thereby further improving the efficiency of the system in performing read operations, and when the system resources are insufficient, the update threshold can be increased to reduce the update frequency.

[0141] Based on a concept similar to the above-mentioned memory system, the present disclosure provides an operation method of a memory system. Fig.11 A flowchart of the operation method provided by the embodiment of the present disclosure is shown in FIG. Fig. 9 As shown, the operating method of the memory system includes the following steps:

[0142] Step S10: Divide each of the first sub-areas into a plurality of data units;

[0143] Step S20: when the mapping data in the data unit changes, marking the data unit as a dirty unit;

[0144] Step S30: determining whether to trigger updating of mapping data in the second sub-region corresponding to the first sub-region based on the number of the dirty cells in the first sub-region.

[0145] In some embodiments, the specific process of executing step S10 may include: establishing a bitmap of the first sub-region, where a bit in the bitmap corresponds to a data unit in the first sub-region, so as to divide the first sub-region into a plurality of data units.

[0146] In some embodiments, the specific process of executing step S20 may include: when a physical address corresponding to at least one logical address in the data unit changes, marking a bit corresponding to the data unit in the bitmap to mark the data unit.

[0147] In some embodiments, the specific process of executing step S30 may include: when the number of marked data units in the first sub-region is greater than or equal to the update threshold, determining to trigger the update of the mapping data in the second sub-region corresponding to the first sub-region; when the number of marked data units in the first sub-region is less than the update threshold, determining not to trigger the update of the mapping data in the second sub-region corresponding to the first sub-region.

[0148] In some embodiments, the operating method of the memory system further includes: receiving a read command packet; and when the read command packet includes mapping data in the second sub-region, acquiring the number of marked data units in the first sub-region corresponding to the second sub-region.

[0149] In some embodiments, the operating method of the memory system further includes: in response to determining that an update of mapping data in a second sub-region corresponding to the first sub-region is triggered, sending a message recommending updating the second sub-region.

[0150] In some embodiments, the operating method of the memory system further includes: in response to determining to update the mapping data in the second sub-region, sending the mapping data stored in the first sub-region corresponding to the second sub-region.

[0151] In some embodiments, the operating method of the memory system also includes: when the logical address of the mapping data in the read command packet is within the logical address range of the mapping data stored in the marked data unit, obtaining the physical address corresponding to the logical address from the first sub-area and performing a read operation; when the logical address of the mapping data in the read command packet is not within the logical address range of the mapping data stored in the marked data unit, performing a read operation based on the physical address in the read command packet.

[0152] In the embodiments of the present disclosure, the operating method of the memory system can be executed by the memory controller 601 in the memory system 600 in any of the aforementioned embodiments. The technical effects that can be achieved by the memory system in the aforementioned embodiments can also be achieved by the operating method of the memory system, which will not be described in detail here.

[0153] The present disclosure also provides an electronic device, which may include Figure 7 See the system shown. Figure 7 The electronic device includes a memory system 600 and a host 700 coupled to the memory system 600; the memory system 600 includes a memory device 602 and a memory controller 601 coupled to the memory device 602; the memory device 602 includes a plurality of first sub-areas 604 storing mapping data; the host 700 includes a host controller 703 and a plurality of second sub-areas 702 corresponding to the plurality of first sub-areas 604; the mapping data includes a mapping relationship from a logical address to a physical address; the range of logical addresses of the mapping data stored in the first sub-areas 604 and the second sub-areas 702 corresponding to each other is the same.

[0154] In some embodiments, the memory controller 601 is configured to: divide the first sub-region 604 into a plurality of data units; mark the data unit when the mapping data in the data unit changes; determine whether to trigger the update of the mapping data in the second sub-region 702 corresponding to the first sub-region 604 based on the number of marked data units in the first sub-region 604; and send a message recommending the update of the second sub-region 702 in response to determining that the update of the mapping data in the second sub-region 702 corresponding to the first sub-region 604 is triggered. The host controller 703 is configured to: receive the message recommending the update of the second sub-region 702, and determine whether to update the mapping data in the second sub-region 702.

[0155] In some embodiments, the memory controller 601 is specifically configured to: establish a bitmap of the first sub-region 604, where a bit in the bitmap corresponds to a data unit in the first sub-region 604, so as to divide the first sub-region 604 into multiple data units; when the physical address corresponding to at least one logical address in the data unit changes, mark the bit corresponding to the data unit in the bitmap to mark the data unit.

[0156] In some embodiments, the host controller 703 is also configured to: send a read command packet to the memory controller 601; the memory controller 601 is also configured to: receive the read command packet, and when the read command packet includes mapping data in the second sub-area 702, obtain the number of marked data units in the first sub-area 604 corresponding to the second sub-area 702.

[0157] In some embodiments, the memory controller 601 is specifically configured to: when the number of marked data units in the first sub-region 604 is greater than or equal to the update threshold, determine to trigger the update of the mapping data in the second sub-region 702 corresponding to the first sub-region 604; when the number of marked data units in the first sub-region 604 is less than the update threshold, determine not to trigger the update of the mapping data in the second sub-region 702 corresponding to the first sub-region 604.

[0158] In some embodiments, the memory controller 601 is further configured to: in response to the host controller 703 determining to update the mapping data in the second sub-area 702, send the mapping data stored in the first sub-area 604 corresponding to the second sub-area 702; the host controller 703 is further configured to: receive the mapping data stored in the first sub-area 604, and update the mapping data in the second sub-area 702 corresponding to the first sub-area 604. Here, updating the mapping data in the second sub-area 702 may include replacing the mapping data in the second sub-area 702 with the received mapping data stored in the first sub-area 604. In this case, the mapping data stored in the first sub-area 604 and the second sub-area 702 corresponding to each other will be consistent again, and the memory controller 601 can reset each bit in the bitmap of the first sub-area 604.

[0159] In the electronic device provided by the embodiment of the present disclosure, the memory device of the memory system includes a first sub-region for storing mapping data, and the host performance enhancement of the host includes a second sub-region for storing mapping data, the first sub-region and the second sub-region correspond to each other, and the range of logical addresses of the mapping data stored in the first sub-region and the second sub-region corresponding to each other is the same. The memory controller can divide the first sub-region into multiple data units by establishing a bitmap, and mark the validity of the mapping data in units of data units in the bitmap, and determine whether to trigger the update of the mapping data of the second sub-region corresponding to the first sub-region based on the number of marked data units. On the one hand, the validity of the mapping data can be marked in units of smaller granularity, thereby improving the accuracy of validity management. On the other hand, the frequency of updating the second sub-region can be adjusted by setting an update threshold, so as to balance the degree of occupation of system resources and the degree of influence on the performance of random read operations, so as to achieve the purpose of improving the overall performance of the system.

[0160] The present disclosure also provides a computer-readable storage medium, on which a computer program is stored. In some embodiments, when the computer program is executed by a processor, the operating method of the memory system in any of the above embodiments can be executed.

[0161] Here, in order to implement all or part of the processes in the operation method of the above-mentioned embodiment, it can be completed by hardware related to computer program instructions, and the computer program can be stored in a computer-readable storage medium, and the execution of the computer program can include the process of the operation method in any of the above-mentioned embodiments. Among them, the computer-readable storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (HDD) or a solid state drive, etc., and the computer-readable storage medium can also include a combination of the above-mentioned multiple storage media.

[0162] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0163] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0164] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory system, characterized in that: The memory system includes a memory device and a memory controller coupled to the memory device; the memory device includes a plurality of first sub-areas storing mapping data; the memory controller is coupled to a host; the host includes a plurality of second sub-areas corresponding to the plurality of first sub-areas; the mapping data includes a mapping relationship from a logical address to a physical address; the first sub-area and the second sub-area corresponding to each other store the same range of logical addresses of the mapping data; the memory controller is configured as follows: Dividing the first sub-area into a plurality of data units; When the mapping data in the data unit changes, marking the data unit; Whether to trigger updating of mapping data in the second sub-region corresponding to the first sub-region is determined based on the number of marked data units in the first sub-region.

2. The memory system according to claim 1, wherein: The memory controller is specifically configured as follows: Establishing a bitmap of the first sub-region, wherein a bit in the bitmap corresponds to a data unit in the first sub-region, so as to divide the first sub-region into a plurality of data units; When a physical address corresponding to at least one logical address in the data unit changes, a bit corresponding to the data unit is marked in the bitmap to mark the data unit.

3. The memory system according to claim 1, wherein: The memory controller is specifically configured as follows: When the number of the marked data units in the first sub-region is greater than or equal to an update threshold, determining to trigger an update of mapping data in the second sub-region corresponding to the first sub-region; When the number of the marked data units in the first sub-region is less than the update threshold, it is determined not to trigger the update of the mapping data in the second sub-region corresponding to the first sub-region.

4. The memory system according to claim 1, wherein: The memory controller is further configured to: Receive read command packet; When the read command packet includes mapping data in the second sub-region, acquiring the number of the marked data units in the first sub-region corresponding to the second sub-region; In response to determining that an update of mapping data in the second sub-region corresponding to the first sub-region is triggered, a message recommending an update of the second sub-region is sent.

5. The memory system according to claim 4, characterized in that: The memory controller is further configured to: When the logical address of the mapping data in the read command packet is within the logical address range of the mapping data stored in the marked data unit, acquiring a physical address corresponding to the logical address from the first sub-area and performing a read operation; When the logical address of the mapping data in the read command packet is not within the logical address range of the mapping data stored in the marked data unit, a read operation is performed based on the physical address in the read command packet.

6. The memory system according to claim 4, characterized in that: The memory controller is further configured to: In response to determining to update the mapping data in the second sub-region, the mapping data stored in the first sub-region corresponding to the second sub-region is sent.

7. The memory system according to claim 3, characterized in that: The number of data units in the first sub-area ranges from 8 to 1024; the ratio of the update threshold to the number of data units in the first sub-area ranges from 25% to 75%.

8. A method for operating a memory system, characterized in that: include: dividing a first sub-region storing mapping data in the memory device into a plurality of data units; When mapping data in the data unit changes, marking the data unit; the mapping data includes a mapping relationship from a logical address to a physical address; Based on the number of marked data units in the first sub-area, determine whether to trigger the update of mapping data in the second sub-area corresponding to the first sub-area in the host; the logical address range of the mapping data stored in the first sub-area and the second sub-area corresponding to each other is the same.

9. The method for operating a memory system according to claim 8, wherein: The step of dividing the first sub-region storing the mapping data in the memory device into a plurality of data units and marking the data units comprises: Establishing a bitmap of the first sub-region, wherein a bit in the bitmap corresponds to a data unit in the first sub-region, so as to divide the first sub-region into a plurality of data units; When a physical address corresponding to at least one logical address in the data unit changes, a bit corresponding to the data unit is marked in the bitmap to mark the data unit.

10. The method for operating a memory system according to claim 8, wherein: The determining whether to trigger updating of mapping data in a second sub-area corresponding to the first sub-area in the host based on the number of marked data units in the first sub-area comprises: When the number of the marked data units in the first sub-region is greater than or equal to an update threshold, determining to trigger an update of mapping data in the second sub-region corresponding to the first sub-region; When the number of the marked data units in the first sub-region is less than the update threshold, it is determined not to trigger the update of the mapping data in the second sub-region corresponding to the first sub-region.

11. The method for operating a memory system according to claim 8, wherein: The operation method also includes: Receive read command packet; When the read command packet includes mapping data in the second sub-region, acquiring the number of the marked data units in the first sub-region corresponding to the second sub-region; In response to determining that an update of mapping data in the second sub-region corresponding to the first sub-region is triggered, a message recommending an update of the second sub-region is sent.

12. The method for operating a memory system according to claim 11, characterized in that: The operation method also includes: When the logical address of the mapping data in the read command packet is within the logical address range of the mapping data stored in the marked data unit, acquiring a physical address corresponding to the logical address from the first sub-area and performing a read operation; When the logical address of the mapping data in the read command packet is not within the logical address range of the mapping data stored in the marked data unit, a read operation is performed based on the physical address in the read command packet.

13. The method for operating a memory system according to claim 11, characterized in that: The operation method also includes: In response to determining to update the mapping data in the second sub-region, the mapping data stored in the first sub-region corresponding to the second sub-region is sent.

14. An electronic device, characterized in that: The electronic device comprises a memory system and a host coupled to the memory system; the memory system comprises a memory device and a memory controller coupled to the memory device; the memory device comprises a plurality of first sub-areas storing mapping data; the host comprises a host controller and a plurality of second sub-areas corresponding to the plurality of first sub-areas; the mapping data comprises a mapping relationship from a logical address to a physical address; the logical address range of the mapping data stored in the first sub-area and the second sub-area corresponding to each other is the same; the memory controller is configured as follows: Dividing the first sub-area into a plurality of data units; When the mapping data in the data unit changes, marking the data unit; determining whether to trigger updating of mapping data in the second sub-region corresponding to the first sub-region based on the number of marked data units in the first sub-region; In response to determining that an update of mapping data in the second sub-region corresponding to the first sub-region is triggered, sending a message recommending an update of the second sub-region; The host controller is configured to: A message recommending updating the second sub-area is received, and it is determined whether to update mapping data in the second sub-area.

15. The electronic device according to claim 14, characterized in that: The memory controller is specifically configured as follows: Establishing a bitmap of the first sub-region, wherein a bit in the bitmap corresponds to a data unit in the first sub-region, so as to divide the first sub-region into a plurality of data units; When a physical address corresponding to at least one logical address in the data unit changes, a bit corresponding to the data unit is marked in the bitmap to mark the data unit.

16. The electronic device according to claim 14, characterized in that: The memory controller is specifically configured as follows: When the number of the marked data units in the first sub-region is greater than or equal to an update threshold, determining to trigger an update of mapping data in the second sub-region corresponding to the first sub-region; When the number of the marked data units in the first sub-region is less than the update threshold, it is determined not to trigger the update of the mapping data in the second sub-region corresponding to the first sub-region.

17. The electronic device according to claim 14, characterized in that: The host controller is further configured to: Sending a read command packet to the memory controller; The memory controller is further configured to: The read command packet is received, and when the read command packet includes mapping data in the second sub-region, the number of the marked data units in the first sub-region corresponding to the second sub-region is acquired.

18. The electronic device according to claim 14, characterized in that: The memory controller is further configured to: In response to the host controller determining to update the mapping data in the second sub-area, sending the mapping data stored in the first sub-area corresponding to the second sub-area; The host controller is further configured to: The mapping data stored in the first sub-region is received, and the mapping data in the second sub-region corresponding to the first sub-region is updated.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the operating method according to any one of claims 8 to 13 is performed.

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