Synchronization method and system of universal serial bus

Abstract

A synchronization method in a universal serial bus (USB) training state comprises the steps that a transmitter sends an SLOS1 ordered set in a LOCK1 state, a receiver receives the SLOS1 ordered set in the LOCK1 state, and the transmitter is stopped from sending a training ordered set according to needs. And if the transmitter continuously transmits the training ordered set in the infinite loop in the LOCK1 state, stopping transmitting the training ordered set by the transmitter according to a lane adapter state machine (LASM). The training ordered set comprises an SLOS1 ordered set. The method further includes transmitting, by the transmitter, the new SLOS1 ordered set, receiving, by the receiver, the new SLOS1 ordered set, and entering, by the transmitter and the receiver, a LOCK2 state. The length of the new SLOS1 ordered set is different from the length of the SLOS1 ordered set.

Description

Technical Field

[0001] The present application generally relates to the field of universal serial bus, and more specifically, to a synchronization method and system thereof for a universal serial bus (USB for short). Background Art

[0002] Universal Serial Bus (USB) is an industrial standard that specifies the physical interface and protocol for connection, data transfer, and power supply between hosts (such as personal computers, peripheral devices (such as keyboards and mobile devices), and intermediate hubs. USB aims to standardize the connection of peripherals to computers, replacing various interfaces such as serial ports, parallel ports, game ports, and Android Debug Bridge (ADB) ports. It has become a universal standard for various devices, such as keyboards, mice, cameras, printers, scanners, flash drives, smartphones, game consoles, and mobile power banks. As of 2023, USB includes four generations of specifications: USB 1.x, USB 2.0, USB 3.x, and USB4.

[0003] USB4 (sometimes referred to as USB 4.0) is a new generation of Universal Serial Bus (USB) standard released by the USB Implementers Forum (USB-IF) in 2019. It is based on the Thunderbolt 3 protocol specification, but also supports multiple data and display protocols, such as DisplayPort and PCI Express (PCIe). The USB4 structure can dynamically share a single high-speed link with multiple hardware endpoints, thereby best providing each transfer service by data type and application. USB4 includes enhanced data transmission and power supply capabilities, as well as a connection-oriented channel architecture designed to combine multiple protocols onto a single physical interface to dynamically share the total speed and performance of the USB4 structure (USB 4Fabric).

[0004] Key features of USB4 include dual-channel operation using existing USB Type-C cables as well as up to 80Gbps operation via 80Gbps certified cables, multiple data and display protocols to efficiently share the maximum aggregate bandwidth on the bus, and backward compatibility with all previous versions of USB.

[0005] USB4 itself does not provide any general data transfer mechanisms or device classes (like USB 3.x), but is primarily used as a way to channel other protocols such as USB 3.2, DisplayPort, and optionally PCIe. According to the USB4 1.0 specification, when the host and device do not support the optional PCIe channel, the non-display bandwidth will be limited to the mandatory 10Gbit / s described by USB 3.2, but includes optional support for 20Gbit / s. The USB4 2.0 specification introduces optional support for new USB3 Gen T channels, which extend the USB3 protocol to be able to use the maximum available bandwidth. USB4 2.0 specifies USB 3.2 ("Enhanced SuperSpeed") channels, DisplayPort 2.1-based channels, and PCIe-based channels.

[0006] The channel adapter that negotiates the USB4 Gen 2 or Gen 3 link should follow the training sub-state machine described in the USB4 specification and operate according to the behaviors and sub-state transitions described therein. The purpose of the training state is to ensure that the transmitter and receiver are synchronized with each other so that they can understand each other's data content. To achieve this goal, the receiver compares the received command set (e.g., SLOS1, SLOS2, TS1, and TS2) with its stored information. Taking the LOCK1 state as an example, after the receiver receives two SLOS1s, it will refer to the stored information to confirm whether the two received SLOS1s are continuous. If so, the sub-state synchronization is successful and the next step can be performed. However, once an incorrect instruction set is transmitted during one of the states (i.e., LOCK1, LOCK2, TS1, and TS2), the channel adapter state machine (LASM) will return to the LOCK1 state, resulting in an infinite loop. This may eventually result in the training state failing to complete successfully. Summary of the invention

[0007] An embodiment provides a method for synchronization in a training state of a universal serial bus (USB). The method includes sending a SLOS1 ordered set by a transmitter in a LOCK1 state, receiving the SLOS1 ordered set by a receiver in a LOCK1 state, and if the transmitter continuously sends a training ordered set in an infinite loop in the LOCK1 state, then stopping the transmitter from sending the training ordered set according to a lane adapter state machine (LASM). The training ordered set includes a SLOS1 ordered set. The method also includes sending a new SLOS1 ordered set by the transmitter, receiving the new SLOS1 ordered set by the receiver, and the transmitter and the receiver entering a LOCK2 state. The length of the new SLOS1 ordered set is different from the length of the SLOS1 ordered set.

[0008] An embodiment provides a universal serial bus (USB) system, which includes a transmitter and a receiver coupled to the transmitter. The transmitter is used to send a training ordered set. The training ordered set includes a SLOS1 ordered set. The receiver is used to receive the training ordered set. If the transmitter continuously sends the training ordered set in an infinite loop in a LOCK1 state, the transmitter stops sending the training ordered set according to a channel adapter state machine (LASM). Then, the transmitter sends a new SLOS1 ordered set in the LOCK1 state. The length of the new SLOS1 ordered set is different from the length of the SLOS1 ordered set.

[0009] These and other objects of the present invention will no doubt become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments illustrated in the various drawings and figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram showing a USB system according to an embodiment of the present invention.

[0011] Figure 2 Shown by Figure 1 Flowchart of the synchronization method in the training state implemented by the USB system.

[0012] Figure 3 Show Figure 2 An example scenario in which a synchronization error occurs between the transmitter and receiver of FIG.

[0013] Figure 4 Show that you can use Figure 2 An exemplary scenario of implementing the method to recover from synchronization errors. DETAILED DESCRIPTION

[0014] For the purpose of describing the innovative aspects of the present disclosure, the following description is directed to specific embodiments. However, one of ordinary skill in the art will readily recognize that the teachings herein can be applied in a variety of different ways. The described implementations can be implemented in any device, system, or network that can send and receive signals according to one or more of the Universal Serial Bus specifications (e.g., USB 1.x, USB 2.0, USB 3.x, and USB4). The terms "Gen 2" and "Gen 3" may refer to the second and third generation standards issued by USB-IF, respectively.

[0015] According to the present disclosure, a "channel" refers to a dual-simplex high-speed differential signaling pair that provides communication between a Downstream Facing Port (DFP) and an Upstream Facing Port (UFP). The signaling rate at which a channel operates defines the communication speed of the channel.

[0016] According to the present disclosure, the lane adapter state machine (LASM) is an element in the logical layer that manages the communication between different channels of the USB. LASM is responsible for adjusting the data format, protocol, and speed of each channel to match the requirements of the destination, as well as describing the behavior of the logical link layer during the link sequence. The logical layer is part of the protocol that defines how data is transmitted in the USB4 architecture. The role of the logical layer is to provide services such as error detection and recovery, transmission of different media, and power management for transmitters and receivers. The channel adapter is an adapter that connects channels. The USB4 port has two channel adapters: a channel 0 adapter and a channel 1 adapter.

[0017] According to the USB4 specification, LASM includes the following states:

[0018] Disabled state: The channel adapter disables the channel.

[0019] CLd state: The channel adapter transmitter and receiver are not started.

[0020] Training state: The channel adapter performs symbol synchronization and channel parameter transmission.

[0021] CL0 state: The channel adapter can transmit and receive transport layer datagrams across the channel.

[0022] Channel Bonding Status: A channel adapter can bond two single-channel links into a dual-channel link.

[0023] CL0, CL1, CL2 states: low power consumption state.

[0024] Also according to the USB4 specification, the Gen 2 and Gen 3 training states include the following sub-states with corresponding transmitter behaviors, as shown in Table 1-1:

[0025] Table 1-1

[0026]

[0027] During the training state, symbols are synchronized and channel parameters are transmitted between the two ends of the channel (ie, transmitter and receiver). In addition, the Gen 2 and Gen 3 sub-state transition behaviors are shown in Table 1-2 below.

[0028] Table 1-2

[0029]

[0030]

[0031] Some embodiments of the present invention are described herein by way of example only and with reference to the accompanying drawings. With specific reference now to the accompanying drawings in detail, it is emphasized that the details shown are by way of example and for the purpose of illustrative discussion of the preferred embodiments of the present invention only, and are presented in order to provide what are believed to be the most useful and easily understood description of the principles and conceptual aspects of the present invention. In this regard, no attempt is made to show the structural details of the present invention in more detail than is necessary for a basic understanding of the present invention, and the description in conjunction with the accompanying drawings makes it clear to those skilled in the art how several forms of the present invention may be embodied in practice.

[0032] Figure 1 Schematic diagram of a universal serial bus (USB) system 100 of an embodiment of the present invention. The USB system 100 includes a transmitter (TX) 110 and a receiver (RX) 120 coupled to the transmitter 110. The transmitter 110 is used to send a training ordered set, and the receiver 120 is used to receive the training ordered set. The receiver 120 can also relay feedback information to the transmitter 110 for synchronization purposes. The transmitter 110 can implement LASM 130. The USB system 100 can comply with the USB4 specification.

[0033] In the case of sending an erroneous ordered set during one of the states (i.e., LOCK1, LOCK2, TS1, or TS2), LASM 130 can fall back to the LOCK1 state and cause the transmitter 110 to send a SLOS1 ordered set. This is to retrain the transmitter 110 and the receiver 120. However, in the case of the real world, when the above situation occurs, the transmitter 110 is likely to continuously send a SLOS1 ordered set in an infinite loop. This will eventually result in the training state failing to complete successfully. Therefore, the present disclosure describes an embodiment that solves the above problem.

[0034] Figure 2 A flowchart of a synchronization method 200 in a training state implemented by the USB system 100 is shown. The training ordered set may be of different types, such as SLOS1, SLOS2, TS1, and TS2 ordered sets. The method 200 includes the following steps:

[0035] S202: The transmitter 110 sends a SLOS1 ordered set in the LOCK1 state;

[0036] S204: The receiver 120 receives the SLOS1 ordered set in the LOCK1 state;

[0037] S206: Does the transmitter continuously send training ordered sets in an infinite loop? If yes, proceed to S207; if no, proceed to S212;

[0038] S207: LASM 130 stops transmitter 110 from sending training ordered sets;

[0039] S208: The transmitter 110 sends a new SLOS1 ordered set;

[0040] S210: The receiver 120 receives a new SLOS1 ordered set; and

[0041] S212: The transmitter 110 and the receiver 120 enter the LOCK2 state.

[0042] It should be noted that the length of the new SLOS1 ordered set in steps S208 and S210 may be different from the length of the original SLOS1 ordered set in steps S202 and S204. That is, in some embodiments, the length of the new SLOS1 ordered set may be longer than the length of the original SLOS1 ordered set. In some other embodiments, the length of the new SLOS1 ordered set may be shorter than the length of the original SLOS1 ordered set. An example of method 200 is described in the following paragraphs and related figures.

[0043] Figure 3 An exemplary scenario in which a synchronization error occurs between the transmitter 110 and the receiver 120 is shown. When a damaged T2 ordered set 340 is sent during the training state, the LASM 130 can detect an error and return to the LOCK1 state, causing the transmitter 110 to send the SLOS1 ordered set 310 and the SLOS2 ordered set 320 in an alternating manner. As a result, the receiver 120 will not be able to synchronize its state with the transmitter 110. This situation will result in an infinite loop, and the transmitter 110 and the receiver 120 will be in the training state indefinitely. This means that the transmitter 110 and the receiver 120 may not be able to enter the CL0 state to transfer data. Therefore, the USB connection may fail.

[0044] Figure 4An exemplary scenario is shown in which an implementation of the method 200 may be utilized to recover synchronization errors. During the training state, the transmitter 110 may transmit the SLOS1 ordered set 410, the SLOS1 ordered set 420, the TS1 ordered set 430, and the TS2 ordered set 440 using the following sequence to synchronize the transmitter 110 with the receiver 120. Note that the receiver 120 may also relay feedback information to the transmitter 110 for synchronization purposes.

[0045] In the case where T2 ordered set 440 is destroyed, LASM 130 can detect an error and return to the LOCK1 state. At this time, transmitter 110 can send a new SLOS1 ordered set 415 to restart training. The new SLOS1 ordered set 415 can be longer than the SLOS1 ordered set 410. For example, the length of the new SLOS1 ordered set 415 can be 1.5 to 2 times the length of the SLOS1 ordered set 410. In some implementations, the new SLOS1 ordered set 415 can be the length of the SLOS1 ordered set 415. The ordered set 415 can be 2 to 3 times the length of the SLOS1 ordered set 410. The present disclosure is not limited to this. A longer SLOS1 ordered set 415 can allow the receiver 120 to have more time to synchronize its state with the transmitter 110, thereby avoiding the above-mentioned infinite loop caused by transmission delay.

[0046] After the LOCK1 state is completed, the transmitter 110 and the receiver 120 enter the subsequent states, namely LOCK2, TS1 and TS2. The transmitter 110 sends the SLOS2 ordered set 425, the TS1 ordered set 435 and the TS2 ordered set 445 respectively. After the transmitter 110 and the receiver 120 are synchronized in the TS2 state, the transmitter 110 and the receiver 120 can enter the CL0 state to send and receive datagrams. In this way, the behavior of the USB system 100 can be restored to normal.

[0047] The above-mentioned embodiment of the USB system can recover itself from the wrong synchronization behavior. As a result, the fault tolerance of the USB system can be enhanced and become more robust.

[0048] The various illustrative elements, logic, logic blocks, modules, circuits, operations, and algorithmic processes described in conjunction with the implementation disclosed herein may be implemented as electronic hardware, firmware, software, or a combination of hardware, firmware, or software, including the structures disclosed in this specification and their structural equivalents. The interchangeability of hardware, firmware, and software has been generally described in terms of functionality, and is shown in the various illustrative elements, blocks, modules, circuits, and processes described above. Whether such functions are implemented in hardware, firmware, or software depends on the specific application and the design constraints imposed on the entire system.

[0049] The hardware and data processing devices used to implement the various illustrative elements, logic, logic blocks, modules and circuits described in conjunction with the aspects disclosed herein can be implemented or executed with a general-purpose single-chip processor or multiple chips. Processors, digital signal processors (digital signal processors, referred to as DSP), application specific integrated circuits (application specific integrated circuits, referred to as ASIC), field programmable gate arrays (field programmable gate arrays, referred to as FPGA) or other programmable logic devices (programmable logic devices, referred to as PLD), discrete gates or transistor logic, discrete hardware elements or any combination thereof are intended to perform the functions described herein. A general-purpose processor can be a microprocessor, or any conventional processor, controller, microcontroller or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. In some embodiments, specific processing, operations and methods can be performed by circuits specific to a given function.

[0050] As mentioned above, in some aspects, the realization of the subject matter described in this specification can be implemented as software.For example, the various functions of the elements disclosed herein or the various blocks or steps of the methods, operations, processes or algorithms disclosed herein can be implemented as one or more modules of one or more computer programs.Such a computer program may include non-transitory processor executable or computer executable instructions encoded on one or more tangible processor-readable or computer-readable storage media, for executing or controlling its operation by the data processing device of the elements including the equipment described herein.As an example and not limitation, such storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, or any other medium that can be used to store program code in the form of instructions or data structures.The above combination should also be included in the scope of storage media.

[0051] Various modifications to the embodiments described in this disclosure will be apparent to those of ordinary skill in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Therefore, the claims are not intended to be limited to the embodiments shown herein, but should be consistent with the broadest scope consistent with the disclosure, the principles and novel features disclosed herein.

[0052] In addition, various features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually in multiple implementations or in any suitable sub-combination. Thus, while features may be described above as functioning in a particular combination, and even initially claimed, one or more features from the claimed combination may be deleted from the claimed combination in some cases, and the claimed combination may be directed to a sub-combination or variants of a sub-combination.

[0053] References in the specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, and / or characteristic described in connection with the embodiment may be included in at least one implementation. The phrase "in one embodiment" appearing in different places in the specification may or may not all refer to the same embodiment.

[0054] The terms used in the description of the various embodiments described herein are only for the purpose of describing a specific embodiment and are not intended to be limiting. As used in the description of the various described embodiments and the appended claims, the singular forms "one", "an" and "the" are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more related listed items. It should also be understood that the terms "include", "comprise", "comprises" and / or "comprising" when used in this specification specify the existence of stated features, integers, steps, operations, elements and / or elements, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, elements and / or combinations thereof.

[0055] In addition, in the specification and claims, the terms "coupled" and "connected" and their derivatives may be used. In some embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.

[0056] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring such operations to be performed in the particular order shown or in a continuous order, or performing all the operations shown, to achieve the desired result. In addition, the accompanying drawings may schematically depict another example process in the form of a flow chart. However, other operations not depicted may be incorporated into the schematically illustrated example process. For example, one or more additional operations may be performed before, after, simultaneously, or between any of the illustrated operations. In certain cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system elements in the described implementation should not be understood as requiring such separation in all implementations, and it should be understood that the described program elements and systems can generally be integrated together in a single software product or packaged into multiple software products. In addition, other embodiments are also within the appended claims. In some cases, the actions recorded in the claims may be performed in different orders and still achieve the desired result.

[0057] Those skilled in the art will readily observe that various modifications and changes can be made to the apparatus and method while retaining the teachings of the present invention.Therefore, the above disclosure should be interpreted as being limited only by the scope and limits of the claims.

Claims

1. A synchronization method in a universal serial bus training state, comprising: The transmitter sends multiple SLOS1 ordered sets in the LOCK1 state; Receiving, by a receiver in the LOCK1 state, the SLOS1 ordered set; If the transmitter continuously sends a plurality of training ordered sets in an infinite loop in the LOCK1 state, stopping the transmitter from sending the plurality of training ordered sets according to the channel adapter state machine, the plurality of training ordered sets including the plurality of SLOS1 ordered sets; The transmitter sends a plurality of new SLOS1 ordered sets, wherein the lengths of the plurality of new SLOS1 ordered sets are different from the length of the SLOS1 ordered set; receiving, by the receiver, the plurality of new SLOS1 ordered-sets; and The transmitter and the receiver enter the LOCK2 state.

2. The synchronization method in a universal serial bus training state as claimed in claim 1, characterized in that: The transmitter sends a plurality of SLOS2 ordered sets in the LOCK2 state, and the receiver receives the plurality of SLOS2 ordered sets in the LOCK2 state.

3. The synchronization method in the universal serial bus training state as claimed in claim 2, characterized in that: The plurality of training ordered sets also include the plurality of SLOS2 ordered sets.

4. The synchronization method in a universal serial bus training state as claimed in claim 1, characterized in that: The method further includes: sending, by the transmitter, a plurality of TS1 ordered sets in the TS1 state, and receiving, by the receiver, the plurality of TS1 ordered sets in the TS1 state.

5. The synchronization method in the universal serial bus training state as claimed in claim 4, characterized in that: The plurality of training ordered sets further include the plurality of TS1 ordered sets.

6. The synchronization method in a universal serial bus training state as claimed in claim 1, characterized in that: The method further includes: the transmitter sending a plurality of TS2 ordered sets in the TS2 state, and the receiver receiving the plurality of TS2 ordered sets in the TS2 state.

7. The synchronization method in a universal serial bus training state as claimed in claim 6, characterized in that: The plurality of training ordered sets further include the plurality of TS2 ordered sets.

8. The synchronization method in a universal serial bus training state as claimed in claim 6, characterized in that: The method further includes, after the transmitter and the receiver are synchronized in the TS2 state, the transmitter and the receiver entering the CL0 state.

9. The synchronization method in a universal serial bus training state as claimed in claim 1, characterized in that: The length of the multiple new SLOS1 ordered sets is at least 1.5 times the length of the multiple SLOS1 ordered sets.

10. A universal serial bus system, comprising: A transmitter, configured to send a plurality of training ordered sets, wherein the plurality of training ordered sets include a plurality of SLOS1 ordered sets; as well as a receiver, coupled to the transmitter, configured to receive the plurality of training ordered sets; in: If the transmitter continuously transmits a plurality of training ordered sets in an infinite loop in the LOCK1 state, the transmitter stops transmitting the plurality of training ordered sets according to the channel adapter state machine. The transmitter sends a plurality of new SLOS1 ordered sets in the LOCK1 state; and The lengths of the multiple new SLOS1 ordered sets are different from the lengths of the multiple SLOS1 ordered sets.

11. The universal serial bus system according to claim 10, wherein: The transmitter transmits the plurality of SLOS1 ordered sets in the LOCK1 state, and the receiver receives the plurality of SLOS1 ordered sets in the LOCK1 state.

12. The universal serial bus system according to claim 10, wherein: The transmitter transmits the plurality of SLOS2 ordered sets in the LOCK2 state, and the receiver receives the plurality of SLOS2 ordered sets in the LOCK2 state.

13. The universal serial bus system according to claim 12, wherein: The plurality of training ordered sets further include the plurality of SLOS2 ordered sets.

14. The universal serial bus system according to claim 10, wherein: The transmitter sends a plurality of TS1 ordered sets in the TS1 state, and the receiver receives the plurality of TS1 ordered sets in the TS1 state.

15. The universal serial bus system according to claim 14, wherein: The plurality of training ordered sets further include the plurality of TS1 ordered sets.

16. The universal serial bus system according to claim 10, wherein: The transmitter sends a plurality of TS2 ordered sets in the TS2 state, and the receiver receives the plurality of TS2 ordered sets in the TS2 state.

17. The universal serial bus system according to claim 16, wherein: The plurality of training ordered sets further include the plurality of TS2 ordered sets.

18. The universal serial bus system according to claim 16, wherein: After the transmitter and the receiver are synchronized in the TS2 state, both the transmitter and the receiver enter the CL0 state.

19. The universal serial bus system according to claim 10, wherein: The length of the multiple new SLOS1 ordered sets is at least 1.5 times the length of the multiple SLOS1 ordered sets.

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