Computable storage core structure, chip unit and system for data compression storage

Abstract

The invention discloses a computable storage core structure, a chip unit and a system for data compression storage. An NVM cross array is used as a basic structure of a storable calculation core, the array is divided into a calculation part and a storage part, and peripheral circuits used for calculation and storage are integrated around the array. A compression / decompression algorithm is mapped into a device of an array calculation part, original data is compressed by adopting an in-memory calculation mode, and the compressed data is programmed in situ and stored into a device of an array storage part. And when the data are taken out, the data are restored through the calculation part. A plurality of computable storage cores form a computable storage piece unit, and further form a computable storage system to realize large-scale data in-storage calculation and in-situ storage. Compared with an existing data compression storage system, the data compression storage system has the advantages that data handling is reduced, energy efficiency is improved, data storage density is greatly improved, and processing of multi-source and unstructured data is more efficient.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and in particular to a computable storage unit based on non-volatile memory (NVM) for performing in-memory calculations and data compression. Background Art

[0002] With the development of the Internet, the amount of data generated by data centers and end-side devices has increased day by day, and has already reached ZB (1 ZB = 10 21 B) The majority of this data is unstructured. This data contains valuable information that needs to be analyzed and stored. However, the development of mainstream storage technologies such as FLASH faces challenges in terms of cost and technology, and the growth rate of storage device capacity has gradually slowed. Another development direction is to adopt more efficient data storage methods to reduce the total amount of data stored, that is, to use data compression technology to process data.

[0003] Data compression technology refers to the use of data redundancy to reduce the space or bandwidth required for data storage and transmission. It is mainly divided into two categories: lossless compression and lossy compression. For most data generated on the Internet, lossy compression is usually used to compress the data when it needs to be stored, in exchange for a higher compression ratio than lossless compression. Lossy compression mainly includes algorithms such as JPEG and JPEG2000 for processing image data, algorithms such as MP3 for processing audio data, and the H.264 algorithm for processing video information. Most of these algorithms use domain transformations and experience-based quantization matrices to process raw data. In recent years, researchers have also discovered the application of deep learning algorithms in the field of data compression. Training deep learning algorithms such as convolutional autoencoders based on partial data samples can better improve the compression and decompression effects of complex data.

[0004] Current data compression technologies typically use CPUs and GPUs as computing cores, processing the raw data and transferring it to a hard drive for storage. This method requires transferring the compressed data when storing it, and reading it from external storage when retrieving it, resulting in significant energy consumption during data transfer. Some ASIC chips are designed to accelerate the data compression calculation process, but they also face overhead issues such as energy consumption and latency associated with transferring compressed data from the computing unit to the storage unit. According to statistics, in systems where storage and computing are separated, the energy consumed to transfer data is several times the energy required to calculate the data. Therefore, it is particularly necessary to design a data compression storage system that can significantly reduce data transfer overhead. Summary of the Invention

[0005] The purpose of the present invention is to solve the problems in the current data compression storage systems based on traditional computing cores such as CPUs, GPUs, and ASICs for accelerating compression algorithms, which require a large amount of data to be frequently transferred between computing units and storage units, resulting in poor compression storage energy efficiency, low data storage density, and difficulty in effectively processing multi-source and unstructured complex data.

[0006] To solve the above problems, the present invention provides a computable storage core and a corresponding larger-scale system for realizing data compression, storage and decompression, which uses non-volatile memory as the main storage medium, and corresponding data compression, storage and decompression operation methods.

[0007] The computational storage core of the present invention is composed of an NVM cross array, computing peripheral circuits, storage peripheral circuits, etc. Compared with other hardware circuits for data compression, the present invention integrates the computing part for data compression and decompression and the storage part for compressed data storage in the same NVM cross array, and integrates peripheral circuits for computing and storage respectively around the NVM cross array. The close integration of computing peripheral circuits and storage peripheral circuits greatly reduces the large amount of overhead caused by data handling and improves the energy efficiency of data compression, storage and restoration processes. At the same time, some NVM devices have the characteristics of multi-value storage, and use cross array in-memory computing to compress and decompress data, which makes the present invention have higher storage density than traditional systems built with general-purpose processors such as CPUs as computing cores. At the same time, the in-memory computing part of the present invention is suitable for performing matrix operations, and can flexibly arrange various data compression algorithms, especially algorithms based on deep learning, which can have better compression effects when compressing, storing and restoring multi-source and unstructured data.

[0008] Specifically, the computable storage core proposed in the present invention includes an NVM cross array, a computing peripheral circuit, and a storage peripheral circuit, wherein the NVM cross array is composed of non-volatile storage cells connected by vertically crossed bit lines, word lines, and source lines, and is used to store matrix operators and compressed data in data compression algorithms; the computing peripheral circuit is composed of input registers, multiplexing circuits, sampling and holding circuits, analog-to-digital conversion circuits (ADCs), shift and addition circuits, etc., and is used for data transmission in the memory data compression and decompression calculation process; the storage peripheral circuit is composed of input data registers, driving circuits, comparators and other circuits, and is used for storing and reading compressed data.

[0009] When faced with larger-scale storage data and compression algorithms, multiple computable storage cores can be integrated to form a computable storage slice unit. The computable storage cores within the slice unit are connected through a specific topological relationship and exchange data with the outside of the slice unit through the L1 cache. Furthermore, the computable storage slice unit can integrate more complex addition tree circuits, special function units such as activation function calculation modules, and some control logic circuits to implement larger-scale compression algorithms.

[0010] On the basis of the computable storage slice unit, multiple slice units are connected by building an on-chip network through the routing module to form a complete computable storage system. The L2 cache, IO interface, etc. can be integrated to communicate with the outside of the chip. At the same time, the integration of chip control logic circuits with more powerful functions such as MCU can enable the chip to have more complex control over internal and external data communication, data programming storage and other functions.

[0011] The computational storage core of the present invention operates as follows: a compression / decompression algorithm is mapped to the devices in the computational portion of the NVM crossbar array of the computational storage core. Raw data is then input into the computational portion of the computational storage core for compression processing using in-memory computation. The resulting compressed data is then stored in-situ in the devices in the NVM crossbar array of the computational storage core for storage. When the compressed data needs to be retrieved, the corresponding data is first read from the storage portion, then input into the computational portion of the computational storage core for decompression, and finally the restored data is output.

[0012] The above operation method may specifically include the following steps:

[0013] 1) Use sample data to train deep learning-based compression and decompression algorithms;

[0014] 2) Mapping the algorithm weight programming to the device of the computational part of the computational storage core NVM crossbar array;

[0015] 3) The original data is compressed and processed by the computational part of the computational storage core;

[0016] 4) programming and storing the compressed data into a device of the NVM crossbar array storage portion of the computational storage core;

[0017] 5) Reading the compressed data stored in the computational storage core storage portion and temporarily storing it in a cache;

[0018] 6) The compressed data is decompressed by the computational part of the computational storage core and temporarily stored in the cache;

[0019] 7) Output the decompressed and restored data through the external communication interface.

[0020] Beneficial technical effects of the present invention:

[0021] 1. The structure of integrating computing and storage functions with the array proposed in the present invention can eliminate the need for data to be transferred between separate computing units and storage units during data compression and storage, thereby greatly improving the energy efficiency of the data compression and storage process.

[0022] 2. Through the multi-value storage characteristics of the non-volatile memory, the storage density of the present invention can be greatly improved.

[0023] 3. By using a data compression algorithm mapped in a computable storage unit composed of a non-volatile memory, such as a compression algorithm based on deep learning, the present invention can achieve better data compression and recovery effects when facing multi-source and unstructured data. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the computational storage core structure of an embodiment of the present invention.

[0025] Figure 2 Schematic diagram of a computable storage slice unit and system according to an embodiment of the present invention, wherein (a) is a structural diagram of the computable storage slice unit, and (b) is a structural diagram of the computable storage system.

[0026] Figure 3 This is an example flowchart of the system operation method according to an embodiment of the present invention.

[0027] Figure 4 Schematic diagram of data flow in the system data compression storage and restoration reading process according to an embodiment of the present invention.

[0028] Figure 5 The technical effect of the embodiment of the present invention is shown: compared with CPU, GPU, ASIC and other systems, the computable storage system of the present invention can greatly improve the energy efficiency of the data compression and storage process. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0030] In this embodiment, the non-volatile storage medium used to store compressed data and map the weights of the compression / decompression algorithm is a resistive random access memory (RRAM), which can store 4 bits per device. The RRAM array size of the computational storage core is 4k (256×16), and the connection line topology is bit line ∥ source line ⊥ word line, with the ADC connected to the source line end. The data to be compressed and stored is RGB image data with a resolution of 32×32, and the compression / decompression algorithm used is a convolutional autoencoder algorithm based on deep learning.

[0031] The basic hardware unit of the present invention is a computational storage core ( Figure 1 ) consists of an RRAM array and peripheral circuits. These include: peripheral circuits for in-memory computation, such as bitline / wordline / source line multiplexing circuits, sample-and-hold circuits, ADCs, shift-and-add circuits, and input / output registers; and peripheral circuits for data storage, such as input / output registers, bitline / wordline / source line driver circuits, multiplexing circuits, and comparators. The RRAM array is divided into a computational portion for data compression / decompression and a storage portion for compressed data storage, enabling tight integration of data processing and storage modules. The location and ratio of the computational and storage portions of the array can be dynamically divided based on the computational and storage loads required for different tasks and data to achieve optimal performance. The computational peripheral circuits are located around the array, connecting the input registers for data input and the sample-and-hold circuits, ADCs, and other circuits for data output to the array via multiplexing circuits. The ADC output is processed by the shift-and-add circuits before being output outside the core. The peripheral circuits used for storage are also tightly integrated around the array, and are located in a different position from the circuits used for calculation. The bit line / word line / source line driver circuits used for data storage and the comparator used for data reading are connected to the array through a multiplexing circuit. The compressed data stored in the array is read out by the comparator and output externally.

[0032] Based on the above-mentioned computable storage core, when facing larger-scale storage data and compression algorithms, multiple computable storage cores can be integrated ( Figure 2 Multiple computable storage cores constitute a computable storage slice unit. The internal computable storage cores are connected through a certain topological relationship and exchange data with the outside of the slice unit through the L1 cache. At the same time, in order to implement a larger-scale compression algorithm, more complex addition tree circuits, special function units such as activation function calculation modules, and some control logic circuits can also be integrated.

[0033] On the basis of the computable storage slice unit, multiple slice units are connected by building an on-chip network through the routing module to form a complete computable storage system, integrating L2 cache, IO interface, etc. to communicate with the outside of the chip. At the same time, the integration of more powerful chip control logic circuits such as MCU can also enable the chip to have more complex control over internal and external data communication, data programming storage and other functions.

[0034] The operation of the computational storage core and the system in this embodiment is generally described as follows: Figure 3 ):

[0035] Step 110: Select a convolutional autoencoder algorithm based on deep learning to compress and decompress the data, and train the algorithm by sampling part of the data from the data set to be compressed and stored.

[0036] Step 120: Map the weight data in the convolutional autoencoder. Map the weight programming in the algorithm to the device used by the computational storage core for in-memory calculations, that is, the array calculation part.

[0037] Step 130: After the data to be compressed and stored is quantized, it is input from the word line through the peripheral circuit module used for in-memory calculation, and the calculation result is obtained from the ADC corresponding to the source line. It is then post-processed through the shift-and-add circuit to obtain the compressed data to be stored and temporarily stored in the output register.

[0038] Step 140: The compressed data in the cache is retrieved and stored in a device for data storage in the computational storage core, namely, the array storage portion.

[0039] Step 150: The compressed data stored in the RRAM array is read out through the peripheral circuit for data storage in the computational memory core, and is temporarily stored in the output register after quantization.

[0040] Step 160: The quantized compressed data in the cache is input from the word line through the peripheral circuit module for in-memory calculation, and is calculated with the portion of the mapping decompression algorithm in the RRAM array. After being read out through the ADC, the decompressed data is post-processed through the shift-and-add module and temporarily stored in the output register.

[0041] Step 170: Output the restored data temporarily stored in the cache through the IO interface for external communication.

[0042] During the operation, the original data is compressed and stored in the data stream after compression, and the data stream after restoration is transmitted to the outside ( Figure 4 ) indicates that during the compression / decompression process, the data stream does not need to frequently interact with external storage, and the data can be stored in situ during the calculation.

[0043] Experiments have shown that the computational storage system of the present invention can reduce data handling overhead by integrating the in-memory computing array and the data storage array in the same NVM crossbar array and tightly integrating the peripheral circuits. Compared with traditional CPU- and GPU-based data compression systems and ASIC chips that only accelerate data compression algorithms, it can greatly reduce the energy consumption of data compression, storage, and decompression processes. Figure 5 ).

[0044] Experiments show that due to the high density of the storage array, the multi-value storage characteristics of RRAM and the tight integration of peripheral circuits, the present invention has a higher storage density than the traditional hardware implementation of data compression by the CPU.

[0045] In addition, since the computational storage core can be configured with data compression algorithms of different scales and sizes, compared with the traditional data compression method that uses fixed pattern transformation and experience-based quantization matrix, this embodiment uses a compression algorithm based on deep learning, which can achieve better compression effects for multi-source and unstructured data, such as text, images, audio, video, etc.

[0046] So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.

[0047] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A computational storage core, comprising a NVM crossbar array, a computational peripheral circuit, and a storage peripheral circuit, wherein the computational peripheral circuit and the storage peripheral circuit are integrated around the NVM crossbar array, and the NVM crossbar array is divided into a computational part and a storage part, wherein: The computing part is connected with the computing peripheral circuit and is used for data compression and decompression; The storage part is connected to the storage peripheral circuit and is used for compressing data storage.

2. The computable storage core according to claim 1, wherein: The device constituting the NVM crossbar array is RRAM.

3. The computable storage core according to claim 1, wherein: The calculation peripheral circuit is used for data transmission in the process of data compression and decompression calculation in memory, including: a multiplexing circuit of bit lines, source lines, and word lines, a sampling and holding circuit, an ADC, a shift-and-add circuit, an input register, and an output register; the storage peripheral circuit is used for storing and reading compressed data, including: an input register, an output register, a driving circuit of bit lines, source lines, and word lines, a multiplexing circuit, and a comparator.

4. The computable storage core according to claim 1, wherein: The NVM crossbar array dynamically divides the computing part and the storage part according to different tasks and data requirements.

5. A computable storage slice unit, which is integrated with multiple computable storage cores as described in any one of claims 1 to 4, wherein the computable storage cores inside the slice unit are connected through a certain topological relationship and exchange data with the outside of the slice unit through an L1 cache.

6. The computable storage slice unit according to claim 5, characterized in that: The computable memory slice unit also integrates an addition tree circuit, a special function unit and a control logic circuit.

7. A computable storage system, comprising a plurality of computable storage slice units as claimed in claim 5, wherein the computable storage slice units are connected by building an on-chip network through a routing module.

8. The computable storage system according to claim 7, characterized in that: The computable storage system also integrates an L2 cache, an external communication interface and a chip control logic circuit.

9. The method for operating the computable storage core according to any one of claims 1 to 4, comprising: Mapping compression and decompression algorithms to the device of the computational part of the NVM crossbar array of the computational storage core; The original data is input into the computing part of the computable storage core and compressed by in-memory computing, and the obtained compressed data is stored in-situ in the device of the NVM cross array storage part of the computable storage core; When compressed data needs to be retrieved, the data is first read out from the storage part, then the read data is input into the computing part of the computable storage core for decompression, and finally the decompressed and restored data is output to the outside.

10. The operating method according to claim 9, characterized in that: The following steps are involved: 1) Use sample data to train deep learning-based compression and decompression algorithms; 2) Map the algorithm weight programming to the device of the computational part of the computational storage core NVM crossbar array; 3) The original data is compressed by the computational part of the computational storage core and temporarily stored in the cache; 4) programming and storing the compressed data into the device of the NVM crossbar array storage part of the computational storage core; 5) Read out the compressed data stored in the storage part of the computational storage core and temporarily store it in the cache; 6) The compressed data is decompressed by the computational part of the computational storage core and temporarily stored in the cache; 7) Output the decompressed and restored data through an external communication interface.

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