In-Memory Computing Device and Its Operating Method

Abstract

The present disclosure relates to an in-memory computing device and an operation method thereof. The in-memory computing device includes: a memory array, which includes memory strings, source lines, word lines, and bit lines; the memory strings include a plurality of memory cells connected in series along a first direction, the memory cells include parallel memory transistors and bypass resistors, the memory strings are connected to the source lines through lower select transistors and to the bit lines through upper select transistors, and the control terminals of the memory cells are connected to the word lines; a driving and detecting circuit, connected to the source lines, the driving and detecting circuit is configured to inject a read current into the source lines, detect and output voltage signals of the source lines; and a peripheral circuit, connected to the word lines and the bit lines, the peripheral circuit is configured to control the voltages of the word lines and the bit lines. Computational tasks can be executed using the architecture of the memory array, operations can be performed on multiple memory strings in parallel, and by detecting voltage changes of the source lines corresponding to each memory cell, the calculation results can be read out from the source lines, achieving high computational efficiency.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and particularly to an in-memory computing device and an operation method thereof. Background Art

[0002] A Not AND Flash (NAND) is a non-volatile memory. The NAND Flash memory has advantages such as high storage density, low cost, long lifespan, and low power consumption, and is widely used in fields such as solid-state drives, USB flash drives, memory cards, and embedded systems.

[0003] Currently, the NAND Flash memory improves storage density through a vertically stacked method, and uses a vertical method to connect memory cells in series, thereby achieving higher storage density and lower cost. However, the computing parallelism and computing efficiency of the NAND Flash memory are very low, and how to effectively improve the computing efficiency of the NAND Flash is an urgent problem to be solved. Summary of the Invention

[0004] Based on this, it is necessary to provide an in-memory computing device and an operation method thereof for the problems in the prior art.

[0005] To achieve the above object, in a first aspect, the present disclosure provides an in-memory computing device, including:

[0006] A storage array, the storage array includes memory strings, source lines, word lines, and bit lines; the memory strings include a plurality of memory cells connected in series along a first direction, the memory cells include a memory transistor and a bypass resistor connected in parallel, the memory strings are connected to the source lines through a lower select transistor, and are connected to the bit lines through an upper select transistor, and the control ends of the memory cells are connected to the word lines;

[0007] A driving and detecting circuit, connected to the source line, the driving and detecting circuit is configured to inject a read current into the source line, detect and output a voltage signal of the source line;

[0008] A peripheral circuit, connected to the word line and the bit line, the peripheral circuit is configured to control the voltages of the word line and the bit line.

[0009] Optionally, the source line is disposed below the memory strings, the source line is arranged along a second direction and a third direction perpendicular to the first direction, and the source line is connected to the first ends of the lower select transistors of the memory strings;

[0010] The word lines are arranged along the first direction, and the word lines are connected to the control ends of the memory cells in the same layer;

[0011] The bit line is disposed above the memory string, the bit line extends along the second direction and is arranged along the third direction, and the bit line is connected to the second end of the upper select transistor of the memory string arranged along the second direction;

[0012] Among them, a plurality of the memory strings arranged along the second direction are respectively connected to a plurality of the source lines arranged along the second direction.

[0013] Optionally, the resistance value of the bypass resistor is greater than the channel equivalent resistance when the memory transistor is turned on and less than the channel equivalent resistance when the memory transistor is turned off.

[0014] Optionally, along the first direction, the driving and detecting circuit is integrated below the source line, and the peripheral circuit is integrated above the bit line; wherein, the driving and detecting circuit includes:

[0015] A current generation circuit for generating a read current;

[0016] A current mirror for copying the read current and injecting the read current into the source line;

[0017] A source follower for reading the voltage signal of the source line;

[0018] An analog-to-digital converter for converting the voltage signal into a digital signal and then outputting it.

[0019] Optionally, it further includes:

[0020] A control logic circuit, the control logic circuit is respectively connected to the driving and detecting circuit and the peripheral circuit;

[0021] The control logic circuit is configured to: according to the weight writing strategy, deploy weight information to the memory cell, and represent the weight information by the threshold voltage of the memory cell;

[0022] Apply a read voltage or a conduction voltage to the word line, and input a read current to the source line;

[0023] According to the voltage drop generated by the source line, calculate the number of the memory transistors turned off in the memory string, and output the calculation result.

[0024] In a second aspect, the present disclosure provides an operation method of an in-memory computing device, including:

[0025] According to the weight writing strategy, deploy weight information to the memory cell, and represent the weight information by the threshold voltage of the memory cell;

[0026] Apply a read voltage or a conduction voltage to the word line, and input a read current to the source line;

[0027] Calculate the number of off memory transistors in the memory string based on the voltage drop generated by the source line, and output the calculation result.

[0028] Optionally, the deploying the weight information to the memory cell according to the weight writing strategy and representing the weight information by the threshold voltage of the memory cell includes:

[0029] Encode each element of the weight matrix into a binary numerical weight "1" or weight "0";

[0030] According to the mapping relationship between the weight matrix and the memory cell, apply a programming voltage or an erase voltage to the memory cell corresponding to the weight element to adjust the threshold voltage of the memory cell to a high threshold voltage or a low threshold voltage, where the high threshold voltage corresponds to the weight "1" and the low threshold voltage corresponds to the weight "0".

[0031] Optionally, the applying a read voltage or a conduction voltage to the word line includes:

[0032] Encode each element of the activation vector into a binary numerical value;

[0033] According to the mapping relationship between the activation vector and the word line, apply the read voltage to the word line corresponding to the encoded activation value "1", and apply the conduction voltage to the word line corresponding to the encoded activation value "0", where the conduction voltage is greater than the read voltage.

[0034] Optionally, the applying a read voltage or a conduction voltage to the word line and inputting a read current to the source line further includes:

[0035] Adjust the voltage of the word line and the read current so that when the memory transistor is on, the current of the memory cell flows through the memory transistor, and when the memory transistor is off, the current of the memory cell flows through the bypass resistor, generating a voltage drop on both sides of the memory cell.

[0036] Optionally, the calculating the number of off memory transistors in the memory string based on the voltage drop generated by the source line and outputting the calculation result includes:

[0037] Perform a multiplication operation on the weight of the memory cell and the activation value of the word line connected to the memory cell to obtain a voltage drop of 1 or 0 for the memory cell;

[0038] Perform an addition operation on the voltage drops of the memory cells in the memory string to obtain the number of off memory transistors in the memory string.

[0039] The in-memory computing device and its operation method of the present disclosure have the following beneficial effects:

[0040] The in-memory computing device of the present disclosure integrates a storage array, a driving and detecting circuit, and a peripheral circuit, achieving a high degree of integration of data storage and computing. It can directly process data inside the storage array without reading the data to an external processor for calculation, avoiding the latency and energy consumption caused by data transmission to the outside. The in-memory computing device of this embodiment can execute computing tasks using the architecture of the storage array, can perform operations on multiple memory strings in parallel, and can read the calculation results from the source line by detecting the voltage change of the source line corresponding to each memory cell, achieving high computing efficiency.

[0041] The operation method of the in-memory computing device of the present disclosure utilizes the in-memory computing device to implement an in-memory computing strategy based on the voltage domain. It characterizes weight information by controlling the threshold voltage of the memory cell and quickly calculates the number of turned-off memory transistors in the memory string by detecting the voltage drop on the source line. This not only improves the computing parallelism and computing efficiency but also reduces the power consumption of data transmission, providing support for computing-intensive applications such as neural networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 It is a structural diagram of the in-memory computing device provided in an embodiment;

[0044] Figure 2 It is a circuit diagram of the storage array provided in an embodiment;

[0045] Figure 3 It is a circuit schematic diagram of the storage array provided in an embodiment;

[0046] Figure 4 It is a circuit diagram of the driving and detecting circuit provided in an embodiment;

[0047] Figure 5 It is a process schematic diagram of the operation method of the in-memory computing device of the memory provided in an embodiment;

[0048] Figure 6 It is a circuit diagram of the operation method of the in-memory computing device provided in an embodiment;

[0049] Figure 7 It is a weight coding schematic diagram provided in an embodiment;

[0050] Figure 8It is the internal structure diagram of the electronic device provided in an embodiment. Detailed implementation manners

[0051] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present disclosure is more thorough and comprehensive.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used in the description of this disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit this disclosure.

[0053] Modern computers usually adopt the von Neumann architecture with separated computing and storage, and data needs to be transmitted between the processor and the memory. In recent years, with the rapid development of artificial intelligence, the scale of neural network models has been continuously expanding. Among them, large language models (LLMs) based on the neural network structure (Transformer) with attention mechanism often have billions to trillions of parameters. Therefore, the computing requirements and data transfer needs during the inference process have increased sharply. At the same time, the demand for deploying large models on edge devices such as the artificial intelligence of things (AIoT), smartphones, and autonomous driving systems has also been continuously growing. In the case of limited storage and computing resources, prominent power consumption constraints, and strict latency requirements on the edge side, the von Neumann architecture that needs to frequently transfer data is inefficient. Existing in-memory computing solutions mostly adopt storage media such as resistive random access memory (RRAM) and static random access memory (SRAM), but these media have low storage density, limited array scale, and high manufacturing cost, and are not suitable for the potential computing requirements of edge-side large model inference.

[0054] However, due to its high storage density, low cost, large array scale, and multi-layer stacked structure, NAND Flash memory has great potential in storing model parameters, providing cheap computing power, and saving chip area. In NAND Flash in-memory computing, the current mainly adopted method is current-domain operation.

[0055] The calculation method of the current-domain operation method is similar to the operation of NAND Flash in the memory scenario. Among them, weights are stored in the array, activation values are input in the form of voltage amplitudes, and the multiply-accumulate results are output in the form of the sum of currents. However, the current-domain operation method can only activate one layer of memory cells each time when reading NAND Flash. A large number of memory cells cannot be effectively parallelized during in-memory computing. The single calculation of the current mainstream memory-computation strategy can only utilize 0.14% - 0.43% of the total number of cells in the array, and the computing parallelism and computing efficiency are very low.

[0056] According to an exemplary embodiment, the present disclosure provides an in-memory computing device, as Figure 1 shown, the in-memory computing device includes a storage array 100, a driving and detecting circuit 200, and a peripheral circuit 300.

[0057] As Figure 2 shown, the storage array 100 includes a storage string Str, a source line SL, a word line WL, and a bit line BL; the storage string Str includes a plurality of memory cells T-R connected in series along the first direction Y, the memory cell T-R includes a storage transistor T and a bypass resistor R connected in parallel, the storage string Str is connected to the source line SL through a lower select transistor BM, the storage string Str is connected to the bit line BL through an upper select transistor TM, and each storage string Str can be independently controlled and accessed through the source line SL and the bit line BL. The control end of the memory cell T-R (the gate of the storage transistor T) is connected to the word line WL, and the switching state of the storage transistor T in the memory cell T-R can be controlled by controlling the voltage change of the word line WL, so as to realize the read and write operations of data.

[0058] In this embodiment, each storage string Str includes n memory cells T-R (n≥1) vertically stacked along the first direction Z. Along the first direction Z, the storage transistors T of the plurality of memory cells T-R are connected in series in sequence along the first direction Z, and the bypass resistors R of the plurality of memory cells T-R are connected in series in sequence along the first direction Z. Along the plane perpendicular to the first direction Z, the storage transistor T includes a channel layer, a tunneling layer, a charge trapping layer, a gate dielectric layer, and a control gate that sequentially surround and cover the peripheral surface of the bypass resistor R.

[0059] Along the first direction Z, n word lines WL1-WL n are arranged at intervals and are respectively connected to the control gates of the n storage transistors T of the storage string Str.

[0060] The driving and detecting circuit 200 is connected to the source line SL, and the driving and detecting circuit 200 is configured to inject a read current I ref into the source line SL, detect the voltage signal of the source line SL, and convert the output voltage signal into a digital signal and then output it, which improves the efficiency and speed of data processing.

[0061] The peripheral circuit 300 is respectively connected to the word line WL and the bit line BL, and the peripheral circuit 300 is configured to control the voltages of the word line WL and the bit line BL. The peripheral circuit 300 is used to implement the read and write operations of the memory cell T-R and cooperate with the driving and detecting circuit 200 to implement data transmission.

[0062] The in-memory computing device of this embodiment integrates the memory array 100, the driving and detecting circuit 200, and the peripheral circuit 300, achieving a high degree of integration of data storage and computing. It can directly process data inside the memory array 100 without reading the data to an external processor for calculation, avoiding delays and energy consumption caused by data transmission to the outside. The in-memory computing device of this embodiment can execute computing tasks using the architecture of the memory array 100, can perform operations on multiple memory strings Str in parallel, and can read the calculation results from the source line by detecting the voltage change of the source line SL corresponding to each memory cell T-R, achieving high computing efficiency.

[0063] In some embodiments, as Figure 2 、 Figure 3 shown, the source line SL is disposed below the memory string Str, and the source line SL is arranged along the second direction Y and the third direction X perpendicular to the first direction Z. The source line SL is connected to the first end of the lower select transistor BM of the memory string Str. In this embodiment, the first end of the lower select transistor BM is the source end of the lower select transistor BM. The second direction Y and the third direction X are in a plane perpendicular to the first direction Z, and the second direction Y intersects the third direction X. In this embodiment, the second direction Y is perpendicular to the third direction X. For example, the source line SL is connected to the memory string Str one-to-one through the lower select transistor BM; or, multiple adjacent memory strings Str are connected to the same source line SL.

[0064] The word lines WL1 - WL n are arranged along the first direction Z, where each word line WL is connected to the control end of the memory cell T-R in the same layer.

[0065] The bit line BL is disposed above the memory string Str, and the bit line BL extends along the second direction Y and is arranged along the third direction X. The bit line BL is connected to the second end of the upper select transistor TM of the memory string Str arranged along the second direction Y. In this embodiment, the second end of the upper select transistor TM is the drain end of the upper select transistor TM.

[0066] In this embodiment, as Figure 2 、 Figure 3 shown, the memory array 100 further includes a lower select line SSL and an upper select line DSL. The lower select line SSL is disposed below the word lines WL1 - WL n and the lower select line SSL is connected to the control end of the lower select transistor BM; the upper select line DSL is disposed below the word lines WL1 - WL nAbove, the upper selection line DSL is connected to the control end of the upper selection tube TM.

[0067] Among them, as Figure 2 , Figure 3 shown, a plurality of memory strings Str arranged along the second direction Y are respectively connected to a plurality of source lines SL arranged along the second direction Y. In this way, on the one hand, the number of memory strings Str processed by each source line SL can be reduced, and on the other hand, each bit line BL can be connected to multiple memory strings Str, and a column of memory strings Str connected to the same bit line BL can be connected to multiple source lines SL, and parallel reading can be performed on a column of memory strings Str connected to the same bit line BL, thereby improving the reading bandwidth.

[0068] In the in-memory computing device of this embodiment, the source lines SL are arranged along the second direction Y and the third direction X, so that the source lines SL of each memory string Str can be separately led out, so that the in-memory computing device supports reading storage information through the source lines SL. Since the source lines SL of each storage block are independent of each other, there are hundreds or thousands of lead-out ports for the memory strings Str in the same column in the storage plane (Plane), thereby improving the parallel reading potential.

[0069] In some embodiments, the resistance value R of the bypass resistor R is greater than the channel equivalent resistance R when the memory transistor T is turned on on and less than the channel equivalent resistance R when the memory transistor T is turned off off .

[0070] In the in-memory computing device of this embodiment, by controlling the magnitudes of the word line voltage V WL and the threshold voltage V of the memory transistor T T , the switching state of the memory transistor T can be controlled. When the word line voltage V WL > V T , the memory transistor T is turned on, and the equivalent resistance value of the memory cell T-R is approximately equal to the channel equivalent resistance R when the memory transistor T is turned on on , and the current mainly passes through the memory transistor T; when V WL < V T , the memory transistor T is turned off, and the equivalent resistance value of the memory cell T-R is approximately equal to the resistance value R of the bypass resistor R, and the current mainly passes through the bypass resistor R. So that whether the memory transistor T is turned on or off, a current path can always be formed in the memory string Str where the memory cell T-R is located, so that when a read operation is performed on the memory cell T-R in the memory string Str, the number of turned-off transistors in the memory string Str can be calculated according to the voltage drop of the memory string Str.

[0071] In some embodiments, as Figure 1 shown, along the first direction Z, the driving and detecting circuit 200 is integrated below the source line SL, and the peripheral circuit 300 is integrated above the bit line BL.

[0072] In this embodiment, the CUA technology can be used to integrate the driving and detecting circuit 200 under the storage array 100. Through vias, the electrical connection between the storage array 100 and the driving and detecting circuit 200 can be achieved, ensuring the stable transmission of current and voltage signals, while maintaining the overall structural compactness and reliability of the in-memory computing device.

[0073] In this embodiment, the hybrid bonding technology (Hybrid-Bonding) can be used to integrate the peripheral circuit 300 above the storage array 100. The hybrid bonding technology ensures the high-precision and high-strength electrical and mechanical connection between the peripheral circuit 300 and the storage array 100, ensuring the stable interconnection between the peripheral circuit 300 and the storage array 100.

[0074] The peripheral circuit 300 may include a page buffer, a row decoder, a column decoder, a data writing circuit, a read sense amplifier circuit, a read-write control circuit, etc. Among them, the data writing circuit is used to write weights and input activation vectors to the storage array 100 to meet the requirements of in-memory computing.

[0075] It should be noted that the CUA technology, that is, complementary metal oxide semiconductor is arranged under the storage array (CMOS Under Array), is a design method that places the peripheral circuits of most NAND chips (such as page buffers, read amplifiers, charge pumps, etc.) under the vertical stack of memory cells. This layout greatly saves the integration space, enabling more area to be used for the memory cell array, thereby improving the storage density and performance.

[0076] In the in-memory computing device of this embodiment, the driving and detecting circuit 200 is integrated under the source line SL, and the peripheral circuit 300 is integrated above the bit line BL. The whole device is highly integrated, which can improve the performance of the memory, reduce its power consumption and cost, and also reduce the delay and interference of signal transmission, improving the read-write speed and reliability of the memory. The peripheral circuit 300 is integrated above the bit line BL, and the peripheral circuit 300 has an extended space, and the memory can flexibly adapt to different application scenarios and performance requirements, such as in-memory computing, high-speed storage, etc.

[0077] In some embodiments, as Figure 4 shown, the driving and detecting circuit 200 includes:

[0078] A current generation circuit 210, which is used to generate a read current I ref ; the current generation circuit 210 generates a constant read current I ref , and the stability and accuracy of the read current I ref are crucial for subsequent current replication and voltage reading.

[0079] Current mirror 220, which is used to copy the read current I ref and inject the read current I into the source line SL ref ; The current mirror 220 in this embodiment is a cascode current mirror, and the current mirror 220 copies the read current I generated by the current generation circuit 210 ref and injects it into the source line SL. In this embodiment, to save the area and power consumption cost of the drive and detection circuit 200, the current mirror 220 copies the read current I ref and then injects it into multiple source lines SL. On the one hand, the cascode current mirror ensures the high-precision copying of the read current I ref and reduces the mismatch error of the current mirror, thus ensuring that a stable current can be obtained on each source line SL. On the other hand, the cascode current mirror has a large output impedance and strong driving ability, which can ensure the stable transmission of the current, so that the output read current I ref has high stability and high precision.

[0080] Source follower 230, which is used to read the voltage signal of the source line SL; The source follower 230 acts as a voltage buffer to read the voltage value at the output end of the source line SL. The source follower 230 is also used to isolate the storage array 100 from the analog-to-digital converter 240 to prevent the high impedance inside the storage array 100 from interfering with the voltage reading

[0081] It should be noted that the input voltage range of the source follower 230 should match the storage array 100 to avoid large-range changes in the output voltage of the source line SL caused by multiple word lines WL, so as to ensure that the voltage reading is not distorted or saturated. In this embodiment, the source follower 230 uses a rail-to-rail operational amplifier

[0082] Analog-to-digital converter 240, which is used to convert the voltage signal into a digital signal and then output. The analog-to-digital converter 240 converts the analog voltage signal output by the source follower 230 into a digital signal for subsequent digital signal processing

[0083] In some embodiments, to save the area and power consumption cost of the drive and detection circuit 200, the source follower 230 and the analog-to-digital converter 240 can be shared by multiple source lines SL. The drive and detection circuit 200 further includes: a multiplexer MUX, which is used to select the source line SL that needs to be voltage-detected to achieve effective reuse of resources

[0084] Exemplarily, the analog-to-digital converter 240 uses a successive approximation register analog-to-digital converter (SAR ADC).

[0085] The in-memory computing device of this embodiment optimizes the driving and detecting circuit 200 so that the driving and detecting circuit 200 can inject a constant read current I into the source line SL ref and accurately read its voltage, providing a reliable basis for the voltage-domain in-memory computing operation of the in-memory computing device, and ensuring its effectiveness and reliability in in-memory computing applications.

[0086] In some embodiments, the in-memory computing device further includes: as Figure 1 shown, a control logic circuit 400. The control logic circuit 400 is respectively connected to the driving and detecting circuit 200 and the peripheral circuit 300. The control logic circuit 400 is connected to the driving and detecting circuit 200 to receive digital signals from the driving and detecting circuit 200, and the digital signals reflect the states of the memory cells T-R in the memory array 100. The control logic circuit 400 is connected to the peripheral circuit 300. The control logic circuit 400 controls the voltages of the word line WL and the bit line BL through the peripheral circuit 300, thereby implementing the read and write operations of the memory cells T-R.

[0087] The control logic circuit 400 is configured to: according to the weight writing strategy, deploy weight information to the memory cells T-R, and represent the weight information by the threshold voltages of the memory cells T-R. For example, different threshold voltages can correspond to different weight values to implement writing data to the memory cells T-R; apply a read voltage V read or a conduction voltage V pass to the word line WL, and input a read current I to the source line ref ; calculate the number of turned-off memory transistors T in the memory string Str according to the voltage drop ΔV generated by the source line SL, and output the calculation result. When the read current I ref passes through the memory string Str, due to the different switching states (i.e., different threshold voltages) of the memory transistors T, a corresponding voltage drop will be generated on the source line SL. The control logic circuit 400 detects the voltage drop ΔV and calculates the number of turned-off memory transistors T in the memory string Str according to the magnitude of the voltage drop ΔV. The control logic circuit 400 outputs the calculation result for subsequent processing or applications.

[0088] The control logic circuit 400 uses the ONFI 5.0 protocol to achieve data transmission between the driving and detecting circuit 200 and the peripheral circuit 300. The control logic circuit 400 uses the PCIe 5.0 protocol to communicate with the terminal.

[0089] The in-memory computing device of this embodiment deploys weight information and calculates and outputs the voltage drop ΔV through the control logic circuit 400. Taking the word line WL as the input port and the source line SL as the output port, by applying different read voltages V to each word line WL readand the conduction voltage V pass , injecting a read current I into the source line SL ref , enabling the device to directly execute computational tasks inside the memory cell T-R, achieving parallel computing of data in the memory cell T-R, being able to process multiple data values simultaneously, and further improving the computing efficiency.

[0090] According to an exemplary embodiment, the present disclosure provides an operation method for an in-memory computing device. The operation method of this embodiment is executed based on the in-memory computing device of the above embodiment. As Figure 5 shown, the operation method of the in-memory computing device includes the following steps S101 to step S103. Among them:

[0091] Step S101: According to the weight writing strategy, deploy the weight information to the memory cell, and represent the weight information by the threshold voltage of the memory cell;

[0092] In this embodiment, referring to Figure 6 、 Figure 7 , and in combination with referring to Figures 1-4 , the control logic circuit 400 deploys the weight information to the memory cell according to the weight writing strategy. Among them, the weight information can be generated by a terminal (such as a neural network processor, a central processing unit, etc.) and transmitted to the control logic circuit 400, or the weight information can be stored in an external database, and the control logic circuit 400 obtains the weight information by accessing the database.

[0093] The weight writing strategy can also be stored in the database. The weight writing strategy defines how to map the weight information to the threshold voltage of the memory cell T-R. The control logic circuit 400 obtains the weight writing strategy by accessing the database.

[0094] The control logic circuit 400 adjusts the voltages of the bit line BL and the word line WL according to the weight writing strategy through the peripheral circuit 300 to set the threshold voltage of the memory cell T-R, thereby representing the weight information, corresponding to deploy the weight information to the memory cell T-R of the memory array 100, and the threshold voltage of the memory transistor T of the memory cell T-R is set to a value corresponding to the weight information.

[0095] Step S102: Apply a read voltage or a conduction voltage to the word line and input a read current to the source line;

[0096] In this embodiment, referring to Figure 6 、 Figure 7 , and in combination with referring to Figures 1-4 , the control logic circuit 400 controls the peripheral circuit 300 to apply a read voltage V read or a conduction voltage V pass to the word line WL; the read voltage V readFor reading the state of the memory cell T-R, while the conduction voltage V pass For conducting the memory transistor T of the memory cell T-R when needed. The control logic circuit 400 controls the driving and detecting circuit 200 to input a read current I to the source line SL that needs to be detected ref The read current I ref For generating a voltage drop ΔV in the memory string Str, so as to reflect the state of the memory cell T-R.

[0097] In this embodiment, the control logic circuit 400 can input an activation vector corresponding to each word line WL to the peripheral circuit 300, and the activation vector determines the word line WL in the memory array 100 that receives the read voltage and the word line WL that receives the conduction voltage V pass of the word line WL.

[0098] Step S103: Calculate the number of turned-off memory transistors in the memory string according to the voltage drop generated by the source line, and output the calculation result.

[0099] In this embodiment, referring to Figure 6 、 Figure 7 and in combination with referring to Figures 1-4 , the driving and detecting circuit 200 calculates the number of turned-off memory transistors T in the memory string Str according to the voltage drop ΔV generated by the source line SL. The magnitude of the voltage drop ΔV is directly related to the number of turned-off memory transistors T in the memory string Str. According to the voltage drop ΔV generated on the source line SL, the driving and detecting circuit 200 calculates the number of turned-off memory transistors T in the memory string Str and outputs the calculation result to the control logic circuit 400. The control logic circuit 400 can further process the calculation result and transmit it to the terminal or other processing units for subsequent use. Among them, the terminal can be but is not limited to various personal computers, laptop computers, smart phones, tablet computers, Internet of Things devices and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart vehicle-mounted devices, projection devices, etc. The portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc.

[0100] The operation method of the in-memory computing device in this embodiment uses the in-memory computing device to implement the in-memory computing strategy based on the voltage domain, represents the weight information by controlling the threshold voltage of the memory cell T-R, and quickly calculates the number of turned-off memory transistors T in the memory string Str by detecting the voltage drop ΔV on the source line SL. It not only improves the computing parallelism and computing efficiency, but also reduces the power consumption of data transmission, providing support for computing-intensive applications such as neural networks.

[0101] In some embodiments, step S101 deploys the weight information to the memory cell according to the weight writing strategy, and represents the weight information by the threshold voltage of the memory cell, including steps S101-1 - step S101-2:

[0102] Step S101-1: Encoding each element of the weight matrix into a binary numerical weight "1" or weight "0".

[0103] In this embodiment, referring to Figure 7 , the weight matrix can be generated by the terminal or stored in an external database. The terminal encodes each element of the weight matrix into a binary numerical weight "1" or weight "0". For each element in the weight matrix, according to its numerical value, it is encoded into binary form, for example, it can be obtained through neural network training.

[0104] In this embodiment, the weight matrix is a floating-point weight matrix, and the weights in the weight matrix are represented by floating-point numbers. Through neural network training, after quantization (selection of quantization range, determination of quantization bits), scaling, and rounding operations, the continuous floating-point weights are converted into discrete binary numerical values.

[0105] Step S101-2: According to the mapping relationship between the weight matrix and the storage unit, applying a programming voltage or an erasing voltage to the storage unit corresponding to the weight element, and adjusting the threshold voltage of the storage unit to a high threshold voltage or a low threshold voltage, where the high threshold voltage corresponds to the weight "1" and the low threshold voltage corresponds to the weight "0".

[0106] In this embodiment, referring to Figure 7 , the mapping relationship between the weight matrix and the storage unit is an address mapping mechanism between each element of the weight matrix and the storage unit T-R of the storage array 100, to ensure that each weight element can uniquely correspond to a storage unit T-R. The mapping relationship between the weight matrix and the storage unit can be generated by the terminal or stored in the database.

[0107] The control logic circuit 400 controls the peripheral circuit 300 to apply a programming voltage or an erasing voltage to the storage unit T-R according to the weight encoded as a binary numerical value in the weight matrix and the mapping relationship between the weight matrix and the storage unit T-R. The storage transistor T of the storage unit T-R will enter the corresponding programming state or erasing state, so as to store the weight information in the form of the threshold voltage.

[0108] In this embodiment, an erasing voltage is applied to each word line WL of the storage array 100. Then, for the storage unit T-R corresponding to the weight "1", the control logic circuit 400 controls the peripheral circuit 300 to apply a programming voltage to the corresponding word line WL to adjust its threshold voltage to a high threshold voltage V T,H . So that the threshold voltage of the storage unit T-R corresponding to the weight "1" is the high threshold voltage V T,H , and the threshold voltage of the storage unit T-R corresponding to the weight "0" is the low threshold voltage V T,L .

[0109] Before the calculation starts in this embodiment, all elements of the weight matrix are bitwise encoded and deployed to corresponding positions in the storage array 100. In this way, each memory cell T-R stores 1 bit of information of its corresponding weight element through the storage transistor T, and the information of the weight element is represented by two threshold voltage states of the storage transistor T. Among them, the high threshold voltage V T,H corresponds to the weight "1" and the low threshold voltage V T,L corresponds to the weight "0", which provides a basis for subsequent in-memory computing, enabling the weight information to directly participate in the calculation in the memory cell T-R, thereby improving the computing efficiency and reducing the power consumption.

[0110] In some embodiments, applying a read voltage or a conduction voltage to the word line in step S102 includes steps S102-1 - step S102-2:

[0111] Step S102-1: Encoding each element of the activation vector into a binary value;

[0112] In this embodiment, the activation vector can be generated by the terminal, or the activation vector can be stored in the database, and the terminal accesses the database to obtain the activation vector. The terminal encodes each element of the activation vector into a binary value, an activation value "1" or an activation value "0". Similarly, the encoding process of the activation vector can be obtained through neural network training.

[0113] In this embodiment, the activation vector is a floating-point activation value matrix, and the activation values in the activation vector are represented as floating-point numbers. Through external input or generated by the previous layer of neural network, after quantization (selection of quantization range, determination of quantization bits), scaling, and rounding operations, the continuous floating-point activation values are converted into discrete binary values.

[0114] Step S102-2: According to the mapping relationship between the activation vector and the word line, apply a read voltage to the word line corresponding to the encoded activation value "1" of the activation vector, and apply a conduction voltage V pass to the word line corresponding to the encoded activation value "0" of the activation vector. The conduction voltage V pass is greater than the read voltage V read .

[0115] In this embodiment, the mapping relationship between the activation vector and the word line is an address mapping mechanism between each element of the activation vector and each word line WL, to ensure that each activation vector can uniquely correspond to a word line WL. The mapping relationship between the weight activation vector and the word line WL can be generated by the terminal or stored in the database.

[0116] The control logic circuit 400 controls the peripheral circuit 300 to input the read voltage V read or the conduction voltage V to the corresponding word line WL according to the activation value after encoding the activation vector and the mapping relationship between the activation vector and the word line.pass .

[0117] For the encoded activation value "1", the control logic circuit 400 controls the peripheral circuit 300 to apply a read voltage V to the corresponding word line WL read . The read voltage V read can keep the memory transistor T connected to the word line WL and having a low threshold voltage (i.e., storing the weight "0") in a conducting state, but will turn off the memory transistor T having a high threshold voltage (i.e., storing the weight "1").

[0118] For the encoded activation value "0", the control logic circuit 400 controls the peripheral circuit 300 to apply a higher voltage, i.e., a conduction voltage V, to the corresponding word line WL pass . The conduction voltage V pass ensures that the memory transistor T remains in a conducting state regardless of whether its threshold voltage is high or low.

[0119] It should be noted that the conduction voltage V pass is greater than the read voltage V read to ensure that the memory transistor T can be successfully turned on when the activation value is "0".

[0120] In this embodiment, V T,L < V read < V T,H < V pass . When and only when the threshold voltage of the memory transistor T is equal to V T,H and the word line voltage is equal to V read , the memory transistor T in the memory cell T-R is in an off state and a voltage drop is generated across the memory cell T-R. In other cases, the memory transistor T is conducting.

[0121] This embodiment maps the information of the activation vector to the voltage of the word line WL, providing a basis for subsequent in-memory computing, enabling the activation value to directly participate in the computing in the memory cell T-R, thereby improving the computing efficiency and reducing the power consumption.

[0122] In some embodiments, when applying the read voltage V read or the conduction voltage V pass to the word line WL and inputting a read current I ref to the source line SL, it further includes: adjusting the voltage of the word line WL and the read current I ref so that when the memory transistor T is conducting, the current of the memory cell T-R flows through the memory transistor T, and when the memory transistor T is off, the current of the memory cell T-R flows through the bypass resistor R, generating a voltage drop ΔV across the memory cell T-R.

[0123] The voltage drop ΔV generated by the off - storage transistor T accumulates along the storage string Str, and finally forms an output voltage V on the source line SL. SL , the output voltage V SL is proportional to the number of off - storage transistors T in the storage string Str. The number of off - storage transistors T in the storage string Str is equal to the value obtained by summing the multiplication of the storage cells T - R in the storage string Str and the WL input information.

[0124] In some embodiments, step S103 calculates the number of off - storage transistors T in the storage string Str according to the voltage drop ΔV generated by the source line SL and outputs the calculation result, including steps S103 - 1 - S103 - 2:

[0125] Step S103 - 1: Perform a multiplication operation on the weight of the storage cell and the activation value of the word line connected to the storage cell, and obtain that the voltage drop of the storage cell is 1 or 0.

[0126] In this embodiment, the control logic circuit 400 performs a multiplication operation on the weight of the storage cell T - R and the activation value of the word line WL connected to the storage cell T - R. The weight of the storage cell T - R is "1" (that is, when the storage transistor T of the storage cell T - R is off), and the activation value of the word line WL connected to the storage cell T - R is "1" (the word line WL is applied with the read voltage V read ), and the voltage drop of the storage cell T - R is obtained as 1.

[0127] The weight of the storage cell T - R is "0" (that is, when the storage transistor T of the storage cell T - R is on) and / or the activation value of the word line WL connected to the storage cell T - R is "zero" (the word line WL is applied with the on - voltage V pass ), and the voltage drop of the storage cell T - R is obtained as 0.

[0128] Step S103 - 2: Perform an addition operation on the voltage drops of the storage cells in the storage string to obtain the number of off - storage transistors in the storage string.

[0129] In this embodiment, based on the architecture of the storage array 100 itself, the voltage drops of all the storage cells T - R in the storage string Str are accumulated and added. Since each storage cell T - R with an off - storage transistor T will generate a voltage drop in the storage string Str, the result of the addition operation can represent the number of off - storage transistors T in the storage string Str.

[0130] For example, there are n storage cells T-R in the storage string Str. Among them, the storage transistors T of m storage cells T-R are turned off. Then, these m turned-off storage transistors T will generate m voltage drops, and these voltage drops will be accumulated together to obtain the total voltage drop value of the storage string Str. According to the total voltage drop value, the number m of the turned-off storage transistors T in the storage string Str can be obtained.

[0131] The operation method of the in-memory computing device in this embodiment realizes obtaining the calculation result of vector matrix multiplication (VMM) presented in the form of voltage by injecting a constant read current I into the storage string Str ref , grounding all the bit lines BL, and detecting the voltage of the source line SL, which improves the detection accuracy and provides strong support for the further application and development of the VMM technology.

[0132] To facilitate further understanding of the solution of the present disclosure, refer to Figures 1-7 , an exemplary in-memory computing device and its operation method of the present disclosure are as follows:

[0133] In the in-memory computing device of this embodiment, the stacked storage N of the storage array 100 is 232, that is, each storage string Str includes 232 vertically stacked storage cells T-R, and the storage array 100 includes 232 word lines WL1-WL 232 .

[0134] Each storage string Str is connected to a source line SL through a select-down transistor BM, and the storage string Str and the source line SL are connected in one-to-one correspondence. In this embodiment, the source lines SL corresponding to the storage cells Str of the same storage page are independently led out, and each storage page has m storage strings Str, which are correspondingly connected to m source lines SL1-SLm. Exemplarily, each storage page contains 128k storage strings Str, and the 128k storage strings Str of each storage page are respectively connected to 128k source lines, that is, the total number m of output ports is 128k.

[0135] In other embodiments, 3 to 4 storage strings Str arranged in sequence in the same storage page can share one output port, which has a lower manufacturing process difficulty and a lower manufacturing cost.

[0136] Each storage cell T-R includes a storage transistor T and a bypass resistor R connected in parallel with the storage transistor T. Along the first direction Z, the storage transistors T of the storage string Str are connected in series in sequence, and the bypass resistors R are connected in series in sequence.

[0137] The resistance value R of the bypass resistor R is much larger than the channel equivalent resistance R when the storage transistor T is turned on on , and much smaller than the channel equivalent resistance R when the storage transistor T is turned off off。

[0138] The channel equivalent resistance R when the storage transistor T is turned off off is approximately infinite. In this embodiment, the resistance value R of the bypass resistor R of the storage cell T-R satisfies R on << R << R off requirements.

[0139] When performing the operation method on the in-memory computing device of this embodiment, the word line WL is used as the input port, and the source line SL is used as the output port.

[0140] According to the weight writing strategy, the weight information is deployed to the storage cell T-R, and the weight information is represented by the threshold voltage of the storage transistor T of the storage cell T-R.

[0141] According to the correspondence between the activation vector and the word line WL, the activation value is correspondingly input to the word line WL, and a read voltage V read or a conduction voltage V pass is applied to the word line WL; and a read current I ref is input to the source line SL.

[0142] When the storage transistor T of a certain layer of storage cells T-R is turned off, a voltage drop ΔV = I ref ·R is generated across the storage cell T-R. These voltage drops are accumulated along the storage string Str, and finally the voltage V SL is output through the source line SL. The magnitude of the output voltage V SL is proportional to the number of turned-off storage transistors T in the storage string Str.

[0143] In the operation method of this embodiment, the number of storage cells T-R that can participate in the calculation in parallel at one time is the product of the total number of word lines WL and the total number of source lines SL, that is, n×m. Combining with the horizontal expansion of the storage array 100, the total number of storage cells T-R that can actually participate in parallel is equal to the total number of all storage cells T-R in the storage array 100. For example, for a four-level storage array (Quad-Level Cell, QLC) with a storage capacity of 1Tb, the total number of parallel cells can reach 256M, and the upper limit of the parallelism of the in-memory computing strategy is greatly improved. The in-memory computing strategy based on the voltage domain in this embodiment increases the parallel potential by several times compared to the original.

[0144] In some embodiments, an electronic device is provided, as shown in Figure 8 . The electronic device can be a terminal. The electronic device includes a controller and a processor. The controller stores a computer program, and when the processor executes the computer program, the steps of the operation method of the in-memory computing device in the above embodiment are implemented.

[0145] The internal structure diagram of the electronic device can be as shown in Figure 8As shown. The electronic device includes a processor, a controller, an input / output interface (Input / Output, abbreviated as I / O), and a communication interface. Among them, the processor, the controller, and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the electronic device is used to provide computing and control capabilities. The controller of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the electronic device is used to exchange information between the processor and external devices. The communication interface of the electronic device is used to communicate with external terminals through a network connection. When the computer program is executed by the processor, it implements an operation method of an in-memory computing device.

[0146] Those skilled in the art can understand that Figure 8 the structure shown in [the figure] is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the electronic device to which the solution of this application is applied. The specific electronic device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0147] It should be noted that the information (including but not limited to electronic device information) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data that have been permitted by the user or fully permitted by all parties, and the collection, use, and processing of relevant data need to comply with relevant regulations.

[0148] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a controller, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memories can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memories can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., and are not limited thereto. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, etc., and are not limited thereto.

[0149] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0150] The above embodiments only represent several implementation manners of the present disclosure. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. An in-memory computing device, characterized in that: include: A storage array, comprising: A memory string comprising a plurality of memory cells connected in series along a first direction, wherein the memory cells include memory transistors and bypass resistors connected in parallel; a source line disposed below the memory string, the source line being arranged along a second direction and a third direction perpendicular to the first direction, the memory string being connected to the source line via a lower gate transistor, the source line being connected to a first end of the lower gate transistor of the memory string; a plurality of the memory strings arranged along the second direction being respectively connected to the plurality of source lines arranged along the second direction; word lines, arranged along the first direction, the word lines being connected to control terminals of the memory cells in the same layer; a bit line provided above the memory strings, the bit line extending along the second direction and arranged along the third direction, the memory strings being connected to the bit line via upper gate transistors, the bit line being connected to second ends of the upper gate transistors of the memory strings arranged along the second direction; a driving and detecting circuit connected to the source line, wherein the driving and detecting circuit is configured to inject a read current into the source line, detect and output a voltage signal of the source line; The peripheral circuit is connected to the word line and the bit line, and is configured to control the voltages of the word line and the bit line.

2. The in-memory computing device according to claim 1, wherein: The resistance value of the bypass resistor is greater than the channel equivalent resistance when the storage transistor is turned on, and is less than the channel equivalent resistance when the storage transistor is turned off.

3. The in-memory computing device according to claim 1, wherein: Along the first direction, the driving and detecting circuit is integrated below the source line, and the peripheral circuit is integrated above the bit line; wherein the driving and detecting circuit includes: a current generating circuit for generating a reading current; a current mirror, configured to replicate the read current and inject the read current into the source line; a source follower, configured to read the voltage signal of the source line; The analog-to-digital converter is used to convert the voltage signal into a digital signal and output it.

4. The in-memory computing device according to claim 3, wherein: The source follower and the analog-to-digital converter are shared by a plurality of source lines; The driving and detecting circuit further includes a multiplexer, and the multiplexer is used to select the source line for voltage detection.

5. The in-memory computing device according to claim 1, wherein: Also includes: a control logic circuit, the control logic circuit being connected to the driving and detecting circuits and the peripheral circuits respectively; The control logic circuit is configured to: deploy the weight information to the storage unit according to the weight writing strategy, and represent the weight information with the threshold voltage of the storage unit; applying a read voltage or a turn-on voltage to the word line and inputting a read current to the source line; The number of the memory transistors turned off in the memory string is calculated according to the voltage drop generated by the source line, and the calculation result is output.

6. A method for operating an in-memory computing device, applied to the in-memory computing device according to any one of claims 1 to 5, characterized in that: The operation method includes: Deploy the weight information to a storage unit according to a weight writing strategy, and use the threshold voltage of the storage unit to represent the weight information as weight "1" or weight "0"; Applying a read voltage or a turn-on voltage to the word line and inputting a read current to the source line, so that the memory transistors in the memory string to which the read voltage is applied and which store a weight of "0" are turned off, and the other memory transistors are turned on; The number of the memory transistors turned off in the memory string is calculated according to the voltage drop generated by the source line, and the calculation result is output.

7. The method for operating an in-memory computing device according to claim 6, wherein: The step of deploying the weight information to a storage unit according to a weight writing strategy and representing the weight information with a threshold voltage of the storage unit includes: Encode each element of the weight matrix as a binary value weight "1" or weight "0"; According to the mapping relationship between the weight matrix and the storage cell, a programming voltage or an erasing voltage is applied to the storage cell corresponding to the weight element to adjust the threshold voltage of the storage cell to a high threshold voltage or a low threshold voltage, wherein the high threshold voltage corresponds to a weight of "1" and the low threshold voltage corresponds to a weight of "0".

8. The method for operating an in-memory computing device according to claim 7, wherein: Applying a read voltage or a turn-on voltage to the word line includes: Encode each element of the activation vector into a binary value; According to the mapping relationship between the activation vector and the word line, the read voltage is applied to the word line corresponding to the encoded activation value "1", and the turn-on voltage is applied to the word line corresponding to the encoded activation value "0", and the turn-on voltage is greater than the read voltage.

9. The method for operating an in-memory computing device according to claim 6, wherein: The step of applying a read voltage or a turn-on voltage to the word line and inputting a read current to the source line further includes: The voltage of the word line and the read current are adjusted so that when the storage transistor is turned on, the current of the storage cell flows through the storage transistor, and when the storage transistor is turned off, the current of the storage cell flows through the bypass resistor, generating a voltage drop on both sides of the storage cell.

10. The method for operating an in-memory computing device according to claim 9, wherein: Calculating the number of the storage transistors turned off in the storage string according to the voltage drop generated by the source line and outputting the calculation result includes: Performing a multiplication operation on the weight of the memory cell and the activation value of the word line connected to the memory cell, so as to obtain a voltage drop of the memory cell as 1 or 0; An addition operation is performed on the voltage drops of the memory cells of the memory string to obtain the number of the memory transistors in the memory string that are turned off.

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