A field effect transistor screening method and system

Abstract

The present invention provides a field effect transistor screening method and system, relating to the technical field of data processing. The method includes: collecting the electrical characteristic signals of the field effect transistor; performing denoising processing on the electrical characteristic signals through a discrete wavelet transform algorithm to obtain denoised electrical characteristic signals; extracting multiple time-domain features from the denoised electrical characteristic signals; screening the main features related to the health of the field effect transistor through a graph attention network model to generate a relevant feature set; constructing a field effect transistor screening model based on a random forest according to the relevant feature set; adjusting the number of decision trees in the field effect transistor screening model based on the random forest according to the importance of the relevant features; training the field effect transistor screening model by using a training set composed of each relevant feature set; obtaining the electrical characteristic signals of the field effect transistor to be screened; and inputting the electrical characteristic signals of the field effect transistor to be screened into the trained field effect transistor screening model to screen out abnormal field effect transistors.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and particularly to a field effect transistor screening method and system. Background Art

[0002] The field effect transistor is an important electronic component, mainly used for amplifying and switching signals. The field effect transistor is widely used in various electronic devices, such as amplifiers, switching circuits, etc. The field effect transistor screening method is to collect the electrical characteristic signals of the field effect transistor and use some algorithms (such as denoising, feature extraction, principal component analysis, etc.) to determine whether the field effect transistor has problems or is in a normal working state.

[0003] The field effect transistor is a core component in many electronic devices, responsible for signal amplification and switching operations. If the field effect transistor has defects or abnormalities, it may cause the circuit to fail to work properly, affecting the function of the entire system. Therefore, by screening healthy field effect transistors, the reliability and stability of the device during use can be ensured, and the performance degradation or failure of the device caused by unqualified or abnormal field effect transistors can be avoided, which is of great significance for enhancing the brand's reputation and market competitiveness.

[0004] However, the existing field effect transistor screening methods usually rely on manual judgment and analysis of test results, resulting in low efficiency and being easily affected by human errors, making it difficult to meet the requirements of rapid production and high-efficiency screening. Secondly, the electrical characteristics of field effect transistors are relatively complex, and traditional screening methods often only rely on some basic current and voltage tests, unable to comprehensively capture all factors affecting the performance of field effect transistors, resulting in some potential abnormalities not being detected, thus leading to insufficient classification accuracy and reliability. Summary of the Invention

[0005] In order to solve the technical problems that the existing field effect transistor screening methods usually rely on manual judgment and analysis of test results, resulting in low efficiency and being easily affected by human errors, making it difficult to meet the requirements of rapid production and high-efficiency screening, and unable to comprehensively capture all factors affecting the performance of field effect transistors, resulting in some potential abnormalities not being detected, thus leading to insufficient classification accuracy and reliability, the present invention provides a field effect transistor screening method and system.

[0006] The technical solutions provided by the embodiments of the present invention are as follows:

[0007] First aspect:

[0008] A field effect transistor screening method provided by an embodiment of the present invention includes:

[0009] S1: Collect the electrical characteristic signals of the field effect transistor and determine the labels corresponding to the electrical characteristic signals;

[0010] S2: Denoise the electrical characteristic signal through the discrete wavelet transform algorithm to obtain the denoised electrical characteristic signal;

[0011] S3: Extract multiple time-domain features from the denoised electrical characteristic signal;

[0012] S4: Screen the time-domain features related to the health of the field effect transistor through the graph attention network model to generate a relevant feature set;

[0013] S5: Construct a field effect transistor screening model based on random forest according to the relevant feature set;

[0014] S6: Adjust the number of decision trees in the field effect transistor screening model according to the importance of the relevant features in the relevant feature set;

[0015] S7: Train the field effect transistor screening model using the training set composed of the relevant feature set until the classification accuracy of the field effect transistor screening model is greater than the preset classification accuracy;

[0016] S8: Obtain the electrical characteristic signal of the field effect transistor to be screened;

[0017] S9: Input the electrical characteristic signal of the field effect transistor to be screened into the trained field effect transistor screening model to screen out abnormal field effect transistors.

[0018] Second aspect:

[0019] A field effect transistor screening system provided by an embodiment of the present invention includes:

[0020] A processor;

[0021] A memory, on which computer-readable instructions are stored. When the computer-readable instructions are executed by the processor, the field effect transistor screening method as in the first aspect is implemented.

[0022] Third aspect:

[0023] A computer-readable storage medium provided by an embodiment of the present invention, on which a computer program is stored. When the program is executed by the processor, the field effect transistor screening method as in the first aspect is implemented.

[0024] The beneficial effects brought by the technical solutions provided by the embodiments of the present invention at least include:

[0025] In an embodiment of the present invention, first, the electrical characteristic signals of the field effect transistor are collected, and through the discrete wavelet transform algorithm, the electrical characteristic signals are denoised, and multiple time-domain features in the denoised electrical characteristic signals are extracted, so as to provide useful information for feature screening and model training. Then, through the graph attention network model, the main features related to the health of the field effect transistor are screened to generate a relevant feature set. According to the relevant feature set, a field effect transistor screening model based on random forest is constructed, and according to the importance of the relevant features, the number of decision trees in the field effect transistor screening model based on random forest is adjusted until the classification accuracy of the field effect transistor screening model is greater than the preset classification accuracy, ensuring that the model can make accurate classification judgments based on the existing data. Finally, the electrical characteristic signals of the field effect transistor to be screened are obtained, and the electrical characteristic signals of the field effect transistor to be screened are input into the trained field effect transistor screening model to screen out abnormal field effect transistors, thereby realizing precise screening, reducing the complexity and subjectivity of manual screening, improving the screening efficiency and accuracy, ensuring the generalization ability of the model, and being able to cope with the challenges in different field effect transistor screenings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0027] Figure 1 It is a schematic flowchart of a method for screening field effect transistors provided by an embodiment of the present invention;

[0028] Figure 2 It is a schematic structural diagram of a system for screening field effect transistors provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] The following describes the technical solutions in the present invention with reference to the drawings.

[0030] In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "example" in the present invention should not be interpreted as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, the use of the word "example" is intended to present concepts in a specific way. In addition, in the embodiments of the present invention, the meaning expressed by "and / or" can be both, or either one of the two.

[0031] In the embodiments of the present invention, the terms "image" and "picture" can sometimes be used interchangeably. It should be noted that when not emphasizing the difference, they convey the same meaning. The terms "of", "corresponding", and "corresponding to" can sometimes be used interchangeably. It should be noted that when not emphasizing the difference, they convey the same meaning.

[0032] In the embodiments of the present invention, sometimes a subscript such as W1 may be written in a non-subscript form such as W1. When not emphasizing the difference, they convey the same meaning.

[0033] To make the technical problems to be solved, technical solutions, and advantages of the present invention clearer, the following will be described in detail with reference to the accompanying drawings and specific embodiments.

[0034] Refer to the attached Figure 1 illustrates a schematic flowchart of a method for screening field effect transistors provided by an embodiment of the present invention.

[0035] The embodiments of the present invention provide a method for screening field effect transistors. This method can be implemented by a field effect transistor screening device, which can be a terminal or a server. The processing flow of the field effect transistor screening method can include the following steps:

[0036] S1: Collect the electrical characteristic signals of the field effect transistor and determine the corresponding labels for the electrical characteristic signals.

[0037] Among them, a field effect transistor is a three-terminal semiconductor device that uses an electric field to control current. It is widely used in electronic circuits, especially suitable for amplifying, switching, and regulating signals. The electrical characteristic signals refer to the signals that describe the performance of the field effect transistor (FET), including gate voltage, drain current, on-resistance, temperature coefficient, and switching speed. These signals can reflect the working state and performance of the field effect transistor. The label is used to mark or indicate the relationship between the signal and the actual state of the field effect transistor, and is usually related to whether the field effect transistor is healthy or its performance is normal.

[0038] It should be noted that by collecting the electrical characteristic signals of the field effect transistor and assigning labels to these signals, a foundation is laid for subsequent data processing and model training. By collecting representative electrical characteristic signals, the working state of the field effect transistor can be comprehensively understood to ensure the accuracy and reliability of the data used in subsequent steps.

[0039] In a possible implementation manner, the electrical characteristic signals specifically include: gate voltage, drain current, on-resistance, temperature coefficient, and switching speed.

[0040] Among them, the gate voltage is the voltage applied to the gate terminal of the field-effect transistor, the drain current is the current flowing between the drain terminal and the source terminal of the field-effect transistor, and the on-resistance refers to the resistance between the source and the drain when the field-effect transistor is fully turned on. The temperature coefficient is the ratio that describes how a certain physical quantity (such as current, resistance, power, etc.) changes with temperature, and the switching speed refers to the time required for the field-effect transistor to switch from one operating state to another.

[0041] S2: By using the discrete wavelet transform algorithm, denoise the electrical characteristic signal to obtain the denoised electrical characteristic signal.

[0042] Among them, the discrete wavelet transform algorithm is a signal processing method that analyzes the signal by decomposing it into multiple sub-signals of different frequencies. The denoised electrical characteristic signal refers to removing the noise components in the signal to restore or improve the signal quality.

[0043] It should be noted that denoising the signal through the discrete wavelet transform (DWT) makes the signal smoother and more accurate. The wavelet transform can effectively separate the noise components in the signal and retain the important feature information, thereby improving the quality of subsequent feature extraction.

[0044] In a possible implementation manner, S2 specifically includes:

[0045] S201: Add white noise to the electrical characteristic signal:

[0046]

[0047] Among them, s(n) represents the noisy signal at the nth sampling point, f(n) represents the original signal at the nth sampling point, σ represents the noise intensity, and e(n) represents the Gaussian white noise at the nth sampling point.

[0048] S202: Decompose the electrical characteristic signal with added white noise through the wavelet basis function to obtain the signal coefficients:

[0049] W r,k (a,b)= ∑ n 1 2 r s[n] ψ * 2 -r n-k

[0050] Among them, W r,k (a,b) represents the signal coefficient calculated through the discrete wavelet transform (DWT) at scale a and position b, r represents the scale index, k represents the position index, represents the conjugate complex number of the mother wavelet.

[0051] S203: Perform soft-threshold processing on the decomposed signal coefficients to remove the noise of the electrical characteristic signal:

[0052]

[0053] Among them, y represents the signal after soft-threshold processing, x represents the signal coefficient, sign represents the sign function, represents the absolute value symbol, and λ represents the threshold parameter.

[0054] S204: Reconstruct the denoised electrical characteristic signal through inverse discrete wavelet transform to obtain the denoised electrical characteristic signal.

[0055] It should be noted that in the screening of field effect transistors, the denoised signal can more truly reflect the working state of the field effect transistor, avoiding the influence of noise on the accuracy of model training and prediction. Therefore, the denoising process provides a more accurate signal basis for subsequent feature extraction and classification analysis.

[0056] S3: Extract multiple time-domain features from the denoised electrical characteristic signal.

[0057] Among them, the time-domain features are the features extracted from the time domain of the signal (i.e., the performance of the signal changing with time), and they describe the basic properties of the signal, such as waveform, amplitude, and change trend, etc. By extracting multiple time-domain features from the denoised electrical characteristic signal, the multi-dimensional characteristics of the signal can be comprehensively reflected.

[0058] In a possible implementation manner, the time-domain features specifically include: maximum value, root mean square amplitude, mean value, peak-to-peak amplitude, variance, standard deviation, skewness, kurtosis, waveform factor, and pulse factor.

[0059] It should be noted that by analyzing the signal from multiple angles, rich information can be provided for subsequent feature screening, which helps to improve the discriminant ability of the model for the health state of field effect transistors. In addition, the time-domain feature extraction is simple and has high computational efficiency, and can quickly process a large amount of signal data, thereby accelerating the subsequent screening process.

[0060] S4: Screen the time-domain features related to the health of field effect transistors through the graph attention network model to generate a relevant feature set.

[0061] Among them, the graph attention network is a deep learning model based on graph structure. It automatically selects the most important node information in the graph by learning the relationships and weights between nodes. The relevant feature set is a set of features that are screened out from all possible features and are most relevant to the health state of field effect transistors.

[0062] It should be noted that the graph attention network (GAT) is used to intelligently screen the features related to the health of the field effect transistor. By modeling the time-domain features as nodes in the graph and representing the relationships between the features with edges, GAT can assign different weights to the features according to the correlation between the nodes, thereby automatically identifying the most important features.

[0063] In a possible implementation manner, S4 specifically includes:

[0064] S401: Construct a graph attention network model with each time-domain feature as a node and the relationships between the time-domain features as edges.

[0065] Among them, the node represents an entity or feature in the graph. The time-domain features (such as the maximum value, root mean square amplitude, etc.) are regarded as the nodes of the graph, and the relationships between the time-domain features are represented by edges. The weight of the edge reflects the degree of association between these features.

[0066] S402: Through linear projection, convert the node features and edge features into hidden features respectively, and input the hidden features into the graph attention network model:

[0067]

[0068] Among them, represents the feature vector of node i at the initial time, represents the initial node weight matrix, represents the input feature vector of node i, represents the initial node bias vector, represents the feature vector of the edge obtained by connecting node i and node j at the initial layer, represents the initial edge weight matrix, represents the input feature vector of the edge obtained by connecting node i and node j, represents the initial edge bias vector.

[0069] S403: Calculate the attention weights of each node through the graph attention mechanism of the graph attention network model:

[0070]

[0071] Among them, represents the feature representation of the edge obtained by connecting node i and node j under the k-th head, LeakyReLU represents the non-linear activation function, represents the layer scalar coefficient, Concat represents the concatenation operation, represents layer weight matrix, represents The feature vector of layer node i, denotes the feature vector of layer node j.

[0072] S404: Normalize the attention weights:

[0073]

[0074] where, denotes the normalized attention weight of edge (x, y) under the k-th head and the layer, exp represents the exponential function, and N i denotes the set of neighbor nodes of node i.

[0075] S405: According to the normalized attention weights, introduce asymmetry in the neighborhood aggregation function to aggregate neighbor node information:

[0076]

[0077] where, denotes the feature vector of node i at the layer, Concat represents the concatenation operation, ELU represents the activation function, denotes the weight matrix of the k-th attention head at the layer, and K represents the total number of attention heads.

[0078] S406: According to the aggregated nodes, generate a relevant feature set by calculating node importance.

[0079] It should be noted that this screening method based on the attention mechanism makes feature selection more flexible and accurate, avoiding the biases and errors brought by manual screening. At the same time, GAT can handle complex feature relationships and non-linear data patterns, providing more accurate feature inputs for subsequent model training, thus improving the accuracy and efficiency of screening.

[0080] S5: Construct a field effect transistor screening model based on the random forest according to the relevant feature set.

[0081] Among them, the random forest is an ensemble learning algorithm composed of multiple decision trees. Each decision tree is trained based on randomly selected features and data subsets, and finally combines the prediction results of multiple decision trees through voting for classification or regression. The field effect transistor screening model refers to a model used to judge and screen whether a field effect transistor (FET) is normal or healthy.

[0082] It should be noted that by constructing a field-effect transistor screening model based on random forest, the prediction results of multiple decision trees can be integrated to achieve accurate classification. Through the integration of bootstrap samples and decision trees, random forest can effectively avoid overfitting and improve the stability and robustness of the model.

[0083] In a possible implementation manner, S5 specifically includes:

[0084] S501: Construct an original data set according to the relevant feature set.

[0085] S502: Randomly generate multiple bootstrap samples from the original data set, where each bootstrap sample contains multiple sample data.

[0086] S503: Construct multiple decision trees based on each bootstrap sample.

[0087] S504: Combine each decision tree to construct a field-effect transistor screening model:

[0088]

[0089] where, represents the predicted class output by the field-effect transistor screening model, means finding a class c such that the weighted voting result of all trees is the largest, represents the number of decision trees in the field-effect transistor screening model, represents the weight of tree t in the field-effect transistor screening model, represents the probability that tree t in the field-effect transistor screening model outputs class c.

[0090] It should be noted that different decision trees obtain the final prediction result through the weighted voting mechanism, which enables the model to integrate the information in different training data and enhance the generalization ability for unknown data. By constructing a training data set based on the relevant feature set, it is ensured that the model training is based on the most discriminative features, further improving the accuracy and efficiency of screening.

[0091] S6: Adjust the number of decision trees in the field-effect transistor screening model according to the importance of the relevant features in the relevant feature set.

[0092] Among them, the number of decision trees refers to the total number of trees that make up the random forest. In the random forest model, the number of trees has an important impact on the performance of the model. More decision trees can usually improve the stability and accuracy of the model, but it will also increase the computational complexity. A reasonable number of trees can optimize the performance of the model. In the random forest, by adjusting the number of decision trees, it is possible to improve the accuracy of the model while avoiding waste of computing resources, ensuring that the model is both efficient and accurate.

[0093] In a possible implementation, S6 specifically includes:

[0094] S601: Calculate the local weight of each relevant feature in each decision tree:

[0095]

[0096] where w t (j) represents the local weight of feature j in decision tree t, N represents the total number of nodes, Q(i, j) represents the splitting quality of node i on feature j, exp represents the exponential function, represents the entropy value of the left subtree, represents the entropy value of the right subtree.

[0097] It should be noted that the local weight refers to the importance measure of a feature in each decision tree in the random forest model. Specifically, the local weight measures the contribution of a feature in a certain decision tree, and it reflects the role of this feature in the node splitting of this decision tree.

[0098] S602: According to the local weights, combined with the normalized weights of the decision trees, calculate the global weights of each relevant feature:

[0099]

[0100] where w(j) represents the global weight of feature j, represents the normalized weight of tree t, represents the sum of the weighted contributions of feature j in all trees, represents the out-of-bag error of tree t.

[0101] It should be noted that the global weight refers to the comprehensive importance of a feature in the entire model, which is usually calculated based on the local weights in each decision tree and the normalized weights of the trees. The global weight reflects the total contribution of this feature to the model prediction result.

[0102] S603: According to the global weights, divide the relevant features into important features and unimportant features:

[0103]

[0104] where w(k) represents the global weight of feature k, represents that feature j belongs to the set of important features , represents that feature j is an unimportant feature set F n .

[0105] S604: Based on the number of important features and the number of unimportant features, adjust the number of decision trees in the field effect transistor screening model:

[0106] ,

[0107] ,

[0108] ,

[0109] Among them, represents the number of added trees, represents a constant, q u represents the probability of selecting important features, q v represents the probability of selecting unimportant features, represents the change in the number of important features, represents the change in the number of unimportant features, represents the change in classification performance. B represents the number of trees, u represents the size of the current important feature set, v represents the size of the current unimportant feature set, and f represents the size of the feature subset of each node.

[0110] It should be noted that by calculating the local weights of each feature in the decision tree and combining the normalized weights of the tree, the global importance of the feature in the entire random forest model is evaluated. This process ensures that the model can dynamically adjust the importance of features according to the contribution degree of the features, thereby optimizing the performance of the model. Through this feature importance evaluation, redundant or irrelevant features can be removed, and the accuracy and computational efficiency of the model can be improved.

[0111] S7: Use the training set composed of relevant feature sets to train the field effect transistor screening model until the classification accuracy of the field effect transistor screening model is greater than the preset classification accuracy.

[0112] The training set is a data set used to train a machine learning model, which contains input features and their corresponding labels (i.e., results). The classification accuracy refers to the proportion of samples predicted correctly by the model in the classification task. The preset classification accuracy is the target accuracy value set during the model training process.

[0113] Among them, those skilled in the art can set the size of the preset classification accuracy according to the actual situation, and the present invention does not make any limitations.

[0114] It should be noted that by using the training set to train the random forest model until the classification accuracy of the model exceeds the preset standard, the efficiency and reliability of the model are ensured. Through training, the model can learn from the actual data and gradually improve its prediction ability and accuracy.

[0115] In a possible implementation manner, the method for training the field effect transistor screening model based on the random forest is specifically as follows: The field effect transistor screening model is trained by an improved crow search algorithm until the classification accuracy of the field effect transistor screening model is greater than the preset classification accuracy.

[0116] Among them, the calculation formula of the classification accuracy is specifically:

[0117]

[0118] Among them, represents the classification accuracy, represents the proportionality coefficient, represents the strength of the forest, represents the correlation of the forest, represents the correlation between trees, q represents the probability of selecting at least one important feature, represents a constant.

[0119] Optionally, the improved crow search algorithm specifically includes:

[0120] S701: Initialize the positions of each crow. Among them, the position of the crow represents the feature subset.

[0121] S702: Set the parameters in the search process. Among them, the parameters include: the maximum number of iterations, the number of crows, and the flight length.

[0122] S703: Calculate the fitness of each crow position:

[0123]

[0124] Among them, F n,t represents the fitness value of the crow position at the t-th iteration, Acc represents the classification accuracy rate, w f represents the weight factor, L f represents the length of the feature subset, L t represents the total number of features in the feature subset, maximize represents maximization.

[0125] S704: Update the positions of each crow according to the fitness:

[0126]

[0127] Among them, y j,t+1 represents the position of crow j at the (t + 1)-th iteration, y j,t represents the position of crow j at the t-th iteration, C j represents the chaotic mapping coefficient of crow j, represents the flight length of crow j at the t-th iteration ,Nz,t Denotes the position of crow z at the t-th iteration, C z Denotes the chaotic mapping coefficient of crow z, AP j,t Denotes the threshold of crow j at the t-th iteration. Choose a rand position means randomly select a position for update.

[0128] S705: Represent the updated position in binary:

[0129]

[0130] Where s represents the Sigmoid function and rand() represents the function that generates random numbers in the range [0, 1).

[0131] S706: Update the fitness according to the binary representation result.

[0132] S707: Repeat steps S703 to S706 until the classification accuracy of the field effect transistor screening model is greater than the preset classification accuracy.

[0133] It should be noted that combining the chaotic crow search algorithm for training the field effect transistor screening model can achieve efficient and accurate anomaly detection. Especially in the process of feature selection, the model performance is improved by streamlining and optimizing features, thus ensuring the accuracy and efficiency of the screening results.

[0134] S8: Obtain the electrical characteristic signals of the field effect transistors to be screened.

[0135] Among them, the field effect transistors to be screened refer to the field effect transistors that are being screened and detected after the model training is completed. By inputting the electrical characteristic signals of the field effect transistors to be screened into the trained screening model, abnormal field effect transistors can be efficiently identified. By matching the electrical characteristic signals to be screened with the features learned in the training set, the model can quickly determine whether the field effect transistor meets the normal working conditions, thus achieving precise anomaly screening.

[0136] S9: Input the electrical characteristic signals of the field effect transistors to be screened into the trained field effect transistor screening model to screen out abnormal field effect transistors.

[0137] Among them, the trained field effect transistor screening model refers to the model that has learned and optimized according to the training set after the training process is completed. Abnormal field effect transistors refer to those field effect transistors that do not work properly, may have faults or performance anomalies.

[0138] It should be noted that by using the trained field effect transistor screening model, the electrical characteristic signals of the field effect transistors to be screened can be efficiently input and evaluated. This process is automated and can accurately identify those field effect transistors with abnormal performance or faults. The model utilizes the knowledge learned during previous training to quickly make judgments, avoiding the errors and inefficiencies of manual screening, and improving the accuracy and speed of screening.

[0139] The beneficial effects brought by the technical solutions provided by the embodiments of the present invention at least include:

[0140] In the embodiments of the present invention, first, the electrical characteristic signals of the field effect transistors are collected, and through the discrete wavelet transform algorithm, the electrical characteristic signals are denoised, and multiple time-domain features in the denoised electrical characteristic signals are extracted, so as to provide useful information for feature screening and model training. Then, through the graph attention network model, the main features related to the health of the field effect transistors are screened to generate a relevant feature set. According to the relevant feature set, a field effect transistor screening model based on random forest is constructed, and according to the importance of the relevant features, the number of decision trees in the field effect transistor screening model based on random forest is adjusted until the classification accuracy of the field effect transistor screening model is greater than the preset classification accuracy, ensuring that the model can make accurate classification judgments based on the existing data. Finally, the electrical characteristic signals of the field effect transistors to be screened are obtained, and the electrical characteristic signals of the field effect transistors to be screened are input into the trained field effect transistor screening model to screen out the abnormal field effect transistors, thereby realizing precise screening, reducing the complexity and subjectivity of manual screening, improving the screening efficiency and accuracy, ensuring the generalization ability of the model, and being able to cope with the challenges in different field effect transistor screenings.

[0141] Refer to the attached Figure 2 illustrates the structural schematic diagram of a field effect transistor screening system provided by the present invention.

[0142] The present invention also provides a field effect transistor screening system 20, which is applied to the above-mentioned field effect transistor screening method and includes:

[0143] A processor 201.

[0144] A memory 202, on which computer-readable instructions are stored. When the computer-readable instructions are executed by the processor 201, the field effect transistor screening method as in the method embodiment is realized.

[0145] The field effect transistor screening system 20 provided by the present invention can execute the above-mentioned field effect transistor screening method and achieve the same or similar technical effects. To avoid repetition, the present invention will not elaborate further.

[0146] The beneficial effects brought by the technical solutions provided by the embodiments of the present invention at least include:

[0147] In an embodiment of the present invention, first, electrical characteristic signals of a field effect transistor are collected, and the electrical characteristic signals are denoised through a discrete wavelet transform algorithm, and multiple time-domain features in the denoised electrical characteristic signals are extracted, so as to provide useful information for feature screening and model training. Next, through a graph attention network model, the main features related to the health of the field effect transistor are screened to generate a relevant feature set. According to the relevant feature set, a field effect transistor screening model based on a random forest is constructed, and according to the importance of the relevant features, the number of decision trees in the field effect transistor screening model based on the random forest is adjusted until the classification accuracy of the field effect transistor screening model is greater than a preset classification accuracy, ensuring that the model can make an accurate classification judgment based on existing data. Finally, the electrical characteristic signals of the field effect transistor to be screened are obtained, and the electrical characteristic signals of the field effect transistor to be screened are input into the trained field effect transistor screening model to screen out abnormal field effect transistors, thereby realizing accurate screening, reducing the complexity and subjectivity of manual screening, improving the screening efficiency and accuracy, ensuring the generalization ability of the model, and being able to cope with challenges in different field effect transistor screenings.

[0148] It should be understood that the processor in the embodiment of the present invention may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0149] It should also be understood that the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0150] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware, or any combination thereof. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions according to the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more collections of available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, or magnetic tape), an optical medium (such as a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state drive.

[0151] It should be understood that the term "and / or" in this document is merely a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. Here, A and B can be singular or plural. Additionally, the character " / " in this document generally represents an "or" relationship between the associated objects before and after, but it may also represent an "and / or" relationship, which can be specifically understood with reference to the context before and after.

[0152] In the present invention, "at least one" means one or more, and "a plurality" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, and c can be single or multiple.

[0153] It should be understood that in various embodiments of the present invention, the magnitudes of the sequence numbers of the above processes do not imply the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0154] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0155] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the devices, apparatuses, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be described herein again.

[0156] In several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of devices or units can be in electrical, mechanical, or other forms.

[0157] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place, or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0158] In addition, the functional units in each embodiment of the present invention can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.

[0159] When a function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or a part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs that can store program codes.

[0160] An embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the field-effect transistor screening method as in the method embodiment.

[0161] The computer-readable storage medium provided by the present invention can implement the steps and effects of the field-effect transistor screening method in the above method embodiment. To avoid repetition, the present invention will not elaborate further.

[0162] The beneficial effects brought by the technical solution provided by the embodiments of the present invention at least include:

[0163] In the embodiments of the present invention, first, the electrical characteristic signals of the field-effect transistors are collected, and through the discrete wavelet transform algorithm, the electrical characteristic signals are denoised, and multiple time-domain features in the denoised electrical characteristic signals are extracted, thereby providing useful information for feature screening and model training. Then, through the graph attention network model, the main features related to the health of the field-effect transistors are screened to generate a relevant feature set. According to the relevant feature set, a field-effect transistor screening model based on random forest is constructed, and according to the importance of the relevant features, the number of decision trees in the field-effect transistor screening model based on random forest is adjusted until the classification accuracy of the field-effect transistor screening model is greater than the preset classification accuracy, ensuring that the model can make accurate classification judgments based on the existing data. Finally, the electrical characteristic signals of the field-effect transistors to be screened are obtained, and the electrical characteristic signals of the field-effect transistors to be screened are input into the trained field-effect transistor screening model to screen out abnormal field-effect transistors, thereby achieving precise screening, reducing the complexity and subjectivity of manual screening, improving the screening efficiency and accuracy, ensuring the generalization ability of the model, and being able to cope with the challenges in different field-effect transistor screenings.

[0164] The above are only the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A field effect transistor screening method, characterized in that Including: S1: Collect the electrical characteristic signals of the field effect transistor and determine the labels corresponding to the electrical characteristic signals; S2: Denoise the electrical characteristic signals through the discrete wavelet transform algorithm to obtain denoised electrical characteristic signals; S3: Extract multiple time-domain features from the denoised electrical characteristic signals; S4: Screen the time-domain features related to the health of the field effect transistor through the graph attention network model to generate a related feature set; S5: Construct a field effect transistor screening model based on the random forest according to the related feature set; S6: Adjust the number of decision trees in the field effect transistor screening model according to the importance of the related features in the related feature set; S6 specifically includes: S601: Calculate the local weights of each related feature in each decision tree: ； Among them, w t (j) represents the local weight of feature j in decision tree t, N represents the total number of nodes, Q(i, j) represents the split quality of node i on feature j, exp represents the exponential function, represents the entropy value of the left subtree, E r represents the entropy value of the right subtree; S602: Calculate the global weights of each related feature according to the local weights and in combination with the normalized weights of the decision tree; ； where \(w(j)\) represents the global weight of feature \(j\), represents the normalized weight of tree \(t\), represents the total weighted contribution of feature \(j\) across all trees, represents the out-of-bag error of tree \(t\); S603: Classify the related features into important features and unimportant features according to the global weights; ； where \(w(k)\) represents the global weight of feature \(k\). means that feature \(j\) belongs to the set of important features , means that feature \(k\) belongs to the set of unimportant features \(F\) n ; S604: Adjust the number of decision trees in the field effect transistor screening model based on the number of important features and the number of unimportant features; ； ； ； Among them, represents the number of added trees, represents a constant, q u represents the probability of selecting important features, q v represents the probability of selecting unimportant features, represents the change in the number of important features, represents the change in the number of unimportant features, represents the change in classification performance. B represents the number of trees, u represents the size of the current set of important features, v represents the size of the current set of unimportant features, and f represents the size of the feature subset of each node; S7: Train the field effect transistor screening model with the training set composed of the related feature set until the classification accuracy of the field effect transistor screening model is greater than the preset classification accuracy; S8: Obtain the electrical characteristic signals of the field effect transistor to be screened; S9: Input the electrical characteristic signals of the field effect transistor to be screened into the trained field effect transistor screening model to screen out abnormal field effect transistors.

2. The field effect transistor screening method according to claim 1, characterized in that, The electrical characteristic signals specifically include: gate voltage, drain current, on-resistance, temperature coefficient, and switching speed.

3. The method for screening field effect transistors according to claim 1, characterized in that, S2 specifically includes: S201: Add white noise to the electrical characteristic signals; S202: Decompose the electrical characteristic signals with added white noise through wavelet basis functions to obtain signal coefficients; S203: Perform soft threshold processing on the decomposed signal coefficients to remove the noise of the electrical characteristic signals; S204: Reconstruct the denoised electrical characteristic signals through inverse discrete wavelet transform to obtain the denoised electrical characteristic signals.

4. The field effect transistor screening method according to claim 1, wherein The time-domain features specifically include: maximum value, root mean square amplitude, mean value, peak-to-peak amplitude, variance, standard deviation, skewness, kurtosis, waveform factor, and pulse factor.

5. The field effect transistor screening method according to claim 1, wherein S4 specifically includes: S401: Construct a graph attention network model with each of the time-domain features as nodes and the relationships between each of the time-domain features as edges; S402: Respectively convert the node features and edge features into hidden features through linear projection and input the hidden features into the graph attention network model; S403: Calculate the attention weights of each of the nodes through the graph attention mechanism of the graph attention network model; S404: Perform normalization processing on the attention weights; S405: According to the normalized attention weights, introduce asymmetry into the neighborhood aggregation function to aggregate neighbor node information; S406: Generate the related feature set according to the aggregated nodes by calculating the node importance.

6. The field effect transistor screening method according to claim 1, characterized in that S5 specifically includes: S501: Construct an original data set according to the relevant feature set; S502: Randomly generate a plurality of bootstrap samples from the original data set, where each of the bootstrap samples contains a plurality of sample data; S503: Construct a plurality of decision trees based on each of the bootstrap samples; S504: Combine each of the decision trees to construct the field effect transistor screening model.

7. The field effect transistor screening method according to claim 1, characterized in that The method for training the field effect transistor screening model based on random forest is specifically: train the field effect transistor screening model through the crow search algorithm until the classification accuracy of the field effect transistor screening model is greater than the preset classification accuracy.

8. A field effect transistor screening system, characterized in that Including: A processor; A memory, on which computer-readable instructions are stored, and when the computer-readable instructions are executed by the processor, the field effect transistor screening method according to any one of claims 1 to 7 is implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, the field effect transistor screening method according to any one of claims 1 to 7 is implemented.

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