Parameter calculation optimization system and method based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to the technical field of radio frequency, and provides an FPGA-based parameter calculation optimization system and method, the parameter calculation optimization system is integrated in a field programmable gate array, and comprises a multi-stage calculation pipeline module, a multi-stage cache module and a control module; the multi-stage calculation assembly line module decomposes and sorts the impedance matching parameter calculation process, reads parameters required by calculation from the multi-stage cache module, and executes the decomposition calculation step according to the sorting to finally obtain an impedance matching parameter calculation result; the multi-stage cache module caches parameters required by the multi-stage calculation pipeline module for executing the corresponding sorting calculation steps; and the control module coordinates read-write operations of the multi-stage calculation assembly line module and the multi-stage cache module, and controls starting of parameter transmission and decomposition calculation steps. According to the method, the calculation complexity is reduced, the timestamps of different parameter calculation results are ensured to be consistent, parameter synchronous output is realized, the calculation delay is remarkably reduced, and the system performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency technology, and in particular to a parameter calculation optimization system and method based on FPGA. Background Art

[0002] In the RF plasma system, the RF power supply provides energy to the reaction chamber and ignites the plasma. In order to effectively load the power of the RF power supply to the reaction chamber, the output impedance of the power supply needs to match the impedance of the reaction chamber. Usually, a matcher is added between the RF power supply and the reaction chamber to achieve impedance matching. The matcher includes a sensor, a computing unit, and an execution unit. The matcher works on the transmission line between the RF power supply and the reaction chamber. The sensor monitors the voltage, current amplitude, phase angle, and frequency value in real time, and transmits these parameters to the computing unit to calculate the impedance admittance, forward power, and reflected power. The execution unit controls the variable capacitor according to the calculation results to achieve impedance matching.

[0003] The matching process involves the calculation of multiple parameters, including resistance, reactance, conductance, susceptance, phase difference, reflection coefficient, etc. The calculation of these parameters is characterized by high computational complexity and asynchronous timestamps, which increases the overall calculation delay. Parameters calculated faster (such as phase difference) will be overwritten by new data, resulting in the output parameters not belonging to the data set at the same time, affecting subsequent analysis and application. Summary of the invention

[0004] The present invention provides a parameter calculation optimization system and method based on FPGA, which is used to solve the defects of high calculation complexity and asynchronous timestamp in the prior art. The present invention reduces the calculation complexity, ensures the consistency of timestamps of calculation results of different parameters, realizes synchronous output of parameters, significantly reduces calculation delay, and improves system performance.

[0005] The present invention provides a parameter calculation optimization system based on FPGA, which is integrated in a field programmable gate array and comprises a multi-level calculation pipeline module, a multi-level cache module and a control module; the multi-level calculation pipeline module is used to decompose and sort the impedance matching parameter calculation process, read the parameters required for calculation from the multi-level cache module, and perform the decomposition calculation steps in order to finally obtain the impedance matching parameter calculation results; the parallel calculation of different parameters is supported in the same-level calculation steps; the multi-level cache module is used to cache the parameters required for the multi-level calculation pipeline module to perform the corresponding sorting calculation steps; the control module is used to coordinate the read and write operations of the multi-level calculation pipeline module and the multi-level cache module, and control the parameter transfer and the start of the decomposition calculation steps.

[0006] According to a parameter calculation optimization system based on FPGA provided by the present invention, the multi-level calculation pipeline module includes multi-level sub-calculation modules; the multi-level cache module includes multi-level sub-cache modules; the multi-level sub-calculation modules correspond to the multi-level sub-cache modules one by one; the control module is specifically used to generate a read signal, a write signal and a calculation start signal; the sub-cache module is used to write the parameters required by the sub-calculation module of the current level when the write signal is valid; the sub-calculation module is used to read the parameters from the sub-cache module of the current level when the read signal is valid; and when the calculation start signal is valid, the parameter calculation step of the current level is started to be executed to obtain the parameter calculation result of the current level.

[0007] According to a parameter calculation optimization system based on FPGA provided by the present invention, the parameter calculation results of the sub-computing units at the current level are used to be transmitted to the sub-computing modules and / or the sub-cache modules at the next level.

[0008] According to the FPGA-based parameter calculation optimization system provided by the present invention, the read signal, the write signal and the calculation start signal are all effective at a high or low level.

[0009] According to an FPGA-based parameter calculation optimization system provided by the present invention, the multi-stage calculation pipeline module is specifically used to divide the impedance matching parameter calculation process into ten calculation steps, and the calculation types include numerical calculation, function calculation, iterative algorithm and complex number calculation.

[0010] The present invention also provides a parameter calculation optimization method based on FPGA, including: decomposing and sorting the impedance matching parameter calculation process, reading the parameters required for the calculation, and executing the decomposition calculation steps in order, and finally obtaining the impedance matching parameter calculation results; supporting parallel calculation of different parameters in the same level calculation steps; caching the parameters required for executing the corresponding sorting calculation steps; coordinating read and write operations, and controlling parameter transfer and the start of the decomposition calculation steps.

[0011] The present invention also provides a matcher, comprising the above-mentioned FPGA-based parameter calculation optimization system.

[0012] The present invention also provides a radio frequency plasma system, comprising the above-mentioned matcher, a radio frequency power supply and a reaction chamber.

[0013] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein when the processor executes the computer program, the FPGA-based parameter calculation optimization method described above is implemented.

[0014] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the FPGA-based parameter calculation optimization method described above is implemented.

[0015] The present invention provides a parameter calculation optimization system and method based on FPGA. The parameter calculation optimization system is integrated in a field programmable gate array, and includes a multi-level calculation pipeline module, a multi-level cache module and a control module; the multi-level calculation pipeline module decomposes and sorts the impedance matching parameter calculation process, reads the parameters required for calculation from the multi-level cache module, and performs the decomposition calculation steps in order, and finally obtains the impedance matching parameter calculation result; supports parallel calculation of different parameters in the same-level calculation steps; the multi-level cache module caches the parameters required for the multi-level calculation pipeline module to perform the corresponding sorting calculation steps; the control module coordinates the read and write operations of the multi-level calculation pipeline module and the multi-level cache module, and controls the parameter transfer and the start of the decomposition calculation steps. The present invention reduces the calculation complexity, ensures the consistency of the timestamps of the calculation results of different parameters, realizes the synchronous output of parameters, significantly reduces the calculation delay, and improves the system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 It is a structural schematic diagram of a parameter calculation optimization system based on FPGA provided by the present invention.

[0018] Figure 2 It is a schematic diagram of the principle of a parameter calculation optimization system based on FPGA provided by the present invention.

[0019] Figure 3 It is a flow chart of a parameter calculation optimization method based on FPGA provided by the present invention.

[0020] Figure 4 It is a structural schematic diagram of the electronic device provided by the present invention.

[0021] Reference numerals: 1: Multi-level computing pipeline module; 2: Multi-level cache module; 3: Control module. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] The impedance matching process of the matcher involves the calculation of multiple parameters, including resistance, reactance, conductance, susceptance, phase difference, reflection coefficient, etc. The calculation of these parameters has the following characteristics: High computational complexity: The calculation of some parameters, such as the reflection coefficient, involves complex calculation processes (such as the calculation of various factors in the division operation), which increases the overall calculation delay.

[0024] Timestamp asynchrony: Parameters calculated faster (such as phase difference) will be overwritten by new data, causing the output parameters to not belong to the data set at the same time, affecting subsequent analysis and application.

[0025] Please refer to Figure 1 , Figure 1 A structural schematic diagram of a parameter calculation and optimization system based on FPGA provided by the present invention.

[0026] The present invention provides a parameter calculation optimization system based on FPGA, which is integrated in a field programmable gate array and comprises a multi-level calculation pipeline module 1, a multi-level cache module 2 and a control module 3; the multi-level calculation pipeline module 1 is used to decompose and sort the impedance matching parameter calculation process, read the parameters required for calculation from the multi-level cache module 2, and perform the decomposition calculation steps in order to finally obtain the impedance matching parameter calculation results; the parallel calculation of different parameters is supported in the same-level calculation steps; the multi-level cache module 2 is used to cache the parameters required for the multi-level calculation pipeline module 1 to perform the corresponding sorting calculation steps; the control module 3 is used to coordinate the read and write operations of the multi-level calculation pipeline module 1 and the multi-level cache module 2, and control the parameter transfer and the start of the decomposition calculation steps.

[0027] This embodiment describes in detail a specific implementation of an FPGA-based parameter calculation optimization system, which is integrated in a field programmable gate array (FPGA) to improve the calculation efficiency of impedance matching parameters in a radio frequency plasma system. The system includes a multi-level calculation pipeline module 1, a multi-level cache module 2, and a control module 3.

[0028] The multi-stage calculation pipeline module 1 is the core of the system. It decomposes the complex impedance matching parameter calculation process into multiple independent calculation steps. These steps are sorted according to the calculation dependencies and constructed into a pipeline to ensure the correctness and efficiency of the calculation. For example, when calculating the resistance R and reactance X, the formula and . Where Z is the impedance, The pipeline module reads the necessary parameters such as impedance Z and phase difference from the multi-level cache module 2. , and execute the decomposed calculation steps. In the same-level calculation steps, the calculation of different parameters can be executed in parallel to further improve the calculation speed. The multi-level cache module 2 is used to cache the parameters required by the multi-level calculation pipeline module 1 when executing the corresponding sorting calculation steps. The cache module adopts a first-in-first-out (FIFO) strategy to ensure the timeliness of the parameters and the continuity of the calculation. The cache depth is dynamically adjusted according to the delay of the pipeline to prevent data overflow and save hardware resources. The control module 3 is responsible for coordinating the read and write operations between the multi-level calculation pipeline module 1 and the multi-level cache module 2. It controls the transmission of parameters and the start of the decomposed calculation steps to ensure data synchronization and the correctness of the calculation. The control module 3 manages the data flow and calculation process through internal logic and timing control, so that the entire system can run efficiently and stably.

[0029] Through this design, the system of this embodiment can achieve efficient parameter calculation optimization on FPGA, which is particularly suitable for application scenarios that require real-time processing and high-precision calculation, such as impedance matching of RF plasma systems.

[0030] Compared with the prior art, the present invention has the following beneficial effects: Synchronous output: The FIFO cache mechanism is used to ensure the consistency of timestamps of calculation results of different parameters and realize synchronous output of parameters.

[0031] Accelerated computing: Optimize the computing process through pipeline design and reordering, significantly reduce computing latency and improve system performance.

[0032] Please refer to Figure 2 , Figure 2 A schematic diagram of the principle of a parameter calculation optimization system based on FPGA provided by the present invention.

[0033] As a preferred embodiment, the multi-level computing pipeline module 1 includes multi-level sub-computing modules; the multi-level cache module 2 includes multi-level sub-cache modules; the multi-level sub-computing modules correspond one-to-one to the multi-level sub-cache modules; the control module 3 is specifically used to generate a read signal, a write signal and a calculation start signal; the sub-cache module is used to write the parameters required by the current-level sub-computing module when the write signal is valid; the sub-computing module is used to read the parameters from the current-level sub-cache module when the read signal is valid; when the calculation start signal is valid, the parameter calculation steps of the current level are started to obtain the parameter calculation results of the current level.

[0034] In this embodiment, the multi-level computing pipeline module 1 is composed of a plurality of sub-computing modules, each of which is responsible for executing a specific computing task. Similarly, the multi-level cache module 2 is composed of a plurality of sub-cache modules, each of which is used to store the parameters required by the corresponding sub-computing module. Each sub-computing module corresponds to its corresponding sub-cache module one by one, ensuring the accurate transmission of parameters and the smooth progress of calculation.

[0035] The control module 3 in this embodiment is used to generate a read signal, a write signal and a calculation start signal. The read signal is used to instruct the sub-calculation module to read parameters from its corresponding sub-cache module, the write signal is used to instruct the sub-cache module to write the parameters required by the current-level sub-calculation module, and the calculation start signal is used to start the calculation process of the sub-calculation module.

[0036] The specific operation process is as follows: When the control module 3 sends a write signal, the parameters required for calculation are written into the current level sub-cache module. These parameters may include voltage amplitude values , current amplitude value and phase difference When the read signal is valid, the sub-calculation module reads these parameters from its corresponding current-level sub-cache module. For example, if the sub-calculation module is responsible for calculating the resistance R, it will use the formula to calculate the result.

[0037] Once the calculation start signal is valid, the sub-computing module starts to perform its calculation task. After the calculation is completed, the result can be used for the next level of calculation or output to an external system. This modular design allows the system to flexibly handle different computing tasks and can adapt to different computing needs by increasing or decreasing the number of sub-computing modules and sub-cache modules.

[0038] Through this design, the system of this embodiment can achieve efficient parameter calculation while maintaining a high degree of flexibility and scalability, which makes the system particularly suitable for application scenarios that require fast and accurate calculations.

[0039] As a preferred embodiment, the parameter calculation result of the current-level sub-computing unit is used to be transmitted to the next-level sub-computing module and / or sub-cache module.

[0040] In this embodiment, the transmission mechanism of parameter calculation results between different sub-computing modules and sub-caching modules will be further described in detail. After each level of sub-computing module completes its calculation task, its result is not only used for the output of the current level, but also can be transmitted to the sub-computing module and / or sub-caching module of the next level for further calculation.

[0041] For example, consider a multi-stage pipeline calculation process, where the first-stage sub-calculation module is responsible for calculating the phase difference between voltage and current , using the formula .in, and are the phases of voltage and current respectively. The calculated phase difference will be passed to the second-level sub-computation module, which may be responsible for calculating .

[0042] Of course, after receiving the calculation result of the first-stage module, the second-stage sub-calculation module can also read the phase difference from its corresponding sub-cache module when the calculation start signal is valid. , and start calculating . It can be used in other parts of the system, for example, in the control module 3 to adjust system parameters, or transferred to the third-level sub-computing module for further calculation.

[0043] In addition, to improve the flexibility and efficiency of the system, the sub-cache module can be designed to support temporary storage and fast access to parameters. In this way, even if there is a short delay or interruption in the calculation process, the system can resume the calculation from the interruption point without restarting the entire calculation process.

[0044] Through this design, the system of this embodiment can achieve effective use of parameter calculation results, reduce repeated calculations, and improve calculation efficiency. At the same time, this modular and pipelined computing architecture also makes the system easy to expand and maintain, and is suitable for various application scenarios that require efficient parameter calculation.

[0045] As a preferred embodiment, the read signal, the write signal and the calculation start signal are all valid at a high or low level.

[0046] In this embodiment, the specific working mechanism of the read signal, the write signal and the calculation start signal when the high level is effective will be described in detail. The control module 3 is responsible for generating these signals to ensure the correct reading and writing of data and the accurate execution of the calculation steps.

[0047] When the read signal rd_en is in a high level state, the sub-calculation module reads the necessary parameters from its corresponding sub-cache module. For example, if the resistance R needs to be calculated, the sub-calculation module will read the voltage amplitude value from the sub-cache module under the trigger of the high level read signal. , current amplitude value and phase difference , and then use the formula To calculate the resistance value.

[0048] Similarly, when the write signal wr_en is in a high level state, the sub-cache module will receive the calculation results from the previous sub-calculation module and store them for use by the next sub-calculation module. , this result will be written into the sub-cache module under the trigger of a high-level write signal.

[0049] When the calculation start signal is active at a high level, the sub-calculation module starts to perform its calculation task. For example, once the sub-calculation module receives all necessary parameters and the calculation start signal becomes high, it will start calculating, such as using the formula To calculate the delivered power .

[0050] This high-level active signal design simplifies the signal processing logic because the high-level state usually indicates an activated or enabled state. In FPGA design, this can be achieved by setting the clock signal of the trigger to a high level trigger, ensuring that data reading, writing, and calculation operations are performed during the high level of the signal.

[0051] In addition, the high-level effective signal design helps to reduce the burrs and jitter of the signal and improve the stability and reliability of the system. In the actual FPGA implementation, these signals can be generated and controlled by logic gate circuits and triggers to ensure the precise timing of the signal and the coordinated operation of the system. In this way, the system of this embodiment can efficiently and accurately perform parameter calculation tasks, and is suitable for application scenarios that require fast response and high-precision calculation.

[0052] As a preferred embodiment, the multi-stage calculation pipeline module 1 is specifically used to divide the impedance matching parameter calculation process into ten stages of calculation steps, and the calculation types include numerical calculation, function calculation, iterative algorithm and complex number calculation.

[0053] After receiving the amplitude and phase values ​​of voltage and current, the system needs to calculate the following parameters: resistance, reactance, conductance, susceptance, voltage and current phase difference, phase difference sine and cosine values, reflection coefficient and its real and imaginary parts, transmitted power, forward power, and reflected power.

[0054] For a signal at a certain moment, the time required to calculate the above parameters varies. For example, the phase difference only requires the combination of logic outputs, and the calculation of trigonometric functions, multiplication, division, square root and other operations requires a long time, resulting in the output of parameters not being output at the same time. In continuous signal acquisition and calculation, if the parameters with shorter delays are not cached, the parameters of the current moment will be washed away by the parameters of subsequent moments, and the parameters finally obtained are not the same timestamp.

[0055] First, it is necessary to perform calculation reordering and pipeline segmentation according to the parameter formula. In this embodiment, the calculation process of the impedance matching parameters is divided into ten specific calculation steps, each of which is responsible for different types of calculation tasks, including numerical calculations, function calculations, iterative algorithms, and complex number calculations.

[0056] In the first stage of pipeline, the input valid bit input_valid is set high, s1_data is set high, and the first stage sub-calculation module needs to calculate the impedance Z, admittance Y and phase difference , using the formula , and This step involves division operations, and a pipeline divider is required to increase the speed. This stage also requires the use of the first-level sub-cache module stage1 to cache the voltage amplitude value V mag , current amplitude value I mag , phase difference . When the divider completes the calculation, the first-stage calculation start signal s1_valid is set high, the output impedance Z and admittance Y, and s2_data is set high. The first-stage sub-calculation module reads the voltage amplitude value, current amplitude value and phase difference in the first-stage first-stage sub-cache module FIFO_S1, sends it to the next-stage sub-calculation module stage2 and writes it to the next-stage sub-cache module FIFO_S2. din is the input of the sub-calculation module, and dout is the output of the sub-calculation module.

[0057] In the second-level pipeline, the second-level sub-calculation module needs to calculate the sine and cosine values ​​of the phase angle using the CORDIC algorithm. and After the calculation is completed, the second-level calculation start signal s2_valid is set high, the sine value and cosine value are output, and s3_data is set high. The second-level sub-calculation module reads the voltage amplitude value, current amplitude value, phase difference, impedance and admittance in the second-level sub-cache module FIFO_S2, sends them to the third-level sub-calculation module and writes them into the third-level sub-cache module.

[0058] In the third-level pipeline, the third-level sub-calculation module needs to calculate the resistance R, reactance X, and conductance G a and electrical conductivity G b , and the factors required for subsequent calculations , z2 , using the formula , , and This step is a multiplication operation, and the required clock cycle is the same, so it is placed in the first-level pipeline for calculation. After the multiplication operation is completed, the third-level calculation start signal is set high, the calculation result is output and the data in the third-level sub-cache module is read, sent to the fourth-level sub-calculation module and written into the fourth-level sub-cache module.

[0059] In the fourth-level pipeline, the fourth-level sub-calculation module needs to calculate the factors of the real and imaginary parts of the reflection coefficient, that is, the numerator and denominator, which is an addition and subtraction operation. After the calculation is completed, the fourth-level calculation start signal is set high, the calculation result is output and the data in the fourth-level sub-cache module is read, sent to the fifth-level sub-calculation module and written into the fifth-level sub-cache module.

[0060] In the fifth-level pipeline, the fifth-level sub-calculation module needs to calculate the real and imaginary parts of the reflection coefficient using the formula and This step is a division operation, and a pipeline divider is used to increase the operation speed. After the calculation is completed, the fifth-level calculation start signal is set high, the calculation result is output and the data in the fifth-level sub-cache module is read, sent to the sixth-level sub-calculation module and written to the sixth-level sub-cache module. Some calculation factors do not participate in subsequent calculations. After the current level of pipeline is completed, the data is discarded to save hardware resources.

[0061] In the sixth-level pipeline, the sixth-level sub-calculation module needs to calculate the reflection coefficient using the formula , that is, square root operation, using the CORDIC algorithm to calculate the square root. After the calculation is completed, the sixth-level calculation start signal is set high, the calculation result is output and the data in the sixth-level sub-cache module is read, sent to the seventh-level sub-calculation module and written into the seventh-level sub-cache module.

[0062] In the seventh-level pipeline, the seventh-level sub-calculation module needs to calculate the square value of the reflection coefficient and delivered power , using the formula , this step is a multiplication operation. After the calculation is completed, the seventh-level calculation start signal is set high, the calculation result is output and the data in the seventh-level sub-cache module is read, sent to the eighth-level sub-calculation module and written into the eighth-level sub-cache module.

[0063] In the eighth-level pipeline, the eighth-level sub-calculation module needs to calculate the forward power denominator, which is a subtraction operation. After the calculation is completed, the eighth-level calculation start signal is set high, the calculation result is output and the data in the eighth-level sub-cache module is read, sent to the ninth-level sub-calculation module and written into the ninth-level sub-cache module.

[0064] In the ninth stage of the pipeline, the ninth stage sub-computing module needs to calculate the forward power , using the formula This step is a division operation, and a pipeline structure divider is used to increase the operation speed. After the calculation is completed, the ninth-level calculation start signal is set high, the calculation result is output and the data in the ninth-level sub-cache module is read, sent to the tenth-level sub-calculation module and written to the tenth-level sub-cache module. The calculation factors are discharged from the pipeline to save hardware resources.

[0065] In the tenth stage of the pipeline, the tenth stage sub-calculation module needs to calculate the reflected power , using the formula , This step is a multiplication operation. This stage is the last stage of the pipeline. After the calculation is completed, the tenth stage calculation start signal is set high, the calculation result is output and other parameters in the tenth stage sub-cache module are read and output at the same time, realizing the function of synchronous output of parameter timestamp.

[0066] The following is a description of the parameter calculation optimization method based on FPGA provided by the present invention. The parameter calculation optimization method based on FPGA described below and the parameter calculation optimization system based on FPGA described above can refer to each other.

[0067] Please refer to Figure 3 , Figure 3 A schematic flow chart of a parameter calculation optimization method based on FPGA provided by the present invention.

[0068] The present invention also provides a parameter calculation optimization method based on FPGA, comprising: 301: Decompose and sort the impedance matching parameter calculation process, read the parameters required for the calculation, and perform the decomposed calculation steps in order, and finally obtain the impedance matching parameter calculation results; support parallel calculation of different parameters in the same level calculation steps; 302: Cache the parameters required to execute the corresponding sorting calculation steps; 303: Coordinates read and write operations, controls parameter passing, and initiates decomposition computation steps.

[0069] The matcher provided by the present invention is described below. The matcher described below and the FPGA-based parameter calculation optimization system described above can be referenced to each other.

[0070] The present invention also provides a matcher, comprising the above-mentioned FPGA-based parameter calculation optimization system.

[0071] The radio frequency plasma system provided by the present invention is described below. The radio frequency plasma system described below and the FPGA-based parameter calculation optimization system described above can be referenced to each other.

[0072] The present invention also provides a radio frequency plasma system, comprising the above-mentioned matcher, a radio frequency power supply and a reaction chamber.

[0073] Figure 4 An example of a structural diagram of an electronic device is shown in FIG. Figure 4 As shown, the electronic device may include: a processor (processor) 401, a communication interface (Communications Interface) 402, a memory (memory) 403 and a communication bus 404, wherein the processor 401, the communication interface 402, and the memory 403 communicate with each other through the communication bus 404. The processor 401 may call the logic instructions in the memory 403 to execute the parameter calculation optimization method based on FPGA, which includes: decomposing and sorting the impedance matching parameter calculation process, reading the parameters required for the calculation, and executing the decomposition calculation steps in order, and finally obtaining the impedance matching parameter calculation results; supporting the parallel calculation of different parameters in the same level calculation steps; caching the parameters required for executing the corresponding sorting calculation steps; coordinating the read and write operations, and controlling the parameter transfer and the start of the decomposition calculation steps.

[0074] In addition, the logic instructions in the above-mentioned memory 403 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0075] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the FPGA-based parameter calculation optimization method provided by the above methods, and the method includes: decomposing and sorting the impedance matching parameter calculation process, reading the parameters required for the calculation, and executing the decomposition calculation steps in the sorting order, and finally obtaining the impedance matching parameter calculation results; supporting parallel calculation of different parameters in the same-level calculation steps; caching the parameters required for executing the corresponding sorting calculation steps; coordinating read and write operations, and controlling parameter transfer and the start of the decomposition calculation steps.

[0076] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the FPGA-based parameter calculation optimization method provided by the above methods is implemented. The method includes: decomposing and sorting the impedance matching parameter calculation process, reading the parameters required for the calculation, and executing the decomposition calculation steps in order, and finally obtaining the impedance matching parameter calculation results; supporting parallel calculation of different parameters in the same-level calculation steps; caching the parameters required for executing the corresponding sorting calculation steps; coordinating read and write operations, and controlling parameter transfer and the start of the decomposition calculation steps.

[0077] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0078] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A parameter calculation optimization system based on FPGA, characterized in that: The parameter calculation optimization system is integrated into a field programmable gate array, and includes a multi-level calculation pipeline module, a multi-level cache module and a control module; The multi-level calculation pipeline module is used to decompose and sort the impedance matching parameter calculation process, read the parameters required for calculation from the multi-level cache module, and perform the decomposed calculation steps in order, and finally obtain the impedance matching parameter calculation results; support parallel calculation of different parameters in the same level calculation steps; The multi-level cache module is used to cache the parameters required by the multi-level calculation pipeline module to execute the corresponding sorting calculation steps; The control module is used to coordinate the read and write operations of the multi-level computing pipeline module and the multi-level cache module, and control parameter transfer and the start of decomposition computing steps.

2. The FPGA-based parameter calculation optimization system according to claim 1, characterized in that: The multi-level computing pipeline module includes multi-level sub-computing modules; the multi-level cache module includes multi-level sub-cache modules; the multi-level sub-computing modules correspond to the multi-level sub-cache modules one by one; The control module is specifically used to generate a read signal, a write signal and a calculation start signal; The sub-cache module is used to write the parameters required by the sub-computing module of the current level when the write signal is valid; The sub-calculation module is used for reading parameters from the sub-cache module at the current level when the read signal is valid; When the calculation start signal is valid, the parameter calculation step of the current level is started to obtain the parameter calculation result of the current level.

3. The FPGA-based parameter calculation optimization system according to claim 2, characterized in that: The parameter calculation results of the sub-computing units at the current level are used to be transmitted to the sub-computing modules and / or the sub-cache modules at the next level.

4. The FPGA-based parameter calculation optimization system according to claim 2, characterized in that: The read signal, the write signal and the calculation start signal are all effective at a high or low level.

5. The FPGA-based parameter calculation optimization system according to any one of claims 1 to 4, characterized in that: The multi-stage calculation pipeline module is specifically used to divide the impedance matching parameter calculation process into ten stages of calculation steps, and the calculation types include numerical calculation, function calculation, iterative algorithm and complex number calculation.

6. A parameter calculation optimization method based on FPGA, characterized in that: include: Decompose and sort the impedance matching parameter calculation process, read the parameters required for the calculation, and perform the decomposed calculation steps in order to finally obtain the impedance matching parameter calculation results; Supports parallel calculation of different parameters in the same level calculation steps; Cache the parameters required to perform the corresponding sort calculation steps; Coordinates read and write operations, controls parameter passing, and initiates decomposition computation steps.

7. A matcher, characterized in that: The invention comprises the parameter calculation and optimization system based on FPGA as described in any one of claims 1 to 5.

8. A radio frequency plasma system, characterized in that: It comprises the matcher, radio frequency power supply and reaction chamber as described in claim 7.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the FPGA-based parameter calculation optimization method as claimed in claim 6 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the FPGA-based parameter calculation optimization method as claimed in claim 6 is implemented.

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