Method and system for generating circuit board design drawing

Abstract

The invention relates to the technical field of circuit board design, in particular to a method and a system for generating a circuit board design drawing. The method comprises the following steps: acquiring an original circuit board design drawing file; performing layer data vectorization on the original circuit board design drawing file to obtain vectorized layer data; constructing a connection matrix of element elements according to the vectorized layer data to obtain the connection matrix; performing overlapping region modeling according to the vectorized layer data and the connection matrix to obtain overlapping region modeling data; performing current density simulation according to the overlapped region modeling data to obtain current density simulation data; and performing virtual node positioning on the overlapping region modeling data according to the current density simulation data and the vectorized layer data, and generating virtual node coordinate data to obtain the virtual node coordinate data. By solving the wiring problem of a complex topological structure and an overlapping region, the wiring efficiency and quality are improved, and the performance and reliability of the circuit board are optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board design, and in particular to a method and system for generating a circuit board design drawing. Background Art

[0002] In the early days, circuit board design was entirely done manually using tape and drawing tools. This method was inefficient, inaccurate, and difficult to handle complex circuits. Later, electronic design automation (EDA) software such as AltiumDesigner and PADS emerged. These software provide a graphical interface and some automated tools to assist engineers in circuit board design, greatly improving design efficiency. EDA software integrates automatic routing functions that can automatically generate routing paths according to preset rules. However, the efficiency and routing quality of early automatic routing algorithms were limited, especially when dealing with complex topologies and high-density routing. Traditional methods have difficulty handling complex topologies and overlapping areas.

[0003] The shortcomings of traditional methods in dealing with complex topological structures and overlapping areas are mainly reflected in: Routing congestion: In areas with dense components, the wiring space is limited. Traditional automatic routing algorithms are prone to causing routing congestion and making it difficult to find a suitable routing path.

[0004] Difficult to optimize: For complex topologies, traditional optimization algorithms have difficulty finding the global optimal solution, resulting in increased wiring length and reduced signal integrity.

[0005] Difficulty in handling overlapping areas: Traditional routing algorithms usually treat the routing of each network as an independent task, without fully considering the mutual influence between networks, especially in overlapping areas, which are prone to routing conflicts and electromagnetic interference. Summary of the invention

[0006] Based on this, it is necessary to provide a method and system for generating a circuit board design drawing to solve at least one of the above technical problems.

[0007] To achieve the above object, a method for generating a circuit board design drawing comprises the following steps: Step S1: obtaining an original circuit board design file; vectorizing the layer data of the original circuit board design file to obtain vectorized layer data; constructing a connection matrix of component elements according to the vectorized layer data to obtain a connection matrix; modeling the overlapping area according to the vectorized layer data and the connection matrix to obtain overlapping area modeling data; simulating the current density according to the overlapping area modeling data to obtain current density simulation data; locating virtual nodes of the overlapping area modeling data according to the current density simulation data and the vectorized layer data, and generating virtual node coordinate data to obtain virtual node coordinate data; Step S2: generating an initial path according to the virtual node coordinate data, the connection matrix and the vectorized layer data, and optimizing the path to obtain path optimization data; generating three-dimensional wiring data according to the path optimization data and the virtual node coordinate data to obtain three-dimensional wiring data; Step S3: determining the candidate test point area according to the three-dimensional wiring data, the vectorized layer data and the virtual node coordinate data to obtain candidate test area data; performing test point optimization processing on the candidate test area data to obtain test point data; Step S4: Integrate layer data according to the three-dimensional wiring data and the vectorized layer data to obtain layer data integration data; create a test point layer according to the test point data to obtain test point layer data; generate layered layers according to the layer data integration data and the test point layer data to obtain layered layer data, so as to realize the circuit board design drawing generation operation.

[0008] The present invention accurately extracts circuit topology information by vectorizing and connecting the original circuit board design drawing, and provides an accurate data basis for the positioning of virtual nodes through overlapping area modeling and current density simulation, and finally generates coordinate data containing complete information of virtual nodes, effectively solving the test problem caused by overlapping pads. Using virtual node coordinate data, connection matrix and vectorized layer data, the initial wiring path is first generated, and then the optimized path that meets the design rules and obstacle avoidance requirements is obtained through the path optimization algorithm. Finally, combined with the three-dimensional coordinate information of the virtual node, three-dimensional wiring data that can be used for manufacturing and testing is generated, which improves the wiring quality and efficiency. By analyzing the accessibility of the virtual node and optimizing the test point position in combination with the wiring information, data containing complete information of the test point is finally generated, ensuring the accessibility, effectiveness and test coverage of the test point, thereby improving the efficiency and accuracy of the circuit board test. By integrating the three-dimensional wiring data and vectorized layer data and creating a special test point layer, complete layer data containing all necessary information is generated. Subsequent layer optimization and format conversion further improve the manufacturability and data compatibility of the circuit board, and finally output layered layer data that can be directly used for production and testing. Therefore, the present invention provides a method for generating a circuit board design drawing, which effectively solves the wiring problems of complex topological structures and overlapping areas, improves wiring efficiency and quality, and optimizes the performance and reliability of the circuit board. This is particularly important for high-density and high-complexity modern circuit board designs.

[0009] Preferably, step S1 comprises the following steps: Step S11: obtaining an original circuit board design file; vectorizing the layer data of the original circuit board design file to obtain vectorized layer data; Step S12: extracting element connection relationships according to the vectorized layer data to obtain element connection relationship data; classifying the element connection relationship data into connection types to obtain connection type classification data; Step S13: constructing a connection matrix according to the connection type classification data to obtain a connection matrix; Step S14: extract overlapping connections from the connection matrix to obtain overlapping connection data; Step S15: performing overlapping area modeling according to the vectorized layer data and the overlapping connection data to obtain overlapping area modeling data; Step S16: performing current density simulation according to the overlapping area modeling data to obtain current density simulation data; Step S17: performing virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data to obtain virtual node positioning data; Step S18: Generate virtual node coordinate data according to the virtual node positioning data and the overlapping connection data to obtain virtual node coordinate data.

[0010] The present invention converts complex graphic information into vector data that can be processed by a computer by acquiring the original circuit board design file and performing layer data vectorization, laying a foundation for subsequent analysis and processing and improving design efficiency. By extracting element connection relationships and classifying connection types from vectorized layer data, different types of connection relationships, such as direct connection, cross-layer connection and overlapping connection, can be accurately identified and distinguished, providing accurate data support for subsequent connection matrix construction and overlapping area processing. By constructing a connection matrix according to connection type classification data, the connection relationship between circuit elements can be clearly represented, providing a data basis for subsequent virtual node insertion and path reconstruction, and helping to improve wiring efficiency and quality. By extracting overlapping connections from the connection matrix, all overlapping connection relationships can be quickly identified, providing necessary input data for subsequent overlapping area modeling and virtual node positioning, thereby effectively solving the test problems caused by overlapping pads. By modeling overlapping areas according to vectorized layer data and overlapping connection data, the shape, area and center point coordinates of the overlapping area can be accurately calculated, providing an accurate geometric model for subsequent current density simulation, thereby improving simulation accuracy. By simulating the current density based on the overlapping area modeling data, the current distribution in the overlapping area can be accurately predicted, providing a scientific basis for the positioning of virtual nodes, thereby selecting the best test points and improving test coverage. By positioning virtual nodes based on current density simulation data and vectorized layer data, virtual nodes can be placed in locations with high current density and easy probe access, thereby improving the feasibility and accuracy of the test. By generating virtual node coordinate data based on virtual node positioning data and overlapping connection data, various information of virtual nodes, such as ID, coordinates, and pad information, can be integrated into a data structure, providing complete data input for subsequent path reconstruction and test point mapping, thereby improving the efficiency and consistency of the entire design process.

[0011] Preferably, step S15 comprises the following steps: Step S151: extracting pad shapes from vectorized layer data according to overlapping connection data to obtain pad shape data; Step S152: performing irregular pad shape processing on the pad shape data to obtain irregular pad shape processed data; Step S153: performing overlapping area calculation on the irregular pad shape processing data to obtain overlapping area calculation data; Step S154: performing overlapping area verification on the overlapping area calculation data according to the pad shape extraction data to obtain overlapping area verification data; Step S155: Generate overlapping area modeling data according to the overlapping area verification data to obtain overlapping area modeling data.

[0012] The present invention obtains accurate pad shape data by performing pad shape extraction on vectorized layer data according to overlapping connection data, provides necessary geometric information for subsequent overlapping area calculation and modeling, and avoids the error caused by using simplified models. By performing irregular pad shape processing on pad shape data, pads of various shapes can be effectively processed, including circular, rectangular and irregular shapes, thereby improving the accuracy and versatility of overlapping area calculation, and being applicable to a wider range of PCB design scenarios. By performing overlapping area calculation on irregular pad shape processing data, information such as the area, shape and boundary coordinates of the overlapping area can be accurately calculated, thereby providing a reliable data basis for subsequent overlapping area verification and modeling. By performing overlapping area verification on overlapping area calculation data according to pad shape extraction data, the validity and accuracy of the calculated overlapping area can be ensured, thereby avoiding the erroneous results caused by calculation errors or algorithm defects, thereby improving the reliability of the design. By performing overlapping area modeling data generation according to overlapping area verification data, overlapping area model data finally used for subsequent steps can be generated, and the data has been strictly verified, thereby ensuring the accuracy and reliability of the data, thereby providing high-quality input data for subsequent current density simulation and virtual node positioning.

[0013] Preferably, step S16 comprises the following steps: Step S161: using finite element analysis technology to perform overlapping area mesh division on the overlapping area modeling data to obtain overlapping area mesh data; Step S162: performing boundary adjustment settings according to the overlapping area grid data to obtain overlapping area boundary condition data; Step S163: solving the current density field according to the grid data of the overlapping area and the boundary condition data of the overlapping area to obtain the current density field data of the overlapping area; Step S164: Calculate the current density gradient according to the current density field data in the overlapping area to obtain current density gradient data; Step S165: Generate current density simulation results according to the current density gradient data to obtain current density simulation data.

[0014] The present invention uses finite element analysis technology to mesh the overlapping area modeling data in the overlapping area, discretizes the overlapping area, provides the necessary calculation basis for the subsequent current density field solution, and can balance the calculation accuracy and calculation efficiency by controlling the grid density. By setting the boundary adjustment according to the overlapping area grid data, the boundary conditions of the current density simulation, such as the size and direction of the current excitation, can be accurately defined to ensure the accuracy and reliability of the simulation results. By solving the current density field according to the overlapping area grid data and the overlapping area boundary condition data, the accurate distribution of the current density in the overlapping area can be obtained, providing key information for the subsequent positioning of the virtual node. By calculating the current density gradient according to the overlapping area current density field data, the changing trend of the current density in space can be understood, and guidance can be provided for the precise positioning and optimization of the virtual node. For example, the area with the largest current density can be found according to the current density gradient. By generating the current density simulation results according to the current density gradient data, the current density field data and the gradient data can be integrated together to form a complete current density simulation result, which provides the necessary data support for the subsequent virtual node positioning and test point mapping.

[0015] Preferably, step S17 comprises the following steps: Step S171: extracting the current density peak point from the current density simulation data to obtain the current density peak point data; Step S172: performing peak point contact analysis on the current density peak point data according to the vectorized layer data to obtain peak point contact data; Step S173: adjusting the initial position of the virtual node according to the peak point contact data and the current density simulation data to obtain the initial position data of the virtual node; Step S174: performing local reachability analysis of the virtual node according to the initial position data of the virtual node and preset probe contact parameters to obtain local reachability analysis data of the virtual node; Step S175: performing test probe contact optimization according to the virtual node local reachability analysis data, the virtual node initial position data and the vectorized layer data to obtain virtual node contact optimization data; Step S176: Perform virtual node feasibility verification according to the virtual node contact optimization data, the connection matrix and the vectorized layer data to obtain virtual node feasibility verification data; Step S177: Generate virtual node positioning data according to the virtual node feasibility verification data and the virtual node contact optimization data to obtain virtual node positioning data.

[0016] The present invention can quickly find the point with the highest current density by extracting the current density peak point from the current density simulation data, provide a reference for the initial positioning of the virtual node, and improve the efficiency of test point selection. By performing peak point contact analysis on the current density peak point data according to the vectorized layer data, it can be determined whether the extracted peak point is easily contacted by the probe, avoiding the selection of points that are blocked by other components or located in difficult-to-contact areas, thereby improving the feasibility of the test. By adjusting the initial position of the virtual node according to the peak point contact data and the current density simulation data, the initial position of the virtual node can be adjusted according to the contactability of the peak point, ensuring that the virtual node is located in a contactable position with a high current density, thereby improving the accuracy and reliability of the test. By performing local accessibility analysis of the virtual node according to the virtual node initial position data and the preset probe contact parameters, the accessibility of the virtual node can be evaluated more finely, taking into account factors such as the size, shape, and maximum tilt angle of the probe, thereby more accurately determining whether the probe can effectively contact the virtual node. By optimizing the contact of the test probe based on the local reachability analysis data of the virtual node, the initial position data of the virtual node, and the vectorized layer data, the contact position and angle of the test probe can be optimized, the best probe contact method can be found, and the stability and accuracy of the test can be improved. By verifying the feasibility of the virtual node based on the virtual node contact optimization data, the connection matrix, and the vectorized layer data, it can be ensured that the selected virtual node position meets the requirements of the circuit connection and will not conflict with other components or wiring, ensuring the integrity and correctness of the design. By generating virtual node positioning data based on the virtual node feasibility verification data and the virtual node contact optimization data, the final virtual node positioning data can be generated. The data contains the precise position of the virtual node, the pad information to which it belongs, and the recommended probe contact method, providing a reliable data basis for subsequent path reconstruction and test point mapping.

[0017] Preferably, step S2 comprises the following steps: Step S21: adding the virtual node of the virtual node coordinate data to the connection matrix, updating the connection relationship, and obtaining connection relationship update data; Step S22: generating an initial path according to the connection relationship update data and the vectorized layer data to obtain initial path data; Step S23: Optimizing the path according to the initial path data and the vectorized layer data to obtain path optimization data; Step S24: generating a three-dimensional path according to the path optimization data and the virtual node coordinate data to obtain three-dimensional path data; Step S25: converting the three-dimensional path data into a three-dimensional wiring data format to obtain three-dimensional wiring data.

[0018] The present invention can seamlessly integrate virtual nodes into the circuit topology structure by adding virtual nodes of virtual node coordinate data to the connection matrix and updating the connection relationship, providing the correct connection relationship for subsequent path generation and optimization, and effectively solving the problem that overlapping pads cannot be tested independently. By performing initial path generation according to the connection relationship update data and vectorized layer data, an initial path connecting all nodes can be quickly generated, laying a foundation for subsequent path optimization and improving the efficiency of wiring design. By performing path optimization according to the initial path data and the vectorized layer data, the initial path can be optimized according to preset wiring rules and obstacle information, such as shortening the path length, reducing the number of corners and avoiding overlapping with obstacles, thereby improving the performance and manufacturability of the circuit board. By performing three-dimensional path generation according to the path optimization data and the virtual node coordinate data, a two-dimensional path can be converted into a three-dimensional path, considering the cross-layer connection and the three-dimensional coordinates of the virtual node, generating three-dimensional wiring data that is more in line with the actual production environment, and providing more accurate information for subsequent layer generation and circuit testing. By performing 3D wiring data format conversion on 3D path data, the 3D path data can be converted into a standard 3D wiring data format, such as the IPC-2581 format, so that it is compatible with other PCB design software and manufacturing equipment, thereby improving the efficiency of data exchange and the versatility of design.

[0019] Preferably, step S23 includes the following steps: Step S231: segmenting the initial path data to obtain path segmentation data; Step S232: performing obstacle identification on the vectorized layer data to obtain obstacle identification data; Step S233: extracting topological relationships from the path segmentation data to obtain topological relationship data; Step S234: performing topology-aware path optimization on the path segmentation data according to the obstacle identification data and the topology relationship data to obtain topology-aware path optimization data; Step S235: performing path merging according to the path optimization data based on topology perception to obtain path merging data; Step S236: convert the path merging data into a standard data format to obtain path optimization data.

[0020] The present invention performs path segmentation on the initial path data, decomposes the path into smaller line segments, can more finely control and optimize each path segment, improve the flexibility and efficiency of path optimization, and provide basic data for subsequent topology-aware optimization. By performing obstacle recognition on the vectorized layer data, obstacles that need to be avoided during the wiring process, such as components, existing routing and prohibited wiring areas, can be accurately identified, provide necessary constraints for path optimization, and avoid wiring errors. By performing topological relationship extraction on the path segmentation data, the connection relationship between the segments in the path, as well as the connection relationship between the segments and the virtual nodes, can be clearly understood, provide necessary topological information for topology-aware path optimization, and ensure that the optimized path still meets the requirements of circuit connection. By performing topology-aware path optimization on the path segmentation data based on obstacle recognition data and topological relationship data, the topological structure of the circuit can be kept unchanged while optimizing the path, avoiding the introduction of new intersections or loops, thereby improving the signal integrity and reliability of the circuit board. By performing path merging based on topology-aware path optimization data, the optimized segments can be recombined into a complete path, redundant points can be removed, path representation can be simplified, and the efficiency of subsequent processing can be improved. By performing standard data format conversion on the path merging data, the path data can be converted into a standard format, such as Gerber format or ODB++ format, so as to be compatible with other PCB design software and manufacturing equipment, thereby improving the efficiency of data exchange and the versatility of design.

[0021] Preferably, step S3 comprises the following steps: Step S31: performing reachability analysis according to the three-dimensional wiring data, the vectorized layer data and the virtual node coordinate data to obtain reachability analysis data; Step S32: constructing a reachability matrix for the reachability analysis data to obtain a reachability matrix; Step S33: determining the candidate test area for the virtual node coordinate data according to the reachability matrix to obtain candidate test area data; Step S34: optimizing the test point positions of the candidate test area data according to the three-dimensional wiring data to obtain test point position optimization data; Step S35: Generate test point data according to the test point position optimization data and the virtual node coordinate data to obtain the test point data.

[0022] The present invention can comprehensively evaluate the reachability of each virtual node by performing reachability analysis based on three-dimensional wiring data, vectorized layer data, and virtual node coordinate data, taking into account factors such as probe parameters, component layout, and wiring conditions, to provide a reliable basis for subsequent test point selection, and effectively avoid selecting unreachable test points. By constructing a reachability matrix for the reachability analysis data, the reachability relationship between virtual nodes can be clearly represented, such as whether there is a spatial conflict or mutual interference, to provide more comprehensive information for subsequent test point candidate area determination, and to help optimize the test point layout. By determining the test point candidate area for the virtual node coordinate data according to the reachability matrix, suitable test point candidate areas can be screened out according to the reachability scores of the virtual nodes and the spatial relationships between them, thereby improving the efficiency and accuracy of test point selection. By optimizing the test point position for the candidate test area data according to the three-dimensional wiring data, the position of the test point can be further optimized, such as maximizing the distance from the corresponding network wiring to reduce the interference of the probe on the signal transmission, or minimizing the probe movement distance, thereby improving the test efficiency. By generating test point data based on test point position optimization data and virtual node coordinate data, test point data containing complete test point information can be generated, including coordinates, network to which it belongs, corresponding virtual node ID, and recommended probe contact method, etc., providing clear guidance for subsequent circuit board testing.

[0023] Preferably, step S4 comprises the following steps: Step S41: Projecting the three-dimensional wiring data onto the corresponding two-dimensional plane and integrating it with the vectorized layer data to obtain layer data integration data; Step S42: Create a test point layer according to the test point data to obtain test point layer data; Step S43: optimizing the layer data integration data and the test point layer data to obtain layer data optimization data; Step S44: performing layer data format conversion on the layer data optimization data to obtain layer data format conversion data; Step S45: generating layered layer data according to the layer data format conversion data to obtain layered layer data.

[0024] The present invention can convert the three-dimensional wiring information into two-dimensional layer data by projecting the three-dimensional wiring data onto the corresponding two-dimensional plane and integrating it with the vectorized layer data, and merge it with the original layer data to generate complete layer data that can be used for manufacturing, thereby ensuring the consistency and integrity of the design. By creating a test point layer according to the test point data, the test point information can be added to an independent layer, which is convenient for subsequent testing and fault diagnosis, and improves the test efficiency. The clear test point layer information also facilitates PCB manufacturers and testers to understand the design intent. By optimizing the layer data integration data and the test point layer data, the manufacturability and reliability of the circuit board can be further improved. For example, by adjusting the routing spacing, adding teardrops, etc., potential manufacturing problems can be avoided and the electrical performance of the circuit board can be improved. By converting the layer data format of the layer data optimization data, the layer data can be converted into a standard Gerber file format, ensuring that the data can be correctly identified and used by the PCB manufacturer, improving the manufacturability of the design, and avoiding data compatibility issues. By converting data according to the layer data format to generate hierarchical layer data, all Gerber files can be organized according to the level to generate the final hierarchical layer data, which is convenient for PCB manufacturers to produce, ensures the integrity and orderliness of the data, and simplifies the production process.

[0025] Preferably, the present invention also provides a system for generating a circuit board design drawing, which is used to execute the method for generating a circuit board design drawing as described above, and the system for generating a circuit board design drawing comprises: The topological decomposition and virtual node insertion module is used to obtain the original circuit board design file; vectorize the layer data of the original circuit board design file to obtain the vectorized layer data; construct the connection matrix of the component elements according to the vectorized layer data to obtain the connection matrix; perform overlapping area modeling according to the vectorized layer data and the connection matrix to obtain overlapping area modeling data; perform current density simulation according to the overlapping area modeling data to obtain current density simulation data; perform virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data, and generate virtual node coordinate data to obtain virtual node coordinate data; The path reconstruction module is used to generate an initial path according to the virtual node coordinate data, the connection matrix and the vectorized layer data, and optimize the path to obtain the path optimization data; generate three-dimensional wiring data according to the path optimization data and the virtual node coordinate data to obtain the three-dimensional wiring data; The test point mapping module is used to determine the test point candidate area according to the three-dimensional wiring data, the vectorized layer data and the virtual node coordinate data to obtain the candidate test area data; perform test point optimization processing on the candidate test area data to obtain the test point data; The layer generation module is used to integrate layer data according to three-dimensional wiring data and vectorized layer data to obtain layer data integration data; to create test point layers according to test point data to obtain test point layer data; and to generate layered layers according to layer data integration data and test point layer data to obtain layered layer data. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of a process flow of a method for generating a circuit board design drawing; Figure 2 for Figure 1 Detailed implementation steps of step S1 in FIG. Figure 3 for Figure 1 Detailed implementation steps of step S2 in FIG.

[0027] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0028] The technical method of the present invention is described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by technicians in this field without creative work are within the scope of protection of the present invention.

[0029] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0030] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are used only to distinguish one unit from another unit. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0031] To achieve this, please refer to Figures 1 to 3, a method for generating a circuit board design drawing, comprising the following steps: Step S1: obtaining an original circuit board design file; vectorizing the layer data of the original circuit board design file to obtain vectorized layer data; constructing a connection matrix of component elements according to the vectorized layer data to obtain a connection matrix; modeling the overlapping area according to the vectorized layer data and the connection matrix to obtain overlapping area modeling data; simulating the current density according to the overlapping area modeling data to obtain current density simulation data; locating virtual nodes of the overlapping area modeling data according to the current density simulation data and the vectorized layer data, and generating virtual node coordinate data to obtain virtual node coordinate data; Step S2: generating an initial path according to the virtual node coordinate data, the connection matrix and the vectorized layer data, and optimizing the path to obtain path optimization data; generating three-dimensional wiring data according to the path optimization data and the virtual node coordinate data to obtain three-dimensional wiring data; Step S3: determining the candidate test point area according to the three-dimensional wiring data, the vectorized layer data and the virtual node coordinate data to obtain candidate test area data; performing test point optimization processing on the candidate test area data to obtain test point data; Step S4: Integrate layer data according to the three-dimensional wiring data and the vectorized layer data to obtain layer data integration data; create a test point layer according to the test point data to obtain test point layer data; generate layered layers according to the layer data integration data and the test point layer data to obtain layered layer data, so as to realize the circuit board design drawing generation operation.

[0032] In the embodiment of the present invention, reference Figure 1 FIG. 1 is a schematic diagram of a step flow of a method for generating a circuit board design drawing according to the present invention. In this example, the method for generating a circuit board design drawing includes the following steps: Step S1: obtaining an original circuit board design file; vectorizing the layer data of the original circuit board design file to obtain vectorized layer data; constructing a connection matrix of component elements according to the vectorized layer data to obtain a connection matrix; modeling the overlapping area according to the vectorized layer data and the connection matrix to obtain overlapping area modeling data; simulating the current density according to the overlapping area modeling data to obtain current density simulation data; locating virtual nodes of the overlapping area modeling data according to the current density simulation data and the vectorized layer data, and generating virtual node coordinate data to obtain virtual node coordinate data; In an embodiment of the present invention, the original circuit board design file (such as a Gerber file) is first obtained and converted into vectorized layer data to extract the coordinates, line width and other information of the graphic elements. Then, a connection matrix is ​​constructed based on the vectorized layer data to record the connection relationship and type between the component elements, including the level and overlap of the overlapping connections. Next, the overlapping area is modeled according to the vectorized layer data and the connection matrix, and the shape, area and center point coordinates of the overlapping area are calculated. Then, the finite element analysis software is used to simulate the current density of the overlapping area to obtain the current density distribution data. Finally, according to the current density simulation data and the vectorized layer data, the virtual node is located in the overlapping area, and the virtual node coordinate data containing the virtual node ID, coordinates and the pad information to which it belongs is generated.

[0033] Step S2: generating an initial path according to the virtual node coordinate data, the connection matrix and the vectorized layer data, and optimizing the path to obtain path optimization data; generating three-dimensional wiring data according to the path optimization data and the virtual node coordinate data to obtain three-dimensional wiring data; In an embodiment of the present invention, an initial path connecting all nodes is generated based on virtual node coordinate data, a connection matrix, and vectorized layer data, including direct connection, cross-layer connection, and connection through virtual nodes. Then, according to preset wiring rules (such as minimum corner, minimum line length, obstacle avoidance, etc.) and the hierarchical relationship of virtual nodes, the initial path is optimized, for example, using the A* algorithm or the Dijkstra algorithm for path search and optimization. Finally, the optimized two-dimensional path is converted into a three-dimensional path, and the vertical transition of the cross-layer connection and the three-dimensional coordinates of the virtual node are considered to generate three-dimensional wiring data containing the starting point, end point, width, and hierarchical information of each path segment.

[0034] Step S3: determining the candidate test point area according to the three-dimensional wiring data, the vectorized layer data and the virtual node coordinate data to obtain candidate test area data; performing test point optimization processing on the candidate test area data to obtain test point data; In an embodiment of the present invention, the accessibility of each virtual node is analyzed based on the three-dimensional wiring data, the vectorized layer data and the virtual node coordinate data, taking into account the obstruction of the probe parameters and the surrounding environment. The accessibility analysis results are stored in the accessibility matrix to guide the determination of the candidate area of ​​the test point. Then, virtual nodes with higher accessibility are screened according to the accessibility matrix, and the candidate test area is defined with them as the center. Finally, the test point position is optimized within the candidate test area, taking into account the distance from the wiring path and the uniformity of the test point distribution, and generating test point data containing information such as the test point coordinates, the network to which it belongs, the corresponding virtual node ID and the recommended probe contact direction.

[0035] Step S4: integrating layer data according to the three-dimensional wiring data and the vectorized layer data to obtain layer data integration data; creating a test point layer according to the test point data to obtain test point layer data; generating a layered layer according to the layer data integration data and the test point layer data to obtain layered layer data, so as to realize the circuit board design drawing generation operation; In an embodiment of the present invention, the three-dimensional wiring data is projected onto the corresponding two-dimensional plane and integrated with the original vectorized layer data to generate layer data integration data containing all layer information. Then, a new test point layer is created based on the test point data, including information such as the location of the test point, network name, test method and parameters. Next, all layer data are optimized, such as removing redundant data, repairing graphic defects and optimizing graphic layout, to improve the manufacturability and reliability of the circuit board. Finally, the optimized layer data is converted into a standard Gerber file format, and hierarchical layer data is generated according to the hierarchical organization, including all information used for manufacturing and testing.

[0036] Preferably, step S1 comprises the following steps: Step S11: obtaining an original circuit board design file; vectorizing the layer data of the original circuit board design file to obtain vectorized layer data; Step S12: extracting element connection relationships according to the vectorized layer data to obtain element connection relationship data; classifying the element connection relationship data into connection types to obtain connection type classification data; Step S13: constructing a connection matrix according to the connection type classification data to obtain a connection matrix; Step S14: extract overlapping connections from the connection matrix to obtain overlapping connection data; Step S15: performing overlapping area modeling according to the vectorized layer data and the overlapping connection data to obtain overlapping area modeling data; Step S16: performing current density simulation according to the overlapping area modeling data to obtain current density simulation data; Step S17: performing virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data to obtain virtual node positioning data; Step S18: Generate virtual node coordinate data according to the virtual node positioning data and the overlapping connection data to obtain virtual node coordinate data.

[0037] As an example of the present invention, refer to Figure 2 As shown, in this example, step S1 includes: Step S11: obtaining an original circuit board design file; vectorizing the layer data of the original circuit board design file to obtain vectorized layer data; In an embodiment of the present invention, the original circuit board design file is obtained and the layer data is vectorized: first, the original circuit board design file is read, such as a Gerber file, an ODB++ file, etc. The graphic information of each layer (such as a copper layer, a solder mask layer, a silk screen layer, etc.) in the Gerber file is converted into vector data using software such as CAM350. The specific operation is to import the Gerber file into the CAM350 software, select the layer to be vectorized, execute the vectorization command, and convert the graphics into a vector graphic composed of line segments and arcs. Then, the coordinate data, line width, level and other information of the vector graphics are extracted and stored as a specific data structure, such as a DXF format or a custom vector data format. This step outputs the vectorized layer data, which contains the vector representation of the graphic elements in all layers.

[0038] Step S12: extracting element connection relationships according to the vectorized layer data to obtain element connection relationship data; classifying the element connection relationship data into connection types to obtain connection type classification data; In an embodiment of the present invention, element connection relationship extraction and connection type classification are performed based on vectorized layer data: all elements in the vectorized layer data are traversed, and the distance and overlapping area between the elements are calculated. If there is an overlapping area between two pads and they belong to the same network, the overlapping connection relationship between them is recorded, and the overlap degree, that is, the ratio of the overlapping area to the total area of ​​the pads, is calculated. If the center coordinates of a pad and a via completely coincide, and they are in adjacent layers, the cross-layer connection relationship between them is recorded. If there is a wire connection between two pads, the direct connection relationship between them is recorded. All connection relationships are classified according to direct connection, cross-layer connection and overlapping connection, and the classification results and information such as overlap degree are stored in the connection type classification data.

[0039] Step S13: constructing a connection matrix according to the connection type classification data to obtain a connection matrix; In an embodiment of the present invention, a connection matrix is ​​constructed according to the connection type classification data: a two-dimensional matrix is ​​created, and the rows and columns of the matrix represent all nodes in the circuit (including pads, vias, etc.). The values ​​of the matrix elements are filled in according to the connection type classification data. If there is a direct connection relationship between two nodes, the corresponding matrix element value is 1; if there is a cross-layer connection relationship between the two nodes, the corresponding matrix element value is the layer difference; if there is an overlapping connection relationship between the two nodes, the corresponding matrix element value is the overlap degree. The connection matrix finally generated fully describes the connection relationship and connection type between the circuit nodes.

[0040] Step S14: extract overlapping connections from the connection matrix to obtain overlapping connection data; In an embodiment of the present invention, overlapping connection extraction is performed on the connection matrix: the connection matrix is ​​traversed to find all elements whose element values ​​are greater than 0 and less than 1, and these elements represent overlapping connection relationships. The row and column indexes corresponding to these elements are extracted, that is, the IDs of the overlapping pads. The IDs of the overlapping pads, the corresponding overlap degrees, and the hierarchical relationships are stored in the overlapping connection data.

[0041] Step S15: performing overlapping area modeling according to the vectorized layer data and the overlapping connection data to obtain overlapping area modeling data; In the embodiment of the present invention, overlapping area modeling is performed based on vectorized layer data and overlapping connection data: according to the pad ID provided by the overlapping connection data, vector graphics data of the corresponding pad is extracted from the vectorized layer data. The vector graphics of the overlapping pads are intersected using Boolean operations to obtain the precise shape of the overlapping area. The geometric information such as the area and center point coordinates of the overlapping area is calculated, and the information is stored in the overlapping area modeling data.

[0042] Step S16: performing current density simulation according to the overlapping area modeling data to obtain current density simulation data; In an embodiment of the present invention, current density simulation is performed based on the overlapping area modeling data: finite element analysis software such as COMSOL is used to simulate the current density of the overlapping area. First, the overlapping area modeling data is imported into the COMSOL software, and the material properties are set according to the material of the pad. Then, current excitation is applied to the boundary of the overlapping area, such as setting the current magnitude and direction. Next, the overlapping area is meshed, and the mesh data and boundary conditions are input into the COMSOL solver. Finally, the current density field is solved, and the current density distribution data is extracted and stored as current density simulation data.

[0043] Step S17: performing virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data to obtain virtual node positioning data; In an embodiment of the present invention, the overlapping area modeling data is virtual node positioned according to the current density simulation data and the vectorized layer data: the point with the largest current density is extracted from the current density simulation data as the initial position of the virtual node. Then, it is determined whether the initial position is located in a contactable area according to the vectorized layer data, for example, whether it is blocked by other components or located in a narrow gap. If the initial position is not contactable, a nearby contactable area is searched along the current density gradient direction, and the first contactable point found is used as the position of the virtual node. The position information of the virtual node is stored in the virtual node positioning data.

[0044] Step S18: Generate virtual node coordinate data according to the virtual node positioning data and the overlapping connection data to obtain virtual node coordinate data; Generate virtual node coordinate data based on virtual node positioning data and overlapping connection data: Integrate the position coordinates of each virtual node in the virtual node positioning data, the corresponding overlapping pad ID, and the hierarchical relationship information to generate virtual node coordinate data. This data includes the unique identifier, three-dimensional coordinates, and original pad information of each virtual node.

[0045] Preferably, step S15 comprises the following steps: Step S151: extracting pad shapes from vectorized layer data according to overlapping connection data to obtain pad shape data; Step S152: performing irregular pad shape processing on the pad shape data to obtain irregular pad shape processed data; Step S153: performing overlapping area calculation on the irregular pad shape processing data to obtain overlapping area calculation data; Step S154: performing overlapping area verification on the overlapping area calculation data according to the pad shape extraction data to obtain overlapping area verification data; Step S155: Generate overlapping area modeling data according to the overlapping area verification data to obtain overlapping area modeling data.

[0046] In an embodiment of the present invention, pad shape extraction is performed on vectorized layer data according to overlapping connection data: the pad IDs of the pads whose shapes need to be extracted are read from the overlapping connection data. Then, pad graphic elements corresponding to these IDs are searched in the vectorized layer data. Vector contour data of these pad graphic elements are extracted, including coordinates of line segments and arcs constituting the pad shape, endpoint information, etc. The extracted pad shape data is stored as a data structure of a polygon or curve, for example, a series of ordered coordinate points are used to represent the boundary of the pad. The shape data of each pad is stored in association with its corresponding ID.

[0047] Perform irregular pad shape processing on pad shape data: Analyze the extracted pad shape data. If the pad shape is a regular shape, such as a circle or a rectangle, directly record its geometric parameters, such as the radius of the circle or the length and width of the rectangle. If the pad shape is an irregular shape, use methods such as polygon approximation or spline curve fitting to process the irregular shape. For example, for polygon approximation, decompose the irregular shape into multiple small line segments, and use a collection of these line segments to approximate the original shape. Store the processed shape data, including the geometric parameters of the regular shape or the approximation curve parameters of the irregular shape, as irregular pad shape processing data.

[0048] Calculate the overlapping area of ​​irregular pad shape processing data: read two sets of irregular pad shape processing data for which the overlapping area needs to be calculated. If the pad shape is regular, the area and shape of the overlapping area are calculated using geometric formulas based on its geometric parameters. For example, to calculate the overlapping area of ​​two circular pads, the center distance can be calculated first, and then the area and shape of the overlapping area can be calculated based on the center distance and radius. If the pad shape is irregular, the overlapping area of ​​the two irregular shapes is calculated using a polygon clipping algorithm or a curve intersection calculation method. The calculated overlapping area information such as the area, shape, and boundary coordinates is stored as overlapping area calculation data.

[0049] Perform overlapping area verification on the overlapping area calculation data based on the pad shape extraction data: Compare the overlapping area calculated in the overlapping area calculation data with the original pad shape extraction data. Verify whether the overlapping area is completely within the shapes of the two pads and does not exceed the boundaries of the pads. For example, after calculating the overlapping area of ​​two polygonal pads, verify whether the polygon vertices of the overlapping area are all inside the two original pad polygons. Store the verification results, such as the validity of the overlapping area and the degree of matching between the overlapping area and the original pad shape, as overlapping area verification data.

[0050] Generate overlapping area modeling data based on overlapping area verification data: If the overlapping area verification result shows that the overlapping area is valid, extract the shape, area, center point coordinates and other information of the overlapping area in the overlapping area calculation data to generate overlapping area modeling data. If the overlapping area verification result shows that the overlapping area is invalid, for example, the overlapping area calculation is wrong or exceeds the pad boundary, re-execute the overlapping area calculation step, or make corrections according to the specific situation until a valid overlapping area is obtained, and finally generate overlapping area modeling data.

[0051] Preferably, step S16 comprises the following steps: Step S161: using finite element analysis technology to perform overlapping area mesh division on the overlapping area modeling data to obtain overlapping area mesh data; Step S162: performing boundary adjustment settings according to the overlapping area grid data to obtain overlapping area boundary condition data; Step S163: solving the current density field according to the grid data of the overlapping area and the boundary condition data of the overlapping area to obtain the current density field data of the overlapping area; Step S164: Calculate the current density gradient according to the current density field data in the overlapping area to obtain current density gradient data; Step S165: Generate current density simulation results according to the current density gradient data to obtain current density simulation data.

[0052] In an embodiment of the present invention, the overlapping area modeling data is meshed using finite element analysis technology: the overlapping area modeling data is imported into finite element analysis software, such as ANSYS or COMSOL. According to the geometric shape and size of the overlapping area, the meshing parameters, such as the maximum unit size, the minimum unit size, and the mesh growth rate, are set. The overlapping area is meshed to generate a mesh composed of basic units such as triangles or quadrilaterals. The generated mesh data, including information such as the node coordinates of each unit, the unit type, and the connection relationship between the units, is stored as the overlapping area mesh data. Ensure that the mesh density is fine enough to accurately capture the details of the current density distribution. For example, a smaller mesh size can be used at the edge of the overlapping area or in areas where the current density changes dramatically.

[0053] Boundary adjustment settings based on overlapping area grid data: Based on the overlapping area grid data, define the boundary conditions of the current density simulation. Apply current excitation to the boundary of the overlapping area, for example, set the magnitude and direction of the input current. The specific current excitation setting method can be selected according to the actual situation. For example, the boundary of the overlapping area can be defined as a constant current density boundary or a constant potential boundary. The set boundary conditions, including boundary type, boundary value, and which grid nodes are acted on, are stored as overlapping area boundary condition data.

[0054] Solve the current density field based on the overlapping area mesh data and the overlapping area boundary condition data: Input the overlapping area mesh data and the overlapping area boundary condition data into the solver of the finite element analysis software. The solver calculates the current density distribution in the overlapping area based on Maxwell's equations and related material properties. The solution process usually adopts a numerical iteration method, such as the finite element method or the finite difference method. The solved current density field data, including the current density value at each mesh node, is stored as the overlapping area current density field data.

[0055] Calculate the current density gradient based on the current density field data in the overlapping area: Calculate the gradient of the current density based on the current density field data in the overlapping area. The current density gradient represents the rate of change and direction of the current density in space. Numerical differentiation methods, such as the finite difference method, can be used to calculate the current density gradient at each grid node. The calculated current density gradient data, including the gradient value and direction at each grid node, are stored as current density gradient data.

[0056] Generate current density simulation results based on current density gradient data: Integrate the overlapping area current density field data, current density gradient data, and overlapping area grid data to generate current density simulation data. The current density simulation data contains the current density distribution, gradient information, and grid information of the overlapping area, which can be used for subsequent virtual node positioning. For example, the current density data can be visualized to more intuitively observe the current density distribution.

[0057] Preferably, step S17 comprises the following steps: Step S171: extracting the current density peak point from the current density simulation data to obtain the current density peak point data; Step S172: performing peak point contact analysis on the current density peak point data according to the vectorized layer data to obtain peak point contact data; Step S173: adjusting the initial position of the virtual node according to the peak point contact data and the current density simulation data to obtain the initial position data of the virtual node; Step S174: performing local reachability analysis of the virtual node according to the initial position data of the virtual node and preset probe contact parameters to obtain local reachability analysis data of the virtual node; Step S175: performing test probe contact optimization according to the virtual node local reachability analysis data, the virtual node initial position data and the vectorized layer data to obtain virtual node contact optimization data; Step S176: Perform virtual node feasibility verification according to the virtual node contact optimization data, the connection matrix and the vectorized layer data to obtain virtual node feasibility verification data; Step S177: Generate virtual node positioning data according to the virtual node feasibility verification data and the virtual node contact optimization data to obtain virtual node positioning data.

[0058] In an embodiment of the present invention, current density peak point extraction is performed on current density simulation data: the current density simulation data is analyzed to find the point with the largest current density. A search algorithm can be used, for example, to traverse all grid nodes to find the node with the largest current density value. The coordinates of the node and the corresponding current density value are extracted. If there are multiple maximum value points with the same current density, the coordinates and current density values ​​of all these points are extracted. The extracted peak point coordinates and current density values ​​are stored as current density peak point data.

[0059] Perform peak point contact analysis on current density peak point data based on vectorized layer data: Compare the coordinates in the current density peak point data with the vectorized layer data. Check whether the peak point is located in any area that hinders the test probe from contacting, such as the component body, pad edge, or other inaccessible areas. For example, calculate the distance between the peak point and the surrounding components to determine whether the peak point is blocked by other components. Store the analysis results, such as whether the peak point is contactable, and if not, the specific reason for the inaccessibility, such as which component is blocking it, as peak point contact data.

[0060] Adjust the initial position of the virtual node according to the peak point contact data and current density simulation data: If the peak point contact analysis results show that the peak point is contactable, the coordinates of the peak point are used as the initial position of the virtual node. If the peak point is not contactable, search for nearby contactable areas along the opposite direction of the gradient according to the current density gradient information in the current density simulation data. During the search process, continue to check whether the new position is contactable until the first contactable point is found. The coordinates of this point are used as the initial position of the virtual node and stored as the initial position data of the virtual node.

[0061] Perform local reachability analysis of the virtual node based on the virtual node initial position data and preset probe contact parameters: Perform local reachability analysis around the virtual node initial position based on preset probe contact parameters, such as the probe diameter, probe shape, and probe maximum tilt angle. Simulate the contact of the test probe at different directions and angles of the virtual node initial position. Determine whether the probe can contact the virtual node initial position while meeting the preset parameters. Store the analysis results, such as the probe's reachability score at different directions and angles, as virtual node local reachability analysis data.

[0062] Optimize the contact of the test probe according to the local accessibility analysis data of the virtual node, the initial position data of the virtual node, and the vectorized layer data: According to the local accessibility analysis data of the virtual node, select the direction and angle with the highest accessibility score as the optimal contact direction and angle of the test probe. If the accessibility score is lower than the preset threshold, search for a better test point position near the initial position of the virtual node according to the vectorized layer data and the current density simulation data, and re-perform the local accessibility analysis until a test point position that meets the accessibility requirements is found. The optimized test point position coordinates and the optimal contact direction and angle of the probe are stored as virtual node contact optimization data.

[0063] Perform virtual node feasibility verification based on virtual node contact optimization data, connection matrix, and vectorized layer data: Check whether the test point location in the virtual node contact optimization data meets the circuit connection requirements. For example, check the connectivity between the test point and the corresponding pad in the connection matrix, and whether the test point is located in the correct network. At the same time, check whether the test point location conflicts with other components or wiring based on the vectorized layer data. The verification results, such as whether the test point meets the circuit connection requirements and whether it conflicts with other elements, are stored as virtual node feasibility verification data.

[0064] Generate virtual node positioning data based on virtual node feasibility verification data and virtual node contact optimization data: If the virtual node feasibility verification result shows that the test point position is feasible, the test point position coordinates, corresponding pad ID, hierarchical relationship, and optimal contact direction and angle of the probe in the virtual node contact optimization data are integrated together to generate virtual node positioning data. If the virtual node feasibility verification result shows that the test point position is not feasible, re-execute the virtual node initial position adjustment and test probe contact optimization steps until a feasible test point position is found, and finally generate virtual node positioning data.

[0065] Preferably, step S2 comprises the following steps: Step S21: adding the virtual node of the virtual node coordinate data to the connection matrix, updating the connection relationship, and obtaining connection relationship update data; Step S22: generating an initial path according to the connection relationship update data and the vectorized layer data to obtain initial path data; Step S23: Optimizing the path according to the initial path data and the vectorized layer data to obtain path optimization data; Step S24: generating a three-dimensional path according to the path optimization data and the virtual node coordinate data to obtain three-dimensional path data; Step S25: converting the three-dimensional path data into a three-dimensional wiring data format to obtain three-dimensional wiring data.

[0066] As an example of the present invention, refer to Figure 3 As shown, in this example, step S2 includes: Step S21: adding the virtual node of the virtual node coordinate data to the connection matrix, updating the connection relationship, and obtaining connection relationship update data; In an embodiment of the present invention, a virtual node of the virtual node coordinate data is added to the connection matrix to update the connection relationship: the virtual node coordinate data is read to obtain the ID of each virtual node and the ID of the original pad to which it is connected. The connection matrix is ​​modified to connect the nodes originally connected to the overlapping pads to the corresponding virtual nodes. The specific operation is as follows: rows and columns representing virtual nodes are added to the connection matrix, and the connection relationship between the virtual nodes and the corresponding original pads is updated to the matrix. For example, if there is an overlap between pad A and pad B, a virtual node V is inserted, the connection relationship between A and B in the connection matrix is ​​deleted, and a new connection relationship is established between A and V, and between B and V. The updated connection matrix is ​​stored as connection relationship update data.

[0067] Step S22: generating an initial path according to the connection relationship update data and the vectorized layer data to obtain initial path data; In an embodiment of the present invention, the initial path is generated according to the connection relationship update data and the vectorized layer data: the connection relationship update data is read to obtain the connection relationship between all nodes. For each connection relationship, the coordinates of the connection node are obtained according to the vectorized layer data. If there is a direct connection relationship or a cross-layer connection relationship between two nodes, the coordinates of the two nodes are directly connected by a straight line segment to generate an initial path. If the connection relationship involves a virtual node, the coordinates of the virtual node are used as the middle point, and two straight line segments are used to connect the coordinates of the virtual node and the two original pads respectively to generate an initial path. The generated initial path data is stored as a series of line segments, each line segment contains information such as the starting point coordinates, the end point coordinates, and the layer to which it belongs.

[0068] Step S23: Optimizing the path according to the initial path data and the vectorized layer data to obtain path optimization data; In an embodiment of the present invention, path optimization is performed based on the initial path data and the vectorized layer data: the initial path data and the vectorized layer data are read. The initial path is optimized to meet preset routing rules, such as minimum corners, minimum line lengths, and obstacle avoidance. A path search algorithm, such as an A* algorithm or a Dijkstra algorithm, can be used to optimize the initial path in combination with obstacle information identified in the vectorized layer data. During the optimization process, the shape, position, and level of the path can be adjusted to reduce the path length, the number of corners, and the overlap with obstacles. The optimized path data, including the starting point coordinates, the end point coordinates, the line width, and the level of each path segment, is stored as path optimization data.

[0069] Step S24: generating a three-dimensional path according to the path optimization data and the virtual node coordinate data to obtain three-dimensional path data; In an embodiment of the present invention, a three-dimensional path is generated based on the path optimization data and the virtual node coordinate data: the path optimization data and the virtual node coordinate data are read. The two-dimensional path is converted into a three-dimensional path based on the hierarchical information of each path segment in the path optimization data and the three-dimensional coordinates of the virtual node in the virtual node coordinate data. For cross-layer connections, vertical path segments connecting different layers are generated based on the starting layer and ending layer of the connection, as well as the location of the vias. For connections involving virtual nodes, a three-dimensional path segment connecting the virtual node and the pad is generated based on the three-dimensional coordinates of the virtual node and the level of the connection pad. The generated three-dimensional path data is stored as a series of three-dimensional line segments, each of which contains information such as the three-dimensional coordinates of the starting point, the three-dimensional coordinates of the end point, the line width, and the level to which it belongs.

[0070] Step S25: converting the three-dimensional path data into a three-dimensional wiring data format to obtain three-dimensional wiring data; In an embodiment of the present invention, the three-dimensional path data is converted into a three-dimensional wiring data format: the three-dimensional path data is read. The three-dimensional path data is converted into a standard three-dimensional wiring data format, such as the IPC-2581 format. During the conversion process, the line segment information, layer information, and line width information in the three-dimensional path data need to be converted into a corresponding data structure in the target format. For example, each three-dimensional line segment is converted into a wiring element in the target format, and its attributes, such as the starting point coordinates, the end point coordinates, the line width, and the network to which it belongs, are set. The converted data is stored as three-dimensional wiring data.

[0071] Preferably, step S23 includes the following steps: Step S231: segmenting the initial path data to obtain path segmentation data; Step S232: performing obstacle identification on the vectorized layer data to obtain obstacle identification data; Step S233: extracting topological relationships from the path segmentation data to obtain topological relationship data; Step S234: performing topology-aware path optimization on the path segmentation data according to the obstacle identification data and the topology relationship data to obtain topology-aware path optimization data; Step S235: performing path merging according to the path optimization data based on topology perception to obtain path merging data; Step S236: convert the path merging data into a standard data format to obtain path optimization data.

[0072] In an embodiment of the present invention, the initial path data is read, and each path is segmented according to the inflection points and vias. For example, if a path contains two inflection points and one via, it is divided into four segments: from the starting point to the first inflection point, from the first inflection point to the via, from the via to the second inflection point, and from the second inflection point to the end point. Each path segment is stored as an independent line segment, including information such as the starting point coordinates, the end point coordinates, the line width, and the level to which it belongs. All segmented path data are stored as path segment data.

[0073] Obstacle identification for vectorized layer data: Analyze the vectorized layer data and identify all obstacles that may hinder routing, such as component shapes, existing routing, prohibited routing areas, etc. Extract the geometric shape and location information of these obstacles, for example, use polygons to represent the boundaries of obstacles. All identified obstacle information, including obstacle type, geometric shape, location, and hierarchy, is stored as obstacle identification data.

[0074] Extract topological relationships from path segmentation data: Analyze the connection relationships between line segments in the path segmentation data and the connection relationships between line segments and virtual nodes. For example, record which line segments share the same endpoints and which line segments are connected to the same virtual node. Store these connection relationships as topological relationship data, and use graph data structures to represent the connection relationships between nodes and edges.

[0075] Perform topology-aware path optimization on the path segmentation data based on the obstacle identification data and the topological relationship data: Optimize the path segmentation data using a topology-aware path optimization algorithm, such as an improved algorithm based on the A* algorithm or the Dijkstra algorithm. During the optimization process, consider the obstacle information in the obstacle identification data and the connection relationship between the line segments in the topological relationship data. For example, when searching for the shortest path, avoid the obstacle area and keep the topological relationship between the line segments unchanged to avoid new intersections or loops. The optimized path segmentation data, including the starting point coordinates, end point coordinates, line width, and level of each line segment, is stored as topology-aware path optimization data.

[0076] Path merging based on topology-aware path optimization data: Read topology-aware path optimization data. Merge line segments belonging to the same path into a complete path. During the merging process, remove redundant points between line segments. For example, if two line segments share an endpoint and are on the same straight line, merge the two line segments into one line segment. Store the merged path data, including the starting point coordinates, end point coordinates, all intermediate turning point coordinates, line width, and hierarchy information of each path, as path merging data.

[0077] Convert the path merge data to a standard data format: Read the path merge data. Convert the path merge data to a standard path data format, for example, convert the coordinate information, line width information, and layer information of each path to the corresponding data structure of the target format. Ensure that the converted data format meets the requirements of the PCB design software, for example, the path data can be converted to Gerber format or ODB++ format. Store the converted data as path optimization data.

[0078] Preferably, step S3 comprises the following steps: Step S31: performing reachability analysis according to the three-dimensional wiring data, the vectorized layer data and the virtual node coordinate data to obtain reachability analysis data; Step S32: constructing a reachability matrix for the reachability analysis data to obtain a reachability matrix; Step S33: determining the candidate test area for the virtual node coordinate data according to the reachability matrix to obtain candidate test area data; Step S34: optimizing the test point positions of the candidate test area data according to the three-dimensional wiring data to obtain test point position optimization data; Step S35: Generate test point data according to the test point position optimization data and the virtual node coordinate data to obtain the test point data.

[0079] In an embodiment of the present invention, a reachability analysis is performed based on three-dimensional wiring data, vectorized layer data, and virtual node coordinate data: the three-dimensional wiring data, vectorized layer data, and virtual node coordinate data are read. For each virtual node, according to preset probe parameters (such as probe diameter, probe shape, and maximum tilt angle), the process of the probe approaching the virtual node from different directions and angles is simulated. The collision detection algorithm is used to detect whether the probe collides with other components, wiring, or board edges during movement. Based on the collision detection results, the reachability score of the virtual node is calculated, such as the number of reachable directions, the maximum reachable angle, or the minimum collision distance. The reachability score and related information (such as reachable direction, angle) of each virtual node are stored as reachability analysis data.

[0080] Construct a reachability matrix for reachability analysis data: Based on the reachability analysis data, create a matrix in which rows and columns represent virtual nodes. Each element of the matrix represents the reachability relationship between two corresponding virtual nodes. For example, the element value can indicate whether two virtual nodes can be accessed by the probe at the same time, or whether there is a spatial conflict between them, such as the reachability direction of one node is blocked by another node. Store the constructed reachability matrix as reachability matrix data.

[0081] Determine the candidate test point area for the virtual node coordinate data according to the accessibility matrix: Analyze the accessibility matrix and the virtual node coordinate data. According to the accessibility score and the spatial conflict information in the accessibility matrix, select the virtual nodes with higher accessibility as the center points of the candidate test point area. For example, select virtual nodes with accessibility scores higher than a preset threshold, and exclude nodes that have spatial conflicts with other high-accessibility nodes. Define a rectangular or circular area as the candidate test point area with each selected virtual node as the center. Store the information such as the center point coordinates, area shape and size of the candidate area as the candidate test area data.

[0082] Optimize the test point position of the candidate test area data according to the three-dimensional wiring data: read the three-dimensional wiring data and the candidate test area data. In each candidate test area, find the best test point position. The optimization goal can be to maximize the distance from the corresponding network wiring to avoid the probe interfering with the signal transmission, or to minimize the probe movement distance. An optimization algorithm, such as a gradient descent method or a genetic algorithm, can be used to search for the best test point position in the candidate area. The optimized test point position coordinates are stored as test point position optimization data.

[0083] Generate test point data based on test point location optimization data and virtual node coordinate data: Combine test point location optimization data and virtual node coordinate data to generate final test point data. Test point data contains information such as the coordinates of each test point, the network it belongs to, the corresponding virtual node ID, and the recommended probe contact direction and angle. This information will be used to guide subsequent circuit testing processes, such as generating test programs and controlling test equipment.

[0084] Preferably, step S4 comprises the following steps: Step S41: Projecting the three-dimensional wiring data onto the corresponding two-dimensional plane and integrating it with the vectorized layer data to obtain layer data integration data; Step S42: Create a test point layer according to the test point data to obtain test point layer data; Step S43: optimizing the layer data integration data and the test point layer data to obtain layer data optimization data; Step S44: performing layer data format conversion on the layer data optimization data to obtain layer data format conversion data; Step S45: generating layered layer data according to the layer data format conversion data to obtain layered layer data.

[0085] In an embodiment of the present invention, the three-dimensional wiring data is projected onto a corresponding two-dimensional plane and integrated with the vectorized layer data: the three-dimensional wiring data is read and projected onto a corresponding two-dimensional plane according to the hierarchical information of each wiring segment. For example, the top-level wiring is projected onto the top-level plane, and the bottom-level wiring is projected onto the bottom-level plane. The projected two-dimensional wiring data is merged with the original vectorized layer data. For example, the wiring data projected onto the top layer is added to the top-level vectorized layer data, and the wiring data projected onto the bottom layer is added to the bottom-level vectorized layer data. The integrated layer data is stored as layer data integration data, which includes vector representations of graphic elements in all layers, including the original graphic elements and the projected wiring.

[0086] Create a test point layer based on the test point data: Create a new layer and name it the test point layer. Read the test point data and add the location information of each test point to the test point layer. You can use specific graphic symbols to represent test points, such as circles or crosses. At the same time, add the attribute information of the test point, such as the network it belongs to, the test method, the test parameters, etc., to the test point layer as the attribute of the graphic symbol. Store the created test point layer data as test point layer data, which contains the graphic symbols, location information, and attribute information of all test points.

[0087] Optimize layer data for layer data integration and test point layer data: Read layer data integration data and test point layer data. Optimize all layer data, such as removing redundant data, repairing graphic defects, optimizing graphic layout, etc. You can use rule-based optimization algorithms to optimize layer data according to preset design rules and manufacturing process requirements. For example, adjust trace spacing, add teardrops, check minimum line width and line spacing, etc. Store the optimized layer data as layer data optimization data, including optimized graphic elements in all layers.

[0088] Perform layer data format conversion on layer data optimization data: Read layer data optimization data. Convert the optimized layer data into the standard Gerber file format. During the conversion process, it is necessary to convert the data of each layer into the corresponding Gerber file and set the parameters of the Gerber file, such as coordinate unit, data format, graphic accuracy, etc. Ensure that the generated Gerber file meets the requirements of the PCB manufacturer. Store the converted Gerber file as layer data format conversion data.

[0089] Generate hierarchical layer data according to the layer data format conversion data: Read all Gerber files in the layer data format conversion data. Organize the Gerber files into a hierarchical data structure according to the level to which each Gerber file belongs. For example, store the top Gerber file, bottom Gerber file, solder mask layer Gerber file, etc. in the corresponding hierarchical directory respectively. Store the organized hierarchical layer data as hierarchical layer data, which contains all Gerber files used for manufacturing and testing, and is organized by level so that PCB manufacturers can use it directly.

[0090] Preferably, the present invention also provides a system for generating a circuit board design drawing, which is used to execute the method for generating a circuit board design drawing as described above, and the system for generating a circuit board design drawing comprises: The topological decomposition and virtual node insertion module is used to obtain the original circuit board design file; vectorize the layer data of the original circuit board design file to obtain the vectorized layer data; construct the connection matrix of the component elements according to the vectorized layer data to obtain the connection matrix; perform overlapping area modeling according to the vectorized layer data and the connection matrix to obtain overlapping area modeling data; perform current density simulation according to the overlapping area modeling data to obtain current density simulation data; perform virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data, and generate virtual node coordinate data to obtain virtual node coordinate data; The path reconstruction module is used to generate an initial path according to the virtual node coordinate data, the connection matrix and the vectorized layer data, and optimize the path to obtain the path optimization data; generate three-dimensional wiring data according to the path optimization data and the virtual node coordinate data to obtain the three-dimensional wiring data; The test point mapping module is used to determine the test point candidate area according to the three-dimensional wiring data, the vectorized layer data and the virtual node coordinate data to obtain the candidate test area data; perform test point optimization processing on the candidate test area data to obtain the test point data; The layer generation module is used to integrate layer data according to three-dimensional wiring data and vectorized layer data to obtain layer data integration data; to create test point layers according to test point data to obtain test point layer data; and to generate layered layers according to layer data integration data and test point layer data to obtain layered layer data.

[0091] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0092] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A method for generating a circuit board design drawing, characterized in that: The following steps are involved: Step S1: Obtain the original circuit board design file; Vectorize the layer data of the original circuit board design file to obtain vectorized layer data; Construct a connection matrix of component elements according to the vectorized layer data to obtain a connection matrix; perform overlapping area modeling according to the vectorized layer data and the connection matrix to obtain overlapping area modeling data; Perform current density simulation according to the overlapping area modeling data to obtain current density simulation data; perform virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data, and generate virtual node coordinate data to obtain virtual node coordinate data; Step S2: generating an initial path according to the virtual node coordinate data, the connection matrix and the vectorized layer data, and optimizing the path to obtain path optimization data; Generate three-dimensional wiring data according to the path optimization data and the virtual node coordinate data to obtain three-dimensional wiring data; Step S3: determining the candidate test point area according to the three-dimensional wiring data, the vectorized layer data and the virtual node coordinate data to obtain the candidate test area data; Performing test point optimization processing on the candidate test area data to obtain test point data; Step S4: integrating layer data according to the three-dimensional wiring data and the vectorized layer data to obtain layer data integration data; Create a test point layer according to the test point data to obtain the test point layer data; Layered layer generation is performed based on the layer data integration data and the test point layer data to obtain layered layer data to achieve the circuit board design drawing generation operation.

2. The method for generating a circuit board design drawing according to claim 1, characterized in that: Step S1 includes the following steps: Step S11: obtaining an original circuit board design file; vectorizing the layer data of the original circuit board design file to obtain vectorized layer data; Step S12: extracting element connection relationships according to the vectorized layer data to obtain element connection relationship data; classifying the element connection relationship data into connection types to obtain connection type classification data; Step S13: constructing a connection matrix according to the connection type classification data to obtain a connection matrix; Step S14: extract overlapping connections from the connection matrix to obtain overlapping connection data; Step S15: performing overlapping area modeling according to the vectorized layer data and the overlapping connection data to obtain overlapping area modeling data; Step S16: performing current density simulation according to the overlapping area modeling data to obtain current density simulation data; Step S17: performing virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data to obtain virtual node positioning data; Step S18: Generate virtual node coordinate data according to the virtual node positioning data and the overlapping connection data to obtain virtual node coordinate data.

3. The method for generating a circuit board design drawing according to claim 2, characterized in that: Step S15 includes the following steps: Step S151: extracting pad shapes from vectorized layer data according to overlapping connection data to obtain pad shape data; Step S152: performing irregular pad shape processing on the pad shape data to obtain irregular pad shape processed data; Step S153: performing overlapping area calculation on the irregular pad shape processing data to obtain overlapping area calculation data; Step S154: performing overlapping area verification on the overlapping area calculation data according to the pad shape extraction data to obtain overlapping area verification data; Step S155: Generate overlapping area modeling data according to the overlapping area verification data to obtain overlapping area modeling data.

4. The method for generating a circuit board design drawing according to claim 2, characterized in that: Step S16 includes the following steps: Step S161: using finite element analysis technology to perform overlapping area mesh division on the overlapping area modeling data to obtain overlapping area mesh data; Step S162: performing boundary adjustment settings according to the overlapping area grid data to obtain overlapping area boundary condition data; Step S163: solving the current density field according to the grid data of the overlapping area and the boundary condition data of the overlapping area to obtain the current density field data of the overlapping area; Step S164: Calculate the current density gradient according to the current density field data in the overlapping area to obtain current density gradient data; Step S165: Generate current density simulation results according to the current density gradient data to obtain current density simulation data.

5. The method for generating a circuit board design drawing according to claim 2, characterized in that: Step S17 includes the following steps: Step S171: extracting the current density peak point from the current density simulation data to obtain the current density peak point data; Step S172: performing peak point contact analysis on the current density peak point data according to the vectorized layer data to obtain peak point contact data; Step S173: adjusting the initial position of the virtual node according to the peak point contact data and the current density simulation data to obtain the initial position data of the virtual node; Step S174: performing local reachability analysis of the virtual node according to the initial position data of the virtual node and preset probe contact parameters to obtain local reachability analysis data of the virtual node; Step S175: performing test probe contact optimization according to the virtual node local reachability analysis data, the virtual node initial position data and the vectorized layer data to obtain virtual node contact optimization data; Step S176: Perform virtual node feasibility verification according to the virtual node contact optimization data, the connection matrix and the vectorized layer data to obtain virtual node feasibility verification data; Step S177: Generate virtual node positioning data according to the virtual node feasibility verification data and the virtual node contact optimization data to obtain virtual node positioning data.

6. The method for generating a circuit board design drawing according to claim 1, characterized in that: Step S2 includes the following steps: Step S21: adding the virtual node of the virtual node coordinate data to the connection matrix, updating the connection relationship, and obtaining connection relationship update data; Step S22: generating an initial path according to the connection relationship update data and the vectorized layer data to obtain initial path data; Step S23: Optimizing the path according to the initial path data and the vectorized layer data to obtain path optimization data; Step S24: generating a three-dimensional path according to the path optimization data and the virtual node coordinate data to obtain three-dimensional path data; Step S25: converting the three-dimensional path data into a three-dimensional wiring data format to obtain three-dimensional wiring data.

7. The method for generating a circuit board design drawing according to claim 6, characterized in that: Step S23 includes the following steps: Step S231: segmenting the initial path data to obtain path segmentation data; Step S232: performing obstacle identification on the vectorized layer data to obtain obstacle identification data; Step S233: extracting topological relationships from the path segmentation data to obtain topological relationship data; Step S234: performing topology-aware path optimization on the path segmentation data according to the obstacle identification data and the topology relationship data to obtain topology-aware path optimization data; Step S235: performing path merging according to the path optimization data based on topology perception to obtain path merging data; Step S236: convert the path merging data into a standard data format to obtain path optimization data.

8. The method for generating a circuit board design drawing according to claim 1, characterized in that: Step S3 includes the following steps: Step S31: performing reachability analysis according to the three-dimensional wiring data, the vectorized layer data and the virtual node coordinate data to obtain reachability analysis data; Step S32: constructing a reachability matrix for the reachability analysis data to obtain a reachability matrix; Step S33: determining the candidate test area for the virtual node coordinate data according to the reachability matrix to obtain candidate test area data; Step S34: optimizing the test point positions of the candidate test area data according to the three-dimensional wiring data to obtain test point position optimization data; Step S35: Generate test point data according to the test point position optimization data and the virtual node coordinate data to obtain the test point data.

9. The method for generating a circuit board design drawing according to claim 1, characterized in that: Step S4 includes the following steps: Step S41: Projecting the three-dimensional wiring data onto the corresponding two-dimensional plane and integrating it with the vectorized layer data to obtain layer data integration data; Step S42: Create a test point layer according to the test point data to obtain test point layer data; Step S43: optimizing the layer data integration data and the test point layer data to obtain layer data optimization data; Step S44: performing layer data format conversion on the layer data optimization data to obtain layer data format conversion data; Step S45: generating layered layer data according to the layer data format conversion data to obtain layered layer data.

10. A system for generating a circuit board design drawing, characterized in that: Used to execute the method for generating a circuit board design drawing according to claim 1, the system for generating a circuit board design drawing comprises: The topological decomposition and virtual node insertion module is used to obtain the original circuit board design file; vectorize the layer data of the original circuit board design file to obtain the vectorized layer data; construct the connection matrix of the component elements according to the vectorized layer data to obtain the connection matrix; perform overlapping area modeling according to the vectorized layer data and the connection matrix to obtain overlapping area modeling data; perform current density simulation according to the overlapping area modeling data to obtain current density simulation data; perform virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data, and generate virtual node coordinate data to obtain virtual node coordinate data; The path reconstruction module is used to generate an initial path according to the virtual node coordinate data, the connection matrix and the vectorized layer data, and optimize the path to obtain the path optimization data; generate three-dimensional wiring data according to the path optimization data and the virtual node coordinate data to obtain the three-dimensional wiring data; The test point mapping module is used to determine the test point candidate area according to the three-dimensional wiring data, the vectorized layer data and the virtual node coordinate data to obtain the candidate test area data; perform test point optimization processing on the candidate test area data to obtain the test point data; The layer generation module is used to integrate layer data according to three-dimensional wiring data and vectorized layer data to obtain layer data integration data; to create test point layers according to test point data to obtain test point layer data; and to generate layered layers according to layer data integration data and test point layer data to obtain layered layer data.

Images