Multi-mode temperature correction scheme for resistive random access memory

Abstract

The invention discloses a multi-mode temperature correction scheme for a resistive random access memory, which comprises the following steps of: firstly, carrying out mathematical modeling on temperature characteristics of a resistive random access memory, deducing a relational expression between column current and actual current of a memory array, further obtaining a corresponding temperature correction formula, and correcting read current; the correction scheme is suitable for a single-device gating mode and a multi-device gating mode at the same time, and the reading reliability of the memory working under the high-temperature condition can be effectively improved. According to the invention, a parallel structure is further introduced to save extra time overhead brought by implementing the correction scheme. The method has important value in high-density storage and storage and calculation integrated application.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor devices and integrated circuits, and in particular relates to a multi-mode temperature correction scheme for resistive random access memory. Background Art

[0002] Among many emerging storage technologies, resistive random access memory (RRAM) has shown great potential in improving chip area and power efficiency due to its advantages of easy multi-value storage, low power consumption, non-volatility and high integration, making it of great technical value in data storage and storage-computing applications. However, with the rapid development of memory chips towards high storage density and three-dimensional integration, the heating problem faced by RRAM is becoming increasingly prominent. As its basic unit, the conductance of the RRAM device is highly sensitive to temperature changes. Temperature rise will significantly cause conductance offset, resulting in a strong dependence of the gate current of the storage array on temperature. This phenomenon seriously affects the stability and reliability of the read operation and becomes one of the key factors hindering its large-scale application. Therefore, it is particularly important to design a universal temperature correction scheme for RRAM, and its design mainly faces the following two challenges. First, the device itself has complex temperature characteristics: Studies have found that RRAM exhibits temperature characteristics similar to semiconductors in the low-conductivity state, that is, the conductance is positively correlated with temperature; while in the high-conductivity state, it exhibits temperature characteristics similar to metals, that is, the conductance is negatively correlated with temperature. Secondly, the memory needs to meet the application requirements of multiple modes. For example, in storage and computing applications, the memory needs to flexibly switch between single-device gating and multi-device gating modes. The temperature characteristics of the resistive variable device are mathematically modeled, and the relationship between the column current and the actual current is derived, thereby obtaining the corresponding temperature correction formula. Summary of the invention

[0003] In order to solve the problem that the reliability and stability of resistive random access memory decrease with the increase of temperature, the present invention proposes a multi-mode temperature correction scheme for resistive random access memory. The correction scheme can effectively improve the reliability of memory reading under high temperature conditions, and is applicable to both single device gating mode and multi-device gating mode.

[0004] In order to achieve the above object, the present invention adopts the following technical solution:

[0005] For a memory array composed of m×n RSDs (m and n are positive integers), the temperature characteristics of a single RSD are first mathematically modeled. The temperature characteristic curves of each resistance state of the RSD are obtained by testing. From the characteristic curves, it can be found that within a local temperature range, the relationship between the conductivity and temperature of a certain resistance state can be linearized, and the formula obtained by modeling is shown as follows:

[0006]

[0007] Where T is any temperature, T 0 is the rated operating temperature, G ij The unit device on the i-th row and j-th column of the memory array is at T 0 The conductivity at temperature, is the conductance value of the unit device on the i-th row and j-th column of the memory array at temperature T, β, G M It is a constant extracted from the temperature characteristic curve of each resistance state of the resistive switching device obtained from the test, and is only related to the resistive switching device itself. 1≤i≤m, 1≤j≤n.

[0008] Furthermore, in the memory array, during the read operation, the word line (WL) addresses of all devices to be read are set to a high level; each read voltage is input from the bit line (BL) and applied to the resistive switching device of the unit where the WL address is set to a high level, forming a current, and forming a total current output on the source line (SL). According to Ohm's law and Kirchhoff's law, the expression of the current in the jth column in SL is as follows:

[0009]

[0010] Where p is the number of resistive switching devices simultaneously enabled in the jth column, 1≤p≤m, and is 1 in the single device mode. i is the read voltage of the i-th row input, I j The jth column of the memory array is at T 0 Current value at temperature, is the current value of the jth column of the memory array at temperature T. Combining the above equations, we can get and I j The purpose of temperature correction is to accurately obtain the rated operating temperature T at any temperature T. 0 The current I j , so the correction formula is as follows:

[0011]

[0012] The significance of this correction formula is that, due to G M , β, T 0 is a constant, so no matter what temperature it works at, it can be controlled by the current state State I when the rated operating temperature is reversed j , thereby effectively suppressing the influence of temperature. The present invention names it as correction formula 1.0.

[0013] In most cases, the read voltage is a constant value, V, and the correction equation 1.0 can be simplified to:

[0014]

[0015] The correction formula 1.0 can also be written in the form of compensation. with I j When compensating for the difference, the formula is as follows:

[0016]

[0017] Furthermore, the temperature characteristics of the resistive switching device can also be extended nonlinearly, and the correction formula obtained by extension is as follows:

[0018]

[0019] Among them, g (k) (G M ) is a high-order nonlinear term, which can also be extracted from the characteristic curve of the resistance switching device conductivity and temperature. Since the correction formula is complicated to calculate, it is considered to replace the high-order term with a semi-empirical quantity, and finally simplify and merge the correction formula as follows:

[0020]

[0021] Among them, ε is an empirical constant, which is different from β and G M , this value is not directly extracted from the characteristic curve, but needs to be manually tested and calibrated, and different resistive devices may have differences. This correction formula containing nonlinearity obtains a more accurate temperature correction effect than correction formula 1.0 at the cost of additional manual overhead, and the present invention names it correction formula 2.0.

[0022] Furthermore, adapted to the proposed correction formula, the present invention proposes a multi-mode universal, low-cost control strategy to operate the memory array. The strategy adopts a parallel processing method, effectively reduces the additional overhead caused by obtaining the current state and formula calculation, and is easy to realize on-chip integration of the correction scheme.

[0023] Specifically, the present invention proposes a method for implementing the above temperature correction scheme on a resistive memory chip, comprising:

[0024] 1) The input signal is generated by the DAC module;

[0025] 2) One or more resistive switching devices in the memory array are selected by a decoder;

[0026] 3) Reading the column current by the readout module;

[0027] 4) Based on the above correction formula, correct the result of the readout module;

[0028] 5) Output the corrected result to the target register.

[0029] In order to reduce time cost and ensure the real-time performance of temperature to improve the accuracy of correction, a parallel step is introduced between the generation of input signal and the implementation of correction to calculate the sum of input quantities and multiply them by the factor G. M β or (G M -ε)β, and obtain the intermediate quantity required for the correction formula calculation in advance or At the same time, the current temperature T is read in parallel through the temperature sensing module.

[0030] Beneficial effects of the present invention: The present invention mathematically models the temperature characteristics of the resistive switching device, derives the relationship between the column current and the actual current of the memory array, and then obtains the corresponding temperature correction formula, which is applicable to both the single device gating mode and the multi-device gating mode, and can effectively improve the reliability of memory reading under high temperature conditions. And by introducing a parallel structure, the additional time overhead brought by the implementation of the correction scheme is saved. This is of great value in high-density storage and storage-computing-in-one applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 The temperature characteristic curves of each resistance state of the resistive switching device used in the embodiment of the present invention are shown in FIG.

[0032] Figure 2 Schematic diagram of parameter extraction based on temperature characteristic curve in the embodiment.

[0033] Figure 3 Schematic diagram of a memory array composed of m×n resistive switching devices in an embodiment of the present invention.

[0034] Figure 4 Control flow diagram for applying a temperature correction scheme to memory array operations.

[0035] Figure 5 Schematic diagram of the correction effect of the single device gating mode in the embodiment.

[0036] Figure 6 It is a schematic diagram of the correction effect of the multi-device gating mode at different temperatures in the embodiment.

[0037] Figure 7 Schematic diagram of the correction effects of a temperature correction scheme based on correction formula 1.0, a temperature correction scheme based on correction formula 2.0, and no correction scheme in the multi-device enabling mode in the embodiment, wherein: (a) shows the distribution diagram of the current errors of the three at the operating temperature, and (b) shows the relationship between the read currents of the three and the actual currents. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical scheme and advantages of the present invention clearer, the multi-mode temperature correction scheme of the present invention is clearly and completely described by embodiments in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] Figure 1 The temperature characteristic curves of each resistance state of the resistive switching device used in this embodiment. A single resistive switching device uses 4-bit multi-value storage. Specifically, within the conductivity range of 5μS to 245μS, a resistance state is set at intervals of 16μS, for a total of 16 resistance states. Then, for each resistance state, 10 devices are programmed to the resistance state, and the temperature is set from 25℃ to 145℃, with 20℃ as a step, and the conductivity of this batch of devices is read at each temperature. The summary is as follows Figure 1 The temperature characteristic curves of each resistance state shown in the figure show that the conductivity of the resistive switching device will seriously deviate from the value at normal temperature when the temperature rises. Specifically, in the low resistance state region, that is, Figure 1 In the lower part of the range, the conductivity increases with increasing temperature; in the high resistance region, i.e. Figure 1 In the upper part of the device, the conductivity decreases as the temperature increases. Due to the change in conductivity, the current read when the device is selected will also change, which will affect the reliability of the read result.

[0040] Figure 2 The following is a schematic diagram of parameter extraction based on the temperature characteristic curve. The horizontal axis is the current conductance, and the vertical axis is the gradient of conductance with respect to temperature, which can be obtained from the temperature characteristic curve. The parameters required for the implementation of this correction formula are β, G M , can be extracted from the figure: For the original data, the linear regression analysis is performed, and the gradient of the straight line is β, and the intercept is G M .

[0041] ε is an empirical constant that can be obtained through additional calibration tests. The method used in this embodiment is: randomly select a memory cell in the memory array and program the resistive switching device in the cell to an arbitrary conductance. First, at the rated operating temperature T 0 Read the current at the rated operating temperature, then read the current again at high temperature T, try different ε values ​​and perform correction according to correction formula 2.0, and obtain the ε value that makes the corrected current closest to the current read at the rated operating temperature; repeat the above steps and obtain the statistical distribution of all ε values, and let their mean be the empirical constant ε used to correct formula 2.0. In this embodiment, the value is about -13.5μS after actual measurement.

[0042] Figure 3This is a schematic diagram of a resistive memory array. The resistive device of each unit adopts a more general 1T1R structure. There are three buses in total, namely the bit line (BL), source line (SL) and word line (WL). In order to support single-device and multi-device gating at the same time, it is set to a structure where WL is parallel to SL and BL is perpendicular to WL. In all applications, the decoders of WL and SL are reused with each other, that is, the same address is used. In the single-device mode, BL and WL are each selected by a decoder with one address, that is, a voltage signal is input on a bus, and the current flows through the resistive device and is output at the SL end, which is subsequently processed by the readout circuit. In the multi-device mode, BL and WL can select multiple row addresses, that is, a voltage signal is input on multiple buses. For each SL, according to Kirchhoff's law, its current is the sum of the currents of all resistive devices connected to it. In the storage-computing application, the signal on BL is the input vector (I), and the weight matrix (W) is stored in the memory array. Through the multi-device mode operation, the current on SL is the result of matrix-vector multiplication (O=I×W), which greatly accelerates the operation efficiency. However, since the resistive switching device storing the weight is sensitive to temperature, Figure 3 As an example, the conductivity at temperature T is Significant deviation from the rated operating temperature T 0 This results in inaccurate output results, which seriously affects the reliability of the memory.

[0043] according to Figure 4 The flow chart shown in the figure shows that the temperature correction scheme of the present invention is used to implement the operation on the resistive memory chip, and the main steps are as follows:

[0044] (1) The DAC module generates an input signal;

[0045] (2) One or more resistive switching devices in the memory array are selected by a decoder;

[0046] (3) The column current is read by a readout module such as ADC / SA;

[0047] (4) Correcting the result of the readout module based on the correction formula;

[0048] (5) Output the corrected result to the target register.

[0049] In order to reduce the additional cost of the correction scheme, other steps are introduced in parallel based on the above steps: First, after the input signal is generated and between the implementation of the correction, the sum of the input quantities is calculated (this operation is omitted in the single device mode) and multiplied by the factor G M β or (G M -ε)β, this operation can obtain the intermediate quantity required for the correction formula calculation in advance or The first is to reduce the time cost; the second is to read the temperature generated by the temperature sensing module in parallel. This operation not only reduces the additional time cost of communicating with the module, but also ensures the real-time nature of the temperature to improve the accuracy of the correction.

[0050] Figure 5 This is a schematic diagram of the correction effect of using correction formula 2.0 in single device gating mode. The left half is a heat map of the reading accuracy with respect to conductivity and temperature when no correction is implemented, and the right half is a heat map after correction. The color indicates the level of reading accuracy, blue represents a higher accuracy, and red represents a lower accuracy. Result explanation. After the correction is implemented, the area of ​​the red part in the figure is greatly reduced, proving the effectiveness of the correction scheme in single device gating mode.

[0051] Figure 6 The following is a schematic diagram of the correction effect for different temperatures in the multi-device selection mode using correction formula 2.0. The implementation plan is to randomly program the memory array with 4 bits. In each operation, 64 rows are selected at the same time, so the column current is the sum of the currents flowing through the 64 resistive devices. The current error in the figure is defined as the difference between the column current at the current temperature and at the rated operating temperature. Before correction, the error increases significantly with increasing temperature, but after correction, the error will not only be significantly reduced, but also significantly reduced by the temperature. After analysis, the correction scheme can ultimately achieve an error reduction of 5 to 25 times.

[0052] Figure 7 The figure below is a schematic diagram of the correction effect of the correction scheme based on correction formula 1.0, the correction scheme based on correction formula 2.0, and the correction scheme without correction in the multi-device gating mode. The temperature is selected as 105℃, and the left figure shows the distribution of the current errors of the three at this temperature, while the right figure more directly shows the relationship between the readout current and the real current of the three.

Claims

1. A multi-mode temperature correction method for resistive memory, for a memory array composed of m×n resistive devices, based on correction formula 1.0 or correction formula 2.0, the current read at any temperature T Correction is performed to obtain the corresponding current I at the rated operating temperature T0 j ; in, V i is the read voltage input in the i-th row, p is the number of resistive switching devices simultaneously selected in the j-th column, I j is the current value of the jth column of the memory array at the rated operating temperature T0, is the current value of the jth column of the memory array at any temperature T; G M , β are constants; ε is an empirical constant; 1≤i≤m, 1≤p≤m, 1≤j≤n, m, n, i, j, p are all positive integers.

2. The multi-mode temperature correction method according to claim 1, characterized in that: When the read voltage is a constant value, the following formula 1.1 is used for temperature correction: Where V is a constant read voltage.

3. The multi-mode temperature correction method according to claim 1, characterized in that: The compensation amount is calculated according to formula 1.2, and then the read current value is compensated to achieve temperature correction; in, To read the current value The amount of compensation to be performed.

4. The multi-mode temperature correction method according to any one of claims 1, characterized in that: Extracting parameter G from the temperature characteristic curve of the resistive switching device M , β, the abscissa of the temperature characteristic curve is conductance, and the ordinate is the gradient of conductance with respect to temperature. A linear regression analysis is performed on the original data, and the gradient of the obtained straight line is β, and the intercept is G M .

5. The multi-mode temperature correction method according to claim 1, characterized in that: The empirical constant ε is obtained by the following method: a memory cell is randomly selected in the memory array, and the resistive switching device in the cell is programmed to an arbitrary conductance. The current is first read at the rated operating temperature T0, and then the current is read again at the high temperature T. Different ε values ​​are tried and corrected according to the correction formula 2.0 to obtain the ε value that makes the corrected current closest to the current read at the rated operating temperature; the above steps are repeated to obtain the statistical distribution of all ε values, and their mean is used as the empirical constant ε used to correct the formula 2.

0.

6. A method for implementing the multi-mode temperature correction method according to any one of claims 1 to 5 on a resistive memory chip, comprising the following steps: 1) The input signal is generated by the DAC module; 2) One or more resistive switching devices in the memory array are selected by a decoder; 3) Reading the column current by the readout module; 4) According to the multi-mode temperature correction method according to any one of claims 1 to 5, the result of the readout module is corrected; 5) Output the corrected result to the target register.

7. The implementation method according to claim 6, characterized in that: A parallel step is introduced between generating the input signal and applying the correction, calculating the sum of the input quantities and multiplying them by the factor G M β or (G M -ε)β, and obtain the intermediate quantity required for the correction formula calculation in advance or At the same time, the current temperature T is read in parallel through the temperature sensing module.

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