Storage device and operating method thereof

Abstract

A storage device includes an array of latch cells and a plurality of inter-cell transfer switches. And two adjacent latch units in each pair are coupled together through an inter-unit transmission switch. Each latch unit includes a first inverter and a first transfer switch connected in series between a first bit node and a second bit node, and a second inverter and a second transfer switch connected in series between the second bit node and the first bit node. The first inverter has an input configured to receive a voltage from a first bit node directly or through a first transfer switch. A second inverter has an input configured to receive a voltage from a second bit node directly or through a second transfer switch. The embodiment of the invention also discloses a method for operating the storage device.

Description

Technical Field

[0001] Embodiments of the present application relate to a storage device and an operating method thereof. Background Art

[0002] The recent trend of integrated circuit (IC) miniaturization has resulted in smaller devices that consume less power but provide more functionality at higher speeds. The miniaturization process has also led to tighter design and manufacturing specifications as well as reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for integrated circuits while ensuring that the design and manufacturing specifications for the standard cell layout are met. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a storage device is provided, comprising: an array of latch units, wherein each latch unit comprises: a first inverter and a first transmission switch, connected in series between a first bit node and a second bit node, the first inverter having an input terminal configured to receive a voltage from the first bit node directly or through the first transmission switch, and a second inverter and a second transmission switch, connected in series between the second bit node and the first bit node, the second inverter having an input terminal configured to receive a voltage from the second bit node directly or through the second transmission switch; and a plurality of inter-unit transmission switches, wherein each pair of two adjacent latch units are coupled together via the inter-unit transmission switch.

[0004] According to another aspect of an embodiment of the present application, a method for operating a storage device is provided, comprising: during the duration of a first time period, setting each latch unit in an array of latch units to a forward connection mode, while each inter-unit transmission switch in a plurality of inter-unit transmission switches is in a connection state, wherein each latch unit has a first bit node and a second bit node, wherein each pair of two adjacent latch units are coupled together by an inter-unit transmission switch, and the inter-unit transmission switch connects the second bit node of a first latch unit in two adjacent latch units to the first bit node of a second latch unit in two adjacent latch units; after the first time period, setting each latch unit in the array of latch units to a latch mode, and setting each inter-unit transmission switch to a disconnect state; in a second time period, setting each latch unit in the array of latch units to a backward connection mode, while each inter-unit transmission switch is in a connection state; and after the second time period, setting each latch unit in the array of latch units to a latch mode, and setting each inter-unit transmission switch to a disconnect state.

[0005] According to another aspect of an embodiment of the present application, a storage device is provided, comprising: an array of at least four latch units, wherein each latch unit comprises: a first inverter and a first transmission switch, connected in series between a first bit node and a second bit node, the first inverter having an input terminal configured to receive a voltage from the first bit node directly or through the first transmission switch, and a second inverter and a second transmission switch, connected in series between the second bit node and the first bit node, the second inverter having an input terminal configured to receive a voltage from the second bit node directly or through the second transmission switch; and at least three multiple inter-unit transmission switches, wherein each inter-unit transmission switch that engages two adjacent latch units is configured to couple the second bit node of the first latch unit in the two adjacent latch units with the first bit node of the second latch unit in the two adjacent latch units. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a circuit diagram of a storage device having a latch unit array according to some embodiments.

[0008] Figure 2A-2D is a circuit diagram of a latch unit implemented with various configurations according to some embodiments.

[0009] Figure 3A-3C are three circuit diagrams of a storage device operating in one of three operating modes according to some embodiments.

[0010] Figure 4 is a circuit diagram of a storage device having a latch unit array according to some embodiments.

[0011] Figure 5A-Figure 5B is a circuit diagram of a storage device whose state changes after a long pulse operation of a forward shift according to some embodiments.

[0012] Figure 6A-6B , Figure 7A-7B , Figure 8A-8B and Figure 9A-9B is a circuit diagram of a storage device whose state changes after a short pulse operation of a backward shift according to some embodiments.

[0013] Fig.10 is a schematic diagram of a process of repeatedly applying a short pulse operation to a storage device according to some embodiments.

[0014] Fig.11is a timing diagram of a process of applying various short pulse operations of backward shifting and long pulse operations of forward shifting to a storage device according to some embodiments.

[0015] Figure 12A-12B , Figure 13A-13B , Figure 14A-14B and Figure 15A-15B is a circuit diagram of a storage device according to some embodiments, the state of which changes after a short pulse operation of a forward shift.

[0016] Fig.16 is a table of various encoding schemes for encoding the state of a storage device having a latch unit according to some embodiments.

[0017] Fig.17 is a table of various encoding schemes for encoding the state of a storage device having a latch unit according to some embodiments.

[0018] Fig.18 is a circuit diagram of a storage device having a latch unit array according to some embodiments.

[0019] Figure 19A-Figure 19C is a circuit diagram of an example implementation of a latch unit for a storage device.

[0020] Fig. 20 is a schematic diagram of a row of storage cells according to some embodiments.

[0021] Fig.21A is a schematic diagram of a row of three storage cells, each storage cell having a storage device, according to some embodiments.

[0022] Fig. 21B is a table that maps combinations of states of three storage cells to coded numbers written with decimal values ​​according to some embodiments.

[0023] Fig. 22 is a schematic diagram of multiple rows of storage cells and an example row controller for a first row according to some embodiments.

[0024] Figure 23A-23B is a table of matrices to be added together according to some embodiments.

[0025] Fig.24 is a flow chart of a method of operating a storage device according to some embodiments.

[0026] Fig.25 is a flow chart of a method of operating a storage device according to some embodiments. DETAILED DESCRIPTION

[0027] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0028] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0029] In some embodiments, the storage device includes an array of latch units and a plurality of inter-unit transmission gates. Each pair of two adjacent latch units is coupled together by an inter-unit transmission gate. Each latch unit includes a first inverter and a first transmission gate connected in series between a first bit node and a second bit node, the first inverter having an input terminal configured to receive a voltage from the first bit node directly or through the first transmission gate, and a second inverter and a second transmission gate connected in series between the second bit node and the first bit node, the second inverter having an output terminal configured to receive a voltage from the second bit node directly or through the second transmission gate. Arithmetic operations are implemented by treating the storage device as a finite state machine. The state change of the storage device is controlled based on the timing of various pulses. Concurrent arithmetic operations in multiple rows of storage devices increase the calculation speed compared to row-by-row arithmetic operations.

[0030] Figure 1 is a circuit diagram of a storage device having a latch unit array according to some embodiments. Figure 1In the embodiment, the storage device 100 includes latch units 110-140, a PMOS transistor 102, an NMOS transistor 108, and inter-unit transmission switches 112, 123, and 134. The latch unit is coupled in series between the drain of the PMOS transistor 102 and the drain of the NMOS transistor 108, and the sources of the PMOS transistor 102 and the NMOS transistor 108 are connected to the upper supply voltage VDD and the lower supply voltage VSS, respectively. The latch unit 110 and the latch unit 120 are connected together as a pair of two adjacent latch units through the inter-unit transmission switch 112. The latch unit 120 and the latch unit 130 are connected together as a pair of two adjacent latch units through the inter-unit transmission switch 123. The latch unit 130 and the latch unit 140 are connected together as a pair of two adjacent latch units through the inter-unit transmission switch 134.

[0031] Each latch unit 110-140 includes a first inverter INV1 and a first transmission switch S1 connected in series between a first bit node BN1 and a second bit node BN2. Each latch unit 110-140 also includes a second inverter INV2 and a second transmission switch S2 connected in series between a second bit node BN2 and a first bit node BN1. The inter-unit transmission switch 112 connects the second bit node BN2 of the latch unit 110 with the first bit node BN1 of the latch unit 120. The inter-unit transmission switch 123 connects the second bit node BN2 of the latch unit 120 with the first bit node BN1 of the latch unit 130. The inter-unit transmission switch 134 connects the second bit node BN2 of the latch unit 130 with the first bit node BN1 of the latch unit 140.

[0032] exist Figure 1 In each latch unit, the input end of the first inverter INV1 is directly connected to the first bit node BN1, and the input end of the second inverter INV2 is directly connected to the second bit node BN2. In some alternative embodiments, the input end of the first inverter INV1 is electrically coupled to the first bit node BN1 through the first transmission switch S1, and the first transmission switch S1 is directly connected to the first bit node BN1. In some alternative embodiments, the input end of the second inverter INV2 is electrically coupled to the second bit node BN2 through the second transmission switch S2, and the second transmission switch S2 is directly connected to the second bit node BN2.

[0033] exist Figure 1In the embodiment, the storage device includes various transmission switches, such as inter-unit transmission switches 112, 123 and 134, a first transmission switch S1 and a second transmission switch S2. Each transmission switch can be operated in a connected state (i.e., a closed state) or a disconnected state (i.e., an open state). The two terminals of the inter-unit transmission switch operated in the connected state are conductively connected together (when the switch is closed), but the two terminals of the inter-unit transmission switch operated in the disconnected state are electrically isolated from each other (when the switch is open).

[0034] Figure 2A-2D is a circuit diagram of a latch unit implemented in various configurations according to some embodiments. Figure 2A-2D In the example circuit of , each transmission switch is implemented as a transmission gate formed by a PMOS transistor and an NMOS transistor connected in parallel between two terminals of the transmission switch. Other implementations of the transmission switch are within the intended scope of the present disclosure. Figure 2A-2C In the example circuit of , each inverter (e.g., the first inverter INV1 and the second inverter INV2) is implemented by a PMOS transistor and an NMOS transistor. In each inverter, the gates of the transistors are connected together as the input of the inverter, the drains of the transistors are connected together as the output of the inverter, and the channels of the transistors are connected in series between the upper supply voltage VDD and the lower supply voltage VSS. Other embodiments of the inverter are within the intended scope of the present disclosure.

[0035] exist Figure 2A In the embodiment, the input terminal of the first inverter INV1 is directly connected to the first bit node BN1, and the output terminal of the first inverter INV1 is electrically coupled to the second bit node BN2 through the first transmission switch S1. The input terminal of the second inverter INV2 is directly connected to the second bit node BN2, and the output terminal of the second inverter INV2 is electrically coupled to the first bit node BN1 through the second transmission switch S2.

[0036] exist Figure 2B In the embodiment, the input end of the first inverter INV1 is electrically coupled to the first bit node BN1 through the first transmission switch S1, and the output end of the first inverter INV1 is directly connected to the second bit node BN2. The input end of the second inverter INV2 is electrically coupled to the second bit node BN2 through the second transmission switch S2, and the output end of the second inverter INV2 is directly connected to the first bit node BN1.

[0037] exist Figure 2C In the embodiment, the input end of the first inverter INV1 is directly connected to the first bit node BN1, and the output end of the first inverter INV1 is electrically coupled to the second bit node BN2 through the first transmission switch S1. The input end of the second inverter INV2 is electrically coupled to the second bit node BN2 through the second transmission switch S2, and the output end of the second inverter INV2 is directly connected to the first bit node BN1.

[0038] exist Figure 2D In the embodiment, the input end of the first inverter INV1 is electrically coupled to the first bit node BN1 through the first transmission switch S1, and the output end of the first inverter INV1 is directly connected to the second bit node BN2. The input end of the second inverter INV2 is directly connected to the second bit node BN2, and the output end of the second inverter INV2 is electrically coupled to the first bit node BN1 through the second transmission switch S2.

[0039] exist Figure 1 and Figure 2A-2D In the embodiment, each latch unit can operate in three operation modes: forward connection mode, backward connection mode and latch mode. A storage device having latch units coupled in series can operate in three operation modes: forward shift mode, backward shift mode and storage mode. Figure 3A-3C According to some embodiments Figure 1 Three circuit diagrams of the storage device 100 operating in one of three operating modes. Figure 3A-3C Each latch unit in the storage device 100 operates in a forward connection mode, a backward connection mode and a latch mode accordingly.

[0040] A storage device having a plurality of latch units generally includes a first latch unit, a last latch unit, and remaining latch units coupled in series between the first latch unit and the last latch unit. Figure 1 In the example storage device of FIG. 1 , the first latch unit is latch unit 110, and the last latch unit is latch unit 140. Latch unit 120 and latch unit 130 are coupled in series between latch unit 110 and latch unit 140 as the remaining latch units.

[0041] exist Figure 3A In the operation of setting the latch unit to the forward connection mode, the first transmission switch S1 in the latch unit 110-140 is set to the connection state, and the second transmission switch S2 in the latch unit 110-140 is set to the disconnection state.

[0042] also, Figure 3AThe storage device 100 in the embodiment operates in the forward shift mode. In the operation of setting the storage device to the forward shift mode, in addition to setting each latch unit (e.g., 110-140) to the forward connection mode and setting each inter-unit transmission switch (e.g., 112, 123, and 134) to the connection state, the first bit node BN1 of the first latch unit (e.g., 110) is maintained at a voltage at a fixed logic level, and the second bit node BN2 of the last latch unit (e.g., 140) is maintained in a floating state. Figure 3A In the example implementation of , in response to a logic low (LOW) voltage applied to the gate of the PMOS transistor 102, the first bit node BN1 of the latch unit 110 (as the first latch unit) is conductively connected to the upper supply voltage VDD, and the PMOS transistor 102 is set to a conductive state. In addition, in response to a logic low voltage applied to the gate of the NMOS transistor 108, the second bit node BN2 of the latch unit 140 (as the last latch unit) remains floating, and the NMOS transistor 108 is set to a non-conductive state.

[0043] exist Figure 3B In the operation of setting the latch units 110-140 to the backward connection mode, each latch unit 110-140 operates in the backward connection mode, and each inter-unit transmission switch 112, 123 and 134 is set to the connection state. In the operation of setting the latch units 110-140 to the backward connection mode, the first transmission switch S1 in the latch units 110-140 is set to the disconnected state, and the second transmission switch S2 of the latch units 110-140 is set to the connected state.

[0044] also, Figure 3B The storage device 100 in FIG. 1 is operated in the backward shift mode. In the operation of setting the storage device to the backward shift mode, in addition to setting each latch unit (e.g., 110-140) to the backward connection mode and setting each inter-unit transmission switch (e.g., 112, 123, and 134) to the connection state, the first bit node BN1 of the first latch unit (e.g., 110) remains in a floating state, and the second bit node BN2 of the last latch unit (e.g., 140) remains in a fixed logic level voltage. Figure 3B In the example implementation of , in response to a logic high (HIGH) voltage applied to the gate of the PMOS transistor 102, the first bit node BN1 of the latch unit 110 (as the first latch unit) remains floating, and the PMOS transistor 102 is set to a non-conductive state. In addition, in response to a logic high voltage applied to the gate of the NMOS transistor 108, the second bit node BN2 of the latch unit 140 (as the last latch unit) is conductively connected to the lower supply voltage VSS, and the NMOS transistor 108 is set to a conductive state.

[0045] exist Figure 3C In the operation of setting the latch units 110-140 to the latch mode, the first transmission switches S1 in the latch units 110-140 are set to the connection state, and the second transmission switches S2 in the latch units 110-140 are set to the connection state.

[0046] also, Figure 3C The storage device 100 in the embodiment operates in the storage mode. In the operation of setting the storage device to the storage mode, in addition to setting each latch unit (e.g., 110-140) to the latch mode and setting each inter-unit transmission switch (e.g., 112, 123, and 134) to the disconnected state, the first bit node BN1 of the first latch unit (e.g., 110) remains in a floating state, and the second bit node BN2 of the last latch unit (e.g., 140) remains in a floating state. Figure 3A In the example implementation of , in response to the logic high voltage applied to the gate of the PMOS transistor 102, the first bit node BN1 of the latch unit 110 (as the first latch unit) remains floating, and the PMOS transistor 102 is set to a non-conductive state. In addition, in response to the logic low voltage applied to the gate of the NMOS transistor 108, the second bit node BN2 of the latch unit 140 (as the last latch unit) remains floating, and the NMOS transistor 108 is set to a non-conductive state.

[0047] Figure 1 The storage device 100 can be used as a finite state machine for storing digital information. When the storage device operates in a storage mode, the state of the finite state machine is identified by the state of each latch unit in the storage device. In each latch unit, the state of the latch unit is identified by the voltage level of the first bit node BN1 or the voltage level of the second bit node BN2. Figure 1 In the embodiment, the state of the storage device 100 (as a finite state machine) is identified by the state of each latch unit 110-140. Figure 4 As shown, the state b0 of the latch unit 110 is identified by the voltage level at the first bit node BN1 of the latch unit 100, the state b1 of the latch module 120 is identified by the voltage level at the second bit node BN2 of the latch module 110, the state b2 of the latch module 130 is identified by the voltage level in the second bit node BN2 of the latch component 130, and the state b3 of the latch component 140 is identified by the voltage level at the first bit node BN1 of the latch component 140.

[0048] The voltage level of each bit node (e.g., BN1 or BN2) is at a high voltage or a low voltage. Each of the voltage HIGH and the voltage LOW is interpreted as one of two binary logic voltage levels. The voltage range of the voltage HIGH and the voltage range of the voltage LOW generally depend on the specific implementation of the inverter used in the latch unit. For example, Figure 2A-2D The latch unit implemented as shown, the voltage HIGH is VDD-Δ H To VDD range, voltage LOW is between VSS to VSS + Δ L In the range of VDD-Δ H Greater than VSS+Δ L .

[0049] exist Figure 4 , the state of the storage device 100 can be identified by the combination "b0b1b2b3", where each bit value b0, b1, b2 and b3 is corresponding to the state of one of the latch units 110, 120, 130 and 140. In one encoding scheme, a voltage HIGH is associated with a binary "1" and a voltage LOW is associated with a binary "0". Figure 4 The five states of the storage device are "1100", "1101", "1111", "1011" and "0011".

[0050] When the storage device 100 is in the storage mode, the state of the storage device 100 is maintained. However, during the time period when the storage device is in the forward shift mode or the backward shift mode, a change in the state of the storage device 100 occurs. In some embodiments, by a long pulse operation of the forward shift, the state of the storage device 100 is set to state "1100". In addition, by a short pulse operation of the backward shift, one of the following situations occurs: state "1100" changes to state "1101", or state "1101" changes to state "1111", state "1111" changes to "1011", or "1011" changes to state "0011".

[0051] Figure 5A-Figure 5B is a circuit diagram of a storage device whose state changes after a long pulse operation of a forward shift according to some embodiments. During the long pulse operation, as Figure 5AAs shown, the storage device is set to the forward shift mode. In response to the first bit node BN1 of the latch unit 110 being maintained at a logic high level (i.e., b0 = "1"), the first bit node BN1 of the latch unit 120 is set to a logic low level, and the second bit node BN2 of the latch module 120 becomes a logic high level (i.e., b1 = "1"). In response to the second bit node BN2 of the latch unit 120 being maintained at a logic high level, the first bit node BN1 of the latch unit 130 is set to a logic low level (i.e., b2 = "0"), while the first bit node BN1 of the latch unit 140 is set to a logic low level (i.e., b3 = "0". Therefore, the state of the storage device 100 changes to the state "1100". The duration of the long pulse operation is designed to be long enough to ensure that the first bit node BN1 of the latch unit 140 becomes a logic low, because any voltage change at the first bit node BN1 of the first latch unit (i.e., 110) has enough time to propagate to the first bit node BN1 of the last latch unit (i.e., 140). In some embodiments, the backward shifting short pulse operation is immediately followed by the forward shifting long pulse operation without first setting the storage device to a storage mode before the short pulse operation begins. In some embodiments, at the end of the long pulse operation, as shown in FIG. Figure 5B As shown, the storage device is set to the storage mode, and the state "1100" of the storage device is maintained. In some embodiments, after the storage device is set to the storage mode, a short pulse operation of backward shifting is applied to the storage device.

[0052] Figure 6A-6B , Figure 7A-7B , Figure 8A-8B and Figure 9A-9B is a circuit diagram of a storage device according to some embodiments, the state of which changes after a short pulse operation of a backward shift.

[0053] exist Figure 6A-6B In the example, before the backward shifted short pulse operation is applied to the storage device, the storage device is in state "1100". During the short pulse operation, Fig. 6A As shown, the storage device is set to the backward shift mode, and the voltage of the second bit node BN2 of the latch unit 140 is maintained at a logic low. The duration of the short pulse operation is designed to be short enough to ensure that the second bit node BN2 of the latch unit 130 is maintained at a logic low (i.e., b2 = "0"). That is, due to the insufficient time of the short pulse operation, the voltage change at the second bit node BN2 of the latch unit 140 will not propagate to the second bit node BN2 of the latch unit 130.

[0054] At the end of short pulse operation, as Figure 6BAs shown, the storage device is set to storage mode. After the inter-unit transmission switch 134 is set to the disconnected state, the second inverter INV2 in the latch unit 140 flips the first bit node BN1 of the latch unit 40 to a logic high (i.e., b3 = "1"). In some embodiments, in the process of flipping the first bit node BN1 of the latch unit 140 from a logic low to a logic high, the voltage of the second bit node BN2 of the latch unit 140 is maintained at a logic low by the capacitor at the input end of the second inverter INV2. After the first bit node BN1 of the latch unit 140 is flipped, the first switch S1 is closed and the storage device is stabilized in the state "1101". In some embodiments, before the first switch S1 is closed, the voltage of the second bit node BN2 of the latch unit 140 is maintained at a logic low level by the NMOS transistor 108, and after the storage device is stabilized in the state "1101", the NMOS transistor 108 becomes a non-conducting state. In some alternative embodiments, the NMOS transistor 108 becomes a non-conducting state without waiting for the first switch S1 to be closed.

[0055] exist Figure 7A-7B In the example, before the short pulse operation of the backward shift is applied to the storage device, the storage device is in the state "1101". During the short pulse operation, Fig. 7A As shown, the storage device is set to the backward shift mode, and due to the logic high voltage at the first bit node BN1 of the latch unit 140, the voltage of the second bit node BN2 of the latch unit 130 is flipped to a logic high (i.e., b2 = "1"). The duration of the short pulse operation is designed to be short enough to ensure that the second bit node BN2 of the latch unit 120 remains at a logic high level (i.e., b1 = "1"). In other words, due to the insufficient time of the short pulse operation, the voltage change at the second bit node BN2 of the latch unit 130 will not propagate to the second bit node BN2 of the latch unit 120.

[0056] At the end of short pulse operation, as Figure 7B As shown, the storage device is set to storage mode. After the inter-unit transmission switch 123 is set to the disconnected state, since the voltage of the second bit node BN2 of the latch unit 130 is maintained at a logic high by the capacitor at the input end of the second inverter INV2, the first bit node BN1 of the latch unit 230 is flipped to a logic low by the second inverter INV2 in the latch unit. Then, the first switch S1 in each latch unit is closed, and the storage device is stabilized in the state "1111". In some embodiments, before the first switch S1 in each latch unit is closed, the NMOS transistor 108 becomes a non-conducting state. In some embodiments, the NMOS transistor 108 becomes a non-conducting state without waiting for the first switch S1 in each latch unit to be closed.

[0057] exist Figure 8A-8BIn the example, before the short pulse operation of the backward shift is applied to the storage device, the storage device is in the state "1111". During the short pulse operation, Fig. 8A As shown, the storage device is set to the backward shift mode, and due to the logic low at the first bit node BN1 of the latch unit 130, the voltage of the second bit node BN2 of the latch unit 120 is flipped to a logic low (i.e., b1 = "0"). The duration of the short pulse operation is designed to be short enough to ensure that the second bit node BN2 of the latch unit 110 remains at a logic low (correspondingly b0 = "1" at the first bit node BN1 of the latch unit 100). In other words, due to the insufficient time of the short pulse operation, the voltage change at the second bit node BN2 of the latch unit 120 will not propagate to the second bit node BN2 of the latch unit 110.

[0058] At the end of short pulse operation, as Figure 8B As shown, the storage device is set to storage mode. After the inter-unit transmission switch 112 is set to the disconnected state, since the voltage of the second bit node BN2 of the latch unit 120 is maintained at a logic low by the capacitor at the input end of the second inverter INV2, the first bit node BN1 of the latch unit is flipped to a logic high by the second inverter INV2 in the latch unit. Then, the first switch S1 in each latch unit is closed, and the storage device is stabilized in the state "1011".

[0059] exist Figure 9A-9B In the example, before the backward shift short pulse operation is applied to the storage device, the storage device is in the state "1011". During the short pulse operation, Fig. 9A As shown, the storage device is set to the backward shift mode, and due to the logic high at the first bit node BN1 of the latch unit 120, the voltage of the second bit node BN2 of the latch unit 110 is flipped to a logic high. Fig. 9A In the present embodiment, the first bit node BN1 of the latch unit 110 is still at logic high.

[0060] During or at the end of the short pulse operation, the second inverter INV2 in the latch unit 120 flips the first bit node BN1 of the latch unit 120 to a logic low because the voltage at the second bit node BN2 of the latch unit 100 is maintained at a logic high by the capacitor at the input terminal of the second inverter INV2. Fig. 9B As shown, the storage device is set to storage mode. The first switch S1 in each latch unit is closed, and the storage device is stable in the state "0011".

[0061] Fig.10is a schematic diagram of a process of repeatedly applying a short pulse operation to a storage device according to some embodiments. By a long pulse operation shifted forward, the storage device is initially set to state "1100", and reference is made to Figure 5A-Figure 5B An example of long pulse operation is described. Then, the storage device sequentially performs four short pulse backward shift operations. After the first short pulse operation of the backward shift, the state "1100" of the storage device changes to the state "1101", and the reference Figure 6A-6B An example of the first short pulse is described. After the second short pulse operation of the backward shift, the state "1101" of the storage device changes to the state "1111", and the reference Figure 7A-7B An example of the second short pulse operation is described. After the third short pulse operation of the backward shift, the state "1111" of the storage device changes to the state "1011", and the reference Figure 8A-8B An example of the third short pulse operation is described. After the fourth short pulse operation of the backward shift, the state of the storage device "1011" changes to the state "0011", and refer to Figure 9A-9B An example of the fourth short-time pulse operation is described.

[0062] Fig.11 FIG. 1 is a timing diagram of a process of applying various short pulse operations of backward shifting and long pulse operations of forward shifting to a storage device according to some embodiments. Fig.11 In the example of , the storage device is in the state of "0011" before time t0. Fig.11 As shown in the timing diagram of , in response to applying a long pulse operation of a forward shift to the storage device, at time t0, the state of the storage device becomes "1100". At time t1, in response to applying a first short pulse operation of a backward shift to the storage device, the state of the storage device becomes "1101". At time t2, in response to applying a second short pulse operation of a backward shift to the storage device, the state of the storage device becomes "1111". At time t3, in response to applying a third short pulse operation of a backward shift to the storage device, the state of the storage device becomes "1011". At time t4, in response to applying a fourth short pulse operation of a backward shift to the storage device, the state of the storage device becomes "0011". Fig.10 The schematic diagram of FIG. 1 depicts the effect of each of the four short pulse operations between time t0 and time t4 on the storage device.

[0063] In addition to the long pulse operation of the forward shift and the short pulse operation of the backward shift, the short pulse width operation of the forward shift is also implemented for the storage device with the latch unit. The short pulse operation of the forward shift and the short pulse operation of the backward shift are operations opposite to each other. For example, when the short pulse operation of the backward shift changes the storage device from state "1100" to state "1101", the short pulse operation of the forward shift changes the storage device from state "1101" to state "1100". When the short pulse operation of the backward shift changes the storage device from state "1101" to state "1111", the short pulse operation of the forward shift changes the storage device from state "1111" to state "1101". When the short pulse operation of the backward shift changes the storage device from state "1111" to state "1011", the short pulse operation of the forward shift changes the storage device from state "1011" to state "1111". When the short pulse operation of the backward shift changes the storage device from the state "1011" to the state "0011", the short pulse operation of the forward shift changes the storage device from the state "0011" to the state "1011".

[0064] Figure 12A-12B , Figure 13A-13B , Figure 14A-14B and Figure 15A-15B is a circuit diagram of a storage device according to some embodiments, the state of which changes after a short pulse operation of a forward shift.

[0065] exist Figure 12A-12B In the example, before a short pulse operation for shifting forward is applied to the storage device, the storage device is in the state of "0011". During the short pulse operation, Fig. 12A As shown, the storage device is set to the forward shift mode, and the voltage of the first bit node BN1 of the latch unit 110 is maintained at a logic high. The duration of the short pulse operation is designed to be short enough to ensure that the first bit node BN1 of the latch unit 120 is maintained at a logic high. That is, due to the insufficient time of the short pulse operation, the voltage change at the second bit node BN2 of the latch unit 110 will not propagate to the second bit node BN2 of the latch unit 120. At the end of the short pulse operation, as shown in FIG. Fig. 12B As shown, the storage device is set to the storage mode. After the inter-unit transmission switch is set to the open state and the second switch S2 in each latch unit is closed, the storage device is stable in the state "1011".

[0066] exist Figure 13A-13B In the example, before a short pulse operation of shifting forward is applied to the storage device, the storage device is in the state of "1011". During the short pulse operation, Fig.13AAs shown, the storage device is set to the forward shift mode. When the inter-cell transmission switch 112 is set to the connection state, the voltage of the first bit node BN1 of the latch unit 120 becomes logic low. The duration of the short pulse operation is designed to be short enough to ensure that the first bit node BN1 of the latch unit 130 remains at logic low. At the end of the short pulse operation, as shown in FIG. Fig. 13B As shown, the storage device is set to the storage mode. After the inter-unit transmission switch is set to the open state and the second switch S2 in each latch unit is closed, the storage device is stable in the state "1111".

[0067] exist Figure 14A-14B In the example, before a short pulse operation of shifting forward is applied to the storage device, the storage device is in the state of "1111". During the short pulse operation, Fig.14A As shown, the storage device is set to the forward shift mode. When the inter-unit transmission switch 123 is set to the connection state, the voltage of the first bit node BN1 of the latch unit 130 becomes logic high. The duration of the short pulse operation is designed to be short enough to ensure that the first bit node BN1 of the latch unit 140 remains at logic high. At the end of the short pulse operation, as shown in FIG. Fig. 14B As shown, the storage device is set to the storage mode. After the inter-unit transmission switch is set to the open state and the second switch S2 in each latch unit is closed, the storage device is stable in the state "1101".

[0068] exist Figure 15A-15B In the example, before a short pulse operation of shifting forward is applied to the storage device, the storage device is in the state of "1111". During the short pulse operation, Fig.15A As shown, the storage device is set to the forward shift mode. When the inter-unit transmission switch 134 is set to the connection state, the voltage of the first bit node BN1 of the latch unit 140 becomes a logic low. When the gate of the NMOS transistor 108 is kept at a logic low, the second bit node BN2 of the latch unit 140 remains floating. At the end of the short pulse operation, as shown in FIG. Fig. 14B As shown, the storage device is set to the storage mode. After the inter-unit transmission switch is set to the open state and the second switch S2 in each latch unit is closed, the storage device is stable in the state "1100".

[0069] Fig.16 is a table of various encoding schemes for encoding the state of a storage device having a latch unit according to some embodiments. Column 1630 of the table lists the encoding schemes based on Figure 4 The five states encoded using the thermometer coding scheme in column 1630 are states 1100, 1101, 1111, 1011, and 0011, each of which is in Fig.10It is schematically shown in FIG.

[0070] exist Fig.16 In the example of FIG. 1 , using the standard coding scheme, the codes 00, 01, 10, 11, and 100 in column 1610 represent states 1100, 1101, 1111, 1011, and 0011 in the thermometer-like coding scheme column 1630, respectively. Using the thermometer coding scheme, the codes 0000, 0001, 0011, 0111, and 1111 in column 1620 represent states 1100, 1101, 1111, 1011, and 0011 in the thermometer-like coding scheme column 1630, respectively.

[0071] Using the code-1 coding scheme, the codes 0, 1, 2, 3, and 4 in column 1640 represent the states 1100, 1101, 1111, 1011, and 0011 in column 1630, similar to the thermometer coding scheme. The short pulse operation of the backward shift performs an arithmetic operation of adding 1 (i.e., +1), which changes the code from 0 to 1, from 1 to 2, from 2 to 3, and from 3 to 4. The short pulse operation of the forward shift performs an arithmetic operation of subtracting 1 (i.e., -1), which changes the code from 1 to 0, from 2 to 1, from 3 to 2, and from 4 to 3. The long pulse operation of the forward shift performs an arithmetic operation of -4, which changes the code from 4 to 0.

[0072] Using the code-2 coding scheme, the codes 0, 4, 8, 12, and 16 in column 1650 represent the states 1100, 1101, 1111, 1011, and 0011 in column 1630, similar to the thermometer coding scheme. The short pulse operation of the backward shift performs an arithmetic operation of adding four (i.e., +4), which changes the code from 0 to 4, from 4 to 8, from 8 to 12, and from 12 to 16. The short pulse operation of the forward shift performs an arithmetic operation of subtracting four (i.e., -4), which changes the code from 4 to 0, from 8 to 4, from 12 to 8, and from 16 to 8. The long pulse operation of the forward shift performs an arithmetic operation of -16, which changes the code from 16 to 0.

[0073] Using the code-3 coding scheme, the codes 1, 2, 4, 8, and 16 in column 1660 represent states 1100, 1101, 1111, 1011, and 0011 in column 1630, similar to the thermometer coding scheme. The short pulse operation of the backward shift performs an arithmetic operation of multiplying by 2, which changes the code from 1 to 2, from 2 to 4, from 4 to 8, and from 8 to 16. The short pulse operation of the forward shift performs an arithmetic operation of dividing by 2, which changes the code from 2 to 1, from 4 to 2, from 8 to 4, and from 16 to 8. The long pulse operation of the forward shift performs an arithmetic operation of dividing by 16, which changes the code from 16 to 1.

[0074] exist Fig.16In the coding scheme, each of the coding-1 coding scheme and the coding-2 coding scheme is based on an arithmetic sequence of the form A, A+b, A+2b, A+3b, and A+4b. In the coding-1 coding scheme, the first term A=0 and the common difference b=1. In the coding-2 coding scheme, the first term A=0 and the common difference b=4. The coding-3 coding scheme is based on a geometric sequence of the form A, A*b, A*b 2 , A*b 3 and A*b 4 In the Code-3 coding scheme, the first term A=1 and the common ratio b=2.

[0075] Fig.16 The encoding scheme in is based on a storage device having four latch units that form a finite state machine of five states. As an example, a storage device implemented with four latch units connected to an inter-unit transmission switch is provided. In other embodiments, a storage device having an array of N latch units connected to an inter-unit transmission switch forms a finite state machine of N+1 states, where N is a positive integer. In some encoding schemes, the N+1 state is represented by N+1 codes based on an arithmetic sequence of N+1 elements, the arithmetic sequence being in the form of A, A+1*b, A+2*b, A+3*b, ..., and A+N*b. In some encoding schemes, the N+1 states are represented by N+1 codes based on a geometric sequence, in the form of A, A*b, A*b2, A*b3, ..., and A*b N As a specific example, for a storage device having an array of eight latch units (ie, N=8), Fig.17 The table in lists the encoding schemes based on arithmetic sequences and geometric sequences. The N+1 states (N=8) represented by the thermometer-like encoding scheme are also listed in the first row of the table.

[0076] exist Figure 4 In a specific embodiment, the state of the storage device 100 is represented by the combination "b0b1b2b3", where the bit values ​​b0, b1, b2, and b3 correspond to the voltage level at the first bit node BN1 of the latch unit 110, the voltage level at the second bit node BN2 of the latch unit 120, the voltage level at the second bit node BN2 of the latch unit 130, and the voltage level at the first bit node BN1 of the latch unit 140, respectively. In some alternative embodiments, such as Fig.18 As shown, the state of the storage device 100 is represented by the combination "b0b1b2b3", where the bit values ​​b0, b1, b2, and b3 are the voltage level at the first bit node BN1 of the latch unit 110, the voltage level at the first bit node BN1 of the latch unit 120, the voltage level at the first bit node BN1 of the latch unit 130, and the voltage level at the first bit node BN1 of the latch unit 140, respectively. Fig.18In the state representation, the five states of the storage device are "1010", "1011", "1001", "1101" and "0101".

[0077] In such Figure 2A-2C In the specific implementation shown, each inverter (ie, the first inverter INV1 and the second inverter INV2) is implemented by a PMOS transistor and an NMOS transistor. Other implementations of the inverter in the latch unit of the storage device are within the intended scope of the present disclosure. Figure 19A-Figure 19C Three example implementations of latch units that can be used in the storage device of the present disclosure are shown in FIG.

[0078] exist Fig.19A In , each of the first inverter INV1 and the second inverter INV2 is implemented by 2n+1 single-stage inverters connected in series. Figure 2A-2C In the example of , each inverter is implemented by a PMOS transistor and an NMOS transistor, which provides an example of a single-stage inverter. By changing the number of single-stage inverters used to form the first inverter INV1, the delay time of the first inverter INV2 is adjusted. By changing the number of single-stage inverters used to form the second inverter INV2, the delay time of the second inverter INV2 is adjusted.

[0079] exist Fig.19B The first inverter INV1 is configured to have a gate bias voltage V bias-P The biased PMOS transistor receives a first supply voltage VDD and is configured to bias the transistor by having a gate bias voltage V bias-N The biased NMOS transistor receives the second supply voltage VSS. The second inverter INV2 is similarly configured to receive the first supply current VDD and the second supply voltage VSS. By adjusting the gate voltage V bias-P and / or V bias-N , the delay time of the first inverter INV1 and / or the second inverter INV2 can be adjusted.

[0080] exist Fig.19C In , the first inverter INV1 and the second inverter INV2 are both implemented by D flip-flops. Figure 19A-Figure 19C , an inter-unit transmission switch S3 (which is connected to the second bit node BN2) and a latch unit 1910A, 1910B or 1910C are shown.

[0081] In some embodiments, Fig. 20 As shown, multiple storage devices are linked together to form a row of storage cells. Fig. 20In some embodiments, the row of storage cells includes cell 0, cell 1, ..., and cell m. Each storage cell includes a storage device. The output of cell 0 is connected to the input of cell 1, the output of cell 1 is connected to the input of cell 2, ..., the output of cell m-1 is connected to the input of cell m. Figure 1 The storage device 100 is used to implement Fig. 20 In the example of the storage cells (e.g., cell 0, cell 1, ..., cell m), the second bit node BN2 of the last latch unit (i.e., 140) is implemented as the input of the storage cell, and the first bit node BN1 of the first latch unit (i.e., 110) is implemented to generate an output bit signal for the output end of the storage cell.

[0082] Fig.21A is a schematic diagram of a row of three storage cells, each storage cell having a storage device, according to some embodiments. Fig.21A In the storage unit, each storage device is implemented by four latch units, which is consistent with Figure 1 The example implementation is similar. The storage device of unit 0 is implemented to encode the first digit q0 of the quaternary number and the corresponding carry bit of the first digit; in the storage device, each of the five states 1100, 1101, 1111, 1011 and 0011 represents one of the five numbers 0, 1, 2, 3 and 4 respectively. The storage device of unit 1 is implemented to encode the second digit q1 of the quaternary number and the corresponding carry of the second digit; in the storage device, each of the five states 1100, 1101, 1111, 1011 and 0011 represents one of the five numbers 0*4, 1*4, 2*4, 3*4 and 4*4 respectively. The storage device of unit 2 is implemented to encode the third digit q2 of the quaternary number and the corresponding carry of the third digit; in the storage device, each of the five states 1100, 1101, 1111, 1011 and 0011 represents one of the five numbers 0*4 2 , 1*4 2 , 2*4 2 , 3*4 2 and 4*4 2 one of the.

[0083] Unit 0 is implemented to detect an overflow indicator "0" in the bit value b0 in the state b0b1b2b3. The overflow indicator "0" in the bit value b0 occurs when the state is changed to 0011. In response to the occurrence of the overflow indicator "0", unit 0 sends a carry bit signal to unit 1, and unit 0 is reset to state 1100 by a long pulse operation of shifting forward. In response to receiving the carry bit signal from unit 0, a short pulse operation of shifting backward is performed on the storage device of unit 1.

[0084] Similarly, unit 1 is implemented to detect an overflow indicator "0" in the bit value b0 in the state b0b1b2b3. The overflow indicator "0" in the bit value b0 occurs when the state is changed to 0011. In response to the occurrence of the overflow indicator "0", unit 1 sends a carry bit signal to unit 2, and unit 1 is reset to state 1100 by a long pulse operation of shifting forward. In response to receiving the carry bit signal from unit 1, a short pulse operation of shifting backward is performed on the storage device of unit 2.

[0085] Similarly, unit 2 is implemented to detect an overflow indicator "0" in the bit value b0 in state b0b1b2b3. The overflow indicator "0" in the bit value b0 occurs when the state changes to 0011. In response to the occurrence of the overflow indicator "0", unit 2 is reset to state 1100 by a long pulse operation of shifting forward, and unit 2 optionally sends a carry bit signal to another circuit.

[0086] exist Fig.21A In the example, the rows of three storage cells are configured to represent the code number q0+q1*4+q2*4 2 . Fig. 21B It is a table that maps the combination of states of three storage cells (i.e., cell 0, cell 1, and cell 2) to coded numbers written with decimal values.

[0087] In showing Fig.21A In the operation example of a row of three storage units, when a decimal value of 3 is represented using a row of three storage units, the states of cell 2, cell 1, and cell 0 are 1100, 1100, and 1011, respectively. In response to adding the decimal value 1 to the decimal value 3, a short pulse operation of shifting backward is performed on the storage device of cell 0, which changes the state of cell 0 from 1011 to 0011. Due to the overflow indicator "0" in state 0011, cell 0 sends a carry bit signal to cell 1, and cell 0 is reset to state 1100 by a long pulse operation of shifting forward. In response to receiving the carry bit signal from cell 0, a short pulse operation of shifting backward is performed on the storage device of cell 1, and the state of cell 1 is changed from 1100 to 1101. The state of cell 2 remains at 1100. At the end of the operation, after adding the decimal value 1 to the decimal value 3, the combination of the states of the three cells (i.e., cell 0, cell 1, and cell 2) is 1100 1101 1100, which corresponds to a decimal value of 4.

[0088] In some embodiments, the storage cell matrix is ​​formed by multiple rows of storage cells, each row being controlled by a corresponding row controller. Fig. 222 is a schematic diagram of multiple rows of storage cells and an example row controller 2210 for row 0 according to some embodiments. The multiple rows of storage cells are arranged in row 0, row 1, row 2, ..., and row 256. Each row of storage cells includes multiple storage cells (e.g., cell 0, cell 1, ..., etc.). Each storage cell includes a storage device (e.g., Figure 1 The storage device 100 in FIG. 1 has a plurality of latch units connected in series. That is, each storage unit includes a storage device having a first latch unit, a last latch unit, and the remaining latch units coupled in series between the first latch unit and the last latch unit. Fig. 22 In the embodiment, each of the bit latch circuits 2221 and 2222 is associated with one of the storage cells (i.e., cell 0 or cell 1), and each of the bit latch circuits 2221 and 2222 is coupled to a first bit node (e.g., Figure 1 Each of the bit latch circuits 2221 and 2222 is configured to capture the voltage at the first bit node of the first latch unit in the storage device of the corresponding storage unit (i.e., unit 0 or unit 1). In the exemplary row controller 2210, various pulses are generated by the pulse generator 2255 for controlling the short pulse operation of the backward shift, the long pulse operation of the forward shift, and the short pulse width operation of the forward shift.

[0089] In some embodiments, whether a single storage unit is subjected to a short pulse operation or a long pulse operation is individually controlled by a row controller, so that a short pulse operation and / or a long pulse operation is selectively performed on each storage unit. For example, in some embodiments, using a quaternary number system q0+q1*4+q2*4 2 The coded storage number is stored in Fig.21A To add the number with decimal value 1 to the stored number, a short pulse operation of shifting backward is performed on the storage device of unit 0. To subtract the number with decimal value 1 from the stored number, a short pulse operation of shifting forward is performed on the storage device of unit 0. To add the number with decimal value 4 to the stored number, a short pulse operation of shifting backward is performed on the storage device of unit 1. To add the number with decimal value 16 to the stored number, a short pulse operation of shifting backward is performed on the storage device of unit 2.

[0090] In some embodiments, based on Fig. 22 The system shown has a storage cell matrix formed by multiple rows of storage cells, which speeds up the addition of two matrices by performing multiple row additions simultaneously. Since each storage cell in a row is individually controlled to receive one of a short pulse and a long pulse operation, different decimal values ​​can be added to different elements in the matrix row. In one example, Figure 23A-23B As shown, the first matrix 2310 is stored in Fig. 22 In order to store Figure 23A-23B The second matrix 2320A or 2320B is added to the first matrix 2310, and the short pulse operation of the backward shift is selectively applied to Fig. 22 The second matrix 2320A includes sub-matrices ((+1, +4, +1), (+4, +16, +4), (+1, +4, +1)). The second matrix 2320B includes sub-matrices ((AW / 4, AW / 2, AW / 4), (AW / 2, AW, AW / 2), (AW / 4, AW / 2, AW / 4)). Each element in the sub-matrix of the second matrix 2320A or 2320B is simultaneously added to the corresponding element in the first matrix 2310.

[0091] Fig.24 is a flow chart of a method of operating a storage device according to some embodiments. Fig.24 The order in which the operations of method 2400 are described is for illustration only; the operations of method 2400 may be performed in the same order as described in Fig.24 It should be understood that the Fig.24 Additional operations may be performed before, during, and / or after the method 2400 shown in FIG. 2400 , and some other processes may only be briefly described herein. The method 2400 includes an operation 2410 and an operation 2420 .

[0092] In operation 2410, a forward-shifted long pulse operation is performed on the storage device. Operation 2410 includes operation 2412 and operation 2414. In operation 2412, each latch unit in the latch unit array is set to a forward connection mode for the duration of the long pulse. Operation 2412 also includes stabilizing the voltage at the second bit node of the last latch unit at the end of the long pulse to a level determined by the first voltage applied to the first bit node of the first latch unit. During the long pulse, the second bit node of the last latch unit is set to floating. Figure 5A In the example shown, each latch unit 110-140 is set to the forward connection mode, and the second bit node BN2 of the latch unit 140 is set to float by keeping the gate voltage of the NMOS transistor 108 at a logic low. Figure 5A , the voltage at the second bit node BN2 of the latch unit 140 is determined by the voltage applied to the first bit node BN1 of the latch unit 110. In one example, the upper supply voltage VDD is applied to the first bit node BN1 of the latch unit 110 through the PMOS transistor 102. After operation 2412, the process proceeds to operation 2414.

[0093] In operation 2414, each latch unit in the array of latch units is set to a latch mode, and each inter-unit transfer switch is set to an open state. Figure 5B In the example embodiment of FIG. 5 , each latch unit 110 - 140 is set to a latch mode, and each inter-unit transmission switch 112 , 123 , and 134 is in an off state.

[0094] In operation 2420, a short pulse operation of backward shifting is performed on the storage device. Operation 2420 includes operation 2422 and operation 2424. In operation 2422, each latch unit in the latch unit array is set to a backward connection mode for the duration of the short pulse. Fig. 6A , Fig. 7A , Fig. 8A and Fig. 9A In the example shown, each latch unit 110 - 140 is set to a backward connection mode. After operation 2422 , the process proceeds to operation 2424 .

[0095] In operation 2424, each latch unit in the array of latch units is set to a latch mode, and each inter-unit transfer switch is set to an open state. Figure 6B , Figure 7B , Figure 8B and Fig. 9B In the example embodiment of FIG. 5 , each latch unit 110 - 140 is set to a latch mode, and each inter-unit transmission switch 112 , 123 , and 134 is in an off state.

[0096] Operation 2422 also includes stabilizing the voltage at the first bit node of the given latch unit at the end of the short pulse operation to a level determined by the initial voltage at the second bit node of the given latch unit at the start of the short pulse operation.

[0097] In one example, at the beginning of a short pulse operation, such as Fig. 6A As shown, the initial voltage at the second bit node BN2 of the latch unit 110-140 is at logic low, logic high, logic low, and logic low (at the drain of the NMOS transistor 108) respectively. At the end of the short pulse operation, as shown in FIG. Figure 6B As shown, the voltage at the first bit node BN1 of the latch units 110 - 140 is at logic high, logic low, logic high, and logic high, respectively.

[0098] In another example, at the beginning of a short pulse operation, such as Fig. 7A As shown, the initial voltage at the second bit node BN2 of the latch unit 110-140 is at logic low, logic high, logic high and logic low, respectively. Figure 7BAs shown, the voltage at the first bit node BN1 of the latch units 110 - 140 is at logic high, logic low, logic low, and logic high, respectively.

[0099] In some embodiments, operation 2424 is repeated until a change in the voltage level at the first bit node of the first latch unit is detected, and then another long pulse operation is performed on the storage device. Figure 6A-6B , Figure 7A-7B , Figure 8A-8B and Figure 9A-9B As shown, operation 2424 is repeated. In response to the voltage level at the first bit node BN1 of the latch unit 110 changing from logic high to logic low, as shown in FIG. Fig. 9B As shown, a long pulse operation of forward shifting is performed on the storage device (such as Figure 5A-Figure 5B operation shown).

[0100] Fig.25 is a flow chart of a method of operating a storage device according to some embodiments. Fig.25 The order of operations of method 2500 described in the description is for illustration only; the operations of method 2500 can be performed in the same manner as described in the description of method 2500. Fig.25 It should be understood that the Fig.25 Additional operations are performed before, during, and / or after the illustrated method 2500 , and some other processes may only be briefly described herein. The method 2500 includes operations 2510 , 2520 , 2530 , and 2540 .

[0101] In operation 2510, each latch unit in the array of latch units is set to a forward connection mode for a first time period. Figure 5A In the example shown, each latch unit 110-140 is set to the forward connection mode. Figure 3A Explain the example operation of the forward connection mode.

[0102] In operation 2520, each latch unit in the array of latch units is set to a latch mode, and each inter-unit transfer switch is set to an off state. Figure 5B In the exemplary embodiment of FIG. 1 , each latch unit 110 - 140 is set to a latch mode, and each inter-unit transmission switch 112 , 123 , and 134 is in an off state. Figure 3C An example operation explaining the backward connection mode.

[0103] In operation 2530, each latch unit in the array of latch units is set to a backward connection mode during a second time period. Fig. 6A , Fig. 7A , Fig. 8A and Fig. 9AIn the example shown, each latch unit 110-140 is set to the backward connection mode. Figure 3B An example operation explaining the backward connection mode.

[0104] In operation 2540, each latch unit in the array of latch units is set to a latch mode, and each inter-unit transfer switch is set to an off state. Figure 6B In the exemplary embodiment of FIG. 1 , each latch unit 110 - 140 is set to a latch mode, and each inter-unit transmission switch 112 , 123 , and 134 is in an off state. Figure 3C An example operation explaining the backward connection mode.

[0105] One aspect of the present invention relates to a storage device. The storage device includes a latch unit array and a plurality of inter-unit transmission switches. Each pair of two adjacent latch units is coupled together through the inter-unit transmission switch. Each latch unit includes: a first inverter and a first transmission switch, which are connected in series between a first bit node and a second bit node, the first inverter having an input terminal configured to receive a voltage from the first bit node directly or through the first transmission switch, and a second inverter and a second transmission switch, which are connected in series between a second bit node and the first bit node, and the second inverter having an input terminal configured to receive a voltage from the second bit node directly or through the second transmission switch.

[0106] In some embodiments, the inter-cell transfer switch is located between a second bit node of a first latch cell of two adjacent latch cells and a first bit node of a second latch cell of two adjacent latch cells.

[0107] In some embodiments, the first bit node of the first latch unit is electrically connected to an upper supply voltage through a PMOS transistor.

[0108] In some embodiments, the first bit node of the first latch unit is coupled to a bit latch circuit, and the bit latch circuit is configured to capture a voltage at the first bit node of the first latch unit.

[0109] In some embodiments, the second bit node of the last latch unit is electrically connected to the lower supply voltage through an NMOS transistor.

[0110] In some embodiments, each of the first transmission switch, the second transmission switch, and the inter-cell transmission switch is a transmission gate.

[0111] In some embodiments, a first inverter is coupled between the first bit node and the first transmission switch, and the first transmission switch is coupled between an output terminal of the first inverter and the second bit node.

[0112] In some embodiments, the first transmission switch is coupled between the first bit node and the input of the first inverter, and the first inverter is coupled between the first transmission switch and the second bit node.

[0113] In some embodiments, the second inverter is coupled between the second bit node and the second transmission switch, and the second transmission switch is coupled between the output terminal of the second inverter and the first bit node.

[0114] In some embodiments, the second transmission switch is coupled between the second bit node and the input of the second inverter, and the second inverter is coupled between the second transmission switch and the first bit node.

[0115] Another aspect of the present disclosure relates to a method for operating a storage device. The method includes: during the duration of a first time period, setting each latch unit in an array of latch units to a forward connection mode, while each of a plurality of inter-unit transmission switches is in a connection state, wherein each latch unit has a first bit node and a second bit node, wherein each pair of two adjacent latch units is coupled together by an inter-unit transmission switch, and the inter-unit transmission switch connects the second bit node of a first latch unit in two adjacent latch units to the first bit node of a second latch unit in two adjacent latch units; after the first time period, setting each latch unit in the array of latch units to a latch mode, and setting each inter-unit transmission switch to a disconnected state; in a second time period, setting each latch unit in the array of latch units to a backward connection mode, while each inter-unit transmission switch is in a connection state; and after the second time period, setting each latch unit in the array of latch units to a latch mode, and setting each inter-unit transmission switch to a disconnected state.

[0116] In some embodiments, each latch unit having a first bit node and a second bit node includes: a first inverter and a first transmission switch connected in series between the first bit node and the second bit node, an input terminal of the first inverter being coupled to the first bit node directly or through the first transmission switch; and a second inverter and a second transmission switch connected in series between the second bit node and the first bit node, an input terminal of the second inverter being coupled to the second bit node directly or through the second transmission switch.

[0117] In some embodiments, setting each latch unit in the array of latch units to a forward connection mode includes: setting a first transmission switch in each latch unit to a connection state; and setting a second transmission switch in each latch unit to a disconnection state.

[0118] In some embodiments, setting each latch unit in the array of latch units to a backward connection mode includes: setting a first transmission switch in each latch unit to a disconnected state; and setting a second transmission switch in each latch unit to a connected state.

[0119] In some embodiments, setting each latch unit in the array of latch units to a latch mode includes: setting a first transmission switch in each latch unit to an open state; and setting a second transmission switch in each latch unit to an open state.

[0120] Another aspect of the present disclosure relates to a storage device. The storage device includes an array of at least four latch units, wherein each latch unit may include: a first inverter and a first transmission switch, connected in series between a first bit node and a second bit node, the first inverter having an input terminal configured to receive a voltage from the first bit node directly or through the first transmission switch, and a second inverter and a second transmission switch, connected in series between the second bit node and the first bit node, the second inverter having an input terminal configured to receive a voltage from the second bit node directly or through the second transmission switch. The storage device also includes a plurality of inter-unit transmission switches of at least three, wherein each inter-unit transmission switch that engages two adjacent latch units is configured to couple the second bit node of the first latch unit in the two adjacent latch units with the first bit node of the second latch unit in the two adjacent latch units.

[0121] In some embodiments, a first inverter is coupled between the first bit node and the first transmission switch, and the first transmission switch is coupled between an output terminal of the first inverter and the second bit node.

[0122] In some embodiments, the first transmission switch is coupled between the first bit node and the input of the first inverter, and the first inverter is coupled between the first transmission switch and the second bit node.

[0123] In some embodiments, the second inverter is coupled between the second bit node and the second transmission switch, and the second transmission switch is coupled between the output terminal of the second inverter and the first bit node.

[0124] In some embodiments, the second transmission switch is coupled between the second bit node and the input of the second inverter, and the second inverter is coupled between the second transmission switch and the first bit node.

[0125] Those skilled in the art will readily appreciate that one or more of the disclosed embodiments achieve one or more of the above advantages. After reading the above description, those skilled in the art will be able to effect various changes, substitutions of equivalents, and various other embodiments broadly disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the attached claims and their equivalents.

Claims

1. A storage device, comprising: An array of latch units, wherein each latch unit comprises: a first inverter and a first transmission switch connected in series between a first bit node and a second bit node, the first inverter having an input terminal configured to receive a voltage from the first bit node directly or through the first transmission switch, and a second inverter and a second transmission switch connected in series between the second bit node and the first bit node, the second inverter having an input terminal configured to receive a voltage from the second bit node directly or through the second transmission switch; and A plurality of inter-cell transmission switches, wherein each pair of two adjacent latch cells are coupled together through the inter-cell transmission switches.

2. The storage device according to claim 1, wherein: The inter-unit transfer switch is located between the second bit node of a first latch unit of the two adjacent latch units and the first bit node of a second latch unit of the two adjacent latch units.

3. The storage device according to claim 1, wherein: The first bit node of the first latch unit is electrically connected to an upper supply voltage through a PMOS transistor.

4. The storage device according to claim 3, wherein: The first bit node of the first latch unit is coupled to a bit latch circuit configured to capture a voltage at the first bit node of the first latch unit.

5. The storage device according to claim 1, wherein The first transmission switch is coupled between the first bit node and the input terminal of the first inverter, and the first inverter is coupled between the first transmission switch and the second bit node.

6. The storage device according to claim 1, wherein: The second inverter is coupled between the second bit node and the second transmission switch, and the second transmission switch is coupled between an output terminal of the second inverter and the first bit node.

7. The storage device according to claim 1, wherein: The second transmission switch is coupled between the second bit node and the input of the second inverter, and the second inverter is coupled between the second transmission switch and the first bit node.

8. A method of operating a storage device, comprising: During the duration of a first time period, each latch unit in the array of latch units is set to a forward connection mode, while each inter-unit transfer switch of a plurality of inter-unit transfer switches is in a connection state, wherein each latch unit has a first bit node and a second bit node, wherein each pair of two adjacent latch units is coupled together by an inter-unit transfer switch, and the inter-unit transfer switch connects the second bit node of a first latch unit of the two adjacent latch units with the first bit node of a second latch unit of the two adjacent latch units; After the first time period, each latch unit in the array of latch units is set to a latch mode and each inter-unit transmission switch is set to an open state; During a second time period, each latch unit in the array of latch units is set to a backward connection mode, while each inter-unit transmission switch is in a connection state; and After the second period of time, each latch unit in the array of latch units is set to a latching mode, and each inter-unit transfer switch is set to an open state.

9. The method according to claim 8, wherein: Each latch unit having the first bit node and the second bit node comprises: a first inverter and a first transmission switch connected in series between the first bit node and the second bit node, an input terminal of the first inverter being coupled to the first bit node directly or through the first transmission switch; and A second inverter and a second transmission switch are connected in series between the second bit node and the first bit node, and an input terminal of the second inverter is coupled to the second bit node directly or through the second transmission switch.

10. A storage device comprising: An array of at least four latch units, wherein each latch unit comprises: a first inverter and a first transmission switch connected in series between a first bit node and a second bit node, the first inverter having an input terminal configured to receive a voltage from the first bit node directly or through the first transmission switch, and a second inverter and a second transmission switch connected in series between the second bit node and the first bit node, the second inverter having an input terminal configured to receive a voltage from the second bit node directly or through the second transmission switch; and A plurality of at least three inter-cell transfer switches, wherein each inter-cell transfer switch engaging two adjacent latch cells is configured to couple the second bit node of a first latch cell of the two adjacent latch cells with the first bit node of a second latch cell of the two adjacent latch cells.

Images