Storage array structure and awakening method thereof

Abstract

The invention discloses a storage array structure and an awakening method thereof, the storage array structure comprises a plurality of storage units, the plurality of storage units are arranged in multiple rows and multiple columns, and each storage unit comprises a selective switch transistor and a ferroelectric capacitor; grid electrodes of the selection switch transistors of the plurality of storage units in the same row are electrically connected with the same word line, first ends of the ferroelectric capacitors of the plurality of storage units in the same row are electrically connected with the same plate line, and drain electrodes of the selection switch transistors of the plurality of storage units in the same column are electrically connected with the same bit line; one or more board lines are electrically connected with the same control bus, and one or more board lines are electrically connected with the same power supply voltage. According to the storage array structure and the wake-up method thereof provided by the invention, the control bus controls the power supply voltage to apply the pulse wake-up signal to the plurality of storage units, so that the polarization fatigue performance of the storage units is repaired, and the reliability of a device is improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a storage array structure and a wake-up method thereof. Background Art

[0002] Ferroelectric memory stores data information by flipping the polarization of capacitors. The film thickness formed by traditional ferroelectric materials (such as organic materials PZT, SBT, etc.) is usually more than 50nm, while the film thickness formed by new ferroelectric materials (such as doped hafnium oxide) is about 5nm to 10nm. New ferroelectric materials are widely used due to their excellent CMOS process compatibility, but in actual work, due to the influence of electric field stress, temperature stress, etc., fatigue problems will occur, resulting in reduced polarization strength of ferroelectric capacitors and reduced reliability. Summary of the invention

[0003] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0004] The present invention provides a storage array structure, comprising:

[0005] A plurality of memory cells, the plurality of memory cells are arranged in a plurality of rows and columns, wherein each of the memory cells comprises a selection switch transistor and a ferroelectric capacitor;

[0006] The gates of the selection switch transistors of the plurality of storage cells in the same row are electrically connected to the same word line, the first ends of the ferroelectric capacitors of the plurality of storage cells in the same row are electrically connected to the same plate line, and the drains of the selection switch transistors of the plurality of storage cells in the same column are electrically connected to the same bit line;

[0007] One or more of the plate lines are electrically connected to the same control bus, and one or more of the plate lines are electrically connected to the same power supply voltage.

[0008] Exemplarily, each of the plate lines is electrically connected to a drain of a control transistor, the gates of one or more of the control transistors are electrically connected to the same control bus, and the sources of one or more of the control transistors are electrically connected to the same supply voltage.

[0009] Exemplarily, the control bus is used to control the on and off of the one or more control transistors.

[0010] Exemplarily, when one or more of the control transistors are turned on, the supply voltage is used to apply a pulse wake-up signal to one or more of the plate lines electrically connected to the one or more control transistors to wake up the storage cells electrically connected to the one or more plate lines.

[0011] Exemplarily, the pulse wake-up signal includes a voltage value and a pulse number, the voltage value of the pulse wake-up signal is greater than the voltage value applied to the word line or the bit line, and the pulse number of the pulse wake-up signal is greater than the pulse number applied to the word line or the bit line.

[0012] Exemplarily, a high level signal and a high level / low level alternating signal are applied to the word line and the bit line, respectively, and a low level signal is applied to the plate line.

[0013] Exemplarily, the storage unit includes:

[0014] A select switch transistor is disposed on the substrate;

[0015] A ferroelectric capacitor is located above the selection switch transistor, and a second end of the ferroelectric capacitor is electrically connected to a source of the selection switch transistor;

[0016] A plate line, located above the ferroelectric capacitor, electrically connected to the first end of the ferroelectric capacitor, and spaced apart from the ferroelectric capacitor;

[0017] The bit line is electrically connected to the drain of the switch transistor and is located above the plate line with a gap therebetween.

[0018] Exemplarily, the ferroelectric capacitor includes a columnar capacitor or a planar capacitor.

[0019] Exemplarily, the plate line extends along a first direction, and the bit line extends along a second direction, and the first direction is perpendicular to or intersects with the second direction.

[0020] The present invention also provides a method for waking up the storage array structure as described in any one of the above items, comprising:

[0021] Applying a first high level signal and a high level / low level alternating signal to the word line and the bit line respectively, and applying a low level signal to the plate line;

[0022] applying a second high level signal to the control bus to turn on the one or more control transistors;

[0023] When one or more of the control transistors are turned on, the supply voltage applies a pulse wake-up signal to one or more of the plate lines electrically connected to the one or more control transistors to wake up the storage cells electrically connected to the one or more plate lines.

[0024] According to the storage array structure and wake-up method thereof provided by the present invention, the capacitors of multiple storage cells in the same row are electrically connected to the same plate line, and one or more of the plate lines are electrically connected to the same control bus, and one or more of the plate lines are electrically connected to the same power supply voltage, so that the control bus controls the power supply voltage to apply a pulse wake-up signal to multiple storage cells, so as to repair the polarization fatigue performance of the storage cells and improve the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0026] In the attached figure:

[0027] Figure 1 is a schematic diagram of a storage array structure according to an embodiment of the present invention;

[0028] Figure 2A is a schematic structural diagram of a storage unit according to an embodiment of the present invention;

[0029] Figure 2B is a schematic structural diagram of a storage unit according to an embodiment of the present invention;

[0030] Figure 3 A circuit diagram of a storage unit in a storage array structure according to an embodiment of the present invention;

[0031] Figure 4 is a flow chart of a method for waking up a storage array structure according to an embodiment of the present invention;

[0032] Figure 5 It is a schematic diagram of applying voltage to the memory array structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0034] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0035] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0036] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0037] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] In order to fully understand the present invention, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0039] The present invention provides a storage array structure, such as Figure 1 As shown, including:

[0040] A plurality of memory cells, the plurality of memory cells are arranged in a plurality of rows and columns, wherein each of the memory cells comprises a selection switch transistor and a ferroelectric capacitor;

[0041] The gates of the selection switch transistors of the plurality of storage cells in the same row are electrically connected to the same word line, the first ends of the ferroelectric capacitors of the plurality of storage cells in the same row are electrically connected to the same plate line, and the drains of the selection switch transistors of the plurality of storage cells in the same column are electrically connected to the same bit line;

[0042] One or more of the plate lines are electrically connected to the same control bus, and one or more of the plate lines are electrically connected to the same power supply voltage.

[0043] For example, Figure 2A and 2B As shown, the storage unit includes: a selection switch transistor, which is located on a substrate; a ferroelectric capacitor, which is located above the selection switch transistor, and the second end of the ferroelectric capacitor is electrically connected to the source of the selection switch transistor; a plate line, which is located above the ferroelectric capacitor, which is electrically connected to the first end of the ferroelectric capacitor, and has a spacing with the ferroelectric capacitor; a bit line, which is electrically connected to the drain of the switch transistor, and is located above the plate line, and has a spacing with the plate line.

[0044] In one embodiment, Figure 2A and 2B As shown, the substrate can be any suitable semiconductor substrate, such as a silicon substrate, and it can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductor materials, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be ceramic substrates such as aluminum oxide, quartz or glass substrates, etc.

[0045] In one embodiment, Figure 2A and 2BAs shown, the gate of the selection switch transistor includes a gate dielectric layer (not shown) and a gate material layer from bottom to top, the gate dielectric layer includes but is not limited to a silicon oxide layer, the gate material layer includes but is not limited to a doped polysilicon layer or a metal layer; sidewalls are also formed on both sides of the gate, the sidewalls include but are not limited to a silicon oxide layer, a silicon nitride layer or an ONO structure (i.e., a stacked structure of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer); a source and a drain are formed on both sides of the gate and the sidewalls, respectively, and a metal silicide may also be formed on the upper surface of the source and the drain to reduce the contact resistance between the source and the drain and the conductive plug leading out thereof. In an embodiment of the present application, the gate of the selection switch transistor is a word line (WL).

[0046] In one embodiment, Figure 2A As shown, the ferroelectric capacitor includes a columnar capacitor. The columnar capacitor includes a columnar inner electrode, a capacitor dielectric layer and an outer electrode. The capacitor dielectric layer is located at the periphery of the columnar inner electrode; the outer electrode is located at the periphery of the capacitor dielectric layer. Wherein, the columnar inner electrode is a metal layer; the capacitor dielectric layer may include but is not limited to a zirconium-doped hafnium oxide thin film layer, wherein the molar ratio of zirconium, hafnium and oxygen in the capacitor dielectric material layer is 0.3:0.3:0.5~0.7:0.7:1.5, and the thickness of the capacitor dielectric layer can be set according to actual needs, for example, 6nm~10nm; the outer electrode is a metal layer, and the material of the outer electrode can be the same as that of the columnar inner electrode.

[0047] In one embodiment, Figure 2B As shown, the ferroelectric capacitor includes a planar capacitor. The planar capacitor includes a lower electrode, a capacitor dielectric layer and an upper electrode, wherein the lower electrode is a metal layer; the capacitor dielectric layer may include but is not limited to a zirconium-doped hafnium oxide thin film layer, wherein the molar ratio of zirconium, hafnium and oxygen in the capacitor dielectric material layer is 0.3:0.3:0.5-0.7:0.7:1.5, and the thickness of the capacitor dielectric layer can be set according to actual needs, for example, 6nm-10nm; the upper electrode is a metal layer, and the material of the upper electrode can be the same as that of the lower electrode.

[0048] In one embodiment, Figure 2A and 2B As shown, the storage unit structure also includes:

[0049] A dielectric layer (not shown) is located between the selection switch transistor and the wiring layer, and between the ferroelectric capacitor and the wiring layer, for isolating the selection switch transistor from the wiring layer, and isolating the capacitor from the wiring layer. Optionally, a dielectric layer is provided between the selection switch transistor and the ferroelectric capacitor, for isolating the selection switch transistor from the ferroelectric capacitor. Figure 2A The columnar capacitor shown is electrically connected to the drain of the selection switch transistor, and no dielectric layer is provided between the columnar capacitor and the selection switch transistor. Figure 2B In the planar capacitor shown, a dielectric layer is arranged between the planar capacitor and the selection switch transistor, and the dielectric layer includes but is not limited to a silicon oxide layer.

[0050] A conductive plug is located in the dielectric layer between the selection switch transistor and the wiring layer, and is used to electrically connect the selection switch transistor to the wiring layer; and is located in the dielectric layer between the selection switch transistor and the ferroelectric capacitor, and is used to electrically connect the ferroelectric capacitor to the wiring layer. Optionally, the conductive plug is located in the dielectric layer between the selection switch transistor and the ferroelectric capacitor, and is used to electrically connect the selection switch transistor to the ferroelectric capacitor. The material of the conductive plug includes but is not limited to tungsten or copper.

[0051] In one embodiment, Figure 2A and 2B As shown, the wiring layer includes a bit line (BL) and a plate line (PL). The plate line is electrically connected to the ferroelectric capacitor, and the plate line extends along a first direction; the bit line is electrically connected to the selection switch transistor, and the bit line extends along a second direction, and the first direction is perpendicular to or intersects the second direction (for example, the angle between the first direction and the second direction includes 80° to 90°). The wiring layer includes but is not limited to copper or aluminum.

[0052] It should be noted that Figure 2A and 2B In order to show the main structure, the dielectric layers are not shown.

[0053] In one embodiment, Figure 1 As shown, multiple memory cells are arranged in multiple rows and columns, the gates of the selection switch transistors of the multiple memory cells in the same row are electrically connected to the same word line, the ferroelectric capacitors of the multiple memory cells in the same row are electrically connected to the same plate line, and the selection switch transistors of the multiple memory cells in the same column are electrically connected to the same bit line.

[0054] The ferroelectric effect of zirconium-doped hafnium oxide uses dielectric capacitance to realize storage function with polarization, so that the amount and polarity of the capacitor storage charge changes with the change of the polarization direction and size of the capacitor; Figure 1 New ferroelectric memory array and Figure 3 As shown in the memory cell circuit diagram, a memory cell contains a ferroelectric storage capacitor C FE, a select transistor and three interconnect lines, word line WL, bit line BL, and plate line PL. In actual work, the polarization direction of the ferroelectric memory cell is changed by changing the direction of the electric field applied to the upper and lower plates (or internal and external electrodes) of the ferroelectric capacitor to generate different residual polarization charges. Since ferroelectric capacitors need to frequently perform polarization flipping in the process of storing data 0 and 1, during the device production process, defects and oxygen vacancies in the ferroelectric storage material will form a potential barrier under the influence of electric field stress and temperature stress, causing the residual polarization strength of the storage capacitor to decrease. This polarization fatigue is related to the operating voltage and temperature. Higher operating voltage and higher temperature will cause the fatigue rate to increase exponentially. However, after the new ferroelectric cell is woken up, the polarization fatigue performance of the ferroelectric memory cell can be repaired, thereby improving the reliability of the device. When the storage cell polarization flips 10 8 After the device is awakened by a higher voltage, the remanent polarization strength increases by 10%. 8 .

[0055] for Figure 2A and 2B The storage unit shown and Figure 1 In the memory array structure shown, the voltage of the plate line PL is directly loaded on the ferroelectric capacitor plate. Therefore, in the embodiment of the present invention, the purpose of waking up the memory cell is achieved by optimizing the voltage operation mode on the plate line PL.

[0056] Exemplarily, the ferroelectric capacitors of multiple memory cells in the same row in the memory array structure are electrically connected to the same plate line, and each plate line is electrically connected to the drain of a control transistor. In one embodiment, for N rows of memory cells, they are respectively electrically connected to N plate lines, and further electrically connected to N control transistors, such as Figure 1 shown.

[0057] Exemplarily, the gates of one or more control transistors are electrically connected to the same control bus. Further, the control bus is used to control the on and off of the one or more control transistors. In one embodiment, for N control transistors, they can be uniformly controlled by one control bus, or they can be controlled by multiple control buses in different areas, or even individually controlled by N control buses, which is not limited in this application. Figure 1 In the illustrated embodiment, all control transistors are uniformly controlled by the same control bus, and therefore, all plate lines are electrically connected to the same control bus.

[0058] Exemplarily, the source of one or more control transistors is electrically connected to the same power supply voltage. In one embodiment, the N control transistors may be connected to the same power supply voltage or to different power supply voltages, which is not limited in the present application. Figure 1In the illustrated embodiment, all control transistors are electrically connected to the same supply voltage and, therefore, all plate lines are electrically connected to the same supply voltage.

[0059] Exemplarily, when one or more control transistors are turned on, the supply voltage is used to apply a pulse wake-up signal to one or more plate lines electrically connected to the one or more control transistors to wake up the storage unit electrically connected to the one or more plate lines. Further, the pulse wake-up signal includes a voltage value and a number of pulses, the voltage value of the pulse wake-up signal is greater than the voltage value applied to the word line or the bit line, and the number of pulses of the pulse wake-up signal is greater than the number of pulses applied to the word line or the bit line.

[0060] In one embodiment, for Figure 1 The memory array structure shown can apply a high level signal and a high level / low level alternating signal to the word line and the bit line, respectively, and apply a low level signal to the plate line. The voltage value of the pulse wake-up signal is higher than the voltage value of the high level signal and the high level / low level alternating signal applied to the word line and the bit line, and the number of pulses of the pulse wake-up signal is greater than the number of pulses of the high level / low level alternating signal applied to the word line or the bit line.

[0061] The present invention also provides a method for storing an array structure, such as Figure 4 As shown, including:

[0062] Step S410: applying a first high level signal and a high level / low level alternating signal to the word line and the bit line respectively, and applying a low level signal to the plate line;

[0063] Step S420: applying a second high level signal to the control bus to turn on the one or more control transistors;

[0064] Step S430: When one or more of the control transistors are turned on, the supply voltage applies a pulse wake-up signal to one or more of the plate lines electrically connected to the one or more control transistors to wake up the storage units electrically connected to the one or more plate lines.

[0065] In one embodiment, when the number of cumulative flips of the memory cell reaches a certain number (e.g., 1E6), the memory array structure is awakened as a whole. In step S410, a first high level signal and a high level / low level alternating signal are applied to the word line WL and the bit line BL, respectively. Figure 5As shown, a first high level signal is applied to the word line WL, a set of 2 high level and 2 low level alternating signals is applied to the bit line BL, and a low level signal is applied to the plate line PL to put the memory cell into working state. Next, step S420 is executed to apply a second high level signal to the control bus to turn on the one or more control transistors. Figure 1 In the storage array structure shown, all control transistors are uniformly controlled by the same control bus, so when the second high level signal is applied to the control bus, all control transistors are turned on. In step S430, when one or more of the control transistors are turned on, the supply voltage applies a pulse wake-up signal to one or more of the plate lines electrically connected to the one or more control transistors to wake up the storage cells electrically connected to the one or more plate lines. Figure 1 In the memory array structure shown, all control transistors are electrically connected to the same power supply voltage. When all control transistors are turned on, a pulse wake-up signal of the power supply voltage VCC1 is applied to all plate lines PL, thereby waking up all memory cells. The voltage of the pulse wake-up signal of the power supply voltage VCC1 is greater than the voltage of the first high level signal and the high level / low level alternating signal applied to the word line WL and the bit line BL, respectively, and the number of pulses of the pulse wake-up signal of the power supply voltage VCC1 is greater than the number of pulses of the high level / low level alternating signal applied to the bit line BL.

[0066] According to the storage array structure and wake-up method provided by the present invention, the ferroelectric capacitors of multiple storage cells in the same row are electrically connected to the same plate line, and one or more of the plate lines are electrically connected to the same control bus, and one or more of the plate lines are electrically connected to the same power supply voltage, so that the control bus controls the power supply voltage to apply a pulse wake-up signal to multiple storage cells, so as to repair the polarization fatigue performance of the storage cells and improve the reliability of the device.

[0067] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A storage array structure, characterized in that: include: A plurality of memory cells, the plurality of memory cells are arranged in a plurality of rows and columns, wherein each of the memory cells comprises a selection switch transistor and a ferroelectric capacitor; The gates of the selection switch transistors of the plurality of storage cells in the same row are electrically connected to the same word line, the first ends of the ferroelectric capacitors of the plurality of storage cells in the same row are electrically connected to the same plate line, and the drains of the selection switch transistors of the plurality of storage cells in the same column are electrically connected to the same bit line; One or more of the plate lines are electrically connected to the same control bus, and one or more of the plate lines are electrically connected to the same power supply voltage.

2. The storage array structure according to claim 1, characterized in that: Each of the plate lines is electrically connected to a drain of a control transistor, the gates of one or more of the control transistors are electrically connected to the same control bus, and the sources of one or more of the control transistors are electrically connected to the same supply voltage.

3. The storage array structure according to claim 2, characterized in that: The control bus is used to control the on and off of the one or more control transistors.

4. The storage array structure according to claim 3, characterized in that: When one or more of the control transistors are turned on, the supply voltage is used to apply a pulse wake-up signal to one or more of the plate lines electrically connected to the one or more control transistors to wake up the storage units electrically connected to the one or more plate lines.

5. The storage array structure according to claim 4, characterized in that: The pulse wake-up signal includes a voltage value and a pulse number. The voltage value of the pulse wake-up signal is greater than the voltage value applied to the word line or the bit line. The pulse number of the pulse wake-up signal is greater than the pulse number applied to the word line or the bit line.

6. The storage array structure according to claim 1, characterized in that: A high level signal and a high level / low level alternating signal are applied to the word line and the bit line, respectively, and a low level signal is applied to the plate line.

7. The storage array structure according to claim 1, characterized in that: The storage unit comprises: A select switch transistor is disposed on the substrate; A ferroelectric capacitor is located above the selection switch transistor, and a second end of the ferroelectric capacitor is electrically connected to a source of the selection switch transistor; A plate line, located above the ferroelectric capacitor, electrically connected to the first end of the ferroelectric capacitor, and spaced apart from the ferroelectric capacitor; The bit line is electrically connected to the drain of the switch transistor and is located above the plate line with a gap therebetween.

8. The storage array structure according to claim 1, characterized in that: The ferroelectric capacitor includes a columnar capacitor or a planar capacitor.

9. The storage array structure according to claim 1, characterized in that: The plate line extends along a first direction, and the bit line extends along a second direction, wherein the first direction is perpendicular to or intersects with the second direction.

10. A method for waking up the storage array structure according to any one of claims 1 to 9, characterized in that: include: Applying a first high level signal and a high level / low level alternating signal to the word line and the bit line respectively, and applying a low level signal to the plate line; applying a second high level signal to the control bus to turn on the one or more control transistors; When one or more of the control transistors are turned on, the supply voltage applies a pulse wake-up signal to one or more of the plate lines electrically connected to the one or more control transistors to wake up the storage cells electrically connected to the one or more plate lines.

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