Semiconductor device

Abstract

This application provides a semiconductor device and a method for forming the same. The semiconductor device includes multiple array blocks, each array block including multiple first address lines and multiple second address lines. The first address lines extend along a first direction, and the second address lines extend along a second direction, intersecting in opposite directions. The first address lines have a first dimension in the first direction, and the second address lines have a second dimension in the second direction. The first dimension is greater than half the second dimension. In the embodiments of this application, the array block design elongates the length of the first address lines along their extension direction, increasing the area of ​​the array block. Since the number of first address lines is not increased, the number of control circuits for the first address lines does not need to be increased. This is equivalent to using fewer first address line control circuits to control a larger array block, thus freeing up more design area for other circuits and further optimizing the overall memory performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device. Background Technology

[0002] To address the extreme challenges of memory miniaturization and three-dimensional stacking, Selector Only Memory (SOM) in non-volatile memory technology has attracted widespread attention from researchers both domestically and internationally. Its storage cell consists of only one selector, combining the functions of memory and selector.

[0003] Current research on memory selection mainly focuses on three-dimensional stacked architectures based on cross-point arrays. In array blocks designed based on this research, the layout space of the circuits is limited, thus affecting the overall performance of the memory.

[0004] Therefore, how to increase the circuit design area in the array block is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a semiconductor device that can increase the circuit design area in an array block.

[0006] This application provides a semiconductor device, including: a plurality of array blocks, each array block including a plurality of first address lines and a plurality of second address lines, the first address lines extending along a first direction, the second address lines extending along a second direction, and the first address lines and the second address lines intersecting in opposite directions, the first address lines having a first size in the first direction, the second address lines having a second size in the second direction, and the first size being greater than half of the second size.

[0007] In some embodiments, each array block includes an array core region and a first via region arranged along the second direction, the area where the first address line and the second address line intersect forms the array core region, the second address line crosses the array core region and the first via region; the number of the second address lines is greater than half the number of the first address lines.

[0008] In some embodiments, the ratio of the area of ​​the array core region to the area of ​​the array block is 65.4% to 71.1%.

[0009] In some embodiments, the size of the array block along the second direction is 230 micrometers to 240 micrometers, and the size of the array block along the first direction is 170 micrometers to 190 micrometers.

[0010] In some embodiments, the array block includes two array core regions and a first via region, with the first via region located between the two array core regions along the second direction; the size of the array core region along the first direction is greater than its size along the second direction.

[0011] In some embodiments, the size of the array core region along the second direction is 80 micrometers to 90 micrometers, and the size of the array core region along the first direction is 160 micrometers to 180 micrometers.

[0012] In some embodiments, the size of the array core region along the first direction is twice the size along the second dimension direction.

[0013] In some embodiments, the system further includes: a first circuit, a second circuit, and an extension circuit, all disposed on the side of the first address line away from the second address line; the first circuit and the extension circuit are both located in the array core region, and the first circuit is electrically connected to the first address line; the second circuit is at least located in the first via region and is connected to the second address line through a conductive plug in the first via region.

[0014] In some embodiments, the system further includes: a second via region, a third address line, and a third circuit; the second via region is located on at least one side of each of the array core regions along the first direction; the third address line extends along the first direction and spans two adjacent array blocks; the third circuit is located on the side of the first address line away from the second address line, the third circuit is at least located in the second via region, and is connected to the third address line through a conductive plug in the second via region.

[0015] In some embodiments, the array blocks are arranged in an array in the first direction and the second direction, and are superimposed in a third direction, which is perpendicular to the plane of the first direction and the second direction; two array blocks superimposed along the third direction are offset from each other in the first direction and the second direction.

[0016] In the semiconductor device provided in this application, each array block includes multiple first address lines and multiple second address lines, and the first size is greater than half of the second size. Compared to the case where the first size is less than half of the second size, the array block design in this application elongates the length of the first address lines in the extension direction, thereby increasing the area of ​​the array block. Since the number of first address lines is not increased, the number of control circuits for the first address lines does not need to be increased. This is equivalent to using fewer first address line control circuits to control a larger array block, thus freeing up more design area for other circuits and further optimizing the overall performance of the memory.

[0017] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0020] Figure 1 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application;

[0021] Figure 2 This application Figure 1 A schematic diagram of the layout of an array block of a semiconductor device in the embodiment;

[0022] Figure 3 This is a top view schematic diagram of the semiconductor device provided in some other embodiments of this application;

[0023] Figure 4 This application Figure 3 A schematic diagram of the layout of an array block of a semiconductor device in the embodiment;

[0024] Figure 5 This is a schematic cross-sectional view of multiple array blocks along a second direction and a third direction provided in some embodiments of this application;

[0025] Figure 6 This is a schematic cross-sectional view of multiple array blocks along a first direction and a third direction provided in some embodiments of this application;

[0026] Figure 7 This is a schematic diagram of the address line arrangement in an array block provided in one embodiment;

[0027] Figure 8 yes Figure 7 The embodiment provides a dimension design drawing of the array block;

[0028] Figure 9 This application Figure 3 and Figure 4 The embodiment provides a dimension design diagram of the array block. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0030] Currently, memory array blocks are primarily laid out with approximately twice the number of bit lines as word lines, but the length of the bit lines is less than half the length of the word lines. This design, where the number of bit lines is approximately twice the number of word lines, makes it easier to control the voltage drop across the bit lines, but the length of the bit lines limits the area of ​​the array blocks and the design area of ​​the underlying circuitry.

[0031] Based on the above reasons, this application provides a semiconductor device comprising multiple array blocks, each array block comprising multiple first address lines and multiple second address lines, the first address lines extending along a first direction, the second address lines extending along a second direction, and the first address lines and the second address lines intersecting in opposite directions, the first address lines having a first size in the first direction, the second address lines having a second size in the second direction, and the first size being greater than half of the second size.

[0032] Compared to the case where the first size is less than half the size of the second size, the array block design in this embodiment extends the length of the first address line extension direction, increasing the area of ​​the array block. Since the number of first address lines is not increased, the number of control circuits for the first address lines does not need to be increased. This is equivalent to using fewer first address line control circuits to control a larger array block, thus freeing up more design area for other circuits and further optimizing the overall performance of the memory.

[0033] The semiconductor devices provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0034] Please see Figure 1 and Figure 2 , Figure 1 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application. Figure 2 This application Figure 1 A schematic diagram of the layout of an array block of the semiconductor device in this embodiment. It should be noted that... Figure 1 and Figure 2 The dashed box in the diagram represents the range of an array block. Figure 1 This mainly displays the arrangement of the first and second address lines in an array block. Figure 2 It mainly shows the layout of the driving circuit in an array block.

[0035] The semiconductor device 100 includes a plurality of array blocks 10, each array block 10 including a plurality of first address lines 11 and a plurality of second address lines 12. The first address lines 11 extend along a first direction Y, and the second address lines 12 extend along a second direction X. The first address lines 11 and the second address lines 12 intersect in opposite directions. The first address lines 11 have a first dimension L1 in the first direction Y, and the second address lines 12 have a second dimension L2 in the second direction X. The first dimension L1 is greater than half of the second dimension L2.

[0036] In some embodiments, the first dimension L1 may be equal to half of the second dimension L2, that is, the length of the first address line 11 is twice the length of the second address line 12.

[0037] The first address line 11 and the second address line 12 intersect in opposite directions, meaning that the first address line 11 and the second address line 12 are not on the same plane. For example... Figure 1 As shown, the first address line 11 can be located below the second address line 12, therefore the second address line 12 partially blocks the first address line 11. It is understood that the first direction Y and the second direction X also intersect at opposite angles; for example, the first direction Y can be perpendicular to or intersect the second direction X at a certain angle.

[0038] In some embodiments, one of the first address line 11 and the second address line 12 is a bit line, and the other is a word line. For example, Figure 1 The first address line 11 is a bit line, and the second address line 12 is a word line.

[0039] like Figure 2 As shown, from the layout of array blocks 10, each array block 10 may include an array core region C and a first via region V1 arranged along the second direction X. The first address line 11 is located in the array core region C, and the second address line 12 crosses the array core region C and the first via region V1. The area where the first address line 11 and the second address line 12 intersect forms the array core region C. The area ratio of the array core region C to the area of ​​the array block 10 is the array efficiency of the array block 10.

[0040] In some embodiments, the array block 10 includes two array core regions C and a first via region V1. Along the second direction X, the first via region V1 is located between the two array core regions C. In other words, the array core regions C are located on both sides of the first via region V1 along the second direction X, which reduces the overall voltage drop.

[0041] In some embodiments, the dimension of each array core region C along the first direction Y is greater than the dimension along the second dimension X, thereby providing space for the layout of the first address lines 11 and the second address lines 12. In some embodiments, the number of the second address lines 12 is greater than half the number of the first address lines 11, and the number of the second address lines 12 increases with the length of the first address lines 11, thereby increasing the area of ​​the array core region C accordingly.

[0042] The semiconductor device 100 may further include a first circuit S1, a second circuit S2, and an extension circuit D. The first circuit S1, the second circuit S2, and the extension circuit D are all located on the side of the first address line 11 away from the second address line 12. The first circuit S1 and the extension circuit D are both located in the array core region C, and the first circuit S1 is electrically connected to the first address line 11. The second circuit S2 is at least located in the first via region V1 and is connected to the second address line 12 through a conductive plug within the first via region V1.

[0043] In some embodiments, the first circuit S1 may include a word line selector, and the second circuit S2 may include a bit line selector. The extension circuit D is located on both sides of the first circuit S1 along the first direction Y, and the extension circuit D may include a decoder and a control circuit.

[0044] Please see Figure 3 and Figure 4 , Figure 3 This is a top view schematic diagram of the semiconductor device provided in some other embodiments of this application. Figure 4 This application Figure 3 A schematic diagram of the layout of an array block of the semiconductor device in this embodiment. It should be noted that... Figure 3 and Figure 4 The dashed box in the image represents the range of an array block 10. Figure 3 This mainly shows the arrangement of the first address line 11 and the second address line 12 in an array block 10. Figure 4 This mainly shows the layout of the driving circuitry in array block 10. The driving circuitry is located at the bottom layer, that is, below the first address line 11.

[0045] Figure 3 and Figure 4 Examples and Figure 1 and Figure 2 The difference in the embodiment is that the semiconductor device 100 has a two-layer stacked architecture.

[0046] The semiconductor device 100 may further include a second via region V2, a third address line 13, and a third circuit S3. The second via region V2 is located on at least one side of each of the array core regions C along the first direction Y. The third address line 13 extends along the first direction Y and spans two adjacent array blocks 10. The third circuit S3 is located on the side of the first address line 11 away from the second address line 12. The third circuit S3 is at least located in the second via region V2 and is connected to the third address line 13 through a conductive plug within the second via region V2.

[0047] In some embodiments, the second via region V2 is located on both sides of the array core region C in the first direction Y.

[0048] In some embodiments, the dimension of each array core region C along the first direction Y is greater than the dimension along the second direction X.

[0049] For example, the dimension of each array core region C along the first direction Y is twice the dimension along the second direction X. When an array block 10 includes two array core regions C, it is equivalent to the dimension of one array core region C along the first direction Y being equal to the sum of the dimensions of the two array core regions C along the second direction X.

[0050] In some embodiments, such as Figure 3 As shown, a third address line 13 extends from this array block 10 to another adjacent array block 10 along the first direction Y. Each array block 10 includes two mutually independent third address lines 13. For example, an array block 10 may contain portions of two adjacent third address lines 13 along the first direction Y, which are spaced apart at positions corresponding to the first circuit S1, with portions of the first address line 11 exposed at the spaced-out positions.

[0051] In some embodiments, the array blocks 10 are arranged in an array along the first direction Y and the second direction X, and are superimposed along a third direction, which is perpendicular to the plane of the first and second directions. Two array blocks 10 superimposed along the third direction are offset from each other.

[0052] For example, two array blocks 10 stacked along the third direction can be offset from each other by half the distance of array block 10 along the first direction Y, and can also be offset from each other by half the distance of array block 10 along the second direction X.

[0053] The semiconductor device 100 may further include a first conductive plug CT1, a second conductive plug CT2, and a third conductive plug CT3. The first conductive plug CT1 is connected between the first circuit S1 and the first address line 11. The second conductive plug CT2 is located in the first via region V1 and is connected between the second circuit S2 and the second address line 12. The third conductive plug CT3 is located in the second via region V2 and is connected between the third circuit S3 and the third address line 13.

[0054] The semiconductor device 100 may also include a memory array located in the core array region C.

[0055] In some embodiments, the storage array may include a first storage cell structure and a second storage cell structure. The first storage cell structure is located between the first address line 11 and the second address line 12, and at the intersection of the first address line 11 and the second address line 12. The second storage cell structure is located between the second address line 12 and the third address line 13, and at the intersection of the second address line 12 and the third address line 13. That is, the first storage cell structure and the second storage cell structure share a layer of second address line 12.

[0056] In other embodiments, the semiconductor device 100 further includes a fourth address line located between the second address line 12 and the third address line 13, the fourth address line extending along the second direction X and crossing the array core region C and the first via region V1.

[0057] The fourth address line can be connected one-to-one with the second address line 12, and they are set to overlap, so Figure 3 The fourth address line is not visible in the circuit. The second address line 12 is a lower-level word line, while the fourth address line can be an upper-level word line. The first conductive plug CT1 is also connected to the fourth address line, meaning that the first circuit S1 jointly drives the second address line 12 and the fourth address line.

[0058] The first storage cell structure is located between the first address line 11 and the second address line 12, and at the intersection of the first address line 11 and the second address line 12; the second storage cell structure is located between the fourth address line and the third address line 13, and at the intersection of the fourth address line and the third address line 13. That is, the first storage cell structure is controlled by the first address line 11 and the second address line 12, and the second storage cell structure is controlled by the third address line 13 and the fourth address line. In some embodiments, an array block 10 may include the first address line 11, the second address line 12, the third address line 13, and the fourth address line, as well as the first storage cell structure and the second storage cell structure, along a third direction.

[0059] Please see Figure 5 and Figure 6 , Figure 5 This is a schematic cross-sectional view of multiple array blocks along a second direction and a third direction provided in some embodiments of this application. Figure 6 This is a schematic diagram of the cross-sectional structure of multiple array blocks along a first direction and a third direction provided in some embodiments of this application. Figure 5 and Figure 6 The diagram shows a first array block B1 and a second array block B2 stacked along the third direction Z, with both array blocks B1 and B2 distributed along the first direction Y and the second direction X.

[0060] The first array block B1 includes, along the third direction Z, a first address line 11, a second address line 12, a third address line 13, and a fourth address line 14, as well as a first memory cell structure C1 and a second memory cell structure C2. The first memory cell structure C1 is located between the first address line 11 and the second address line 12, the second memory cell structure C2 is located between the third address line 13 and the fourth address line 14, and the fourth address line 14 is located between the second address line 12 and the second memory cell structure C2.

[0061] The second array block B2 includes, along a third direction, a fifth address line 15, a sixth address line 16, a seventh address line 17, and an eighth address line 18, as well as a third memory cell structure C3 and a fourth memory cell structure C4. The third memory cell structure C3 is located between the fifth address line 15 and the sixth address line 16, and the fourth memory cell structure C4 is located between the seventh address line 17 and the eighth address line 18. The eighth address line 18 is located between the sixth address line 16 and the fourth memory cell structure C4.

[0062] In some embodiments, each memory cell structure is located at the intersection between two address lines. Each memory cell structure may include a first electrode, a gating layer, a second electrode, a phase-change memory layer, and a third electrode stacked along the third direction Z. Taking the first memory cell structure C1 as an example, its first electrode is connected to the first address line 11, and its third electrode is connected to the second address line 12.

[0063] In other embodiments, each memory cell structure may include a first electrode, a gating layer, and a second electrode stacked along a third direction Z. Taking the first memory cell structure C1 as an example, its first electrode is connected to the first address line 11, and its second electrode is connected to the second address line 12. The gating layer serves both storage and switching functions.

[0064] In some embodiments, the material of the gate layer is a dual-function material (DFM). For example, the material of the gate layer may include any suitable bidirectional threshold switch (OTS) material, which may include chalcogenide alloys such as germanium (Ge), arsenic (As), and selenium (Se) and their compounds. The first electrode and the second electrode may be made of the same material or different materials. The materials of the first electrode and the second electrode include, but are not limited to, copper (Cu), aluminum (Al), gold (Au), tungsten (W), carbon (C) and their compounds, conductive doped semiconductors, etc.

[0065] In some embodiments, the second array block B2 is offset relative to the first array block B1 along the first direction Y and along the second direction X.

[0066] In some embodiments, such as Figure 5 As shown, the second array block B2 is offset relative to the first array block B1 along the second direction X by half an array block distance; as Figure 6 As shown, the second array block B2 is offset relative to the first array block B1 along the first direction Y by half an array block distance.

[0067] In some embodiments, the first array block B1 further includes a first conductive plug CT1, a second conductive plug CT2, and a third conductive plug CT3. For example... Figure 6 As shown, the first conductive plug CT1 is located on the side of the first address line 11 away from the second address line 12, and is connected to the first address line 11. Figure 5 As shown, the second conductive plug CT2 is located on the side of the second address line 12 away from the fourth address line 14, and is connected to the second address line 12. Figure 6 As shown, the third conductive plug CT3 is located on the side of the third address line 13 away from the fifth address line 15, and is connected to the third address line 13.

[0068] The second array block B2 also includes conductive plugs to connect the address lines. The connection method of the conductive plugs and address lines in the first array block B1 can be referred to, and will not be repeated here.

[0069] Please see Figure 7 , Figure 7 This is a schematic diagram illustrating the arrangement of address lines in an array block according to one embodiment. Figure 1 and Figure 3 The difference in the embodiments is that, Figure 7 In this embodiment, the dimension of the first address line 11 along the first direction Y is less than half the dimension of the second address line 12 along the second direction X, and the number of the first address lines 11 is greater than or equal to twice the number of the second address lines 12, which can reduce the voltage drop of the first address lines 11.

[0070] contrast Figure 3 (or Figure 1 )and Figure 7 It can be seen that, Figure 1 and Figure 3 In the array block 10 of the semiconductor device 100 provided in the embodiment, the length of the first address line 11 is lengthened and the number of the second address lines 12 is increased. Therefore, the area of ​​the array core region C (or memory array) is increased, and the space of the array block 10 along the first direction Y becomes larger. Correspondingly, the length of the third address line 13 is also increased, but the number remains unchanged.

[0071] Since the number of first address lines 11 (connecting to the first circuit S1) and third address lines 13 (connecting to the corresponding third circuit S3) remains unchanged, the areas of the first circuit S1 and the third circuit S3 can remain the same. Figure 4 It can be seen that the array block 10 has a third circuit S3, an expansion circuit D and a first circuit S1 arranged along the first direction Y. Since the areas of the first circuit S1 and the third circuit S3 can remain unchanged, the area of ​​the expansion circuit D can be relatively increased, which increases the design flexibility and further optimizes the overall performance of the memory.

[0072] Although the area of ​​array block 10 increases, the main increase is in the area of ​​the expansion circuit D and the array core area C. Therefore, the area ratio of the expansion circuit D in array block 10 increases, and the area ratio of the array core area C in array block 10 also increases. As a result, the utilization rate of the expansion circuit D increases, and the array efficiency improves.

[0073] In some embodiments, the semiconductor device 100 includes a plurality of array blocks 10 arranged in an array, with an isolation region between two adjacent array blocks 10, thereby reducing interference between adjacent array blocks 10. However, this isolation region occupies a portion of the area of ​​the entire semiconductor device 100.

[0074] In the semiconductor device 100 provided in this application, since the area of ​​a single array block 10 is increased, the number of array blocks 10 in the entire semiconductor device 100 is reduced, and the number and area of ​​isolation regions are also reduced, thereby further improving the array efficiency of the array blocks 10.

[0075] Please see Figure 8 and Figure 9 , Figure 8 yes Figure 7 The embodiment provides a dimension design drawing of the array block. Figure 9 This application Figure 3 and Figure 4 The embodiment provides a dimension design diagram of the array block.

[0076] like Figure 8 As shown, the size BXL1 of array block 10 along the second direction X can be 230um to 240um, the size BYL1 of array block 10 along the first direction Y can be 90um to 110um, and the size AXL1 of array core region C along the second direction X and the size ALY1 of array core region C along the first direction Y can both be 80um to 90um. Depending on the different size values, the array efficiency of array core region C is 61.8% to 67.5%.

[0077] like Figure 4 and Figure 9 As shown, the size BXL2 of the array block 10 along the second direction X can be 230um to 240um, the size BYL2 of the array block 10 along the first direction Y can be 170um to 190um, the size AXL2 of the array core region C along the second direction X is 80um to 90um, and the size ALY2 of the array core region C along the first direction Y can both be 160um to 180um. The array efficiency of the array core region C is 65.4% to 71.1%. Relative to... Figure 8 In this embodiment, the array efficiency of the array block 10 in the semiconductor device 100 provided by this application is improved by 3% to 4%, and the overall cost is reduced.

[0078] This application also provides a method for forming a semiconductor device in any of the above embodiments, and all methods for forming such semiconductor devices are within the protection scope of this application.

[0079] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0080] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0081] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0082] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A semiconductor device, characterized in that, include: Multiple array blocks, each array block including multiple first address lines and multiple second address lines, the first address lines extending along a first direction, the second address lines extending along a second direction, and the first address lines and second address lines intersecting in opposite directions, the first address lines having a first size in the first direction, the second address lines having a second size in the second direction, the first size being greater than half of the second size, the area where the first address lines and second address lines intersect forming an array core area, the ratio of the area of ​​the array core area to the area of ​​the array block being 65.4% to 71.1%.

2. The semiconductor device according to claim 1, characterized in that, Each array block includes an array core region and a first via region arranged along the second direction, and the second address line crosses the array core region and the first via region; The number of the second address lines is greater than one-half the number of the first address lines.

3. The semiconductor device according to claim 2, characterized in that, The array block has a size of 230 micrometers to 240 micrometers along the second direction, and the array block has a size of 170 micrometers to 190 micrometers along the first direction.

4. The semiconductor device according to claim 2, characterized in that, The array block includes two array core regions and a first via region. Along the second direction, the first via region is located between the two array core regions. The size of the array core region along the first direction is greater than its size along the second direction.

5. The semiconductor device according to claim 4, characterized in that, The array core region has a size of 80 micrometers to 90 micrometers along the second direction, and the array core region has a size of 160 micrometers to 180 micrometers along the first direction.

6. The semiconductor device according to claim 4, characterized in that, The size of the array core region along the first direction is twice the size along the second direction.

7. The semiconductor device according to claim 1, characterized in that, Also includes: The first circuit, the second circuit, and the expansion circuit are all located on the side of the first address line that is away from the second address line. Both the first circuit and the expansion circuit are located in the array core area, and the first circuit is electrically connected to the first address line; The second circuit is located at least in the first via area and is connected to the second address line through a conductive plug in the first via area.

8. The semiconductor device according to claim 2, characterized in that, Also includes: The second via area, the third address line, and the third circuit; The second via region is located on at least one side of each of the array core regions along the first direction; The third address line extends along the first direction and crosses two adjacent array blocks; The third circuit is located on the side of the first address line away from the second address line. The third circuit is at least located in the second via area and is connected to the third address line through a conductive plug in the second via area.

9. The semiconductor device according to claim 1, characterized in that, The array blocks are arranged in the first direction and the second direction, and are superimposed in the third direction, which is perpendicular to the plane of the first direction and the second direction. The two array blocks stacked along the third direction are offset from each other in the first direction and the second direction.

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