Durability Testing Method, Device, Electronic Equipment and Medium of RRAM Memristor

Abstract

The present application provides a method, device, electronic device and medium for durability testing of a RRAM memristor. The method includes: obtaining the current state of the RRAM device; determining the order of a continuous plurality of reset operations and a continuous plurality of set operations based on the current state of the RRAM device; the reset operation represents erasing the RRAM memristor device; the set operation represents programming the RRAM memristor device; using a gradually increasing pulse intensity to determine the resistance range of the RRAM device; the gradually increasing pulse intensity includes an initial pulse intensity capable of flipping the current state of the RRAM; according to the highest resistance state and the lowest resistance state within the resistance range of the RRAM device, selecting the fixed pulse parameters used for durability testing, and loading continuous alternating reset operations and set operations to perform durability testing on the RRAM device. In this way, it is possible to avoid premature failure of the durability test caused by over-reset or over-set problems.

Description

Technical Field

[0001] The present application relates to the technical field of device testing, and particularly to a durability testing method, device, electronic device and medium for a RRAM memristor. Background Art

[0002] The working mechanism of RRAM (Resistive Random-Access Memory, resistive random access memory, also known as a memristive device) is generally considered to be the breakage and formation of oxygen vacancy conducting filaments in the resistive material under different polar electric fields, resulting in the conversion of the device between a high resistance state and a low resistance state, representing the two storage states of '1' and '0' in binary data. Generally, the durability of a RRAM memristor is tested to determine the maximum number of programming cycles that the memory device can withstand.

[0003] However, in the related art, the durability test of the RRAM memristive device causes the durability test to fail prematurely. Summary of the Invention

[0004] The present application provides a durability testing method, system and computer-readable storage medium for a RRAM memristor.

[0005] The present application provides a durability testing method for a RRAM memristor, including:

[0006] Obtaining the current state of the RRAM device;

[0007] Based on the current state of the RRAM device, determining the sequence of a continuous plurality of reset operations and a continuous plurality of set operations; the reset operation represents erasing the RRAM memristive device; the set operation represents programming the RRAM memristive device;

[0008] Using a gradually increasing pulse intensity to determine the resistance range of the RRAM device; the gradually increasing pulse intensity includes an initial pulse intensity capable of flipping the current state of the RRAM; the resistance range of the RRAM device includes a highest resistance state and a lowest resistance state;

[0009] According to the highest resistance state and the lowest resistance state within the resistance range of the RRAM device, selecting fixed pulse parameters used for the durability test, and loading continuous alternating reset operations and set operations to perform a durability test on the RRAM device.

[0010] Further, the gradually increasing pulse intensity includes a gradually increasing set pulse intensity;

[0011] Correspondingly, the continuous plurality of set operations refer to continuously programming the RRAM memristive device using the gradually increasing set pulse intensity;

[0012] The manner of gradually increasing the set pulse intensity includes: by fixing the pulse width and fixing the stepwise increasing pulse height, or by fixing the pulse height and fixing the stepwise increasing pulse width, or by simultaneously fixing the stepwise increasing pulse width and the increasing pulse height.

[0013] Furthermore, the current state of the RRAM device includes that the resistance state of the RRAM device is the highest resistance state; with the strengthening of the gradually increasing set pulse intensity loaded each time, the resistance state of the RRAM device will gradually transition from the highest resistance state to the lowest resistance state.

[0014] Furthermore, the gradually increasing pulse intensity includes the gradually increasing reset pulse intensity;

[0015] Correspondingly, the continuous multiple reset operations refer to continuously erasing the RRAM memristor device using the gradually increasing reset pulse intensity;

[0016] The manner of gradually increasing the gradually increasing reset pulse intensity includes: by fixing the pulse width and fixing the stepwise increasing pulse height, or by fixing the pulse height and fixing the stepwise increasing pulse width, or by simultaneously fixing the stepwise increasing pulse width and the increasing pulse height.

[0017] Furthermore, the current state of the RRAM device includes that the resistance state of the RRAM device is the lowest resistance state; with the strengthening of the gradually increasing reset pulse intensity loaded each time, the resistance state of the RRAM device will gradually transition from the lowest resistance state to the highest resistance state.

[0018] Furthermore, the size of the fixed step is inversely proportional to the display fineness of the durability test.

[0019] Furthermore, using the gradually increasing pulse intensity to determine the resistance range of the RRAM device includes: according to the determined sequence of the reset operation and the set operation, starting from the initial pulse intensity, using the combination of the continuous multiple reset operations and the continuous multiple set operations to scan the resistance range window of the RRAM device, and obtaining the highest resistance state and the lowest resistance state of the RRAM device;

[0020] and / or,

[0021] Performing a durability test on the RRAM device by loading consecutive alternating reset operations and set operations includes: forming a cyclic pulse with a single set pulse and a single reset pulse, and loading the cyclic pulse multiple times to perform a durability test on the RRAM device, recording the high-resistance state and the low-resistance state of the RRAM device after each pulse until the RRAM device fails.

[0022] An embodiment of the present application provides a durability test device for an RRAM memristor, including:

[0023] An acquisition module, configured to acquire the current state of the RRAM device;

[0024] An operation sequence determination module, configured to determine the sequence of consecutive multiple reset operations and consecutive multiple set operations based on the current state of the RRAM device; the reset operation represents erasing the RRAM memristive device; the set operation represents programming the RRAM memristive device;

[0025] A fixed pulse parameter determination module, configured to determine the resistance range of the RRAM device using a gradually increasing pulse intensity; the gradually increasing pulse intensity includes an initial pulse intensity capable of flipping the current state of the RRAM; the resistance range of the RRAM device includes the highest resistance state and the lowest resistance state;

[0026] A durability test module, configured to select the fixed pulse parameters used in the durability test according to the highest resistance state and the lowest resistance state within the resistance range of the RRAM device, and load consecutive alternating reset operations and set operations to perform a durability test on the RRAM device.

[0027] The present application provides an electronic device, including one or more processors, configured to implement the method described in any one of the above.

[0028] The present application provides a computer-readable storage medium, on which a program is stored, and when the program is executed by a processor, the method described in any one of the above is implemented.

[0029] The present application provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, the method described in any one of the above is implemented.

[0030] In some embodiments, for the durability test method of the RRAM memristor of the present application, before the endurance test of the RRAM memristive device, a gradually increasing pulse intensity is used to determine the resistance state range of the RRAM device. Since the resistance state range of the RRAM device defines the highest resistance state and the lowest resistance state, and then the endurance test is continued starting from the highest resistance state and the lowest resistance state, by balancing the reset and set pulse parameters, it is possible to avoid the premature failure of the durability test caused by over-reset or over-set problems, which is beneficial to obtaining relatively stable and accurate durability test results, thereby improving the service life of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1a FIG. shows a schematic diagram of the durability failure types of the RRAM memristive device in the related art;

[0032] Figure 1b FIG. shows another schematic diagram of the durability failure types of the RRAM memristive device in the related art;

[0033] Figure 2 FIG. shows a flowchart of the durability test method of the RRAM memristor provided by the embodiments of the present application;

[0034] Figure 3 FIG. shows Figure 2 FIG. shows a schematic flowchart for determining the sequence of consecutive multiple reset operations and consecutive multiple set operations of the durability test method of the RRAM memristor;

[0035] Figure 4a FIG. shows Figure 2 FIG. shows a flowchart of consecutive multiple set operations on the RRAM memristive device in the durability test method of the RRAM memristor;

[0036] Figure 4b FIG. shows Figure 2 FIG. shows a method flowchart of consecutive multiple reset operations on the RRAM memristive device in the durability test method of the RRAM memristor;

[0037] Figure 5a FIG. shows Figure 4a FIG. shows a schematic diagram of consecutive multiple set operation pulses;

[0038] Figure 5b FIG. shows Figure 4b FIG. shows a schematic diagram of consecutive multiple reset operation pulses;

[0039] Figure 6 FIG. shows Figure 4a and Figure 4b FIG. shows a resistance state change diagram of consecutive multiple set operations and consecutive multiple reset operations on the RRAM memristive device;

[0040] Figure 7 As shown Figure 2 Schematic diagram of consecutive alternating fixed set pulses and fixed reset pulses of the endurance test method for the RRAM memristor shown

[0041] Figure 8 Schematic diagram of the structure of the endurance test device for the RRAM memristor provided by the embodiment of the present application

[0042] Figure 9 Schematic diagram of the structure of the electronic device provided by the embodiment of the present application Detailed implementation manners

[0043] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with one or more embodiments of this specification. Instead, they are merely examples of devices and methods consistent with some aspects of one or more embodiments of this specification as detailed in the appended claims.

[0044] It should be noted that: In other embodiments, the steps of the corresponding methods are not necessarily executed in the order shown and described in this specification. In some other embodiments, the steps included in the method may be more or less than those described in this specification. In addition, a single step described in this specification may be decomposed into multiple steps for description in other embodiments; and multiple steps described in this specification may also be combined into a single step for description in other embodiments.

[0045] To solve the technical problem that the endurance test of the RRAM memristive device in the related art may cause the premature failure of the endurance test, the embodiment of the present application provides an endurance test method for the RRAM memristor. By using a gradually increasing pulse intensity before the endurance test of the RRAM memristive device, the resistance state interval of the RRAM device is determined. Since the resistance state interval of the RRAM device defines the highest resistance state and the lowest resistance state, and then continue to perform the endurance test starting from the highest resistance state and the lowest resistance state, it is possible to avoid the premature failure of the endurance test caused by over-reset or over-set problems by balancing the reset and set pulse parameters, which is beneficial to obtaining relatively stable and accurate endurance test results, thereby improving the service life of the device. The detailed analysis is as follows:

[0046] Figure 1a and Figure 1b Schematic diagrams of the endurance failure types of the RRAM memristive device in the related art are shown respectively.

[0047] As shown inFigure 1a and Figure 1b As shown in Figure 1b , in the durability test of RRAM memristor devices in the related art, inappropriate cycling pulse parameters selected may affect the resistance interval window and the stability of high and low resistance states thereof, and unbalanced reset / set pulse conditions may cause premature failure of the high resistance state or low resistance state thereof, thereby resulting in an incorrect evaluation of the durability results of the memristor devices.

[0048] Due to the durability test of RRAM memristor devices in the related art, starting from a relatively high resistance state position close to the highest resistance state as the starting position for the low resistance state flip. At this time, it is called over-reset, that is, for the device, RESET (reset)>SET (set), which may cause premature failure of the low resistance state.

[0049] Due to the durability test of RRAM memristor devices in the related art, starting from a relatively low resistance state position close to the lowest resistance state as the starting position for the high resistance state flip. At this time, it is called over-set, that is, for RRAM memristor devices, SET (set)>RESET (reset), which easily causes premature failure of the high resistance state.

[0050] Therefore, the embodiments of the present application use a gradually increasing pulse intensity to determine the resistance interval of the RRAM device, and can determine the highest resistance state and the lowest resistance state in the resistance states of the RRAM device, and then continue to perform the endurance test starting from the highest resistance state and the lowest resistance state. Each window of the subsequent durability test is not easily shifted. In this way, the reset pulse parameters and the set pulse parameters can be balanced, and premature failure of the durability test caused by over-reset or over-set problems can be avoided, which is beneficial to obtaining relatively stable and accurate durability test results, thereby improving the service life of the RRAM memristor device. In this way, situations such as unstable conductive filaments caused by over-reset or over-set will not occur, thereby improving the service life of the RRAM memristor device.

[0051] Figure 2 The figure shows a schematic flow chart of a durability test method for an RRAM memristor provided by an embodiment of the present application.

[0052] As Figure 2 shown, the durability test method for the RRAM memristor may include but is not limited to the following steps 110 to 140:

[0053] Step 110, obtain the current state of the RRAM device. Wherein, the current state of the RRAM device is used to represent the current resistance state of the RRAM device. These resistance states are high and low. By judging the current state of the RRAM device and reading the initial resistance value R0 of the RRAM device.

[0054] Step 120: Determine the sequence of consecutive reset operations and consecutive set operations based on the current state of the RRAM device; a reset operation means erasing the RRAM memristor device, and a set operation means programming the RRAM memristor device. The consecutive set operations refer to performing multiple set operations with a short interval each time, which can achieve enhancement. The consecutive reset operations refer to performing multiple reset operations with a short interval each time, which can achieve inhibition.

[0055] In the above step 120, the consecutive reset operations refer to continuously using a gradually increasing reset pulse intensity, and the consecutive set operations refer to continuously using a gradually increasing set pulse intensity. The interval for applying the gradually changing pulses can be relatively short. After being stimulated by high-frequency signals, the RRAM device can obtain the highest resistance state or the lowest resistance state of the device faster.

[0056] This step 120 can determine the sequence of consecutive reset operations and consecutive set operations. If the current state is the high-resistance state of the RRAM device, then perform consecutive set operations first, and then consecutive reset operations; if the device is currently in the low-resistance state, then perform consecutive reset operations first, and then consecutive set operations. Thus, determine the resistance range of the RRAM device through the following step 130.

[0057] Step 130: Use a gradually increasing pulse intensity to determine the resistance range of the RRAM device; the gradually increasing pulse intensity includes the initial pulse intensity capable of flipping the current state of the RRAM; the resistance range of the RRAM device includes the highest resistance state and the lowest resistance state.

[0058] Since during the flipping process, the more the resistance state flips, the more difficult it is to flip, so by continuously increasing the pulse intensity, the resistance range of the RRAM device can be obtained more accurately.

[0059] Step 140: According to the highest resistance state and the lowest resistance state within the resistance range of the RRAM device, select the fixed pulse parameters used for the endurance test, and apply consecutive alternating reset operations and set operations to perform the endurance test on the RRAM device.

[0060] These fixed pulse parameters can mean that the numerical values of the pulse parameters remain unchanged. For example, the fixed pulse parameters are alternative pulse parameters, and these alternative pulse parameters are different from the gradually increasing pulse intensity. Of course, the fixed pulse parameters can also be any value in the gradually increasing pulse intensity. Since the initially determined highest resistance state and lowest resistance state are used as references, the fixed pulse parameters selected for the endurance test can reproduce this window, so these fixed pulse parameters are selected. Therefore, when the subsequent endurance test uses this fixed pulse combination, the window of each high-resistance to low-resistance change is not easily tilted or offset.

[0061] The fixed pulse parameters used for the above-mentioned durability include fixed set pulse parameters and fixed reset pulse parameters. The fixed set pulse parameters can achieve the lowest resistance state within the resistance range window obtained in the above steps of the device; the fixed reset pulse parameters can achieve the highest resistance state within the resistance range window obtained in the above steps of the device. Since the formation and breakage of the conductive filaments in the RRAM device are affected by process conditions of the resistive switching material and have a certain randomness, the operator can set the tolerance error range for the highest and lowest resistance states. The specific setting of the tolerance error range usually depends on the specific application requirements, process conditions, and required performance level of the RRAM device, and can be set between 1% and 10%. After selecting the fixed pulse parameters for the durability test, the durability test can be started.

[0062] Among them, the above step 140 can further include: forming a cycle pulse by a single set pulse and a single reset pulse, loading the cycle pulse multiple times, performing a durability test on the RRAM device, and recording the high resistance state and the low resistance state of the RRAM device after each pulse until the RRAM device fails.

[0063] Exemplarily, load continuous alternating reset operations and set operations. For example, if the set pulse parameter is A and the reset pulse operation is B, the durability test is specifically performed as A - B - A - B - A - B - A - B - …… until the RRAM device fails. One A + B is one cycle count, and the total cycle count before the RRAM device fails is used as the durability test result. Moreover, through steps 110 to 130 before starting the actual durability test in this article, the start positions of reset and set can be better determined.

[0064] During the durability test, by loading continuous alternating reset operations and set operations, etc., the resistance range of the RRAM device determined by using a gradually increasing pulse intensity can be reproduced.

[0065] In contrast, the above-mentioned durability test method for the RRAM memristor can also adopt the following method to determine the failure of the RRAM device:

[0066] Once the switching ratio of the current cycle is lower than the set minimum switching ratio threshold, it is determined as a durability failure, and the total number of cycle counts before failure is used as the durability test result; among them, the switching ratio of the current cycle is the ratio of the high resistance value after a single reset pulse to the low resistance value after a single set pulse.

[0067] Figure 3 Shown as Figure 2 Schematic diagram of the process for determining the sequence of continuous multiple reset operations and continuous multiple set operations of the durability test method of the RRAM memristor shown.

[0068] Combined Figure 2 As shown, the gradually increasing pulse intensity includes the gradually increasing set pulse intensity;

[0069] Correspondingly, the continuous multiple set operations refer to continuously programming the RRAM memristor device using the gradually increasing set pulse intensity;

[0070] The gradually increasing manner of the gradually increasing set pulse intensity includes: by fixing the pulse width and fixing the step - increasing pulse height, or by fixing the pulse height and fixing the step - increasing pulse width, or by simultaneously fixing the step - increasing pulse width and the increasing pulse height.

[0071] In some examples, the gradually changing set pulse intensity can be that the voltage is fixed, the lower electrode is grounded, and the voltage of the upper electrode increases from the starting voltage in a fixed step, generally in the range of 0.5V to 2.5V; the gradually increasing pulse intensity in this article can gradually determine the lowest resistance state, thereby improving the accuracy of determining the resistance range of the RRAM device.

[0072] As an embodiment, the current state of the RRAM device includes that the resistance state of the RRAM device is the highest resistance state; with the strengthening of the gradually increasing set pulse intensity loaded each time, the resistance state of the RRAM device will gradually transition from the highest resistance state to the lowest resistance state.

[0073] In the embodiment of the present application, subsequent endurance tests start from the highest resistance state and gradually transition to the lowest resistance state, avoiding premature failure of the endurance test caused by over - reset or over - set problems, which is beneficial to obtaining relatively stable and accurate endurance test results.

[0074] As an embodiment, the gradually increasing pulse intensity includes the gradually increasing reset pulse intensity;

[0075] Correspondingly, the continuous multiple reset operations refer to continuously erasing the RRAM memristor device using the gradually increasing reset pulse intensity;

[0076] The gradually increasing manner of the gradually increasing reset pulse intensity includes: by fixing the pulse width and fixing the step - increasing pulse height, or by fixing the pulse height and fixing the step - increasing pulse width, or by simultaneously fixing the step - increasing pulse width and the increasing pulse height.

[0077] In some examples, the above - mentioned gradually changing reset pulse intensity can be that the voltage is fixed, the upper electrode is grounded, and the voltage of the lower electrode increases from the starting voltage in a fixed step, generally in the range of 0.5V to 2.5V.

[0078] The gradually increasing pulse intensity in this text can gradually determine the highest resistance state, thereby improving the accuracy of determining the resistance range of the RRAM device.

[0079] As an example, the current state of the RRAM device includes that the resistance state of the RRAM device is the lowest resistance state; with the strengthening of the gradually increasing reset pulse intensity loaded each time, the resistance state of the RRAM device will gradually transition from the lowest resistance state to the highest resistance state.

[0080] In the embodiment of this application, subsequent endurance tests are carried out, starting from the lowest resistance state and gradually transitioning to the highest resistance state, avoiding the premature failure of the endurance test caused by over-reset or over-set problems, which is beneficial to obtaining relatively stable and accurate endurance test results.

[0081] As an example, the size of the fixed step is inversely proportional to the display fineness of the endurance test.

[0082] The size of the fixed step in this text can be set at the beginning of the endurance test and used in subsequent endurance tests. When the size of the fixed step needs to be adjusted, before each endurance test, after modifying the size of the fixed step, the endurance test is carried out again.

[0083] The larger the fixed step in this text, the smaller the display fineness. The smaller the fixed step in this text, the larger the display fineness. This is convenient for displaying the current resistance state of the RRAM in the endurance test.

[0084] Continuing as Figure 2 shown, the above step 130 may further include: according to the determined sequence of the reset operation and the set operation, starting from the initial pulse intensity, using a combination of multiple consecutive reset operations and multiple consecutive set operations to scan the resistance range window of the RRAM device, and obtaining the highest resistance state of the RRAM device and the lowest resistance state of the RRAM device.

[0085] Since the resistance state range of the RRAM device is affected by factors such as the resistive switching material system and process conditions, before the operator defines the high resistance state and the low resistance state, the device can be subjected to multiple set and reset operations to evaluate the average high resistance state range and the average low resistance state range.

[0086] The combination in this text refers to multiple consecutive reset operations followed by multiple consecutive set operations or multiple consecutive set operations followed by multiple consecutive reset operations. In this way, the specific sequence of the reset operation and the set operation is determined according to the actual situation to determine the highest resistance state of the RRAM device and the lowest resistance state of the RRAM device. In this way, the endurance test can continue from the highest resistance state and / or the lowest resistance state of the RRAM device.

[0087] Specifically, for example, it is determined that there are multiple consecutive reset operations first, from the lowest resistance state to the highest resistance state. Then, there are multiple consecutive set operations, from the highest resistance state to the lowest resistance state. Next, starting from the lowest resistance state of the RRAM device, the endurance test is continued, and the highest resistance state ± tolerance error range to the lowest resistance state ± tolerance error range is cyclically reproduced in sequence, and then the low resistance - high resistance window within the tolerance error range is reproduced.

[0088] Similarly, for example, it is determined that there are multiple consecutive set operations first, from the highest resistance state to the lowest resistance state. Then, there are multiple consecutive reset operations, from the lowest resistance state to the highest resistance state. Next, starting from the highest resistance state of the RRAM device, the endurance test is continued, and the lowest resistance state ± tolerance error range to the highest resistance state ± tolerance error range is cyclically reproduced in sequence, and then the high resistance - low resistance window within the tolerance error range is reproduced.

[0089] In the embodiments of the present application, by balancing the reset and set pulse parameter conditions, it is avoided that the endurance test fails prematurely due to over - reset or over - set problems, which is beneficial to obtaining relatively stable and accurate endurance test results, thereby improving the service life of the device.

[0090] As Figure 3 shown, the above - mentioned step 110 can be further implemented by the following first step, and the above - mentioned step 120 can be implemented by the second step:

[0091] Step 1: First, judge the current state of the RRAM device and read the initial resistance value R0 of the RRAM device.

[0092] Step 2: If the current resistance state of the RRAM device is the low resistance state, first perform multiple consecutive reset operations, and then perform multiple consecutive set operations. After obtaining the lowest resistance state R L, min of the RRAM device, select the fixed reset pulse parameter for the endurance test, and use this fixed reset pulse parameter to start from the lowest resistance state R L, min and reproduce the previously obtained highest resistance state R H, max . Then, select the fixed set pulse parameter for the endurance test, and use this fixed set pulse parameter to start from the highest resistance state R H, max and reproduce the previously obtained lowest resistance state R L, min .

[0093] As Figure 3 shown, if the current resistance state of the RRAM device is the high resistance state, first perform multiple consecutive set operations to obtain the lowest resistance state R L, min of the RRAM device, and then perform multiple consecutive reset operations to obtain the highest resistance state R H, max of the RRAM device. Continuing Figure 3 shown, after obtaining the highest resistance state R H, maxAfter that, select the fixed set pulse parameters for the endurance test, and use these fixed set pulse parameters to reproduce the lowest resistance state R H, max starting from the highest resistance state R L, min . Then, select the fixed reset pulse parameters for the endurance test, and use these fixed reset pulse parameters to reproduce the highest resistance state R L, min starting from the lowest resistance state R H, max . Since the resistance state range of the RRAM device is affected by the resistive switching material system, process conditions, etc., the operator can perform multiple set and reset operations on the device before defining the high resistance state and the low resistance state to evaluate the average high resistance state range and the average low resistance state range.

[0094] Step 3: Set the minimum switching ratio R ratio for endurance failure. Until the high-low resistance switching ratio of the RRAM device is lower than the set minimum switching ratio, record the number of cycles of the set operation and the reset operation at this time as the endurance test result. For a detailed description, please continue to refer to Figure 3 as shown.

[0095] Continue Figure 3 as shown. By adopting the following steps, it is possible to determine that the high-low resistance switching ratio of the RRAM device is lower than the set minimum switching ratio, and record the number of cycles of the set operation and the reset operation at this time as the endurance test result. It can but is not limited to include the following first to fourth steps:

[0096] First step: Apply a combination of continuous alternating set pulses and reset pulses, and record the resistance value R HRS , R LRS of the RRAM device after the pulse. Second step: Determine whether it is . Third step: If not, return to the first step. Fourth step: If so, record the number of cycles n as the endurance test result. Among them, is the resistance value of the RRAM device after the reset pulse, and R LRS is the resistance value of the RRAM device after the set pulse. is the ratio of the high resistance state of the device after the reset pulse to the low resistance state of the device after the set pulse.

[0097] Figure 4a is shown as Figure 2 the flowchart of continuously performing multiple set operations on the RRAM memristor device in the endurance test method of the RRAM memristor shown. Figure 4b is shown as Figure 2 the flowchart of the method of continuously performing multiple reset operations on the RRAM memristor device in the endurance test method of the RRAM memristor shown.

[0098] It should be noted that: the number of cycles of the durability test is marked by n; the number of pulses in consecutive set operations or consecutive reset operations is marked by x; the number of repetitions of the same pulse in consecutive set operations or consecutive reset operations is marked by y; and the constant N is the maximum number of times the same pulse is allowed to be continuously applied.

[0099] As Figure 4a shown, first, on the premise that x = 0 and y = 0, continue to perform consecutive reset operations:

[0100] (1). Apply a set pulse with a fixed pulse width and an initial pulse height.

[0101] (2). The resistance value of the RRAM device is Rx, and x = x + 1.

[0102] (3). Judge whether < ; if so, execute (4). Apply a set pulse with a fixed pulse width and a pulse height that increases in a fixed step, y = 0, and return to execute step (2); if not, execute (5), y < N, and execute step (6).

[0103] (6). Repeat applying the current set pulse, y = y + 1, and return to execute step (2).

[0104] Then, obtain the lowest resistance state R L, min .

[0105] As Figure 4b shown in the example is similar to Figure 4a the example shown, compared with Figure 4a the example shown, the difference is that in the Figure 4b example, on the premise that x = 0 and y = 0, continue to perform consecutive set operations, and replace Figure 4a the "set pulse" in the example shown with a "reset pulse", and finally, obtain the highest resistance state R H, max .

[0106] Step 2: Perform multiple consecutive SET operations on the RRAM device. Multiple consecutive SET operations refer to continuously programming the RRAM memristor device with gradually increasing SET pulse intensities. The gradually increasing pulse intensity in this embodiment is reflected in fixing the pulse width and increasing the pulse height with a fixed step. At the beginning, apply a SET pulse with a fixed pulse width and an initial pulse height to the RRAM device in the high-resistance state, and read the resistance value of the RRAM device after the pulse. When reading the resistance value, multiple readings can be taken and averaged. After the RRAM device is loaded with the SET pulse, the resistance state of the RRAM device will change from the high-resistance state to the low-resistance state. After continuously strengthening the SET pulse intensity (continuously increasing the pulse height), the resistance state of the RRAM device will transition from the highest resistance state to the lowest resistance state. If the resistance state of the RRAM device does not change to a lower resistance state after the SET pulse is applied, then repeat the application of the current pulse parameters until the set maximum number of times N is reached.

[0107] Figure 5a as shown in Figure 4a the schematic diagram of the multiple consecutive SET operation pulses shown. Figure 5b as shown in Figure 4b the schematic diagram of the multiple consecutive RESET operation pulses shown.

[0108] Step 3: As Figure 5a and Figure 5b shown, perform multiple consecutive RESET operations on the RRAM device. Multiple consecutive RESET operations refer to continuously programming the RRAM memristor device with gradually increasing RESET pulse intensities. The gradually increasing pulse intensity in this embodiment is reflected in fixing the pulse width and increasing the pulse height with a fixed step. At the beginning, apply a RESET pulse with a fixed pulse width and an initial pulse height to the RRAM device in the low-resistance state, and read the resistance value of the RRAM device after the pulse. When reading the resistance value, multiple readings can be taken and averaged. After the RRAM device is loaded with the RESET pulse, the resistance state of the RRAM device will change from the low-resistance state to the high-resistance state. After continuously strengthening the RESET pulse intensity (continuously increasing the pulse height), the resistance state of the RRAM device will transition from the lowest resistance state to the highest resistance state. If the resistance state of the RRAM device does not change to a higher resistance state after the RESET pulse is applied, then repeat the application of the current pulse parameters until the set maximum number of times N is reached. The voltage polarities of the RESET pulse and the SET pulse are different.

[0109] Step 4: Obtain the resistance range of the RRAM device, and obtain the lowest resistance state R L, min and the highest resistance state R H, max of the RRAM device from the above multiple consecutive SET operations and multiple consecutive RESET operations. Figure 6 as shown in Figure 4a and Figure 4bThe resistance state change diagram showing continuous multiple set operations and continuous multiple reset operations on the RRAM memristive device.

[0110] Step 5: Select fixed pulse parameters for subsequent endurance tests according to the resistance range of the RRAM device. The fixed pulse parameters used in the subsequent endurance tests include fixed set pulse parameters and fixed reset pulse parameters. The fixed set pulse parameters can achieve the lowest resistance state within the resistance range window obtained for the RRAM device in the above steps; the fixed reset pulse parameters can achieve the highest resistance state within the resistance range window obtained for the RRAM device in the above steps. Since the formation and rupture of the conductive filaments in the RRAM device are affected by process conditions of the resistive switching material and there is a certain randomness, the operator can set the tolerance error range for the highest and lowest resistance states. The specific setting of the tolerance error range usually depends on the specific application requirements, process conditions, and required performance level of the RRAM device, and can be set between 1% and 10%.

[0111] Step 6: As Figure 7 shown, start the endurance test of the RRAM device by loading a combination of consecutive alternating single set pulses and single reset pulses, and record the high and low resistance states after each pulse. The operator can set an appropriate minimum switching ratio for the endurance test failure according to the application scenario. The switching ratio of the current cycle is the ratio of the high resistance value after a single reset pulse to the low resistance value after a single set pulse. Once the switching ratio of the current cycle is lower than the set minimum switching ratio threshold, it is defined as endurance failure, and the total number of cycles before failure is the endurance test result.

[0112] This application can effectively avoid the problem of premature failure of the endurance test caused by over-resetting or over-setting, help obtain more stable and accurate endurance test results, and thus improve the overall service life of the RRAM device.

[0113] Based on the same inventive concept as the above method, an embodiment of this application also provides an endurance test device for an RRAM memristor, as Figure 8 shown. The endurance test device for the RRAM memristor can include the following modules:

[0114] An acquisition module 31 for acquiring the current state of the RRAM device;

[0115] An operation sequence determination module 32 for determining the sequence of consecutive multiple reset operations and consecutive multiple set operations based on the current state of the RRAM device; the reset operation represents erasing the RRAM memristive device; the set operation represents programming the RRAM memristive device.

[0116] A fixed pulse parameter determination module 33 is configured to determine the resistance range of the RRAM device by using a gradually increasing pulse intensity, where the gradually increasing pulse intensity includes an initial pulse intensity capable of flipping the current state of the RRAM.

[0117] A durability test module 34 is configured to select fixed pulse parameters used for the durability test according to the highest resistance state and the lowest resistance state within the resistance range of the RRAM device, and load continuous and alternating reset operations and set operations to perform a durability test on the RRAM device.

[0118] An embodiment of the present application provides an electronic device, including the above-mentioned durability test device for the RRAM memristor.

[0119] The durability test method for the RRAM memristor in the embodiment of the present application is applied to an electronic device. The above-mentioned electronic device may be a PC (Personal Computer) terminal device. Among them, the PC terminal device may include, but is not limited to, a desktop computer, a tablet computer, or a laptop computer.

[0120] Figure 9 The following shows a schematic structural diagram of an electronic device 50 provided by an embodiment of the present application.

[0121] As Figure 9 shown, the electronic device 50 includes one or more processors 51, configured to implement the durability test method for the RRAM memristor as described above.

[0122] In some embodiments, the electronic device 50 may include a storage medium 59. For example, the computer-readable storage medium may store a program that can be called by the processor 51, and may include a non-volatile storage medium. In some embodiments, the electronic device 50 may include a memory 58 and an interface 57. In some embodiments, the electronic device 50 may also include other hardware according to actual applications.

[0123] The computer-readable storage medium in the embodiment of the present application stores a program, and when the program is executed by the processor 51, it is configured to implement the durability test method for the RRAM memristor described above.

[0124] The present application provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, the method described in any one of the above is implemented.

[0125] An embodiment of the present application also provides a computer program, stored in a computer-readable storage medium, such as Figure 9 shown in the storage medium 59, and when the processor executes the computer program, it causes the processor 51 to execute the method described above.

[0126] This application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain program code. Computer-readable storage media include both permanent and non-permanent, removable and non-removable media, and may implement information storage by any method or technology. The information may be computer-readable instructions, data structures, program modules, or other data. Examples of computer-readable storage media include but are not limited to: phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tapes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0127] The above are only the preferred embodiments of this specification and are not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification shall be included within the scope of protection of this specification.

[0128] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, commodity or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, commodity or device. Without further limitation, the elements defined by the statement "comprising an..." do not exclude the presence of additional identical elements in the process, method, commodity or device comprising the said elements.

Claims

1. A durability test method for an RRAM memristor, characterized in that, Including: Obtain the current state of the RRAM device; Based on the current state of the RRAM device, determine the sequence of consecutive reset operations and consecutive set operations; the reset operation represents erasing the RRAM memristor device; the set operation represents programming the RRAM memristor device; Use a gradually increasing pulse intensity to determine the resistance range of the RRAM device; the gradually increasing pulse intensity includes an initial pulse intensity capable of flipping the current state of the RRAM; The resistance range of the RRAM device includes the highest resistance state and the lowest resistance state; wherein, using the gradually increasing pulse intensity to determine the resistance range of the RRAM device includes: starting from the initial pulse intensity in accordance with the determined sequence of reset operations and set operations, using the combination of the consecutive reset operations and the consecutive set operations to scan the resistance range window of the RRAM device, and obtain the highest resistance state and the lowest resistance state of the RRAM device; the gradually increasing pulse intensity includes a gradually increasing set pulse intensity and / or a gradually increasing reset pulse intensity; the gradually increasing manner includes: by fixing the pulse width and fixing the step-by-step increasing pulse height, or by fixing the pulse height and fixing the step-by-step increasing pulse width, or, simultaneously fixing the step-by-step increasing pulse width and the increasing pulse height; According to the highest resistance state and the lowest resistance state within the resistance range of the RRAM device, select the fixed pulse parameters used in the durability test, and load consecutive alternating reset operations and set operations to perform a durability test on the RRAM device; The method further includes: determining the failure of the RRAM device in the following manner: if the switching ratio of the current cycle is lower than the set minimum switching ratio threshold, it is determined as a durability failure, and record the number of cycles of the set operation and the reset operation as the durability test result; wherein, the switching ratio of the current cycle is the ratio of the high resistance value after a single reset pulse to the low resistance value after a single set pulse.

2. The durability test method of the RRAM memristor according to claim 1, characterized in that The consecutive set operations refer to continuously programming the RRAM memristor device using the gradually increasing set pulse intensity; The gradually increasing manner of the gradually increasing set pulse intensity includes: by fixing the pulse width and fixing the step-by-step increasing pulse height, or by fixing the pulse height and fixing the step-by-step increasing pulse width, or, simultaneously fixing the step-by-step increasing pulse width and the increasing pulse height.

3. The durability test method of the RRAM memristor according to claim 2, characterized in that The current state of the RRAM device includes that the resistance state of the RRAM device is the highest resistance state; As the gradually increasing set pulse intensity is loaded each time, the resistance state of the RRAM device will gradually transition from the highest resistance state to the lowest resistance state.

4. The durability test method of the RRAM memristor according to claim 1, characterized in that The consecutive reset operations refer to continuously erasing the RRAM memristor device using the gradually increasing reset pulse intensity; The manner of gradually increasing the intensity of the reset pulse includes: by fixing the pulse width and fixing the step-increasing pulse height, or by fixing the pulse height and fixing the step-increasing pulse width, or by simultaneously fixing the step-increasing pulse width and the increasing pulse height.

5. The durability test method of the RRAM memristor according to claim 4, characterized in that, The current state of the RRAM device includes that the resistance state of the RRAM device is the lowest resistance state; With the strengthening of the gradually increasing reset pulse intensity loaded each time, the resistance state of the RRAM device will gradually transition from the lowest resistance state to the highest resistance state.

6. The durability test method of the RRAM memristor according to any one of claims 2 to 5, characterized in that, The size of the fixed step is inversely proportional to the display fineness of the durability test.

7. The durability test method of the RRAM memristor according to any one of claims 1 to 5, characterized in that, The durability test of the RRAM device by loading continuous and alternating reset operations and set operations includes: forming a cycle pulse by a single set pulse and a single reset pulse, loading the cycle pulse multiple times to perform the durability test on the RRAM device, and recording the high resistance state and the low resistance state of the RRAM device after each pulse until the RRAM device fails.

8. A durability test device for an RRAM memristor, characterized in that, Including: An acquisition module for acquiring the current state of the RRAM device; An operation sequence determination module for determining the sequence of consecutive multiple reset operations and consecutive multiple set operations based on the current state of the RRAM device; the reset operation represents erasing the RRAM memristive device; the set operation represents programming the RRAM memristive device; A fixed pulse parameter determination module for determining the resistance range of the RRAM device using a gradually increasing pulse intensity; the gradually increasing pulse intensity includes the initial pulse intensity capable of flipping the current state of the RRAM; The resistance range of the RRAM device includes the highest resistance state and the lowest resistance state; wherein, determining the resistance range of the RRAM device using a gradually increasing pulse intensity includes: starting from the initial pulse intensity in accordance with the determined sequence of the reset operation and the set operation, using the combination of the consecutive multiple reset operations and the consecutive multiple set operations to scan the resistance range window of the RRAM device to obtain the highest resistance state and the lowest resistance state of the RRAM device; the gradually increasing pulse intensity includes a gradually increasing set pulse intensity and / or a gradually increasing reset pulse intensity; the manner of gradually increasing includes: by fixing the pulse width and fixing the step-increasing pulse height, or by fixing the pulse height and fixing the step-increasing pulse width, or by simultaneously fixing the step-increasing pulse width and the increasing pulse height; A durability test module, which is used to select the fixed pulse parameters used in the durability test according to the highest resistance state and the lowest resistance state within the resistance range of the RRAM device, load continuous and alternating reset operations and set operations, and perform a durability test on the RRAM device; the following method is adopted to determine the failure of the RRAM device: if the switching ratio of the current cycle is lower than the set minimum switching ratio threshold, it is determined as a durability failure, and the number of cycles of the set operation and the reset operation is recorded as the durability test result; wherein, the switching ratio of the current cycle is the ratio of the high resistance value after a single reset pulse to the low resistance value after a single set pulse.

9. An electronic device, characterized in that, It includes one or more processors, which are used to implement the durability test method of the RRAM memristor described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, A program is stored thereon, and when the program is executed by the processor, the durability test method of the RRAM memristor described in any one of claims 1-7 is implemented.

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