Multilayer silicon capacitor stacked device and packaging method thereof

Abstract

The invention provides a multilayer silicon capacitor stacking device and a packaging method thereof, and belongs to the field of semiconductor processing. The multilayer silicon capacitor stack device comprises a plurality of wafers, each wafer comprises a silicon substrate, a first silicon capacitor and a second silicon capacitor which are symmetrically arranged on the upper side and the lower side of the silicon substrate, a first bonding pad, a third bonding pad, a second bonding pad and a fourth bonding pad, the first bonding pad and the second bonding pad are connected to the first silicon capacitor, and the third bonding pad and the fourth bonding pad are connected to the second silicon capacitor. The first bonding pad is connected to the first silicon capacitor, the third bonding pad and the fourth bonding pad are connected to the second silicon capacitor, a first through hole is formed between the first bonding pad and the third bonding pad, a second through hole is formed between the second bonding pad and the fourth bonding pad, and the first through hole and the second through hole are filled with metal, so that the capacitors on the upper side and the lower side of a single wafer are connected in parallel. And meanwhile, the plurality of wafers are electrically connected with one another through the wafer interconnection structures via the corresponding bonding pads, so that stacking of the plurality of wafers and parallel connection of the capacitors are realized, and the capacitance density and the storage capacity of the silicon capacitor are improved by several times under the condition of the same projection size.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor processing, and in particular to a multi-layer silicon capacitor stack device and a packaging method thereof. Background Art

[0002] Silicon capacitors are widely used in communication base stations, automobiles, implantable medical systems, mobile terminals, aerospace and other fields due to their excellent stability, reliability, aging resistance and other characteristics. Silicon capacitors are usually processed by semiconductor technology, using processes such as lithography, etching and chemical vapor deposition to prepare three-dimensional structures and functional layer films. In order to improve the capacitance density and storage capacity of silicon capacitors, the industry has adopted a variety of strategies, including optimizing the etching process to adjust the etching depth-to-width ratio and introducing materials with high dielectric constants. However, in the process of changing the etching depth-to-width ratio, when the depth-to-width ratio exceeds a certain value, the step coverage of the capacitor dielectric material in the three-dimensional structure area is difficult to ensure, which will cause voids between the functional layer films inside the capacitor, thereby affecting the performance of the capacitor. In addition, in the case of ultra-thin, the dielectric constant (K value) of the high dielectric constant material will decrease, and it is difficult to form a crystal layer, etc. These factors limit the ability to manufacture high-performance capacitors through semiconductor processes. Therefore, there is an urgent need to develop new technologies and methods to break through the existing limitations and effectively improve the capacitance density and storage capacity of silicon capacitors. Summary of the invention

[0003] The present invention provides a multilayer silicon capacitor stacking device and a packaging method thereof, which improves the structure of the silicon capacitor, adds a parallel structure of capacitors on the upper and lower sides of a single wafer and a parallel stacking structure of capacitors between multiple wafers to effectively improve the capacitance density and storage capacity of the silicon capacitor.

[0004] The present invention provides a multi-layer silicon capacitor stack device, comprising: A plurality of wafers, each of the plurality of wafers comprising: Silicon substrate; A first silicon capacitor and a second silicon capacitor, wherein the first silicon capacitor and the second silicon capacitor are symmetrically arranged on upper and lower sides of the silicon substrate respectively; A first pad and a third pad, wherein the first pad and the third pad are symmetrically arranged on upper and lower sides of the silicon substrate, respectively, and the first pad is electrically connected to the first electrode of the first silicon capacitor, and the third pad is electrically connected to the first electrode of the second silicon capacitor; A second pad and a fourth pad, wherein the second pad and the fourth pad are symmetrically arranged on upper and lower sides of the silicon substrate, respectively, and the second pad is electrically connected to the second electrode of the first silicon capacitor, and the fourth pad is electrically connected to the second electrode of the second silicon capacitor; a first through hole, arranged between the first pad and the third pad in a direction perpendicular to the surface of the silicon substrate and filled with metal; a second through hole, arranged between the second pad and the fourth pad in a direction perpendicular to the surface of the silicon substrate and filled with metal; Among them, the first pad of one of the multiple wafers is electrically connected to the third pad of another one of the multiple wafers through a wafer interconnection structure, and the second pad of the one of the multiple wafers is electrically connected to the fourth pad of the other one of the multiple wafers through the wafer interconnection structure, so that the first silicon capacitor electrically connected to the first pad and the second pad of the one of the multiple wafers and the second silicon capacitor electrically connected to the third pad and the fourth pad of the other one of the multiple wafers are connected in parallel.

[0005] In one embodiment, the wafer interconnection structure includes a wafer bonding structure, which includes a bonding structure formed by respectively applying anisotropic conductive adhesive between the first pad and the second pad of the one of the multiple wafers and the third pad and the fourth pad of the other of the multiple wafers and performing hot pressing.

[0006] In one embodiment, the metal is any one or more of titanium, tungsten, copper, gold, chromium, nickel, and titanium nitride.

[0007] In one embodiment, the metal is filled in the first through hole and the second through hole by any one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and electroplating filling.

[0008] In one embodiment, the first pad, the second pad, the third pad and the fourth pad cover adjacent scribe lane regions on the wafer.

[0009] The present invention also provides a packaging method for a multi-layer silicon capacitor stack device, comprising: A first silicon capacitor and a second silicon capacitor are symmetrically formed on the upper surface and the lower surface of the silicon substrate respectively; In a direction perpendicular to the surface of the silicon substrate, a first through hole and a second through hole are respectively formed at two ends of the first silicon capacitor; A first pad and a third pad, as well as a second pad and a fourth pad are symmetrically formed on the upper surface and the lower surface of the silicon substrate, respectively, and the first through hole and the second through hole are filled with metal, wherein the first pad covers the first through hole and is electrically connected to the first electrode of the first silicon capacitor, the second pad covers the second through hole and is electrically connected to the second electrode of the first silicon capacitor, the third pad covers the first through hole and is electrically connected to the first electrode of the second silicon capacitor, and the fourth pad covers the second through hole and is electrically connected to the second electrode of the second silicon capacitor; and Through a wafer interconnection process, a first pad of one of the multiple wafers is electrically connected to a third pad of another of the multiple wafers, and a second pad of the one of the multiple wafers is electrically connected to a fourth pad of the other of the multiple wafers, so that the first silicon capacitor electrically connected to the first pad and the second pad of the one of the multiple wafers and the second silicon capacitor electrically connected to the third pad and the fourth pad of the other of the multiple wafers are connected in parallel.

[0010] In one embodiment, the wafer interconnection process includes wafer bonding, and the wafer bonding includes applying anisotropic conductive adhesive between the first pad and the second pad of one of the multiple wafers and the third pad and the fourth pad of another of the multiple wafers, respectively, and performing hot pressing.

[0011] In one embodiment, the metal is any one or more of titanium, tungsten, copper, gold, chromium, nickel, and titanium nitride.

[0012] In one embodiment, the metal is filled in the first through hole and the second through hole by any one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and electroplating filling.

[0013] In one embodiment, the first pad, the second pad, the third pad and the fourth pad cover adjacent scribe lane regions on the wafer.

[0014] The multilayer silicon capacitor stacking device and packaging method provided by the present invention realize parallel connection of capacitors on the upper and lower sides of the wafer by setting through holes on the wafer and depositing metal, and at the same time realize parallel stacking of wafer-level silicon capacitors by electrically connecting the pads of each wafer through a wafer interconnection structure, thereby achieving a several-fold increase in the capacitance density and storage capacity of the silicon capacitor under the same projection size conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 is a schematic diagram of a capacitor cross-sectional structure of a single wafer according to an embodiment of the present invention; Figure 2 According to an embodiment of the present invention Figure 1 A top view of a through hole of a single wafer is shown; Figure 3 is a schematic cross-sectional structure diagram of capacitors connected in parallel on a single wafer according to an embodiment of the present invention; Figure 4 is a schematic cross-sectional structure diagram of a capacitor stack of multiple wafers according to an embodiment of the present invention; Figure 5 is a schematic diagram of a capacitor cross-sectional structure of a single wafer according to another embodiment of the present invention; Figure 6 According to another embodiment of the present invention Figure 5 A top view of a through hole of a single wafer is shown; Figure 7 is a schematic cross-sectional structure diagram of capacitors of a single wafer connected in parallel according to another embodiment of the present invention; Figure 8 is a schematic cross-sectional structure diagram of a capacitor stack of multiple wafers according to another embodiment of the present invention; Fig. 9 is a flow chart of a packaging method for a multi-layer silicon capacitor stack device according to an embodiment of the present invention; Fig.10 is a flow chart of a packaging method for a multi-layer silicon capacitor stack device according to another embodiment of the present invention; Fig.11 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below in conjunction with the drawings in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other in the absence of conflict. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0019] It should be further noted that, in this article, the terms "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0020] In the present invention, "at least one" means one or more, and "more" means two or more than two. The terms "first", "second", "third", "fourth", etc. (if any) in the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0021] In the embodiments of the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0022] In the embodiments of the present invention, it should be noted that for the convenience of description, on the premise of making the description of the contents of the present invention clear, as an example, the parts with the same structure in the drawings only mark the main components, and the markings and corresponding descriptions of other parts with the same structure are omitted.

[0023] Combine the following Figures 1 to 8 Specific embodiments of the present invention are described.

[0024] The present invention provides a multi-layer silicon capacitor stack device, such as Figure 8 As shown, it includes multiple wafers. Each of the multiple wafers includes a silicon substrate, multiple first silicon capacitors, multiple second silicon capacitors, and multiple connection structures that realize parallel connection of the multiple first silicon capacitors with the corresponding multiple second silicon capacitors. Each connection structure includes a first pad to a fourth pad, a first through hole, and a second through hole, such as Figure 7 shown.

[0025] Considering the similarities between the capacitors on each wafer and between the connection structures, in order to more clearly describe the structure of the multi-layer silicon capacitor stack device of the present invention, the following will refer to Figures 1 to 4 , the present invention is described in detail by taking a pair of capacitors in each wafer and their corresponding connection structures as an example.

[0026] Specifically, the capacitor cross-sectional structure of each of the plurality of wafers is as follows: Figure 1 As shown, the top view of the through hole is as follows Figure 2 Reference Figure 1 and Figure 2 The first silicon capacitor 120 and the second silicon capacitor 130 are symmetrically arranged on the upper and lower sides of the silicon substrate 110, respectively. The electrodes of the capacitor close to the silicon substrate in the vertical direction Y are the first electrodes 121 and 131, and the electrodes away from the silicon substrate are the second electrodes 122 and 132. The two ends of the capacitor in the horizontal direction X are as shown in FIG. Figure 1 The capacitor 100 has spacing regions 114 and 115 for separating the capacitor 100 from other capacitors not shown. The first through hole 111 and the second through hole 112 are respectively provided in the spacing regions 114 and 115. Note that the first through hole 111 and the second through hole 112 may be as shown in FIG. Figure 2 The square hole shown may alternatively be a round hole or a through hole having other geometric shapes.

[0027] The cross-sectional structure of capacitors connected in parallel on a single wafer is shown below: Figure 3 As shown, except Figure 1 and Figure 2 In addition to the structure shown, the first pad 123 , the second pad 124 , the third pad 133 , and the fourth pad 134 are also included.

[0028] Specifically, Figure 3 As shown, the first pad 123 and the third pad 133, the second pad 124 and the fourth pad 134 are symmetrically arranged on the upper and lower sides of the silicon substrate 110. Among them, the first pad 123 and the second pad 124 are located at both ends of the first silicon capacitor 120, the first pad 123 is electrically connected to the first electrode 121 of the first silicon capacitor 120, and the second pad 124 is electrically connected to the second electrode 122 of the first silicon capacitor 120. The third pad 133 and the fourth pad 134 are located at both ends of the second silicon capacitor 130, the third pad 133 is electrically connected to the first electrode 131 of the second silicon capacitor 130, and the fourth pad 134 is electrically connected to the second electrode 132 of the second silicon capacitor 130.

[0029] like Figure 3As shown, in the vertical direction Y, the first through hole 111 is located between the first pad 123 and the third pad 133 corresponding to the first silicon capacitor 120 and the second silicon capacitor 130, and the second through hole 112 is located between the second pad 124 and the fourth pad 134. The inner wall of the through hole may be provided with an insulating layer to prevent leakage and crosstalk. Preferably, the first through hole 111 and the second through hole 112 may be through silicon vias made by a through silicon via (TSV) process.

[0030] like Figure 3 As shown, the first through hole 111 and the second through hole 112 are filled with metal, so that the first pad 123 and the third pad 133 are electrically connected to each other, and the second pad 124 and the fourth pad 134 are electrically connected to each other, thereby realizing the parallel connection of the first silicon capacitor 120 and the second silicon capacitor 130, thereby doubling the capacitance density.

[0031] Figure 4 is a schematic cross-sectional structure diagram of a capacitor stack of multiple wafers according to an embodiment of the present invention.

[0032] like Figure 4 As shown, in the included reference Figures 1 to 3 In the stacking structure of multiple wafers of a single wafer described, the first pad 123 and the second pad 124 of any one wafer are electrically connected to the corresponding third pad 133 and the fourth pad 134 of another wafer, respectively, thereby realizing parallel connection of corresponding capacitors in multiple wafers, thereby achieving a significant increase in the capacitor capacity density.

[0033] Optionally, the electrical connection between the pads can be formed by welding. Preferably, the electrical connection between the pads can be formed in the form of a wafer bonding structure. The wafer bonding structure can be formed by applying anisotropic conductive adhesive between the pads that need to be electrically connected and then hot pressing. Anisotropic conductive adhesive has good flexibility and impact resistance, and can achieve reliable connection of extremely small pitch components.

[0034] In the stacking of multiple wafers, due to the symmetry of the capacitors and pads on the upper and lower sides of the substrate of a single wafer, in addition to Figure 4 In addition to achieving stacking of multiple wafers in the manner shown, stacking of multiple wafers can also be achieved by electrically connecting pads with the same reference numerals corresponding to any two wafers, or by any combination of the above two connection methods.

[0035] In the above embodiment, the silicon capacitors symmetrically arranged on the upper and lower surfaces of the silicon substrate of a single wafer are connected in parallel through symmetrically arranged pads and through holes filled with metal between the pads. At the same time, the corresponding pads of multiple different wafers of the same structure are electrically connected to each other through connection structures such as wafer bonding structures, so that multiple wafers can be stacked and capacitors can be connected in parallel, which greatly improves the capacitance density of the capacitors while maintaining the same high withstand voltage capability.

[0036] The present invention is described in detail above by taking a pair of capacitors in each wafer and their corresponding connection structures as an example. Figures 5 to 8 , the present invention will be described by taking multiple pairs of capacitors in each wafer and their corresponding connection structures as examples.

[0037] Specifically, the capacitor cross-sectional structure of each of the plurality of wafers is as follows: Figure 5 As shown, the top view of the through hole is as follows Figure 6 It should be noted that although Figure 5 and Figure 6 3 pairs of silicon capacitors are shown to be symmetrically arranged on the upper and lower sides of the silicon substrate, but this is just an example given for the convenience of description, and the number of capacitors symmetrically arranged on the upper and lower sides of the silicon substrate is not limited thereto.

[0038] refer to Figure 5 and Figure 6 , a plurality of first silicon capacitors 520 and a plurality of second silicon capacitors 530 are symmetrically arranged on the upper and lower sides of the silicon substrate 510, and the adjacent capacitors on each side are separated from each other by the spacing area 513. The electrodes of each capacitor close to the silicon substrate in the vertical direction Y are first electrodes 521 and 531, and the electrodes away from the silicon substrate are second electrodes 522 and 532. Among the capacitors on each side, the capacitors located at the ends of the silicon substrate in the horizontal direction X (for example, the capacitors close to the edge of the wafer) are far from the ends of the silicon substrate 510, such as Figure 5 As shown, spacing regions 514 and 515 are also provided. Corresponding first through holes 511 and second through holes 512 are respectively provided in the spacing regions 513 of adjacent capacitors and the spacing regions 514 and 515 of the ends. In the same spacing region, only one through hole, i.e., the first through hole 511 or the second through hole 512, may be provided. Figure 6 Note that the first through hole 511 and the second through hole 512 may be as shown in FIG. Figure 6 The square hole shown may alternatively be a round hole or a through hole having other geometric shapes.

[0039] The cross-sectional structure of capacitors connected in parallel on a single wafer is shown below: Figure 7 As shown, except Figure 5 and Figure 6In addition to the structure shown, it also includes multiple first pads 523 , multiple second pads 524 , multiple third pads 533 , and multiple fourth pads 534 .

[0040] Specifically, in Figure 7 In the embodiment, a plurality of first pads 523 and a plurality of third pads 533, a plurality of second pads 524 and a plurality of fourth pads 534 are symmetrically arranged on the upper and lower sides of the silicon substrate 510. In each first silicon capacitor 520, the first pad 523 and the second pad 524 are respectively located at the two ends of the corresponding first silicon capacitor 520, the first pad 523 is electrically connected to the first electrode 521 of the corresponding first silicon capacitor 520, and the second pad 524 is electrically connected to the second electrode 522 of the corresponding first silicon capacitor 520. In each second silicon capacitor 530, the third pad 533 and the fourth pad 534 are respectively located at the two ends of the corresponding second silicon capacitor 530, the third pad 533 is electrically connected to the first electrode 531 of the corresponding second silicon capacitor 530, and the fourth pad 534 is electrically connected to the second electrode 532 of the corresponding second silicon capacitor 530. The adjacent pads on each side of the silicon substrate 510 are electrically connected to each other.

[0041] like Figure 7 As shown, in the vertical direction Y, the plurality of first through holes 511 are located between the plurality of first pads 523 and the plurality of third pads 533 symmetrically arranged with each other, and the plurality of second through holes 512 are located between the plurality of second pads 524 and the plurality of fourth pads 534 symmetrically arranged with each other. An insulating layer may be provided on the inner wall of the through hole to prevent leakage and crosstalk. Preferably, the plurality of first through holes 511 and the plurality of second through holes 512 may be through silicon vias made by a through silicon via (TSV) process.

[0042] like Figure 7 As shown, multiple first through holes 511 and multiple second through holes 512 are filled with metal, so that the first pad 523 and the third pad 533 that are symmetrical to each other are electrically connected, and the second pad 524 and the fourth pad 534 that are symmetrical to each other are electrically connected, thereby realizing the parallel connection of the first silicon capacitor 520 and the second silicon capacitor 530 that are symmetrical to each other, and then doubling the capacitance density.

[0043] Figure 8 is a schematic cross-sectional structure diagram of a capacitor stack of multiple wafers according to an embodiment of the present invention.

[0044] like Figure 8 As shown, in the included reference Figures 5 to 7In the stacking structure of multiple wafers of a single wafer described, the multiple first pads 523 and the multiple second pads 524 of any one wafer are respectively electrically connected to the corresponding multiple third pads 533 and the multiple fourth pads 534 of another wafer, thereby realizing parallel connection of corresponding capacitors in multiple wafers, and further achieving a significant increase in the capacitor capacity density.

[0045] Optionally, the electrical connection between the pads can be formed by welding. Preferably, the electrical connection between the pads can be formed in the form of a wafer bonding structure. The wafer bonding structure can be formed by applying anisotropic conductive adhesive between the pads that need to be electrically connected and then performing hot pressing.

[0046] In the stacking of multiple wafers, due to the symmetry of the capacitors and pads on the upper and lower sides of the substrate of a single wafer, in addition to Figure 8 In addition to achieving stacking of multiple wafers in the manner shown, stacking of multiple wafers can also be achieved by electrically connecting pads with the same reference numerals corresponding to any two wafers, or by any combination of the above two connection methods.

[0047] In the above embodiment, multiple silicon capacitors are symmetrically arranged on the upper and lower surfaces of the silicon substrate of a single wafer, and the capacitors on the same side are interconnected by electrically connecting the adjacent pads of the silicon capacitors on the same side, and the silicon capacitors symmetrically arranged on the upper and lower surfaces of the silicon substrate are connected in parallel by symmetrically arranged pads and through holes filled with metal between the pads, thereby doubling the capacitance density on a single wafer. At the same time, corresponding pads of multiple different wafers of the same structure are electrically connected to each other through connection structures such as wafer bonding structures, thereby realizing the stacking of multiple wafers and the parallel connection of capacitors, thereby greatly improving the capacitance density of capacitors and maintaining the same high withstand voltage capability.

[0048] In one embodiment, the filled metal is any one or more of titanium, tungsten, copper, gold, chromium, nickel, titanium nitride, and the like.

[0049] In one embodiment, the metal is filled in the through hole by any one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and electroplating filling.

[0050] In one embodiment, the metal is filled in the through hole by any one of physical vapor deposition, chemical vapor deposition and atomic layer deposition combined with an electroplating process. A seed layer is formed in the through hole by a deposition process, providing a uniform starting surface for electroplating. During the electroplating process, metal ions are uniformly deposited on the surface of the seed layer, which helps to achieve uniform filling of the through hole. In particular, for silicon through vias with a high aspect ratio, the seed layer can guide the metal ions to grow uniformly throughout the through hole, thereby improving the reliability of the electrical connection.

[0051] In one embodiment, each of the bonding pads partially or completely covers the adjacent spacing area on the wafer.

[0052] In one embodiment, the spacing area between adjacent capacitors may be a scribe line area on a wafer. The scribe line area refers to a reserved area on a wafer for slicing or cutting, usually located between chips on a wafer. Through holes may be provided in the scribe line area covered by the pads, thereby achieving parallel connection of corresponding capacitors on the upper and lower surfaces of a single wafer and parallel connection of corresponding capacitors between different wafers without affecting the existing structure of the capacitors.

[0053] The packaging method of the multilayer silicon capacitor stack device provided by the present invention is described below. The packaging method of the multilayer silicon capacitor stack device described below and the multilayer silicon capacitor stack device described above can be referred to each other.

[0054] Considering the similarities between the capacitors on each wafer and between the connection structures, in order to more clearly describe the packaging method of the multi-layer silicon capacitor stack device of the present invention, the following will refer to Fig. 9 Combined with Figures 1 to 4 , the present invention is described in detail by taking a packaging method of a pair of capacitors in each wafer and their corresponding connection structures as an example.

[0055] like Fig. 9 As shown, the present invention also provides a packaging method for a multi-layer silicon capacitor stack device, which is used to prepare the multi-layer silicon capacitor stack device. Figures 1 to 4 The packaging method is described, and the packaging method includes: Step S910 , manufacturing a first silicon capacitor 120 and a second silicon capacitor 130 symmetrically disposed on the upper surface and the lower surface of the silicon substrate 110 , respectively.

[0056] Specifically, Figure 1 As shown, in a single wafer, a first silicon capacitor 120 and a second silicon capacitor 130 are symmetrically manufactured on the upper and lower sides of a silicon substrate 110, respectively. The electrodes of the capacitor close to the silicon substrate in the vertical direction Y are first electrodes 121 and 131, and the electrodes away from the silicon substrate are second electrodes 122 and 132. The two ends of the capacitor in the horizontal direction X are as shown in FIG. Figure 1 and Figure 2 Shown are spacing areas 114 and 115 for spacing from other capacitors not shown.

[0057] Step S920 , in a direction perpendicular to the surface of the silicon substrate, a first through hole 111 and a second through hole 112 are respectively formed at two ends of the first silicon capacitor 120 .

[0058] Specifically, Figure 1 and Figure 2 As shown, in the vertical direction Y, the first through hole 111 and the second through hole 112 are respectively made in the spacing areas 114 and 115. It is noted that the first through hole 111 and the second through hole 112 can be as follows Figure 2 The through hole is a square hole as shown, and optionally, the through hole may be a round hole or a through hole having other geometric shapes. To prevent leakage and crosstalk, an insulating layer may be formed on the inner wall of the first through hole 111 and the second through hole 112 by deep hole sputtering or thermal oxidation. As an example, the first through hole 111 and the second through hole 112 may be made by a through silicon via (TSV) process.

[0059] Step S930 , symmetrically arranged first pad 123 and third pad 133 , and second pad 124 and fourth pad 134 are respectively manufactured on the upper surface and the lower surface of the silicon substrate, and the first through hole 111 and the second through hole 112 are filled with metal.

[0060] Specifically, refer to Figure 3 , through the deposition process, the first pad 123 and the third pad 133, the second pad 124 and the fourth pad 134 are symmetrically made on the upper and lower sides of the silicon substrate 110, and the metal filling in the first through hole 111 and the second through hole 112 is completed through the deposition process. The first pad 123 and the second pad 124 are located at both ends of the first silicon capacitor 120, the first pad 123 covers the first through hole 111 and is electrically connected to the first electrode 121 of the first silicon capacitor 120, and the second pad 124 covers the second through hole 112 and is electrically connected to the second electrode 122 of the first silicon capacitor 120. The third pad 133 and the fourth pad 134 are located at both ends of the second silicon capacitor 130, the third pad 133 covers the first through hole 111 and is electrically connected to the first electrode 131 of the second silicon capacitor 130, and the fourth pad 134 covers the second through hole 112 and is electrically connected to the second electrode 132 of the second silicon capacitor 130. As an example, the filling of the via with metal and the formation of the corresponding pad are done simultaneously by the same deposition process.

[0061] like Figure 3 As shown, since the first solder pad 123 and the third solder pad 133 both cover the first through hole 111, the first solder pad 123 and the third solder pad 133 are electrically connected to each other, and since the second solder pad 124 and the fourth solder pad 134 both cover the second through hole 112, the second solder pad 124 and the fourth solder pad 134 are electrically connected to each other, thereby realizing the parallel connection of the first silicon capacitor 120 and the second silicon capacitor 130, thereby doubling the capacitance density.

[0062] Optionally, the pads may be made before the through holes, that is, the first through hole 111 and the second through hole 112 may be made after the symmetrically arranged first pad 123 and the third pad 133 and the second pad 124 and the fourth pad 134 are made. Specifically, after the symmetrically arranged first pad 123 and the third pad 133 and the second pad 124 and the fourth pad 134 are made by the deposition process, the first through hole 111 is made between the first pad 123 and the third pad 133, and the second through hole 112 is made between the second pad 124 and the fourth pad 134 in the vertical direction Y, and the deposition process is used again to fill the first through hole 111 and the second through hole 112 with metal. Thereby, the first silicon capacitor 120 and the second silicon capacitor 130 are connected in parallel, thereby doubling the capacitance density.

[0063] Step S940, through the wafer interconnection process, the first pad 123 of one of the multiple wafers is electrically connected to the third pad 133 of another of the multiple wafers, and the second pad 124 of the one of the multiple wafers is electrically connected to the fourth pad 134 of the other of the multiple wafers.

[0064] Specifically, refer to Figure 4 , including reference Figures 1 to 3 In the described single wafer, the first pad 123 and the second pad 124 of any wafer are electrically connected to the corresponding third pad 133 and the fourth pad 134 of another wafer respectively by using a wafer interconnection process. Through the electrical connection of the corresponding pads, the corresponding capacitors in the multiple wafers are connected in parallel, thereby achieving a significant increase in the capacitor capacity density.

[0065] The wafer interconnection process may be welding. Preferably, the wafer interconnection process may be wafer bonding, including applying anisotropic conductive adhesive between pads that need to be electrically connected and forming electrical connections through hot pressing.

[0066] The present invention is described above by taking a packaging method of a pair of capacitors in each wafer and their corresponding connection structures as an example. Fig.10 Combined with Figures 5 to 8 , the present invention is described by taking a packaging method of multiple pairs of capacitors in each wafer and their corresponding connection structures as an example.

[0067] like Fig.10 As shown, the present invention also provides a packaging method for a multi-layer silicon capacitor stack device, which is used to prepare the multi-layer silicon capacitor stack device. Figures 5 to 8 The packaging method is described, and the packaging method includes: In step S1010 , a plurality of first silicon capacitors 520 and a plurality of second silicon capacitors 530 are respectively manufactured on the upper surface and the lower surface of the silicon substrate 510 symmetrically.

[0068] Specifically, Figure 5 As shown, in a single wafer, a plurality of first silicon capacitors 520 and a plurality of second silicon capacitors 530 are symmetrically manufactured on the upper and lower sides of a silicon substrate 510, respectively. Adjacent capacitors on each side are separated from each other by a spacing region 513. The electrodes of each capacitor close to the silicon substrate in the vertical direction Y are first electrodes 521 and 531, and the electrodes away from the silicon substrate are second electrodes 522 and 532. Among the capacitors on each side that are located at the end of the silicon substrate in the horizontal direction X (for example, the capacitors close to the edge of the wafer), the end away from the silicon substrate 510 is as shown in FIG. Figure 5 and Figure 6 As shown, they extend outwardly to form spacing regions 514 and 515.

[0069] Step S1020 , in a direction perpendicular to the surface of the silicon substrate, a first through hole 511 and a second through hole 512 are respectively formed at two ends of each first silicon capacitor 520 .

[0070] Specifically, Figure 5 and Figure 6 As shown, in the vertical direction Y, the first through hole 511 and the second through hole 512 are respectively made in the spacing area 513 and the spacing areas 514 and 515. Among them, only one through hole, namely the first through hole 511 or the second through hole 512, can be set in the same spacing area. Figure 6 Note that the first through hole 511 and the second through hole 512 may be as shown in FIG. Figure 6 The square hole shown may alternatively be a round hole or a through hole having other geometric shapes. To prevent leakage and crosstalk, an insulating layer may be formed on the inner wall of the first through hole 511 and the second through hole 512 by deep hole sputtering or thermal oxidation. As an example, the first through hole 511 and the second through hole 512 may be made by a through silicon via (TSV) process.

[0071] Step S1030 , symmetrically forming a plurality of first pads 523 and a plurality of third pads 533 , a plurality of second pads 524 and a plurality of fourth pads 534 on the upper surface and the lower surface of the silicon substrate, respectively, and filling the first through hole 511 and the second through hole 512 with metal.

[0072] Specifically, through the deposition process, a plurality of symmetrical first pads 523 and a plurality of third pads 533, a plurality of symmetrical second pads 524 and a plurality of fourth pads 534 are respectively made on the upper and lower sides of the silicon substrate 510, and through the deposition process, the metal filling in the first through hole 511 and the second through hole 512 is completed. In each first silicon capacitor 520, the first pad 523 and the second pad 524 are respectively located at the two ends of the corresponding first silicon capacitor 520, the first pad 523 covers the corresponding first through hole 511 and is electrically connected to the first electrode 521 of the corresponding first silicon capacitor 520, and the second pad 524 covers the corresponding second through hole 512 and is electrically connected to the second electrode 522 of the corresponding first silicon capacitor 520. In each second silicon capacitor 530, a third pad 533 and a fourth pad 534 are respectively located at two ends of the corresponding second silicon capacitor 530, the third pad 533 covers the corresponding first through hole 511 and is electrically connected to the first electrode 531 of the corresponding second silicon capacitor 530, and the fourth pad 534 covers the corresponding second through hole 512 and is electrically connected to the second electrode 532 of the corresponding second silicon capacitor 530. The adjacent pads on each side of the silicon substrate 510 are electrically connected to each other. As an example, the filling of the metal in the through hole and the formation of the corresponding pads are completed simultaneously by the same deposition process.

[0073] like Figure 7 As shown, for each pair of symmetrically arranged first silicon capacitors 520 and second silicon capacitors 530, since the symmetrically arranged first pads 523 and third pads 533 both cover the corresponding first through holes 511, the symmetrically arranged first pads 523 and third pads 533 are electrically connected to each other, and since the symmetrically arranged second pads 524 and fourth pads 534 both cover the corresponding second through holes 512, the second pads 524 and fourth pads 534 are electrically connected to each other, thereby realizing the parallel connection of each pair of symmetrically arranged first silicon capacitors 520 and second silicon capacitors 530, and since the adjacent pads on each side of the silicon substrate 510 are electrically connected to each other, the parallel connection of multiple first silicon capacitors 520 and multiple second silicon capacitors 530 on a single wafer is realized, thereby doubling the capacitance density.

[0074] Optionally, the pads may be made before the through holes, that is, the first through holes 511 and the second through holes 512 may be made after the symmetrically arranged first pads 523 and the third pads 533 and the second pads 524 and the fourth pads 534 are made. Specifically, after the symmetrically arranged first pads 523 and the third pads 533 and the second pads 524 and the fourth pads 534 are made by the deposition process, the first through hole 511 is made between the symmetrically arranged first pads 523 and the corresponding third pads 533 in the vertical direction Y, and the second through hole 512 is made between the symmetrically arranged second pads 524 and the corresponding fourth pads 534, and the deposition process is used again to fill the first through hole 511 and the second through hole 512 with metal. This realizes the parallel connection of each pair of symmetrically arranged first silicon capacitors 520 and second silicon capacitors 530. At the same time, since adjacent pads on each side of the silicon substrate 510 are electrically connected to each other, the parallel connection of multiple first silicon capacitors 520 and multiple second silicon capacitors 530 on a single wafer is realized.

[0075] Step S1040, through the wafer interconnection process, the multiple first pads 523 of one of the multiple wafers are electrically connected to the corresponding multiple third pads 533 of another of the multiple wafers, and the multiple second pads 524 of the one of the multiple wafers are electrically connected to the corresponding multiple fourth pads 534 of another of the multiple wafers.

[0076] Specifically, refer to Figure 8 , including reference Figures 5 to 7 In the multiple wafers of the described single wafer, the multiple first pads 523 and the multiple second pads 524 of any wafer are electrically connected to the corresponding multiple third pads 533 and the multiple fourth pads 534 of another wafer respectively by using a wafer interconnection process. Through the electrical connection of the corresponding pads, the corresponding capacitors in the multiple wafers are connected in parallel, thereby achieving a significant increase in the capacitance density of the capacitors.

[0077] The wafer interconnection process may be welding. Preferably, the wafer interconnection process may be wafer bonding, including applying anisotropic conductive adhesive between pads that need to be electrically connected and forming electrical connections through hot pressing.

[0078] The above embodiment realizes the interconnection of capacitors on the same side by symmetrically manufacturing multiple silicon capacitors on the upper and lower surfaces of the silicon substrate of a single wafer, and then symmetrically manufacturing multiple pads electrically connected to the corresponding electrodes of the capacitors, and electrically connecting the adjacent pads on the same side. At the same time, through holes are set between the pads that are symmetrical up and down, and metal is filled in the through holes to realize the electrical connection of the corresponding pads on the upper and lower surfaces of the silicon substrate, thereby realizing the parallel connection of the capacitors on the upper and lower surfaces of the silicon substrate of a single wafer, and doubling the capacitance density on a single wafer. At the same time, through connection structures such as wafer bonding structures, the corresponding pads of multiple different wafers of the same structure are electrically connected to each other, realizing the stacking of multiple wafers and the parallel connection of capacitors, realizing a significant increase in the capacitance density of capacitors, and maintaining the same high withstand voltage capability.

[0079] In one embodiment, the filled metal is any one or more of titanium, tungsten, copper, gold, chromium, nickel, and titanium nitride.

[0080] In one embodiment, the metal filling is accomplished by any one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and electroplating filling.

[0081] In one embodiment, the material filling is completed by any one of physical vapor deposition, chemical vapor deposition and atomic layer deposition combined with an electroplating process. A uniform seed layer is formed in the through hole through the deposition process, and during the electroplating process, metal ions are uniformly deposited on the surface of the seed layer, which helps to achieve uniform filling of the through hole. In particular, for silicon through vias with a high aspect ratio, the seed layer can guide the metal ions to grow uniformly throughout the through hole, thereby improving the reliability of the electrical connection.

[0082] In one embodiment, the pads partially or completely cover the adjacent spacing areas on the silicon substrate, and the spacing areas may be scribe lane areas on the wafer. Through holes may be provided in the scribe lane areas covered by the pads, thereby achieving parallel connection of corresponding capacitors on the upper and lower surfaces of a single wafer and parallel connection of corresponding capacitors between different wafers without affecting the existing structure of the capacitors.

[0083] Fig.11 is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Fig.11As shown, the electronic device may include: a processor 1110, a communication interface 1120, a memory 1130 and a communication bus 1140, wherein the processor 1110, the communication interface 1120, and the memory 1130 communicate with each other through the communication bus 1140. The processor 1110 may call the logic instructions in the memory 1130 to execute a packaging method for a multi-layer silicon capacitor stack device, the method comprising: making a symmetrically arranged first silicon capacitor and a second silicon capacitor, a first pad and a third pad, a second pad and a fourth pad on the upper surface and the lower surface of the silicon substrate, respectively; making a first through hole between the first pad and the third pad symmetrically arranged to each other, making a second through hole between the second pad and the fourth pad symmetrically arranged to each other in a direction perpendicular to the surface of the silicon substrate, and filling the first through hole and the second through hole with metal; and electrically connecting the first pad of one of the multiple wafers to the third pad of another of the multiple wafers through a wafer interconnection process, and electrically connecting the second pad of the one of the multiple wafers to the fourth pad of the other of the multiple wafers.

[0084] In addition, the logic instructions in the above-mentioned memory 1130 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0085] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-layer silicon capacitor stack device, characterized in that: include: A plurality of wafers, each of the plurality of wafers comprising: Silicon substrate; A first silicon capacitor and a second silicon capacitor, wherein the first silicon capacitor and the second silicon capacitor are symmetrically arranged on upper and lower sides of the silicon substrate respectively; A first pad and a third pad, wherein the first pad and the third pad are symmetrically arranged on upper and lower sides of the silicon substrate, respectively, and the first pad is electrically connected to the first electrode of the first silicon capacitor, and the third pad is electrically connected to the first electrode of the second silicon capacitor; A second pad and a fourth pad, wherein the second pad and the fourth pad are symmetrically arranged on upper and lower sides of the silicon substrate, respectively, and the second pad is electrically connected to the second electrode of the first silicon capacitor, and the fourth pad is electrically connected to the second electrode of the second silicon capacitor; a first through hole, arranged between the first pad and the third pad in a direction perpendicular to the surface of the silicon substrate and filled with metal; a second through hole, arranged between the second pad and the fourth pad in a direction perpendicular to the surface of the silicon substrate and filled with metal; Among them, the first pad of one of the multiple wafers is electrically connected to the third pad of another one of the multiple wafers through a wafer interconnection structure, and the second pad of the one of the multiple wafers is electrically connected to the fourth pad of the other one of the multiple wafers through the wafer interconnection structure, so that the first silicon capacitor electrically connected to the first pad and the second pad of the one of the multiple wafers and the second silicon capacitor electrically connected to the third pad and the fourth pad of the other one of the multiple wafers are connected in parallel.

2. The multi-layer silicon capacitor stack device according to claim 1, characterized in that: The wafer interconnection structure includes a wafer bonding structure, which includes a bonding structure formed by applying anisotropic conductive adhesive between the first pad and the second pad of the one of the multiple wafers and the third pad and the fourth pad of the other of the multiple wafers and performing hot pressing.

3. The multi-layer silicon capacitor stack device according to claim 1 or 2, characterized in that: The metal is any one or more of titanium, tungsten, copper, gold, chromium, nickel, and titanium nitride.

4. The multi-layer silicon capacitor stack device according to claim 3, characterized in that: The metal is filled in the first through hole and the second through hole by any one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and electroplating filling.

5. The multi-layer silicon capacitor stack device according to claim 1, characterized in that: The first pad, the second pad, the third pad and the fourth pad cover the scribe line area adjacent thereto on the wafer.

6. A packaging method for a multi-layer silicon capacitor stack device, characterized in that: include: A first silicon capacitor and a second silicon capacitor are symmetrically formed on the upper surface and the lower surface of the silicon substrate respectively; In a direction perpendicular to the surface of the silicon substrate, a first through hole and a second through hole are respectively formed at two ends of the first silicon capacitor; A first pad and a third pad, as well as a second pad and a fourth pad are symmetrically formed on the upper surface and the lower surface of the silicon substrate, respectively, and the first through hole and the second through hole are filled with metal, wherein the first pad covers the first through hole and is electrically connected to the first electrode of the first silicon capacitor, the second pad covers the second through hole and is electrically connected to the second electrode of the first silicon capacitor, the third pad covers the first through hole and is electrically connected to the first electrode of the second silicon capacitor, and the fourth pad covers the second through hole and is electrically connected to the second electrode of the second silicon capacitor; and Through a wafer interconnection process, a first pad of one of the multiple wafers is electrically connected to a third pad of another of the multiple wafers, and a second pad of the one of the multiple wafers is electrically connected to a fourth pad of the other of the multiple wafers, so that the first silicon capacitor electrically connected to the first pad and the second pad of the one of the multiple wafers and the second silicon capacitor electrically connected to the third pad and the fourth pad of the other of the multiple wafers are connected in parallel.

7. The packaging method according to claim 6, characterized in that: The wafer interconnection process includes wafer bonding, and the wafer bonding includes applying anisotropic conductive adhesive between the first pad and the second pad of the one of the multiple wafers and the third pad and the fourth pad of the other of the multiple wafers, respectively, and performing hot pressing.

8. The packaging method according to claim 6 or 7, characterized in that: The metal is any one or more of titanium, tungsten, copper, gold, chromium, nickel, and titanium nitride.

9. The packaging method according to claim 8, characterized in that: The metal is filled in the first through hole and the second through hole by any one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and electroplating filling.

10. The packaging method according to claim 6, characterized in that: The first pad, the second pad, the third pad and the fourth pad cover the scribe line area adjacent thereto on the wafer.

Images