System and method for multi-stage pulsing in RF plasma tool

Abstract

Systems and methods of multi-stage pulsing are described. The systems and methods include generating four or more states. During each of the four or more states, a radio frequency (RF) generator generates an RF signal. The RF signal has four or more power levels, and each of the four or more power levels corresponds to the four or more states. The multi-stage pulses facilitate finer control in processing the substrate.

Description

This application is a divisional application of application number 202080046995.9, application date April 24, 2020, and invention name “System and method for multi-level pulses in RF plasma tools”. Technical Field

[0001] Embodiments of the present invention relate to systems and methods for multi-level pulsing in radio frequency (RF) plasma tools. Background Art

[0002] The background description provided here is for the purpose of generally presenting the context of the present disclosure. The work of the presently designated inventors is neither explicitly nor implicitly admitted to be prior art against the present disclosure to the extent that it is described in this background section and in aspects of the specification that were not determined to be prior art at the time the application was filed.

[0003] In a plasma tool, one or more radio frequency (RF) generators are coupled to an impedance matching circuit. The impedance matching circuit is coupled to a plasma chamber. RF signals are supplied from the RF generators to the impedance matching circuits. The impedance matching circuits output RF signals upon receiving these RF signals. The RF signals are supplied from the impedance matching circuits to the plasma chamber for processing wafers in the plasma chamber. However, the wafers are not processed to the desired level of detail.

[0004] It is against this background that the embodiments described in this disclosure are presented. Summary of the invention

[0005] Embodiments of the present disclosure provide apparatus, methods, and computer programs for multi-stage pulses in radio frequency (RF) plasma tools. It should be understood that embodiments herein can be implemented in a variety of ways, such as processes, apparatus, systems, parts of hardware, or methods on computer-readable media. Several embodiments are described below.

[0006] In the following description, several embodiments of multi-level pulses are provided. And, several benefits associated with multi-level pulses are provided. Two or more of the embodiments described herein can be combined to operate with each other, or each of the embodiments described herein can operate independently of each other to provide specific embodiments associated with multi-level pulses.

[0007] An RF generator that facilitates multi-state pulsing is described. The RF generator generates an RF signal having four or more power levels and provides the RF signal to an impedance matching circuit coupled to an electrode of a plasma chamber. The RF signal achieves multi-state pulsing during a clock cycle. For example, during a clock cycle, the RF signal transitions from a first power level to a second power level, further transitions from the second power level to a third power level, and transitions from the third power level to a fourth power level. At the end of the clock cycle, the RF signal transitions from the fourth power level back to the first power level. The multi-state pulsing is repeated periodically for multiple clock cycles.

[0008] Each of the first, second, third, and fourth power levels is a different power level. For example, one or more power values ​​of the first power level are exclusive or different from one or more power values ​​of the second power level, different from one or more power values ​​of the third power level, and different from one or more power values ​​of the fourth power level. Also, one or more power values ​​of the second power level are different from one or more power values ​​of the third power level, and different from one or more power values ​​of the fourth power level. One or more power values ​​of the third power level are different from one or more power values ​​of the fourth power level.

[0009] The multi-state pulse is not limited to four power levels. For example, a power level less than four is generated. For example, two or three power levels are generated by the RF generator. For another example, a power level greater than four (e.g., five, six, or seven) is generated by the RF generator.

[0010] The multi-state pulse is performed to achieve a balance between different phases of a processing operation, such as a balance between a deposition phase during an etching operation and an etching phase during the etching operation. For example, two lower power levels of the multi-state pulse are applied to perform the deposition phase, and two higher power levels of the multi-state pulse are applied to perform the etching phase. The two lower power levels have lower power than the two higher power levels. For example, the etching operation is a conductor etching performed in an inductively coupled plasma (ICP) chamber. The RF generator is coupled to an electrode of the ICP plasma chamber, such as a transformer coupled plasma (TCP) electrode or a bias electrode, via an impedance matching circuit.

[0011] In one embodiment, a pulse train calibration method for reducing line power loss is described. The pulse train calibration method includes simulating a multi-state power pulse train to be generated, applying the train to a known 50 ohm load, and measuring the voltage or power of the multi-state power pulse train. For example, the voltage or power is measured for each state of the multi-state power pulse train. The power of each state of the power pulse train can be changed to account for line losses based on the measured voltage or power, or the measured complex voltage and current. Examples of lines include a radio frequency (RF) cable coupling the output of an RF generator to the input of a matching section, or a combination of an RF cable and an RF transmission line coupling the output of the matching section to an electrode of a plasma chamber.

[0012] In one embodiment, a voltage pulse flattening method for reducing line power loss is described. The voltage pulse flattening method includes measuring or determining the pulse shape under a known load, and compensating the power to obtain a square RF pulse response. The pulse shape is measured by using a voltage or power or complex voltage and current probe. This is voltage control within the pulse. The pulse is divided into multiple sub-pulses. For each sub-pulse, voltage or power control is performed. For example, for the portion of the pulse where the voltage or power is too low, the power is changed to achieve a square flat pulse. The voltage pulse flattening method is performed to address power loss in the line.

[0013] In one embodiment, a duty cycle calibration method for reducing line power loss is described. The duty cycle calibration method includes measuring the duty cycle and adjusting the duration of the duty cycle for each state in a multi-state pulse to account for line power loss.

[0014] In the case of multi-level pulses (eg, four or a higher number of power levels), it is sometimes difficult for the matching section to reduce the reflected power.

[0015] In one embodiment, a transformer coupled capacitor tuned (TCCT) matching section is provided to reduce reflected power during multi-state pulses. The TCCT matching section is used with a source RF generator and is modified for multi-level pulses, such as fourth-order or higher-order pulses. The TCCT matching section is provided with timing information about the multi-level pulses so that it can be tuned to the multi-level pulses.

[0016] In one embodiment, a state matching section tuning method is described. The state tuning method includes tuning the TCCT matching section during one state, and performing frequency tuning (eg, tuning the RF generator) during the other 3, 4, or 5 remaining states to reduce reflected power.

[0017] In one embodiment, instead of the source TCCT matching section or the bias matching section, a solid-state matching device is used so that it can tune to the multi-state pulse faster to reduce the reflected power. The solid-state matching device is made from transistors, or semiconductor diodes, or a combination thereof.

[0018] In the case of multi-level pulses, it is difficult for the matching section to keep up with the multi-level pulses to minimize the reflected power.

[0019] In one embodiment, a matching section tuning method with a fixed frequency is described. In the case of four states, the matching section is tuned in the first state and maintains a fixed frequency of the RF generator in the other three states. The frequency is determined to minimize the sum of the products of the weights of the four states and the reflected power. For example, the frequency is such that C1P1+C2P2+C3P3+C4P4 is minimum for states 1 to 4, where C1 to C4 are weights, and P1 to P4 are reflected powers during each state. The weights C1 to C4 can be percentages of the duty cycle of each state. Instead of the reflected power, the power reflection coefficient can be minimized.

[0020] When a transformer coupled plasma (TCP) electrode (eg, one or more TCP coils) and a bias electrode are pulsed to have multiple states (eg, four or more power levels), it is desirable to achieve uniformity in process rates, such as etch rate or deposition rate.

[0021] In one embodiment, a clock synchronization method between TCP and bias electrode is provided. In the clock synchronization method, a high-resolution clock for multiple states is provided. The high-resolution clock supplies a digital pulse signal with multiple states (e.g., four or more states) to an RF generator that provides power to the TCP electrode and the bias electrode. The synchronization promotes the realization of uniformity.

[0022] In one embodiment, an Ethernet control automation technology (EtherCAT) synchronization method and system are provided to achieve uniformity. EtherCAT cables are used to synchronize different devices (e.g., TCPRF generators, bias RF generators, and matching sections). EtherCAT cables are used to transmit communication pulse trains to communicate with different devices. For example, a communication pulse train has a start time and a stop time. The start time is the start of a series of pulses, and the stop time is the time when the series stops. The start and stop times are repeated. The pulse train may be embedded with information about multiple states for different devices. This information will include the start and stop times of each state of each device. In addition, using EtherCAT cables for synchronization will eliminate the need to provide TTL signals to different devices via multiple synchronization cables to synchronize different devices. Each synchronization cable carries a TTL signal. No synchronization cable is needed. An example of an EtherCAT cable is an Ethernet cable.

[0023] Also, it is desirable to control process uniformity in a multi-state pulse (eg, four or more states), and achieve process rate or etch depth.

[0024] In one embodiment, a synchronization master (e.g., a pulse master) is provided to control processing uniformity and achieve processing rate. For example, the pulse master includes an analog-to-digital voltage control interface (ADVCI) to synchronize the TCP and bias RF generators. For example, the ADVCI can generate a digital pulse signal or TTL signal with two states to provide to the TCP RF generator, and can generate another digital pulse signal or another TTL signal with four states to provide to the bias RF generator. These two states and four states are generated within one clock cycle of the clock signal. For another example, the ADVCI can generate a digital pulse signal or TTL signal with four states to provide to the TCP RF generator, and can generate a digital pulse signal or TTL signal with four states to provide to the bias RF generator. The four states are generated during the clock cycle of the clock signal.

[0025] In one embodiment, a pulse master is used with endpoint detection to control process uniformity and achieve process rate. The pulse master is used to synchronize optical emission spectroscopy (OES) with Lam's spectroscopic reflectometry in the case of multi-state (e.g., multi-stage) pulses. Endpoint or process point detection is performed using OES and Lam's spectroscopic reflectometry. Lam spectroscopic reflectometer (LSR) or OES measures the intensity of light reflected from the wafer.

[0026] In one embodiment, an on-off time modification method with selective synchronization between a source RF generator and a bias RF generator is provided. The on-off time modification method includes changing (e.g., delaying or advancing) the on time and off time of RF power in each state to change 2 plasma impedance states to 4 plasma impedance states, or to change four plasma impedance states to eight plasma impedance states. The on and off times can be adjusted or changed within each state to achieve four plasma impedance states from 2 plasma impedance states. For example, the on time of applying RF power is slightly delayed in state S1, and / or the off time is achieved slightly earlier in state S1. In the case where the on and off times of RF power of both TCP and bias RF generator are changed, both TCP and bias RF generator are synchronized with each other. For example, when multi-state power having four states or eight states is generated by the source RF generator, the bias RF generator operates in a continuous wave (CW) mode. As another example, when a multi-state power having four states or eight states is generated by the bias RF generator, the source RF generator operates in a continuous wave (CW) mode. And, for example, different processes are performed in each state. For example, deposition on a wafer may occur in one state, and etching of the wafer may occur in another state.

[0027] The process is controlled to minimize defects in the wafer due to spikes at transition edges and to protect the RF generator when the RF generator is operated in four or more states.

[0028] In one embodiment, a pulse shaping method is provided to achieve process control. For example, the pulse shaping method includes shaping the power rising edge and / or the power falling edge of the RF signal generated by the RF generator. And for another example, the pulse shaping method includes shaping the frequency rising edge and / or the frequency falling edge of the RF signal. For another example, the pulse shaping method includes shaping the power rising edge and / or the falling edge of the RF signal, and shaping the frequency rising edge and / or the falling edge.

[0029] It is further desirable to control the process to achieve uniformity in processing the substrate.

[0030] In one embodiment, to achieve uniformity, a system with multiple power controllers and multiple automatic frequency tuners (AFTs) is provided.

[0031] In one embodiment, a method of frequency tuning trajectory at microsecond level to achieve uniformity is described. In this method, each RF signal is frequency tuned at microsecond level to reduce reflected power for each recipe, thereby generating a trajectory of the RF signal, and the trajectory is applied during the application of the recipe to process the wafer. The trajectory is generated to learn the trajectory, which is then applied during the processing of the wafer.

[0032] In one embodiment, a closed state setting method is described. In the closed state setting method, the closed state is set at any point in the multi-level pulse sequence. The closed state can be at any point in the pulse sequence. In the pulse sequence, the closed state does not need to be achieved before repeating the first state.

[0033] Some advantages of the systems and methods described herein include using a two-state RF generator to generate a multi-state plasma impedance, such as four or more plasma impedance states. The multi-state plasma impedance is generated by generating multiple combinations of parameter levels of the source RF generator and the bias RF generator. The multi-state plasma impedance is used to achieve uniformity in processing substrates and also for finer control during processing of substrates.

[0034] Also, some advantages of the multi-state pulse systems and methods described herein include increasing the level of control in processing a substrate. By implementing four or more states with variable levels during processing of a substrate, finer control in processing a substrate is achieved. Furthermore, by controlling the state transitions for transitions between two of the variable levels, additional finer control in processing a substrate is achieved to achieve a predetermined processing result.

[0035] Advantages of the systems and methods described herein using EtherCAT cables include enabling rapid transmission of information between various components of a plasma tool or plasma system. Data such as parameter levels measured during four or more states are rapidly transmitted from a processor to an EtherCAT frame. Also, data such as parameter levels used to generate four or more states are rapidly transmitted from an EtherCAT frame to a processor. This rapid transmission allows for faster data transmission when multi-state pulses are used, thereby allowing for control during processing of a substrate.

[0036] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The embodiments are understood by referring to the following description in conjunction with the accompanying drawings.

[0038] Figure 1 is a diagram of an embodiment of a plasma system for illustrating the use of a two-state radio frequency (RF) generator to generate a multi-state plasma impedance.

[0039] Figure 2 is a diagram of an embodiment of the system, which is used to illustrate the details of the RF generator.

[0040] Figure 3A FIG. 1 is a diagram for explaining an embodiment of a synchronization signal.

[0041] Figure 3B is an embodiment of a graph illustrating the relationship between parameters of a source RF signal and time.

[0042] Figure 3C is an embodiment of a graph illustrating the relationship between parameters of a bias RF signal and time.

[0043] Figure 4A for Figure 3A A graphical embodiment of the invention is used to illustrate Figure 3A synchronization signal.

[0044] Figure 4B for Figure 3B A graphical implementation scheme of .

[0045] Figure 4C is an embodiment of a graph for illustrating the relationship between another bias RF signal parameter and time.

[0046] Figure 5A FIG. 1 is a diagram for explaining an embodiment of a synchronization signal.

[0047] Figure 5B is an embodiment of a graph illustrating the relationship between parameters of a source RF signal and time.

[0048] Figure 5C is an embodiment of a graph illustrating the relationship between parameters of a bias RF signal and time.

[0049] Fig. 6A FIG. 1 is a diagram for explaining an embodiment of a synchronization signal.

[0050] Figure 6B is an embodiment of a graph illustrating the relationship between parameters of a source RF signal and time.

[0051] Figure 6C is an embodiment of a graph illustrating the relationship between parameters of a bias RF signal and time.

[0052] Fig.6D is a diagram for explaining an embodiment of an on-off time modification method using selective synchronization between a source RF generator and a bias RF generator.

[0053] Figure 7 is a diagram of an embodiment of a plasma system for illustrating multi-step parameter pulsing.

[0054] Figure 8 is a diagram of an embodiment of a plasma system for illustrating multi-step frequency pulsing.

[0055] Fig. 9 is a diagram of an embodiment of a plasma system for illustrating simultaneous multi-step parameter pulsing and multi-step frequency pulsing.

[0056] Fig. 10A for Figure 3A A graphical embodiment of the invention is used to illustrate Figure 3A synchronization signal.

[0057] Fig. 10B For illustration Fig. 9 A graphical implementation of the relationship between the variable of the RF signal and time.

[0058] Fig. 10C For illustration Fig. 9 A graphical implementation of the relationship between the variable of the RF signal and time.

[0059] Fig. 10D For illustration Fig. 9 An embodiment of a graph showing the relationship between a variable of an RF signal and time t.

[0060] Fig. 10E For illustration Fig. 9 A graphical implementation of the relationship between the variable of the RF signal and time.

[0061] Fig.10F For illustration Fig. 9 A graphical implementation of the relationship between the variable of the RF signal and time.

[0062] Figure 10G For illustration Fig. 9 An embodiment of a graph showing the relationship between a variable of an RF signal and time t.

[0063] Fig. 10H For illustration Fig. 9 A graphical implementation of the relationship between the variable of the RF signal and time.

[0064] Fig.10I For illustration Fig. 9 A graphical implementation of the relationship between the variable of the RF signal and time.

[0065] Fig.10J A diagram of an implementation of a system having multiple power controllers and multiple automatic frequency tuners (AFTs).

[0066] Figure 10Kis a diagram for explaining an implementation of an RF signal having four states S(n-3), S(n-2), S(n-1), and Sn, which is used to illustrate the power level of the RF signal.

[0067] Fig.10L is a diagram for explaining an implementation of another RF signal having four states S(n-3), S(n-2), S(n-1), and Sn, which are used to illustrate the power level of the RF signal.

[0068] Figure 10M is a diagram for illustrating an implementation of yet another RF signal having four states S(n-3), S(n-2), S(n-1), and Sn, which is used to illustrate the power level of the RF signal.

[0069] Fig.10N is a diagram for explaining an implementation of another RF signal having four states S(n-3), S(n-2), S(n-1), and Sn, which are used to illustrate the power level of the RF signal.

[0070] Fig.10O is a diagram for illustrating an implementation of yet another RF signal having four states S(n-3), S(n-2), S(n-1), and Sn, which is used to illustrate the power level of the RF signal.

[0071] Figure 10P is a diagram of an implementation of a method for illustrating achieving a power level of zero during one or more of states S(nA) to Sn, where (nA) is an integer less than n.

[0072] Fig.11A is a diagram of an embodiment of a plasma system for illustrating control of the slope of a state transition.

[0073] Fig. 11B for Fig.11A A diagram of an implementation scheme of a system is used to illustrate the functionality of the system.

[0074] Fig. 12A For illustration Figure 3A A graphical implementation of a synchronization signal.

[0075] Fig. 12B For illustration Fig.11A and 11B A graphical implementation of the relationship between the variable of the RF signal and time.

[0076] Fig. 12C For illustration Fig.11A and 11B A graphical implementation of the relationship between the variable of the RF signal and time.

[0077] Fig.12D For illustration Fig.11A and 11B A diagram of an embodiment of a graph of different transition types of a variable of an RF signal versus time.

[0078] Fig.12E For illustration Fig.11A and 11B A diagram of an embodiment of a graph of different transition types of a variable of an RF signal versus time.

[0079] Fig.12F A diagram of an implementation scheme of a pulse shaping method.

[0080] Figure 12G A diagram of another embodiment of a pulse shaping method.

[0081] Fig.12H A diagram of yet another implementation of a pulse shaping method.

[0082] Fig.12I A diagram of yet another implementation of a pulse shaping method.

[0083] Fig.12J A diagram of another embodiment of a pulse shaping method.

[0084] Figure 12K A diagram of yet another implementation of a pulse shaping method.

[0085] Figure 12L A diagram of another embodiment of a pulse shaping method.

[0086] Fig.13A is a diagram of an embodiment of a system for illustrating the transmission of information between various components of a plasma system via one or more EtherCAT cables.

[0087] Fig. 13B is a diagram of an embodiment of a system for illustrating the transmission of information between various components of a plasma system via one or more EtherCAT cables.

[0088] Fig.14 A diagram of an implementation scheme for an EtherCAT frame.

[0089] Fig.15A is a diagram of an embodiment of a system for illustrating the transmission of information between various components of a plasma system via one or more EtherCAT cables.

[0090] Fig. 15Bis a diagram of an embodiment of a system for illustrating the transmission of information between various components of a plasma system via one or more EtherCAT cables.

[0091] Fig.16 A diagram of an implementation scheme for an EtherCAT frame.

[0092] Fig.17 is a diagram for illustrating an embodiment of a system of an RF generator coupled to an EtherCAT cable.

[0093] Fig.18 For the purpose of illustrating coupling to Fig.17 Figure 2 is a diagram of a system implementation of an RF generator and a matching section coupled to an EtherCAT cable.

[0094] Fig.19A An embodiment of an EtherCAT synchronization system is described in which an EtherCAT cable is coupled between two components of a plasma system.

[0095] Fig.19B is a diagram of an implementation of an EtherCAT synchronization system in which an EtherCAT cable is coupled between a source radio frequency (RF) generator and a bias RF generator, and another EtherCAT cable is coupled between the source RF generator and a source match.

[0096] Fig.19C An embodiment of an EtherCAT synchronization system is described, wherein components of a plasma system are coupled in a daisy chain.

[0097] Fig.19D An implementation of an EtherCAT synchronization system is described in which components of a plasma system are coupled in a daisy chain fashion.

[0098] Fig. 20 A diagram of an embodiment of a system for illustrating a pulse train calibration method.

[0099] Fig.21 is a diagram of an embodiment of a system for explaining a voltage pulse smoothing method.

[0100] Fig. 22 is a diagram of an embodiment of a system for illustrating a duty cycle calibration method.

[0101] Fig.23 A system is shown for illustrating the use of a transformer coupled capacitor tuned (TCCT) matching section.

[0102] Fig.24A A diagram for explaining a system implementation of a tuning method of a state matching unit.

[0103] Fig. 24B A diagram of a system for explaining another embodiment of a tuning method of a state matching section.

[0104] Fig.25A is a diagram for explaining an embodiment of a system of a source solid state matching portion.

[0105] Fig.25B A diagram for explaining an embodiment of a system using a biased solid-state matching section instead of a biased matching section.

[0106] Fig.26A A diagram of an embodiment of a system for explaining a method for tuning a matching section at a fixed frequency.

[0107] Fig.26B A diagram of an embodiment of a system for explaining a method for tuning a matching section at a fixed frequency.

[0108] Fig. 27 is a diagram of an embodiment of a system for illustrating a clock synchronization method between a transformer coupled plasma (TCP) and a bias electrode.

[0109] Fig.28A An embodiment of a system for illustrating synchronization of masters.

[0110] Fig.28B An embodiment of a system for illustrating synchronization of masters.

[0111] Fig.29 A diagram of an embodiment of a system for illustrating the use of a multi-state control unit with endpoint detection.

[0112] Fig.30 A system including a power controller, an automatic frequency tuner, a processor, and a power supply is shown for illustrating a method of trajectory frequency tuning or power tuning at microsecond levels. DETAILED DESCRIPTION

[0113] The following embodiments describe multi-stage pulse systems and methods in radio frequency (RF) plasma tools. It will be apparent that the embodiments herein can be implemented without some or all of these specific details. In other cases, well-known processing operations are not described in detail to avoid unnecessarily obscuring the embodiments herein.

[0114] In the following description, several multi-level pulse embodiments are provided. Two or more of the embodiments described herein may be combined to interoperate, or each of the embodiments described herein may operate independently of each other to provide specific embodiments associated with multi-level pulses.

[0115] An RF generator that facilitates multi-state pulsing is described herein. The RF generator generates an RF signal having four or more power levels and provides the RF signal to an impedance matching circuit coupled to an electrode of a plasma chamber. The RF signal implements multi-state pulsing during a clock cycle. For example, during a single clock cycle, the RF signal transitions from a first power level to a second power level, further transitions from the second power level to a third power level, and transitions from the third power level to a fourth power level. The multi-state pulsing is repeated periodically for multiple clock cycles.

[0116] Each of the first, second, third, and fourth power levels is a different power level. For example, one or more power values ​​of the first power level are exclusive or different from one or more power values ​​of the second power level, different from one or more power values ​​of the third power level, and different from one or more power values ​​of the fourth power level. Also, one or more power values ​​of the second power level are different from one or more power values ​​of the third power level, and different from one or more power values ​​of the fourth power level. One or more power values ​​of the third power level are different from one or more power values ​​of the fourth power level. For example, the difference between the highest power value of the power level of the RF signal and the lowest power value of the power level of the RF signal is less than a predetermined percentage. For example, the highest power value of the first power level is at most 20% greater than the lowest power value of the first power level. Similarly, the highest power value of the second power level is at most 20% greater than the lowest power value of the second power level.

[0117] In one embodiment, the same power level is applied during two or more states. For example, one power level is applied during the first state and the second state, a different power level is applied during the third state, and another different power level is applied during the fourth state.

[0118] The multi-state pulse is performed to achieve a balance between different phases during a processing operation, such as a deposition operation, an etching operation, a cleaning operation, a sputtering operation, etc. For example, a first power level and a second power level of the RF signal are used to perform a deposition phase during an etching operation, and a third power level and a fourth power level of the RF signal are used to perform an etching phase during an etching operation. As another example, during each state of the multi-state pulse, a different phase is performed. As another example, a phase is performed during one or more states of the multi-state pulse, and another phase is performed during one or more of the remaining states of the multi-state pulse. For example, the etching operation is a conductor etching performed in an inductively coupled plasma (ICP) chamber. The RF generator is coupled to an electrode of the ICP plasma chamber, such as a transformer coupled plasma (TCP) electrode or a bias electrode, via an impedance matching circuit.

[0119] The RF generator receives a digital pulse signal indicating a duty cycle (e.g., duration) of each of the power levels of the RF signal to be generated by the RF generator. The digital pulse signal indicates a time period during which each of the power levels will be supplied from the RF generator. The digital pulse signal has a plurality of states, such as four or more states. For example, the digital pulse signal has a first logic level during a first state, a second logic level during a second state, a third logic level during a third state, and a fourth logic level during a fourth state. Each logic level is defined by a voltage level of a voltage signal generated by a digital pulse source. The digital pulse source is coupled to the RF generator to provide the digital pulse signal to the RF generator. In addition, the RF generator receives a clock signal having a plurality of clock cycles to facilitate repetition of multi-level pulses. The clock signal is generated by a digital pulse source or a frequency source coupled to the RF generator to provide the clock signal to the RF generator.

[0120] It should be noted that the description of four power levels above is an example. In one embodiment, the RF generator generates an additional number of power levels during a clock cycle, such as five, or six, or seven, or eight power levels, and these power levels are repeated for multiple clock cycles. With an increased number of power levels, finer control during substrate processing within the plasma chamber is achieved. For example, with an increased number of power levels during a clock cycle, optimized etching of the substrate or optimized deposition of material on the substrate or a combination thereof is achieved. In one embodiment, less than four power levels are generated, such as three power levels or two power levels.

[0121] And, the plasma chamber can be an ICP chamber. For example, the RF generator is coupled to an electrode of the plasma chamber, such as a TCP electrode or a bias electrode, via an impedance matching circuit. In order to display multiple states such as multiple stages, the RF signal is supplied to the TCP electrode via a matching section, and a continuous wave (CW) RF signal or a dual-state RF signal is supplied to the bias electrode via another matching section. For another example, the multi-stage RF signal is supplied to the bias electrode via a matching section, and the CW RF signal or the dual-state RF signal is supplied to the TCP electrode via another matching section. For another example, the multi-stage RF signal is supplied to the bias electrode via a matching section, and the multi-stage RF signal is supplied to the TCP electrode via another matching section. The bias electrode is a lower electrode located in a substrate support or chuck of the plasma chamber.

[0122] A two-state RF generator for generating four or more plasma impedance states.

[0123] Figure 11 is a diagram of an embodiment of a plasma system 100 for illustrating the generation of a plasma impedance having four or more states using a two-state RF generator, such as a source RF generator 102 or a bias RF generator 104. The system 100 includes a host computer 106, a source RF generator 102, a bias RF generator 104, a source match 108, a bias match 110, and a plasma chamber 112.

[0124] When used herein, examples of a host computer include a desktop computer, a tablet computer, a smartphone, and a laptop computer. When used herein, examples of an RF generator include an RF generator having an operating frequency of 400 kilohertz (kHz), or an operating frequency of 2 megahertz (MHz), or an operating frequency of 27 MHz, or an operating frequency of 60 MHz. For example, the bias RF generator 104 has an operating frequency of 2 MHz, and the source RF generator 102 has an operating frequency of 60 MHz, or vice versa. For another example, the bias RF generator 104 has an operating frequency of 400 kHz, and the source RF generator 102 has an operating frequency of 60 MHz, or vice versa.

[0125] As used herein, examples of matching sections include networks of components such as inductors, capacitors, and resistors coupled to one another. For example, the matching section includes a plurality of serial circuits and a plurality of shunt circuits, and each of the serial circuits includes a capacitor or an inductor or a series combination thereof, and each of the shunt circuits includes a capacitor or an inductor or a series combination thereof. It should be noted that in one embodiment, the terms matching section, impedance matching circuit, and impedance matching network are used interchangeably herein. Examples of the plasma chamber 112 include a transformer coupled plasma (TCP) plasma chamber and an inductively coupled plasma (ICP) plasma chamber.

[0126] The host computer 106 includes a processor 118 and a memory device 120 and the processor 118 is coupled to the memory device 120. As used herein, examples of a processor include a central processing unit (CPU), a microcontroller, a controller, a microprocessor, an application specific integrated circuit (ASIC), and a programmable logic device (PLD). As used herein, examples of a memory device include a read-only memory, a random access memory, or a combination thereof. For example, the memory device is a flash memory or a redundant array of independent disks.

[0127] The plasma chamber 112 includes a dielectric window 124, above which is a TCP coil 126. For example, the dielectric window 124 forms a top surface of the plasma chamber 112. The TCP coil 126 is an example of an electrode of the plasma chamber 112. The plasma chamber 112 also includes a substrate support 128, such as a chuck, on which a substrate S is placed for processing. The substrate support 128 is an example of an electrode of the plasma chamber 112. The substrate S is placed on the top surface of the substrate support 128. The substrate support 128 has a lower electrode embedded therein. For example, the lower electrode is made of metal, such as aluminum or an aluminum alloy.

[0128] The processor 118 is coupled to the source RF generator 102 via a transmission cable system 130. Similarly, the processor 118 is coupled to the bias RF generator via a transmission cable system 134. When used herein, the transmission cable system includes one or more transmission cables. For example, when used herein, the transmission cable includes a serial transmission cable that is used for serial transmission of data between the processor 118 and the RFG coupled to the processor 118. In the serial transmission of data, one bit is transmitted at a time. Another example of a transmission cable includes a parallel transmission cable that is used for parallel transmission of data between the processor 118 and the RFG coupled to the processor 118. In the parallel transmission of data, multiple bits are transmitted simultaneously. Yet another example of a transmission cable includes a universal serial bus (USB) cable.

[0129] The output 154 of the source RF generator 102 is coupled to the input 156 of the source matching section 108 via the RF cable 138, and the output 158 ​​of the source matching section 108 is coupled to the TCP coil 126 via the RF transmission line 140. Similarly, the output 160 of the bias RF generator 104 is coupled to the input 162 of the bias matching section via the RF cable 142, and the output 164 of the bias matching section 110 is coupled to the substrate support 128 via the RF transmission line 144. An example of an RF transmission line includes an RF rod. The RF rod is surrounded by an insulator material, which is further surrounded by an RF sheath of the RF transmission line. The insulator material of the RF transmission line is between the RF rod and the RF sheath. Another example of an RF transmission line includes an RF sheath surrounding the insulator material and the RF rod and one or more RF straps coupled to the RF rod. Yet another example of an RF transmission line includes an RF sheath surrounding the insulator material and the RF rod, one or more RF straps, and an RF cylinder coupled to the RF sheath via at least one of the one or more RF straps.

[0130] The processor 118 includes a clock source that generates and transmits a synchronization signal 146, such as a digital clock signal or a digital pulse signal, to the source RF generator 102 via the transmission cable system 130. An example of a clock source includes a phase-locked loop circuit that generates a synchronization signal with a duty cycle of 50%. Another example of a clock source includes a phase-locked loop circuit coupled to a duty cycle control circuit at its output to change the duty cycle of the synchronization signal from 50% to greater than or less than 50% (e.g., 80% or 10%) to output a synchronization signal with a changed duty cycle. The clock source of the processor 118 also transmits the synchronization signal 146 to the bias RF generator 104 via the transmission cable system 134.

[0131] In addition, the processor 118 transmits source variables such as the frequency of the RF signal 152 to be generated or parameters of the RF signal 152 to the source RF generator 102 via the transmission cable system 130. When used herein, examples of variables include frequency and parameters. For example, the variable is frequency or power. When used herein, examples of parameters include voltage and power. For example, the parameter is voltage or power. And, the processor 118 transmits bias variables such as the frequency of the RF signal 168 and parameters of the RF signal 168 to the bias RF generator 104 via the transmission cable system 134.

[0132] The source RF generator 102 generates an RF signal 152 when receiving the synchronization signal 146 and the source variables via the transmission cable system 130. The RF signal 152 has source variables such as frequency and power or voltage received by the source RF generator 102 from the processor 118. The RF signal 152 is transmitted from the output terminal 154 of the source RF generator 102 to the input terminal 156 of the source matching section 108 via the RF cable 138. The source matching section 108 receives the RF signal 152 and modifies the impedance of the RF signal 152 so that the impedance of the load coupled to the output terminal 158 of the source matching section 108 matches the impedance of the source coupled to the input terminal 156 of the source matching section 108. The source matching section 108 modifies the impedance of the RF signal 152 to output a modified RF signal 166 at the output terminal 158 of the source matching section 108. The modified RF signal 166 is transmitted from the output terminal 158 to the TCP coil 126 via the RF transmission line 140.

[0133] Similarly, upon receiving the synchronization signal 146 and the bias variable via the transmission cable system 134, the bias RF generator 104 generates an RF signal 168. The RF signal 168 has the bias variable, such as frequency and power or voltage, received by the bias RF generator 104 from the processor 118. The RF signal 168 is transmitted from the output 160 of the bias RF generator 104 to the input 162 of the bias matching section 110 via the RF cable 142. The bias matching section 110 receives the RF signal 168 and modifies the impedance of the RF signal 168 so that the impedance of the load coupled to the output 164 of the bias matching section 110 matches the impedance of the source coupled to the input 162 of the bias matching section 110. The bias matching section 110 modifies the impedance of the RF signal 168 to output the modified RF signal 170 at the output 164 of the bias matching section 110. The modified RF signal 170 is transmitted from the output 164 via the RF rod of the RF transmission line 144 to the lower electrode embedded in the substrate support 128 .

[0134] It should be noted that in one embodiment, the modified RF signal 166 has the same number of parameter levels as the RF signal 152 that caused the modified RF signal 166 to be generated. For example, each of the RF signals 152 and 166 has two parameter levels during one cycle of the synchronization signal 146. And, in one embodiment, each of the RF signal 152 and the modified RF signal 166 transitions from one parameter level to another parameter level at the same time. For example, when the RF signal 152 transitions from one parameter level to another parameter level, the modified RF signal 166 transitions from one parameter level to another parameter level. In one embodiment, the modified RF signal 166 has the same parameter level as the parameter level of the RF signal 152. For example, when the RF signal 152 has a first parameter level, the modified RF signal has the same first parameter level.

[0135] It should be noted that in one embodiment, the modified RF signal 170 has the same number of parameter levels as the RF signal 168 that caused the modified RF signal 170 to be generated. For example, each of the RF signals 168 and 170 has three parameter levels during one cycle of the synchronization signal 146. And, in one embodiment, each of the RF signal 168 and the modified RF signal 170 transitions from one parameter level to another parameter level at the same time. For example, when the RF signal 168 transitions from one parameter level to another parameter level, the modified RF signal 170 transitions from one parameter level to another parameter level. In one embodiment, the modified RF signal 170 has the same parameter level as the parameter level of the RF signal 168. For example, when the RF signal 168 has a first parameter level, the modified RF signal has the same first parameter level.

[0136] When one or more process gases, such as an oxygen-containing gas, a fluorine-containing gas, or a combination thereof, are additionally supplied to the housing or enclosure of the plasma chamber 112 in addition to the modified RF signals 166 and 170, plasma is generated or maintained within the housing or enclosure of the plasma chamber 112. The plasma is used to process the substrate S and has impedance. For example, the plasma is used to deposit a material on the substrate S, or to etch the substrate S, or to sputter the substrate S, or to clean the substrate S, or a combination thereof.

[0137] In one embodiment, instead of TCP coil 126, multiple TCP coils are placed above dielectric window 124. In one embodiment, in addition to TCP coil 126, one or more additional TCP coils are placed on one side of plasma chamber 112.

[0138] Figure 2 2 is a diagram of an embodiment of a system 200, which is used to illustrate the details of the RF generator 202. The system 200 includes the RF generator 202 and the host computer 106. The system 200 also includes a matching section 216 and an RF cable 218. The RF generator 202 is a source RF generator 102 or a bias RF generator 104 ( Figure 1 ). The matching section 216 is the source matching section 108 or the bias matching section 110 ( Figure 1 ) is an example of a RF cable 218. The RF cable 218 is the RF cable 138 or the RF cable 142 ( Figure 1 ) and is coupled to an output 217 of an RF power source 222. The RF generator 202 includes a digital signal processor (DSP) 204, a parameter controller (PRS1) 206, a parameter controller (PRS2) 208, a frequency controller (FC) 210, a driver system 212, and an RF power source 222.

[0139] As used herein, examples of digital signal processors include controllers, microprocessors, and microcontrollers, and these terms are sometimes used interchangeably herein. As used herein, examples of parameter controllers include a combination of a processor and a memory device. The processor of the parameter controller is coupled to the memory device of the parameter controller. Similarly, as used herein, examples of frequency controllers include a combination of a processor and a memory device. The processor of the frequency controller is coupled to the memory device of the frequency controller. As used herein, examples of driver systems include circuits having one or more drivers (e.g., one or more transistors coupled to each other). As used herein, examples of RF power supplies include electronic oscillators that generate periodic oscillating RF signals, such as sine waves.

[0140] Processor 118 is coupled to DSP 204 via transmission cable system 214. Transmission cable system 214 is a transmission cable system 130 or a transmission cable system 134 ( Figure 1). The digital signal processor 204 is coupled to parameter controllers 206 and 208, and to a frequency controller 210. The parameter controllers 206 and 208 are coupled to a driver system 212, which is coupled to an RF power supply 222. Also, the frequency controller 210 is coupled to the driver system 212. The RF power supply 222 is coupled to the matching section 216 via an RF cable 218.

[0141] The processor 118 provides variables such as source variables or bias variables and the synchronization signal 146 to the DSP 204 via the transmission cable system 214. Upon receiving the variables, the DSP 204 provides parameters such as power level or voltage level for the state S1 of the RF signal 220 to the parameter controller 206 to store the parameters for the state S1 in the memory device of the parameter controller 206. For example, a parameter level such as power level or voltage level is an envelope of the RF signal. For example, a parameter level is a unique level of level and a unique level of level that is higher or lower than another parameter level. For another example, the parameter level is one or more zero-to-peak amplitudes, or one or more zero-to-peak magnitudes, or one or more peak-to-peak amplitudes, or one or more peak-to-peak magnitudes of the RF signal. The amplitudes of the parameter levels differ from each other within a predetermined range, such as 0 to 5%, and do not include the amplitude of another or different parameter level. For another example, the parameter level has a maximum value and a minimum value. The maximum value is the largest of all values ​​of the parameter class, and the minimum value is the smallest of all values ​​of the parameter class. When the maximum value of a first parameter class is less than the minimum value of a second parameter class, the first parameter class is lower than the second parameter class, and when the minimum value of the first parameter class is greater than the maximum value of the second parameter class, the first parameter class is higher than the second parameter class.

[0142] And, in response to receiving the variable, the DSP 204 provides a parameter, such as a power level or a voltage level, for state S2 of the RF signal 220 to the parameter controller 208 to store the parameter for state S2 in a memory device of the parameter controller 208. Similarly, upon receiving the variable, the DSP 204 provides a frequency level to the frequency controller 210 to store in a memory device of the frequency controller 210.

[0143] In one embodiment, a level (e.g., a level of one of the variables) comprises one or more values. For example, a power level comprises one or more power values ​​that differ from each other within a predetermined range, or a voltage level comprises one or more voltage values ​​that differ from each other within a preset range. As another example, a variable level of an RF signal is one or more zero-to-peak amplitudes, or one or more zero-to-peak magnitudes, or one or more peak-to-peak amplitudes, or one or more peak-to-peak magnitudes of the RF signal. The amplitudes of the variable levels differ from each other within a predetermined range, such as 0 to 5%, and do not include the amplitude of another or different variable level. As another example, a variable level is a unique horizontal level, and a unique horizontal level that is higher or lower than another variable level.

[0144] In one embodiment, the values ​​of the first variable level are different from the values ​​of the second variable level. For example, the values ​​of the first variable level do not include the values ​​of the second variable level. As another example, the values ​​of the first variable level are different from any of the values ​​of the second variable level.

[0145] When the synchronization signal 146 is received, the DSP 204 identifies a cycle of the synchronization signal 146. For example, the DSP 204 determines that cycle 1 of the synchronization signal 146 starts at a first time and ends at a second time, and cycle 2 of the synchronization signal 146 starts at the second time and ends or stops at a third time. For example, the DSP 204 determines that the logic level of the synchronization signal 146 transitions from 0 to 1 at the start time and transitions from 0 to 1 again at the stop time, and there are no other transitions from 0 to 1 between these transitions at the start and stop times to identify the cycle of the synchronization signal 146. The DSP 204 counts each cycle to determine the number of cycles of the synchronization signal 146.

[0146] Also, when identifying the cycle, during each cycle of the synchronization signal, the DSP 204 transmits a command signal for state S1 to the parameter controller 206. For example, at a time point of transitioning from state S2 or state S0 to state S1, the DSP 204 transmits a command signal for state S1 to the parameter controller 206. The command signal for state S1 transmitted to the parameter controller 206 includes a time period of state S1 during each cycle, during which the parameter controller 206 will provide a parameter level for state S1 to the driver system 212. Upon receiving the command signal for state S1, the parameter controller 206 retrieves the parameter level for state S1 from the memory device of the parameter controller 206 and transmits the parameter level to the driver system 212 for the time period of state S1. For example, at a time point of transitioning from state S2 or state S0 to state S1, the parameter controller 206 transmits the parameter level for state S1 to the driver system 212. After the time period of state S1 , during the cycles of the synchronization signal 146 , the parameter controller 206 does not transmit the parameter level for state S1 to the driver system 212 .

[0147] Similarly, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S2 to the parameter controller 208 during each cycle of the synchronization signal. For example, at a time point of transitioning from state S1 or state S0 to state S2, the DSP 204 transmits a command signal for state S2 to the parameter controller 208. The command signal for state S2 transmitted to the parameter controller 208 includes a time period of state S2 during each cycle, during which the parameter controller 208 will provide a parameter level for state S2 to the drive system 212. Upon receiving the command signal for state S2, the parameter controller 208 retrieves the parameter level for state S2 from a memory device of the parameter controller 208 and transmits the parameter level to the drive system 212 for the time period of state S2. For example, at a time point of transitioning from state S1 or state S0 to state S2, the parameter controller 208 transmits the parameter level for state S2 to the drive system 212. After the time period of state S2 , during the cycles of the synchronization signal 146 , the parameter controller 208 does not transmit the parameter level for state S2 to the driver system 212 .

[0148] Also, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal to the frequency controller 210 during each cycle of the synchronization signal. Upon receiving the command signal, the frequency controller 210 retrieves the frequency level from the memory device of the frequency controller 210 and transmits the frequency level to the driver system 212.

[0149] In response to receiving the parameter level and frequency level for state S1, the driver system 212 generates a drive signal for state S1 for a time period of state S1 and transmits the drive signal to the RF power supply 222. For example, at a time point of transitioning from state S2 or state S0 to state S1, when the parameter level and frequency level for state S1 are received, the driver system 212 generates a drive signal for state S1 for a time period of state S1 and transmits the drive signal to the RF power supply 222. The RF power supply 222 generates state S1 of the RF signal 220 when receiving the drive signal for state S1 from the driver system 212. For example, when receiving the drive signal for state S1 from the driver system 212, the RF power supply 222 causes the RF signal 220 to transition from state S0 or state S2 to state S1. During the time period of state S1, the state S1 of the RF signal has the parameter level and frequency level for state S1.

[0150] Similarly, in response to receiving the parameter level and frequency level for state S2, the driver system 212 generates a drive signal for state S2 for a time period of state S2 and transmits the drive signal to the RF power supply 222. For example, at a time point of transitioning from state S1 or state S0 to state S2, when receiving the parameter level and frequency level for state S2, the driver system 212 generates a drive signal for state S2 for a time period of state S2 and transmits the drive signal to the RF power supply 222. The RF power supply 222 generates state S2 of the RF signal 220 when receiving the drive signal for state S2 from the driver system 212. For example, when receiving the drive signal for state S2 from the driver system 212, the RF power supply 222 causes the RF signal 220 to transition from state S0 or state S1 to state S2. During the time period of state S2, the state S2 of the RF signal has the parameter level and frequency level for state S2.

[0151] Also, in one embodiment, during each cycle of the synchronization signal 146, there is a time period when the RF signal 220 has a parameter level of zero. The RF signal 220 has a parameter level of zero during a no-state (NS), such as state S0. For example, the parameter level of the RF signal described herein is zero when the parameter level is close to zero or substantially zero. For example, the parameter level is zero when the parameter level is less than a predetermined value. An example of a predetermined value for the parameter level is 1 watt. Another example of a predetermined value for the parameter level is 0.25 watts. Yet another example of a predetermined value for the parameter level is 0.5 watts. When the synchronization signal 146 is received, during each cycle of the synchronization signal 146, the DSP 204 does not transmit instruction signals for states S1 and S2 to the parameter controllers 206 and 208 during the time period of the no-state.

[0152] During the time period of the idle state in which the command signals for the states S1 and S2 are not received, the parameter controllers 206 and 208 do not transmit or stop transmitting the parameter levels for the states S1 and S2 to the driver system 212. For example, after the time period of the state S1, the parameter controller 206 does not transmit the parameter level for the state S1 to the driver system 212. For another example, after the time period of the state S2, the parameter controller 208 does not transmit the parameter level for the state S2 to the driver system 212.

[0153] When the parameter levels of states S1 and S2 are not received, the driver system 212 does not transmit a drive signal to the RF power supply 222. When the drive signal is not received during the time period of the null state, the RF power supply generates the RF signal 220 having a parameter level of zero during the null state. For example, when the drive signal is not received, the RF power supply 222 transitions the RF signal 220 from state S1 or state S2 to the null state S0.

[0154] In one embodiment, instead of parameter controller 206, parameter controller 208, and frequency controller 210, one or more controllers (e.g., one or more processors) are used to perform the functions described herein as being performed by parameter controllers 206 and 208, and frequency controller 210. Each of the one or more controllers includes a processor and a memory device, and the processor is coupled to the memory device.

[0155] In one implementation, instead of DSP 204, parameter controller 206, parameter controller 208, and frequency controller 210, one or more controllers (e.g., one or more processors) are used to perform the functions described herein as being performed by DSP 204, parameter controllers 206 and 208, and frequency controller 210. Each of the one or more controllers includes a processor and a memory device, and the processor is coupled to the memory device.

[0156] Figure 3A 3 is an embodiment of a graph 300 for illustrating a synchronization signal 302. Graph 300 depicts the logic level of synchronization signal 302 relative to time t. Synchronization signal 302 is synchronization signal 146 ( Figure 1 ). The logic level of the synchronization signal 302 is plotted on the y-axis and time t is plotted on the x-axis. As used herein, the logic level ranges from 0 to 1, with a logic level of 0 corresponding to 0 volts (V) of direct current (DC) and a logic level of 1 corresponding to 5 volts DC. As used herein, the synchronization signal is a digital pulse signal such as a square wave having logic levels 1 and 0.

[0157] The synchronization signal 302 has a duty cycle of 50%. For example, the synchronization signal 302 has a logic level of 1 from time t0 to time t5. The synchronization signal 302 has a logic level of 0 from time t5 to time t10, has a logic level of 1 from time t10 to time t15, and has a logic level of 0 from time t15 to time t20.

[0158] The time interval between time t0 and time t20 is divided into a plurality of equal time intervals. For example, the time interval between time t0 and time t20 is divided into a first time interval between time t0 and time t1, a second time interval between time t1 and time t2, a third time interval between time t2 and time t3, a fourth time interval between time t3 and time t4, a fifth time interval between time t4 and time t5, a sixth time interval between time t5 and time t6, a seventh time interval between time t6 and time t7, an eighth time interval between time t7 and time t8, a ninth time interval between time t8 and time t9, a tenth time interval between time t9 and time t10, and a fourth time interval between time t11 and time t12. 0 and time t11, a twelfth time interval between time t11 and time t12, a thirteenth time interval between time t12 and time t13, a fourteenth time interval between time t13 and time t14, a fifteenth time interval between time t14 and time t15, a sixteenth time interval between time t15 and time t16, a seventeenth time interval between time t16 and time t17, an eighteenth time interval between time t17 and time t18, a nineteenth time interval between time t18 and time t19, and a twentieth time interval between time t19 and time t20. Each of the first to twentieth time intervals is equal or the same.

[0159] The synchronization signal 302 has a plurality of cycles, such as cycle 1 and cycle 2, and repeats logic levels 1 and 0 during each cycle. For example, the synchronization signal 302 transitions from logic level 1 to logic level 0 at time t5 during cycle 1, and transitions from logic level 1 to logic level 0 at time t15 during cycle 2. For another example, at time t0 of cycle 1, the synchronization signal 302 transitions from logic level 0 of cycle 0 to logic level 1 of cycle 1. Cycle 0 belongs to the synchronization signal 302 and precedes cycle 1 of the synchronization signal 302. Similarly, at time t10 of cycle 1, the synchronization signal 302 transitions from logic level 0 of cycle 1 to logic level 1 of cycle 2. Time t0 to t10 occurs during cycle 1 of the synchronization signal described herein, and time t10 to t20 occurs during cycle 2 of the synchronization signal. Cycle 1 starts at time t0 and ends at time t10, and cycle 2 starts at time t10 and ends at time t20.

[0160] Here, each cycle of the synchronization signal is repeated periodically. For example, cycle 2 of the synchronization signal is after cycle 1 of the synchronization signal and is subsequent to cycle 1, and cycle 1 of the synchronization signal is after cycle 0 of the synchronization signal and is subsequent to cycle 0.

[0161] Figure 3B For purposes of illustrating an embodiment of a graph 304 of a parameter 306 of an RF signal 152 relative to time, the RF signal 152 is a source RF signal. The parameter 306 is plotted on the y-axis and time t is plotted on the x-axis.

[0162] The parameter 306 periodically changes between parameter levels PR1 and PR2 in synchronization with the synchronization signal 302. For example, the parameter 306 changes between parameter levels PR1 and PR2 during cycle 1 of the synchronization signal 302, and changes between parameter levels PR1 and PR2 again during cycle 2 of the synchronization signal 302. For example, the parameter 306 has a parameter level PR1 during a state S1 stage from time t0 to time t5, a parameter level PR2 during a state S2 stage from time t5 to time t10, a parameter level PR1 during another state S1 stage from time t10 to time t15, and a parameter level PR2 during another state S2 stage from time t15 to time t20. During cycle 1 of the synchronization signal 302, the parameter 306 changes from parameter level PR2 to parameter level PR1 at time t0, and changes from parameter level PR1 to parameter level PR2 at time t5. During cycle 2 of the synchronization signal 302, the parameter 306 again transitions from parameter level PR2 to parameter level PR1 at time t10, and transitions from parameter level PR1 to parameter level PR2 at time t15. Parameter level PR1 is an example of a parameter level for state S1 of the RF signal 152, and parameter level PR2 is an example of a parameter level for state S2 of the RF signal 152.

[0163] The parameter level PR1 is less than the parameter level PR2. For example, the power value of the parameter level PR1 is lower than the power value of the parameter level PR2. For another example, the power value of the parameter level PR1 is not greater than the power value of the parameter level PR2. The parameter level PR1 is greater than zero.

[0164] In one embodiment, the transition time is the time of transition between two parameter levels and is the time period between the two times. For example, instead of transitioning from power level PR1 to power level PR2 at time t5, parameter 306 begins its transition from parameter level PR1 at a first time and ends its transition to parameter level PR2 at a second time. The first time is before time t5 and between time t2 and t5, and the second time is after time t5 and between time t5 and t8. The time period of transition is the transition time between the first time and the second time.

[0165] In one embodiment, instead of transitioning between parameter levels PR1 and PR2, parameter 306 transitions between 0 and parameter level PR2, or between 0 and parameter level PR1.

[0166] In one embodiment, in addition to the synchronization signal 302, a digital pulse signal is also received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 302 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal periodically transitions between two logic levels in the same manner in which the parameter 306 transitions between the parameter levels PR1 and PR2. For example, during cycle 1 of the synchronization signal 302, the digital pulse signal transitions from logic level 1 to logic level 0 at time t0, and transitions from logic level 0 to logic level 1 at time t5. During cycle 2 of the synchronization signal 302, the digital pulse signal transitions from logic level 1 to logic level 0 at time t10, and transitions from logic level 0 to logic level 1 at time t15. Upon receiving the digital pulse signal, the DSP 204 identifies the time periods of the states S1 and S2 of the parameter 306 from the digital pulse signal, and generates a command signal having these time periods. For example, the time period of the state S1 of the parameter 306 is the same as the time period of the logic level 1 of the digital pulse signal, and the time period of the state S2 of the parameter 306 is the same as the time period of the logic level 2 of the digital pulse signal.

[0167] Figure 3C is an embodiment of a graph 308 for illustrating the RF signal 168 ( Figure 1)(which is a bias RF signal). Parameter 310 is plotted on the y-axis, and time t is plotted on the x-axis. Parameter 310 periodically transitions between parameter levels 0, PR1, and PR2 in synchronization with synchronization signal 302. For example, parameter 310 transitions between parameter levels 0, PR2, and PR1 during cycle 1 of synchronization signal 302, and transitions between parameter levels 0, PR2, and PR1 again during cycle 2 of synchronization signal 302. For example, parameter 306 has parameter level 0 during state S0 stage from time t0 to time t2, parameter level PR2 during state S2 stage from time t2 to time t8, and parameter level PR1 during state S1 stage from time t8 to time t10. The parameter levels of 0, PR2, and PR1 are repeated during cycle 2 of synchronization signal 302. During cycle 1 of the synchronization signal 302, the parameter 310 transitions from parameter level PR1 to parameter level 0 at time t0, transitions from parameter level 0 to parameter level PR2 at time t2, transitions from parameter level PR2 to parameter level PR1 at time t8, and transitions from parameter level PR1 to parameter level 0 at time t10. During cycle 2 of the synchronization signal 302, the parameter 310 transitions again from parameter level PR1 to parameter level 0 at time t10, transitions from parameter level 0 to parameter level PR2 at time t12, transitions from parameter level PR2 to parameter level PR1 at time t18, and transitions from parameter level PR1 to parameter level 0 at time t20.

[0168] Parameter level 0 is an example of a parameter level for state S0 of RF signal 168 , parameter level PR1 is an example of a parameter level for state S1 of RF signal 168 , and parameter level PR2 is an example of a parameter level for state S2 of RF signal 168 .

[0169] When the combination of the parameter levels of the parameters 306 and 310 during the first time period is different from the combination of the parameter levels of the parameters 306 and 310 during the second time period, the plasma impedance state of the first time period is different from the plasma impedance state of the second time period. For example, the parameter level of the parameter 306 of the source RF signal is PR1 during the time period between time t0 and t2, and the parameter level of the parameter 310 of the bias RF signal is 0 during the time period between time t0 and t2 to define the plasma chamber 112 ( Figure 1) in the plasma chamber 112. The state of the impedance of the plasma within the plasma chamber 112 is sometimes referred to herein as a plasma impedance state (PS). The parameter level of the parameter 306 of the source RF signal is PR1 during the time period between time t2 and t5, and the parameter level of the parameter 310 of the bias RF signal is PR2 during the time period between time t2 and t5 to define another plasma impedance state PS2.

[0170] As another example, the parameter level of the parameter 306 of the source RF signal is PR2 during the time period between time t5 and t8, and the parameter level of the parameter 310 of the bias RF signal is PR2 during the time period between time t5 and t8 to define another plasma impedance state PS3 that is different from each of the plasma impedance states PS1 and PS2.

[0171] As another example, the parameter level of the parameter 306 of the source RF signal is PR2 during the time period between time t8 and t10, and the parameter level of the parameter 310 of the bias RF signal is PR1 during the time period between time t8 and t10 to define another plasma impedance state PS4 that is different from each of the plasma impedance states PS1, PS2, and PS3. In this way, during each cycle of the synchronization signal 302, a plurality of plasma impedance states, for example, four plasma impedance states PS1 to PS4, are generated due to changes in the parameter levels of the bias and source RF signals. The plasma chamber 112 having the plurality of plasma impedance states PS1 to PS4 ( Figure 1 ) is an example of a multi-state plasma impedance.

[0172] In one implementation, parameter 306 pertains to RF signal 168 , and parameter 310 pertains to RF signal 152 .

[0173] In one embodiment, in addition to the synchronization signal 302, a digital pulse signal is also received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 302 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal periodically transitions between three logic levels in the same manner in which the parameter 310 transitions between parameter levels 0, PR2, and PR1. For example, during cycle 1 of the synchronization signal 302, the digital pulse signal transitions from logic level 1 to logic level 0 at time t0, transitions from logic level 0 to logic level 2 at time t2, and transitions from logic level 2 to logic level 1 at time t8. Logic level 2 is greater than logic level 1. For example, logic level 2 has a higher DC voltage than logic level 1. During cycle 2 of the synchronization signal 302, the digital pulse signal changes from logic level 1 to logic level 0 at time t10, changes from logic level 0 to logic level 2 at time t12, and changes from logic level 2 to logic level 1 at time t18. Upon receiving the digital pulse signal, the DSP 204 identifies the time periods of the states S0, S2, and S1 of the parameter 310 from the digital pulse signal, and generates a command signal having these time periods. For example, the time period of the state S0 of the parameter 310 is the same as the time period of the logic level 0 of the digital pulse signal, the time period of the state S1 of the parameter 310 is the same as the time period of the logic level 1 of the digital pulse signal, and the time period of the state S2 of the parameter 310 is the same as the time period of the logic level 2 of the digital pulse signal.

[0174] Figure 4A This is an implementation of FIG. 300 .

[0175] Figure 4B This is an implementation scheme of Figure 304.

[0176] Figure 4C is an embodiment of a graph 400 for illustrating the RF signal 168 ( Figure 1)(which is a bias RF signal). Parameter 402 is plotted on the y-axis, and time t is plotted on the x-axis. Parameter 402 periodically transitions between parameter levels 0, PR2, and PR1 in synchronization with synchronization signal 302. For example, parameter 402 transitions between parameter levels 0, PR2, and PR1 during cycle 1 of synchronization signal 302, and transitions between parameter levels 0, PR2, and PR1 again during cycle 2 of synchronization signal 302. For example, parameter 402 has parameter level 0 during a state S0 stage from time t0 to time t2, parameter level PR2 during a state S2 stage from time t2 to time t8, parameter level PR1 during a state S1 stage from time t8 to time t9, and parameter level 0 during another state S0 stage from time t9 to time t10. Parameter levels 0, PR2, and PR1 are repeated during cycle 2 of synchronization signal 302. During cycle 1 of the synchronization signal 302, the parameter 402 transitions from parameter level 0 to parameter level PR2 at time t2, transitions from parameter level PR2 to parameter level PR1 at time t8, and transitions from parameter level PR1 to parameter level 0 at time t9. During cycle 2 of the synchronization signal 302, the parameter 402 transitions again from parameter level 0 to parameter level PR2 at time t12, transitions from parameter level PR2 to parameter level PR1 at time t18, and transitions from parameter level PR1 to parameter level 0 at time t19.

[0177] When the combination of the parameter levels of the parameters 306 and 402 during the first time period is different from the combination of the parameter levels of the parameters 306 and 402 during the second time period, the plasma impedance state of the first time period is different from the plasma impedance state of the second time period. For example, the parameter level of the parameter 306 of the source RF signal is PR1 during the time period between time t0 and t2, and the parameter level of the parameter 402 of the bias RF signal is 0 during the time period between time t0 and t2 to define the plasma impedance state PS1. The parameter level of the parameter 306 of the source RF signal is PR1 during the time period between time t2 and t5, and the parameter level of the parameter 402 of the bias RF signal is PR2 during the time period between time t2 and t5 to define another plasma impedance state PS2.

[0178] As another example, the parameter level of the parameter 306 of the source RF signal is PR2 during the time period between time t5 and t8, and the parameter level of the parameter 402 of the bias RF signal is PR2 during the time period between time t5 and t8 to define another plasma impedance state PS3 that is different from each of the plasma impedance states PS1 and PS2.

[0179] For yet another example, the parameter level of the parameter 306 of the source RF signal is PR2 during the time period between time t8 and t9, and the parameter level of the parameter 402 of the bias RF signal is PR1 during the time period between time t8 and t9 to define another plasma impedance state PS4 that is different from each of the plasma impedance states PS1, PS2, and PS3.

[0180] As another example, the parameter level of the parameter 306 of the source RF signal is PR2 during the time period between time t9 and t10, and the parameter level of the parameter 402 of the bias RF signal is 0 during the time period between time t9 and t10 to define another plasma impedance state PS5 that is different from each of the plasma impedance states PS1, PS2, PS3, and PS4.

[0181] As a result, during each cycle of the synchronization signal 302, a plurality of plasma impedance states, such as five plasma impedance states PS1 to PS5, are generated due to the changes in the parameter levels of the bias and source RF signals. The plasma chamber 112 having the plurality of plasma impedance states PS1 to PS5 ( Figure 1 ) is an example of a multi-state plasma impedance.

[0182] In one implementation, parameter 306 pertains to RF signal 168 , and parameter 402 pertains to RF signal 152 .

[0183] In one embodiment, in addition to the synchronization signal 302, a digital pulse signal is also received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 302 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal periodically transitions between three logic levels in the same manner in which the parameter 402 transitions between parameter levels 0, PR2, and PR1. For example, during cycle 1 of the synchronization signal 302, the digital pulse signal transitions from logic level 0 to logic level 2 at time t2, from logic level 2 to logic level 1 at time t8, and from logic level 1 to logic level 0 at time t9. During cycle 2 of the synchronization signal 302, the digital pulse signal transitions from logic level 0 to logic level 2 at time t12, from logic level 2 to logic level 1 at time t18, and from logic level 1 to logic level 0 at time t19. When receiving the digital pulse signal, the DSP 204 identifies the time periods of the states S0, S2, and S1 of the parameter 402 from the digital pulse signal, and generates a command signal having these time periods. For example, the time period of the state S0 of the parameter 402 is the same as the time period of the logic level 0 of the digital pulse signal, the time period of the state S1 of the parameter 402 is the same as the time period of the logic level 1 of the digital pulse signal, and the time period of the state S2 of the parameter 402 is the same as the time period of the logic level 2 of the digital pulse signal.

[0184] Figure 5A 1 is an embodiment of a graph 500 for illustrating a synchronization signal 502. Graph 500 depicts the logic level of synchronization signal 502 relative to time t. Synchronization signal 502 is synchronization signal 146 ( Figure 1 ). The logic level of the synchronization signal 502 is plotted on the y-axis, and time t is plotted on the x-axis.

[0185] The synchronization signal 502 has a duty cycle of 70%. For example, the synchronization signal 502 has a logic level of 1 from time t0 to time t7. The synchronization signal 502 has a logic level of 0 from time t7 to time t10, has a logic level of 1 from time t10 to time t17, and has a logic level of 0 from time t17 to time t20.

[0186] The synchronization signal 502 has a plurality of cycles, and during each cycle, logic levels 1 and 0 are repeated. For example, the synchronization signal 502 transitions from logic level 1 to logic level 0 at time t7 during cycle 1, and transitions from logic level 1 to logic level 0 at time t17 during cycle 2. For another example, at time t0 of cycle 1, the synchronization signal 502 transitions from logic level 0 of cycle 0 of the synchronization signal 502 to logic level 1 of cycle 1. Similarly, at time t10 of cycle 1, the synchronization signal 502 transitions from logic level 0 of cycle 1 to logic level 1 of cycle 2. Cycle 0 of the synchronization signal 502 precedes cycle 1 of the synchronization signal 502, and cycle 1 of the synchronization signal 502 precedes cycle 2 of the synchronization signal 502.

[0187] In one embodiment, the synchronization signal 502 has another duty cycle, such as a 50% duty cycle or a 60% duty cycle, instead of a 70% duty cycle.

[0188] Figure 5B is an embodiment of a graph 504 illustrating a parameter 506 of the RF signal 152 (which is a source RF signal) relative to time. The parameter 506 is plotted on the y-axis and time t is plotted on the x-axis.

[0189] The parameter 506 periodically changes between parameter levels 0, PR1, and PR2 in synchronization with the synchronization signal 502. For example, the parameter 506 changes between parameter levels 0, PR2, and PR1 during cycle 1 of the synchronization signal 502, and changes between parameter levels 0, PR2, and PR1 again during cycle 2 of the synchronization signal 502. For example, the parameter 506 has a parameter level 0 during a state S0 stage from time t0 to time t3, a parameter level PR2 during a state S2 stage from time t3 to time t8, a parameter level PR1 during a state S1 stage from time t8 to time t9, and a parameter level 0 during another state S0 stage from time t9 to time t10. The parameter 506 repeats the occurrence sequence of states S0, S2, S1, and S0 during cycle 2 of the synchronization signal 502. During cycle 1 of synchronization signal 502, parameter 506 transitions from parameter level 0 to parameter level PR2 at time t3, transitions from parameter level PR2 to parameter level PR1 at time t8, and transitions from parameter level PR1 to parameter level 0 at time t9. During cycle 2 of synchronization signal 502, parameter 506 repeatedly transitions between parameter levels 0, PR2, and PR1.

[0190] In one embodiment, in addition to the synchronization signal 502, a digital pulse signal is also received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 502 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal periodically transitions between three logic levels in the same manner in which the parameter 506 transitions between parameter levels 0, PR2, and PR1. For example, during cycle 1 of the synchronization signal 502, the digital pulse signal transitions from logic level 0 to logic level 2 at time t3, from logic level 2 to logic level 1 at time t8, and from logic level 1 to logic level 0 at time t9. During cycle 2 of the synchronization signal 502, the digital pulse signal transitions from logic level 0 to logic level 2 at time t13, from logic level 2 to logic level 1 at time t18, and from logic level 1 to logic level 0 at time t19. When receiving the digital pulse signal, the DSP 204 identifies the time periods of the states S0, S2, and S1 of the parameter 506 from the digital pulse signal, and generates a command signal having these time periods. For example, the time period of the state S0 of the parameter 506 is the same as the time period of the logic level 0 of the digital pulse signal, the time period of the state S2 of the parameter 506 is the same as the time period of the logic level 2 of the digital pulse signal, and the time period of the state S1 of the parameter 506 is the same as the time period of the logic level 1 of the digital pulse signal.

[0191] Figure 5C is an embodiment of a graph 508 for illustrating the RF signal 168 ( Figure 1)(which is a bias RF signal). The parameter 510 is plotted on the y-axis, and time t is plotted on the x-axis. The parameter 510 periodically transitions between parameter levels PR1, PR2, and 0 in synchronization with the synchronization signal 502. For example, the parameter 510 transitions between parameter levels PR1, PR2, and 0 during period 1 of the synchronization signal 502, and transitions between parameter levels PR1, PR2, and 0 again during period 2 of the synchronization signal 502. For example, the parameter 510 has a parameter level PR1 during a state S1 stage from time t0 to time t2, a parameter level PR2 during a state S2 stage from time t2 to time t5, a parameter level PR1 during another state S1 stage from time t5 to time t9, and a parameter level 0 during a state S0 stage from time t9 to time t10. The parameter levels of PR1, PR2, and 0 are repeated during period 2 of the synchronization signal 502. During cycle 1 of the synchronization signal 502, the parameter 510 transitions from parameter level 0 to parameter level PR1 at time t0, transitions from parameter level PR1 to parameter level PR2 at time t2, transitions from parameter level PR2 to parameter level PR1 at time t5, and transitions from parameter level PR1 to parameter level 0 at time t9. During cycle 2 of the synchronization signal 502, the parameter 510 transitions again from parameter level 0 to parameter level PR1 at time t10, transitions from parameter level PR1 to parameter level PR2 at time t12, transitions from parameter level PR2 to parameter level PR1 at time t15, and transitions from parameter level PR1 to parameter level 0 at time t19.

[0192] When the combination of the parameter levels of the parameters 506 and 510 during the first time period is different from the combination of the parameter levels of the parameters 506 and 510 during the second time period, the plasma impedance state of the first time period is different from the plasma impedance state of the second time period. For example, the parameter level of the parameter 506 of the source RF signal is 0 during the time period between time t0 and t2, and the parameter level of the parameter 510 of the bias RF signal is PR1 during the time period between time t0 and t2 to define the plasma impedance state PS1. The parameter level of the parameter 506 of the source RF signal is 0 during the time period between time t2 and t3, and the parameter level of the parameter 510 of the bias RF signal is PR2 during the time period between time t2 and t3 to define another plasma impedance state PS2.

[0193] For another example, the parameter level of the parameter 506 of the source RF signal is PR2 during the time period between time t3 and t5, and the parameter level of the parameter 510 of the bias RF signal is PR2 during the time period between time t3 and t5 to define another plasma impedance state PS3 that is different from each of the plasma impedance states PS1 and PS2. For yet another example, the parameter level of the parameter 506 of the source RF signal is PR2 during the time period between time t5 and t8, and the parameter level of the parameter 510 of the bias RF signal is PR1 during the time period between time t5 and t8 to define another plasma impedance state PS4 that is different from each of the plasma impedance states PS1, PS2, and PS3.

[0194] As another example, the parameter level of the parameter 506 of the source RF signal is PR1 during the time period between time t8 and t9, and the parameter level of the parameter 510 of the bias RF signal is PR1 during the time period between time t8 and t9 to define another plasma impedance state PS5 that is different from each of the plasma impedance states PS1, PS2, PS3, and PS4. As another example, the parameter level of the parameter 506 of the source RF signal is 0 during the time period between time t9 and t10, and the parameter level of the parameter 510 of the bias RF signal is 0 during the time period between time t9 and t10 to define another plasma impedance state PS6 that is different from each of the plasma impedance states PS1, PS2, PS3, PS4, and PS5. In this way, during each cycle of the synchronization signal 502, due to the changes in the parameter levels of the bias and source RF signals, a plurality of plasma impedance states, for example, six plasma impedance states PS1 to PS6, are generated. The plasma chamber 112 having a plurality of plasma impedance states PS1 to PS6 ( Figure 1 ) is an example of a multi-state plasma impedance.

[0195] In one implementation, parameter 506 pertains to RF signal 168 , and parameter 510 pertains to RF signal 152 .

[0196] In one embodiment, in addition to the synchronization signal 502, a digital pulse signal is also received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 502 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal periodically transitions between three logic levels in the same manner in which the parameter 506 transitions between parameter levels 0, PR1, and PR2. For example, during cycle 1 of the synchronization signal 502, the digital pulse signal transitions from logic level 0 to logic level 1 at time t0, from logic level 1 to logic level 2 at time t2, from logic level 2 to logic level 1 at time t5, and from logic level 1 to logic level 0 at time t9. During cycle 2 of the synchronization signal 502, the digital pulse signal changes from logic level 0 to logic level 1 at time t10, changes from logic level 1 to logic level 2 at time t12, changes from logic level 2 to logic level 1 at time t15, and changes from logic level 1 to logic level 0 at time t19. Upon receiving the digital pulse signal, the DSP 204 identifies the time periods of the states S0, S2, and S1 of the parameter 510 from the digital pulse signal and generates a command signal having these time periods. For example, the time period of the state S0 of the parameter 510 is the same as the time period of the logic level 0 of the digital pulse signal, the time period of the state S2 of the parameter 510 is the same as the time period of the logic level 2 of the digital pulse signal, and the time period of the state S1 of the parameter 510 is the same as the time period of the logic level 1 of the digital pulse signal.

[0197] Fig. 6A 6 is an embodiment of a graph 600 for illustrating a synchronization signal 602. Graph 600 depicts the logic level of synchronization signal 602 relative to time t. Synchronization signal 602 is synchronization signal 146 ( Figure 1 ). The logic level of the synchronization signal 602 is plotted on the y-axis, and time t is plotted on the x-axis.

[0198] The synchronization signal 602 has a duty cycle of 30%. For example, the synchronization signal 602 has a logic level of 1 from time t0 to time t3. The synchronization signal 602 has a logic level of 0 from time t3 to time t10, has a logic level of 1 from time t10 to time t13, and has a logic level of 0 from time t13 to time t20.

[0199] The synchronization signal 602 has a plurality of cycles, and during each cycle, logic levels 1 and 0 are repeated. For example, the synchronization signal 602 transitions from logic level 1 to logic level 0 at time t3 during cycle 1, and transitions from logic level 1 to logic level 0 at time t13 during cycle 2. For another example, at time t0 of cycle 1, the synchronization signal 602 transitions from logic level 0 of cycle 0 of the synchronization signal 602 to logic level 1 of cycle 1. Similarly, at time t10 of cycle 1, the synchronization signal 602 transitions from logic level 0 of cycle 1 to logic level 1 of cycle 2. Cycle 0 of the synchronization signal 602 precedes cycle 1 of the synchronization signal 602, and cycle 1 of the synchronization signal 602 precedes cycle 2 of the synchronization signal 602.

[0200] In one embodiment, the synchronization signal 602 has another duty cycle, such as a 50% duty cycle or a 60% duty cycle, instead of a 30% duty cycle.

[0201] Figure 6B 6 is an embodiment of a graph 604 illustrating a parameter 606 of the RF signal 152 (which is a source RF signal) relative to time. The parameter 606 is plotted on the y-axis and time t is plotted on the x-axis.

[0202] The parameter 606 is synchronized with the synchronization signal 602 and periodically changes between parameter levels PR2, PR1, and 0. For example, the parameter 606 changes between parameter levels PR2, PR1, and 0 during cycle 1 of the synchronization signal 602, and changes between parameter levels PR2, PR1, and 0 again during cycle 2 of the synchronization signal 602. For example, the parameter 606 has a parameter level PR2 during a state S2 stage from time t0 to time t3, a parameter level PR1 during a state S1 stage from time t3 to time t7, and a parameter level 0 during a state S0 stage from time t7 to time t10. The parameter 606 repeats the occurrence sequence of states S2, S1, and S0 during cycle 2 of the synchronization signal 602. Also, during cycle 1 of the synchronization signal 602, the parameter 606 transitions from parameter level 0 to parameter level PR2 at time t0, transitions from parameter level PR2 to parameter level PR1 at time t3, and transitions from parameter level PR1 to parameter level 0 at time t7. During cycle 2 of the synchronization signal 602, the parameter 606 repeats transitions between parameter levels PR2, PR1, and 0. For example, during cycle 2 of the synchronization signal 602, the parameter 606 transitions from parameter level 0 to parameter level PR2 at time t10, transitions from parameter level PR2 to parameter level PR1 at time t13, and transitions from parameter level PR1 to parameter level 0 at time t17.

[0203] In one embodiment, in addition to the synchronization signal 602, a digital pulse signal is also received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 602 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal periodically transitions between three logic levels in the same manner in which the parameter 606 transitions between parameter levels 0, PR2, and PR1. For example, during cycle 1 of the synchronization signal 602, the digital pulse signal transitions from logic level 0 to logic level 2 at time t0, from logic level 2 to logic level 1 at time t3, and from logic level 1 to logic level 0 at time t7. During cycle 2 of the synchronization signal 602, the digital pulse signal transitions from logic level 0 to logic level 2 at time t10, from logic level 2 to logic level 1 at time t13, and from logic level 1 to logic level 0 at time t17. Upon receiving the digital pulse signal, the DSP 204 identifies the time periods of the states S2, S1, and S0 of the parameter 606 from the digital pulse signal, and generates a command signal having these time periods. For example, the time period of the state S0 of the parameter 606 is the same as the time period of the logic level 0 of the digital pulse signal, the time period of the state S2 of the parameter 606 is the same as the time period of the logic level 2 of the digital pulse signal, and the time period of the state S1 of the parameter 606 is the same as the time period of the logic level 1 of the digital pulse signal.

[0204] Figure 6C is an embodiment of a graph 608 for illustrating the RF signal 168 ( Figure 1)(which is a bias RF signal). Parameter 610 is plotted on the y-axis, and time t is plotted on the x-axis. Parameter 610 periodically transitions between parameter levels 0, PR1, and PR2 in synchronization with synchronization signal 602. For example, parameter 610 transitions between parameter levels 0, PR1, and PR2 during cycle 1 of synchronization signal 602, and transitions between parameter levels 0, PR1, and PR2 again during cycle 2 of synchronization signal 602. For example, parameter 610 has parameter level 0 during a state S0 stage from time t0 to time t1, parameter level PR1 during a state S1 stage from time t1 to time t5, parameter level PR2 during a state S2 stage from time t5 to time t8, and parameter level 0 during another state S0 stage from time t8 to time t10. Parameter levels 0, PR1, and PR2 are repeated during cycle 2 of synchronization signal 602. During cycle 1 of the synchronization signal 602, the parameter 610 transitions from parameter level 0 to parameter level PR1 at time t1, transitions from parameter level PR1 to parameter level PR2 at time t5, and transitions from parameter level PR2 to parameter level 0 at time t8. During cycle 2 of the synchronization signal 602, the parameter 610 transitions again from parameter level 0 to parameter level PR1 at time t11, transitions from parameter level PR1 to parameter level PR2 at time t15, and transitions from parameter level PR2 to parameter level 0 at time t18.

[0205] When the combination of the parameter levels of the parameters 606 and 610 during the first time period is different from the combination of the parameter levels of the parameters 606 and 610 during the second time period, the plasma impedance state of the first time period is different from the plasma impedance state of the second time period. For example, the parameter level of the parameter 606 of the source RF signal is PR2 during the time period between time t0 and t1, and the parameter level of the parameter 610 of the bias RF signal is 0 during the time period between time t0 and t1 to define the plasma impedance state PS1. The parameter level of the parameter 606 of the source RF signal is PR2 during the time period between time t1 and t3, and the parameter level of the parameter 610 of the bias RF signal is PR1 during the time period between time t1 and t3 to define another plasma impedance state PS2.

[0206] As another example, the parameter level of the parameter 606 of the source RF signal is PR1 during the time period between time t3 and t5, and the parameter level of the parameter 610 of the bias RF signal is PR1 during the time period between time t3 and t5 to define another plasma impedance state PS3 that is different from each of the plasma impedance states PS1 and PS2. As yet another example, the parameter level of the parameter 606 of the source RF signal is PR1 during the time period between time t5 and t7, and the parameter level of the parameter 610 of the bias RF signal is PR2 during the time period between time t5 and t7 to define another plasma impedance state PS4 that is different from each of the plasma impedance states PS1, PS2, and PS3.

[0207] As another example, the parameter level of the parameter 606 of the source RF signal is 0 during the time period between time t7 and t8, and the parameter level of the parameter 610 of the bias RF signal is PR2 during the time period between time t7 and t8 to define another plasma impedance state PS5 that is different from each of the plasma impedance states PS1, PS2, PS3, and PS4. As another example, the parameter level of the parameter 606 of the source RF signal is 0 during the time period between time t8 and t10, and the parameter level of the parameter 610 of the bias RF signal is 0 during the time period between time t8 and t10 to define another plasma impedance state PS6 that is different from each of the plasma impedance states PS1, PS2, PS3, PS4, and PS5. In this way, during each cycle of the synchronization signal 602, due to the changes in the parameter levels of the bias and source RF signals, a plurality of plasma impedance states, for example, six plasma impedance states PS1 to PS6, are generated. The plasma chamber 112 having a plurality of plasma impedance states PS1 to PS6 ( Figure 1 ) is an example of a multi-state plasma impedance.

[0208] In one implementation, parameter 606 pertains to RF signal 168 , and parameter 610 pertains to RF signal 152 .

[0209] In one embodiment, in addition to the synchronization signal 602, a digital pulse signal is also received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 602 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal periodically transitions between three logic levels in the same manner in which the parameter 610 transitions between parameter levels 0, PR1, and PR2. For example, during cycle 1 of the synchronization signal 602, the digital pulse signal transitions from logic level 0 to logic level 1 at time t1, from logic level 1 to logic level 2 at time t5, and from logic level 2 to logic level 1 at time t8. During cycle 2 of the synchronization signal 602, the digital pulse signal transitions from logic level 0 to logic level 1 at time t11, from logic level 1 to logic level 2 at time t15, and from logic level 2 to logic level 1 at time t18. Upon receiving the digital pulse signal, the DSP 204 identifies the time periods of the states S0, S2, and S1 of the parameter 610 from the digital pulse signal, and generates a command signal having these time periods. For example, the time period of the state S0 of the parameter 610 is the same as the time period of the logic level 0 of the digital pulse signal, the time period of the state S2 of the parameter 610 is the same as the time period of the logic level 2 of the digital pulse signal, and the time period of the state S1 of the parameter 610 is the same as the time period of the logic level 1 of the digital pulse signal.

[0210] In one embodiment, instead of using Figure 3C )、402( Figure 4C )、510( Figure 5C ) and 610( Figure 6C ) instead of parameter level PR1 for any of parameters 310, 402, 510, and 610, parameter level PR3 is used. Parameter level PR3 is greater than or lower than parameter level PR1. Similarly, instead of parameter level PR2 for any of parameters 310, 402, 510, and 610, parameter level PR4 is used. Parameter level PR4 is greater than or lower than parameter level PR2.

[0211] Fig.6D FIG. 1 is a diagram for explaining an embodiment of an on-off time modification method using selective synchronization between a source RF generator and a bias RF generator. Fig.6DAs described, there is a time delay from time t1 to time t2 in turning on the RF signal generated by the first RF generator (e.g., source RF generator or bias RF generator) compared to the second RF generator (e.g., source RF generator or bias RF generator). Also, the time when the RF power supplied by the first RF generator is turned off is shifted forward from time t4 to time t3. Thus, instead of two plasma impedance states S1 and S0, more than two plasma impedance states, such as six, eight, ten, or twenty plasma impedance states, are generated.

[0212] Multi-state pulse components

[0213] Figure 7 1 is a diagram for explaining an embodiment of a plasma system 700 for multi-stage parameter pulses. The plasma system 700 includes an RF generator 702 and a host computer 106. The RF generator 702 is a source RF generator 102 ( Figure 1 ) or bias RF generator 104 ( Figure 1 ). The RF generator 702 includes the DSP 204, a plurality of parameter controllers PRS1a, PRS2a, PRS3a, etc. up to PRSna, where n is an integer greater than three. For example, n is four or more. For example, the RF generator 702 includes four parameter controllers, one of which is used for state S1a, another of which is used for state S2a, another of which is used for state S3a, and another of which is used for state S4a. For another example, the RF generator 702 includes five parameter controllers, one of which is used for state S1a, another of which is used for state S2a, another of which is used for state S3a, another of which is used for state S4a, and one of which is used for state S5a. The RF generator 702 also includes a frequency controller (FC) 210, a driver system 710, and an RF power supply 222.

[0214] The DSP 204 is coupled to each of the parameter controllers PRS1a to PRSna of the RF generator 702. The parameter controllers PRS1a to PRSna are coupled to the driver system 710, which is coupled to the RF power source 222. And, the frequency controller 210 is coupled to the driver system 710.

[0215] The processor 118 provides the parameters for the states S1a to Sna, such as parameter levels, and the synchronization signal 146 to the DSP 204 via the transmission cable system 214. Upon receiving the parameter levels for the states S1a to Sna, the DSP 204 provides the parameters for the state S1a of the RF signal 712, such as power levels or voltage levels, to the parameter controller PRS1a to store the parameters for the state S1a in the memory device of the parameter controller PRS1a. The RF signal 712 is the RF signal 152 or the RF signal 168 ( Figure 1 ) example.

[0216] And, in response to receiving the parameter levels for states S1a to Sna, the DSP 204 provides the parameter level for state S2a of the RF signal 712, such as a power level or a voltage level, to the parameter controller PRS2a to store the parameter level for state S2a in the memory device of the parameter controller PRS2a. In addition, in response to receiving the parameter levels for states S1a to Sna, the DSP 204 provides the parameter level for state S3a of the RF signal 712, such as a power level or a voltage level, to the parameter controller PRS3a to store the parameters for state S3a in the memory device of the parameter controller PRS3a. In response to receiving the parameters for states S1a to Sna, the DSP 204 provides the parameter level for state Sna of the RF signal 712, such as a power level or a voltage level, to the parameter controller PRSna to store the parameters for state Sna in the memory device of the parameter controller PRSna. Similarly, upon receiving parameters for states S1a through Sna, the DSP 204 provides frequency levels, such as a single frequency level, for all states S1a through Sna to the frequency controller 210 for storage in a memory device of the frequency controller 210 .

[0217] In one embodiment, the value of the (n-1)th parameter level is different from the value of the nth parameter level. For example, the value of the (n-1)th parameter level does not include the value of the nth parameter level. As another example, none of the values ​​of the (n-1)th parameter level is the same as any of the values ​​of the nth parameter level.

[0218] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S1a to the parameter controller PRS1a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S1a to the parameter controller PRS1a at a time of transition from a state other than or in addition to state S1a (e.g., state Sna or state S0) to state S1a. The command signal for state S1a transmitted to the parameter controller PRS1a includes a time period of state S1a during each cycle of the parameter controller PRS1a to provide parameter levels for state S1a to the driver system 710. Upon receiving the command signal for state S1a, the parameter controller PRS1a retrieves the parameter levels for state S1a from a memory device of the parameter controller PRS1a and transmits these parameter levels to the driver system 710 for the time period of state S1a. For example, the parameter controller PRS1a transmits the parameter level for state S1a to the driver system 710 at the time of transition from a state other than state S1a to state S1a. After the time period of state S1a, during the period of the synchronization signal 146, the parameter controller PRS1a does not transmit the parameter level for state S1a to the driver system 710.

[0219] Similarly, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S2a to the parameter controller PRS2a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S2a to the parameter controller PRS2a at the time of transitioning from a state other than or in addition to state S2a (e.g., state S1a or state S3a or state S0) to state S2a. The command signal for state S2a transmitted to the parameter controller PRS2a includes a time period of state S2a during each cycle of the parameter controller PRS2a to provide parameter levels for state S2a to the driver system 710. Upon receiving the command signal for state S2a, the parameter controller PRS2a retrieves the parameter levels for state S2a from the memory device of the parameter controller PRS2a and transmits these parameter levels to the driver system 710 for the time period of state S2a. For example, the parameter controller PRS2a transmits the parameter level for state S2a to the drive system 710 at the time of transition from a state different from state S2a to state S2a. After the time period of state S2a, during the period of the synchronization signal 146, the parameter controller PRS2a does not transmit the parameter level for state S2a to the drive system 710.

[0220] Also, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S3a to the parameter controller PRS3a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S3a to the parameter controller PRS3a at the time of transitioning from a state other than or in addition to state S3a (e.g., state S2a or state S1a or state S0) to state S3a. The command signal for state S3a transmitted to the parameter controller PRS3a includes a time period of state S3a during each cycle of the parameter controller PRS3a to provide the parameter level for state S3a to the driver system 710. Upon receiving the command signal for state S3a, the parameter controller PRS3a retrieves the parameter level for state S3a from the memory device of the parameter controller PRS3a and transmits these parameter levels to the driver system 710 for the time period of state S3a. For example, the parameter controller PRS3a transmits the parameter level for state S3a to the drive system 710 at the time of transition from a state other than state S3a to state S3a. After the time period of state S3a, during the period of the synchronization signal 146, the parameter controller PRS3a does not transmit the parameter level for state S3a to the drive system 710.

[0221] In addition, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state Sna to the parameter controller PRSna during each cycle of the synchronization signal 146. For example, the DSP 204 transmits the command signal for state Sna to the parameter controller PRSna at the time of transition from a state different from or in addition to state Sna (e.g., state S(n-1)a or state S0) to state Sna. The command signal for state Sna transmitted to the parameter controller PRSna includes a time period of state Sna during each cycle of the parameter controller PRSna to provide parameter levels for state Sna to the driver system 710. Upon receiving the command signal for state Sna, the parameter controller PRSna retrieves the parameter levels for state Sna from a memory device of the parameter controller PRSna and transmits the parameter levels to the driver system 710 for the time period of state Sna. For example, the parameter controller PRSna transmits the parameter levels for state Sna to the driver system 710 at the time of transition from a state different from state Sna to state Sna. After the time period of the state Sna, during the period of the synchronization signal 146 , the parameter controller PRSna does not transmit the parameter level for the state Sna to the drive system 710 .

[0222] Also, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal to the frequency controller 210 during each cycle of the synchronization signal 146. Upon receiving the command signal, the frequency controller 210 obtains the frequency level from the memory device of the frequency controller 210 and transmits the frequency level to the driver system 710.

[0223] In response to receiving the parameter level and frequency level for state S1a, the driver system 710 generates a drive signal for state S1a for a time period of state S1a and transmits the drive signal to the RF power supply 222. For example, when the parameter level and frequency level for state S1a are received at a time of transition to state S1a from a state different from or other than state S1a (e.g., state Sna or state S2a or state S3a or state S0), the driver system 710 generates a drive signal for state S1a for a time period of state S1a and transmits the drive signal to the RF power supply 222. The RF power supply 222 generates state S1a of the RF signal 712 when receiving the drive signal for state S1a from the driver system 710. For example, when receiving the drive signal for state S1a from the driver system 710, the RF power supply 222 causes the RF signal 712 to transition from a state different from state S1a to state S1a. The state S1a of the RF signal 712 has a frequency level during the time period of the state S1a and a parameter level for the state S1a.

[0224] Similarly, in response to receiving the frequency level and the parameter level for state S2a, the driver system 710 generates a drive signal for state S2a for a time period of state S2a and transmits the drive signal to the RF power supply 222. For example, when receiving the frequency level and the parameter level for state S2a at a time of transition from a state other than or in addition to state S2a (e.g., state S1a or state S3a or state Sna or state S0) to state S2a, the driver system 710 generates a drive signal for state S2a for a time period of state S2a and transmits the drive signal to the RF power supply 222. The RF power supply 222 generates state S2a of the RF signal 712 upon receiving the drive signal for state S2a from the driver system 710. For example, upon receiving the drive signal for state S2a from the driver system 710, the RF power supply 222 causes the RF signal 712 to transition from a state other than state S2a to state S2a. State S2a of the RF signal 712 has a frequency level during the time period of state S2a and a parameter level for state S2a.

[0225] And, in response to receiving the frequency level and the parameter level for state S3a, the driver system 710 generates a driving signal for state S3a for a time period of state S3a, and transmits the driving signal to the RF power supply 222. For example, when receiving the frequency level and the parameter level for state S3a at a time of transition from a state different from or other than state S3a (e.g., state S2a or state S4a or state Sna or state S0) to state S3a, the driver system 710 generates a driving signal for state S3a for a time period of state S3a, and transmits the driving signal to the RF power supply 222. The RF power supply 222 generates state S3a of the RF signal 712 when receiving the driving signal for state S3a from the driver system 710. For example, when receiving the driving signal for state S3a from the driver system 710, the RF power supply 222 causes the RF signal 712 to transition from a state different from state S3a to state S3a. State S3a of the RF signal 712 has a frequency level during the time period of state S3a and a parameter level for state S3a.

[0226] In addition, in response to receiving the frequency level and the parameter level for the state Sna, the driver system 710 generates a drive signal for the state Sna for a time period of the state Sna and transmits the drive signal to the RF power supply 222. For example, when the frequency level and the parameter level for the state Sna are received at the time of transition to the state Sna from a state different from or other than the state Sna (e.g., state S(n-1)a or state S0 or state S3a or state S2a), the driver system 710 generates a drive signal for the state Sna for a time period of the state Sna and transmits the drive signal to the RF power supply 222. The RF power supply 222 generates the state Sna of the RF signal 712 when receiving the drive signal for the state Sna from the driver system 710. For example, when receiving the drive signal for the state Sna from the driver system 710, the RF power supply 222 causes the RF signal 712 to transition from a state different from the state Sna to the state Sna. The state Sna of the RF signal 712 has the frequency level and the parameter level for the state Sna during the time period of the state Sna.

[0227] Also, in one embodiment, during each cycle of the synchronization signal 146, there is a time period in which the RF signal 712 has a parameter level of zero. The RF signal 712 has a parameter level of zero during an idle state, such as state S0. Upon receiving the synchronization signal 146, during each cycle of the synchronization signal 146, during the time period of the idle state, the DSP 204 does not send instruction signals of states S1a to Sna to the parameter controllers PRS1a to PRSna.

[0228] During the time period of the empty state in which the command signal for the states S1a to Sna is not received, the parameter controllers PRS1a to PRSna do not transmit or stop transmitting the parameter level for the states S1a to Sna to the drive system 710. For example, after the time period of the state S1a, the parameter controller PRS1a does not transmit the parameter level for the state S1a to the drive system 710. For another example, after the time period of the state S2a, the parameter controller PRS2a does not transmit the parameter level for the state S2a to the drive system 710.

[0229] When the parameter level for the states S1a to Sna is not received, the driver system 710 does not transmit a driving signal to the RF power supply 222. When the driving signal is not received during the time period of the null state, the RF power supply 222 generates an RF signal 712 having a parameter level of zero during the null state. For example, when the driving signal is not received, the RF power supply 222 transitions the RF signal 712 from a state other than or in addition to the null state S0 (e.g., state S1a or state S2a or state Sna) to the null state S0.

[0230] States S1a to Sna and the empty state are states of parameters of the RF signal 712. For example, referring to Figure 7 The illustrated states S1a through Sna and the empty state each represent a parameter level of the RF signal 712. For example, the state S1a of the RF signal 712 represents a first parameter level of the RF signal 712, and the state S2a of the RF signal 712 represents a second parameter level of the RF signal 712.

[0231] In one embodiment, instead of the parameter controllers PRS1a to PRSna and the frequency controller 210, one or more controllers, such as one or more processors, are used to perform the functions described herein as performed by the parameter controllers PRS1a to PRSna and the frequency controller 210.

[0232] In one embodiment, instead of DSP 204, parameter controllers PRS1a to PRSna, and frequency controller 210, one or more controllers, such as one or more processors, are used to perform the functions described herein as performed by DSP 204, parameter controllers PRS1a to PRSna, and frequency controller 210.

[0233] Figure 8 1 is a diagram for explaining an embodiment of a plasma system 800 for multi-level frequency pulses. The plasma system 800 includes an RF generator 802 and a host computer 106. The RF generator 802 is a source RF generator 102 ( Figure 1 ) or bias RF generator 104 ( Figure 1). The RF generator 802 includes the DSP 204, a plurality of frequency controllers FCS1a, FCS2a, FCS3a, etc. up to FCSna, where n is an integer greater than three. For example, n is four or more. For example, the RF generator 802 includes four frequency controllers, one of which is used for state S1a, another of which is used for state S2a, another of which is used for state S3a, and another of which is used for state S4a. For another example, the RF generator 802 includes five frequency controllers, one of which is used for state S1a, another of which is used for state S2a, another of which is used for state S3a, another of which is used for state S4a, and one of which is used for state S5a. The RF generator 802 also includes a parameter controller 814, a driver system 810, and an RF power supply 222.

[0234] The DSP 204 is coupled to each of the frequency controllers FCS1a to FCSna of the RF generator 802. The frequency controllers FCS1a to FCSna are coupled to a driver system 810, which is coupled to the RF power source 222. Also, a parameter controller 814 is coupled to the driver system 810.

[0235] The processor 118 provides the frequencies, such as frequency levels, for states S1a to Sna and the synchronization signal 146 to the DSP 204 via the transmission cable system 214. Upon receiving the frequency levels for states S1a to Sna, the DSP 204 provides the frequencies, such as frequency levels, for state S1a of the RF signal 812 to the frequency controller FCS1a to store the frequencies for state S1a in the memory device of the frequency controller FCS1a. The RF signal 812 is the RF signal 152 or the RF signal 168 ( Figure 1 ) example.

[0236] And, in response to receiving the frequency levels for states S1a to Sna, the DSP 204 provides the frequency level for state S2a of the RF signal 812 to the frequency controller FCS2a to store the frequency level for state S2a in the memory device of the frequency controller FCS2a. In addition, in response to receiving the frequency levels for states S1a to Sna, the DSP 204 provides the frequency level for state S3a of the RF signal 812 to the frequency controller FCS3a to store the frequency level for state S3a in the memory device of the frequency controller FCS3a. In response to receiving the frequency levels for states S1a to Sna, the DSP 204 provides the frequency level for state Sna of the RF signal 812 to the frequency controller FCSna to store the frequency level for state Sna in the memory device of the frequency controller FCSna. Similarly, upon receiving a parameter level, such as a single parameter level, for all states S1a to Sna, the DSP 204 provides the parameter level to the parameter controller 814 to store in the memory device of the parameter controller 814.

[0237] In one embodiment, the value of the (n-1)th frequency level is different from the value of the nth frequency level. For example, the value of the (n-1)th frequency level does not include the value of the nth frequency level. As another example, the value of the (n-1)th frequency level is not the same as any of the values ​​of the nth frequency level.

[0238] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S1a to the frequency controller FCS1a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits the command signal for state S1a to the frequency controller FCS1a at the time of transitioning from a state other than or in addition to state S1a (e.g., state S2a or state S0 or state S3a) to state S1a. The command signal for state S1a transmitted to the frequency controller FCS1a includes a time period of state S1a during each cycle of the drive system 810 during which the frequency controller FCS1a will provide the frequency level for state S1a. Upon receiving the command signal for state S1a, the frequency controller FCS1a retrieves the frequency level for state S1a from a memory device of the frequency controller FCS1a and transmits the frequency level to the driver system 810 for the time period of state S1a. For example, the frequency controller FCS1a transmits the frequency level for state S1a to the driver system 810 when transitioning from a state other than state S1a to state S1a. After the time period of state S1a, during the period of the synchronization signal 146, the frequency controller FCS1a does not transmit the frequency level for state S1a to the driver system 810.

[0239] Similarly, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S2a to the frequency controller FCS2a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S2a to the frequency controller FCS2a at a time of transitioning from a state other than or in addition to state S2a (e.g., state S1a or state S0 or state S3a) to state S2a. The command signal for state S2a transmitted to the frequency controller FCS2a includes a time period of state S2a during each cycle of the driver system 810 during which the frequency controller FCS2a will provide the frequency level for state S2a. Upon receiving the command signal for state S2a, the frequency controller FCS2a retrieves the frequency level for state S2a from a memory device of the frequency controller FCS2a and transmits the frequency level to the driver system 810 for the time period of state S2a. For example, the frequency controller FCS2a transmits the frequency level for state S2a to the driver system 810 at the time of transition from a state different from state S2a to state S2a. After the time period of state S2a, during the cycle of the synchronization signal 146, the frequency controller FCS2a does not transmit the frequency level for state S2a to the driver system 810.

[0240] Also, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S3a to the frequency controller FCS3a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S3a to the frequency controller FCS3a at a time of transitioning from a state other than or in addition to state S3a (e.g., state S2a or state S1a or state S0) to state S3a. The command signal for state S3a transmitted to the frequency controller FCS3a includes a time period of state S3a during each cycle of the driver system 810 during which the frequency controller FCS3a will provide a frequency level for state S3a. Upon receiving the command signal for state S3a, the frequency controller FCS3a retrieves the frequency level for state S3a from a memory device of the frequency controller FCS3a and transmits the frequency level to the driver system 810 for the time period of state S3a. For example, the frequency controller FCS3a transmits the frequency level for state S3a to the driver system 810 at the time of transition from a state other than state S3a to state S3a. After the time period of state S3a, during the cycle of the synchronization signal 146, the frequency controller FCS3a does not transmit the frequency level for state S3a to the driver system 810.

[0241] In addition, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for the state Sna to the frequency controller FCSna during each cycle of the synchronization signal 146. For example, the DSP 204 transmits the command signal for the state Sna to the frequency controller FCSna at the time of transitioning from a state different from or in addition to the state Sna (e.g., state S(n-1)a or state S0) to the state Sna. The command signal for the state Sna transmitted to the frequency controller FCSna includes a time period of the state Sna during each cycle of the state Sna during which the frequency controller FCSna will provide the frequency level for the state Sna to the driver system 810. Upon receiving the command signal for the state Sna, the frequency controller FCSna retrieves the frequency level for the state Sna from the memory device of the frequency controller FCSna and transmits the frequency level to the driver system 810 for the time period of the state Sna. For example, the frequency controller FCSna transmits the frequency level for the state Sna to the driver system 810 at the time of transitioning from a state different from the state Sna to the state Sna. After the time period of the state Sna, during the period of the synchronization signal 146, the frequency controller FCSna does not transmit the frequency level for the state Sna to the driver system 810.

[0242] Also, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal to the parameter controller 814 during each cycle of the synchronization signal 146. Upon receiving the command signal, the parameter controller 814 retrieves the parameter level from the memory device of the parameter controller 814 and transmits the parameter level to the driver system 810.

[0243] In response to receiving the parameter level and the frequency level for state S1a, the driver system 810 generates a drive signal for state S1a for a time period of state S1a and transmits the drive signal to the RF power supply 222. For example, when the parameter level and the frequency level for state S1a are received at a time of transition to state S1a from a state different from or other than state S1a (e.g., state S2a or state S3a or state Sna or state S0), the driver system 810 generates a drive signal for state S1a for a time period of state S1a and transmits the drive signal to the RF power supply 222. The RF power supply 222 generates state S1a of the RF signal 812 upon receiving the drive signal for state S1a from the driver system 810. For example, upon receiving the drive signal for state S1a from the driver system 810, the RF power supply 222 causes the RF signal 812 to transition from a state different from state S1a to state S1a. The state S1a of the RF signal 812 has a parameter level during the time period of the state S1a and a frequency level for the state S1a.

[0244] Similarly, in response to receiving the parameter level and the frequency level for state S2a, the driver system 810 generates a drive signal for state S2a for a time period of state S2a and transmits the drive signal to the RF power supply 222. For example, when the parameter level and the frequency level for state S2a are received at a time of transition to state S2a from a state other than or in addition to state S2a (e.g., state S1a or state S0 or state S3a), the driver system 810 generates a drive signal for state S2a for a time period of state S2a and transmits the drive signal to the RF power supply 222. The RF power supply 222 generates state S2a of the RF signal 812 upon receiving the drive signal for state S2a from the driver system 810. For example, upon receiving the drive signal for state S2a from the driver system 810, the RF power supply 222 causes the RF signal 812 to transition from a state other than state S2a to state S2a. State S2a of the RF signal 712 has a parameter level during the time period of state S2a and a frequency level for state S2a.

[0245] And, in response to receiving the parameter level and the frequency level for state S3a, the driver system 810 generates a driving signal for state S3a for a time period of state S3a, and transmits the driving signal to the RF power supply 222. For example, when the parameter level and the frequency level for state S3a are received at a time of transition to state S3a from a state different from or other than state S3a (e.g., state S2a or state S0 or state S1a or state S4a), the driver system 810 generates a driving signal for state S3a for a time period of state S3a, and transmits the driving signal to the RF power supply 222. The RF power supply 222 generates state S3a of the RF signal 812 upon receiving the driving signal for state S3a from the driver system 810. For example, upon receiving the driving signal for state S3a from the driver system 810, the RF power supply 222 causes the RF signal 812 to transition from a state different from state S3a to state S3a. State S3a of the RF signal 812 has a parameter level during the time period of state S3a and a frequency level for state S3a.

[0246] For example, in response to receiving the parameter level and the frequency level for state Sna, the driver system 810 generates a drive signal for state Sna for a time period of state Sna and transmits the drive signal to the RF power supply 222. For example, when the parameter level and the frequency level for state Sna are received at a time of transition from a state different from or other than state Sna (e.g., state S(n-1)a or state S0) to state Sna, the driver system 810 generates a drive signal for state Sna for a time period of state Sna and transmits the drive signal to the RF power supply 222. The RF power supply 222 generates the state Sna of the RF signal 812 upon receiving the drive signal for state Sna from the driver system 810. For example, upon receiving the drive signal for state Sna from the driver system 810, the RF power supply 222 causes the RF signal 812 to transition from a state different from state Sna to state Sna. The state Sna of the RF signal 812 has the parameter level and the frequency level for state Sna during the time period of state Sna.

[0247] Also, in one embodiment, during each cycle of the synchronization signal 146, there is a time period in which the RF signal 812 has a frequency level of zero. The RF signal 812 has a frequency level of zero during an idle state, such as state S0. Upon receiving the synchronization signal 146, during each cycle of the synchronization signal 146, the DSP 204 does not transmit command signals for states S1a to Sna to the frequency controllers FCS1a to FCSna and the parameter controller 814 during the time period of the idle state.

[0248] During the time period of the empty state in which the command signal for the states S1a to Sna is not received, the frequency controllers FCS1a to FCSna do not transmit or stop transmitting the frequency level for the states S1a to Sna to the drive system 810, and the parameter controller 814 stops transmitting the parameter level to the drive system 810. For example, after the time period of the state S1a, the frequency controller FCS1a does not transmit the frequency level for the state S1a to the drive system 810. For another example, after the time period of the state S2a, the frequency controller FCS2a does not transmit the frequency level for the state S2a to the drive system 810.

[0249] When the parameter level and the frequency level for the states S1a to Sna are not received, the driver system 810 does not transmit a driving signal to the RF power supply 222. When the driving signal is not received during the time period of the null state, the RF power supply 222 generates an RF signal 812 having a parameter level of zero during the null state. For example, when the driving signal is not received, the RF power supply 222 transitions the RF signal 812 from a state other than or in addition to the null state S0 (e.g., state S1a or state S2a or state Sna) to the null state S0.

[0250] The states S1a to Sna and the empty state are states of the frequency of the RF signal 812. For example, referring to Figure 8 The illustrated states S1a through Sna and the null state each represent a frequency level of the RF signal 812. For example, the state S1a of the RF signal 812 represents a first frequency level of the RF signal 712, and the state S2a of the RF signal 812 represents a second frequency level of the RF signal 812.

[0251] In one embodiment, instead of the frequency controllers FCS1a to FCSna and the parameter controller 814, one or more controllers, such as one or more processors, are used to perform the functions described herein as performed by the frequency controllers FCS1a to FCSna and the parameter controller 814.

[0252] In one embodiment, instead of the DSP 204, frequency controllers FCS1a to FCSna, and parameter controller 814, one or more controllers, such as one or more processors, are used to perform the functions described herein as performed by the DSP 204, frequency controllers FCS1a to FCSna, and parameter controller 814.

[0253] Fig. 9 1 is a diagram for illustrating an embodiment of a plasma system 900 for simultaneous multi-stage parameter pulses and multi-stage frequency pulses. The plasma system 900 includes an RF generator 902 and a host computer 106. The RF generator 902 is a source RF generator 102 ( Figure 1 ) or bias RF generator 104 ( Figure 1 ) is an example of a RF generator 902. The RF generator 902 includes a DSP 204, frequency controllers FCS1a to FCSna, and parameter controllers PRS1a to PRSna. The RF generator 902 also includes a driver system 910 and an RF power supply 222.

[0254] The DSP 204 is coupled to each of the frequency controllers FCS1a to FCSna and each of the parameter controllers PRS1a to PRSna of the RF generator 902. The frequency controllers FCS1a to FCSna and the parameter controllers PRS1a to PRSna are coupled to a driver system 910, which is coupled to the RF power source 222.

[0255] The processor 118 provides the frequency levels for states S1a to Sna and the parameter levels for states S1a to Sna, as well as the synchronization signal 146 to the DSP 204 via the transmission cable system 214. Upon receiving the frequency levels for states S1a to Sna, the DSP 204 utilizes the parameters described above with reference to Figure 8 In the manner described, the frequency levels for the states S1a to Sna of the RF signal 912 are provided to the frequency controllers FCS1a to FCSna so that the frequency levels for the states S1a to Sna are stored in the memory devices of the frequency controllers FCS1a to FCSna. The RF signal 912 is the RF signal 152 or the RF signal 168 ( Figure 1 ) example. Similarly, upon receiving the parameter levels for states S1a to Sna, DSP 204 utilizes the Figure 7 In the manner described, the parameter levels for the states S1a to Sna of the RF signal 912 are provided to the parameter controllers PRS1a to PRSna so that the parameter levels for the states S1a to Sna are stored in the memory devices of the parameter controllers PRS1a to PRSna.

[0256] Upon receiving the synchronization signal 146, during each cycle of the synchronization signal 146, the DSP 204 utilizes the same Figure 8 In the same manner, the command signals for the states S1a to Sna are transmitted to the frequency controllers FCS1a to FCSna. In addition, upon receiving the synchronization signal 146, during each cycle of the synchronization signal 146, the DSP 204 utilizes the same method as described above. Figure 7 In the same manner, command signals for states S1a to Sna are transmitted to parameter controllers PRS1a to PRSna.

[0257] As mentioned above Figure 8 In the manner described above, upon receiving the command signal for the state S1a to Sna, the frequency controllers FCS1a to FCSna retrieve the frequency levels for the state S1a to Sna from the memory devices of the frequency controllers FCS1a to FCSna and transmit these frequency levels to the driver system 910 for the time period of the state S1a to Sna. Similarly, as described above with reference to Figure 7In the described method, when receiving the instruction signal for the state S1a to Sna, the parameter controllers PRS1a to PRSna obtain the parameter levels for the states S1a to Sna from the memory devices of the parameter controllers PRS1a to PRSna, and transmit these parameter levels to the drive system 910 for the time period of the states S1a to Sna.

[0258] In the above reference Figure 7 and 8 In a manner, in response to receiving the frequency levels for states S1a to Sna and the parameter levels for states S1a to Sna, the driver system 910 generates the drive signals for states S1a to Sna for the frequency levels and states S1a to Sna for the parameter levels, and transmits the drive signals to the RF power supply 222. For example, when the frequency level for state Sna and the parameter level for state Sna are received at a time of transition from a state other than or in addition to state Sna (e.g., state S(n-1)a or state S0) to state Sna, the driver system 910 generates the drive signals for state Sna for the frequency level and state Sna for the parameter level for a time period of state Sna, and transmits the drive signals to the RF power supply 222. The RF power supply 222 generates the state Sna for the frequency level and state Sna for the parameter level of the RF signal 912 when receiving the drive signals for state Sna for the frequency level and parameter level from the driver system 910. For example, upon receiving a driving signal for state Sna of a frequency level from the driver system 910, the RF power supply 222 changes the frequency level of the RF signal 912 from a state different from or other than the state Sna to the state Sna. The state Sna of the RF signal 912 has the frequency level of the state Sna. Upon receiving a driving signal for state Sna of a parameter level from the driver system 910, the RF power supply 222 changes the parameter level of the RF signal 912 from a state different from the state Sna to the state Sna. The state Sna of the RF signal 912 has the parameter level of the state Sna.

[0259] Also, in one embodiment, during each cycle of the synchronization signal 146, there is a time period in which the RF signal 912 has a frequency level of zero and a parameter level of zero. The RF signal 912 has a frequency level of zero and a parameter level of zero during an idle state, such as state S0. Upon receiving the synchronization signal 146, during each cycle of the synchronization signal 146, the DSP 204 does not transmit command signals for states S1a to Sna to the frequency controllers FCS1a to FCSna during the time period of the idle state, and does not transmit command signals for states S1a to Sna to the parameter controllers PRS1a to PRSna.

[0260] In the aforementioned reference Figure 8 In the manner of FIG. 1 , during the time period of the idle state in which the command signal for the frequency level of the state S1a to Sna is not received, the frequency controllers FCS1a to FCSna do not transmit or stop transmitting the frequency level for the state S1a to Sna to the driver system 910. Similarly, in the aforementioned reference Figure 7 In the manner, during the time period of the empty state in which no command signal for the parameter level of the state S1a to Sna is received, the parameter controllers PRS1a to PRSna do not transmit or stop transmitting the parameter level for the state S1a to Sna to the drive system 910.

[0261] When the frequency level for states S1a to Sna and the parameter level for states S1a to Sna are not received, the driver system 910 does not transmit a driving signal to the RF power supply 222. When the driving signal is not received during the time period of the null state, the RF power supply 222 generates an RF signal 912 having a parameter level of zero during the null state. For example, when the driving signal is not received, the RF power supply 222 causes the RF signal 912 to transition from a state other than the null state S0 or other than the null state S0 (e.g., state S1a of the frequency level or state S2a of the frequency level or state Sna of the frequency level) to the null state S0 of the frequency level. Similarly, when the driving signal is not received, the RF power supply 222 causes the RF signal 912 to transition from a state other than the null state S0 or other than the null state S0 of the parameter level (e.g., state S1a of the parameter level or state S2a of the parameter level or state Sna of the parameter level) to the null state S0 of the parameter level.

[0262] In one embodiment, instead of the frequency controllers FCS1a to FCSna and the parameter controllers PRS1a to PRSna, one or more controllers, such as one or more processors, are used to perform the functions described herein as performed by the frequency controllers FCS1a to FCSna and the parameter controllers PRS1a to PRSna.

[0263] In one embodiment, instead of the DSP 204, frequency controllers FCS1a to FCSna, and parameter controllers PRS1a to PRSna, one or more controllers, such as one or more processors, are used to perform the functions described herein as performed by the DSP 204, frequency controllers FCS1a to FCSna, and parameter controllers PRS1a to PRSna.

[0264] In one embodiment, when the RF signal 152 ( Figure 1) has a plurality of variable levels (e.g., four variable levels), the bias RF generator 104 generates the RF signal 168, which is a continuous wave signal having a single variable level or a different number of variable levels (e.g., two, three, eight, or ten variable levels) from the RF signal 152. For another example, when the RF signal 168 ( Figure 1 ) has multiple variable levels (e.g., four variable levels), the source RF generator 102 generates an RF signal 152, which is a continuous wave signal with a single variable level or a different number of variable levels than the RF signal 168 (e.g., two or three or eight or ten variable levels).

[0265] In one embodiment, RF signals 152 and 168 have the same number of levels of variation, such as six levels of variation or eight levels of variation.

[0266] Fig. 10A is an embodiment of a graph 300 for illustrating a synchronization signal 302 .

[0267] Fig. 10B For illustrating the RF signal 912 ( Fig. 9 ) is an embodiment of a graph 1004 of a variable 1006. The variable 1006 is plotted on the y-axis and time t is plotted on the x-axis.

[0268] The variable 1006 periodically changes between the variable levels V8a, 0, V6a, and V2a in synchronization with the synchronization signal 302. For example, the variable 1006 changes between the variable levels V8a, 0, V6a, and V2a during cycle 1 of the synchronization signal 302, and changes between the variable levels V8a, 0, V6a, and V2a again during cycle 2 of the synchronization signal 302. For example, the variable 1006 has a variable level of V8a during the state S4a from time t0 to time t2.5, a variable level of zero during the empty state from time t2.5 to time t5, a variable level of V6a during the state S3a from time t5 to time t7.5, and a variable level of V2a during the state S1a from time t7.5 to time t10. Time t2.5 occurs between time t2 and t3. Similarly, time t7.5 occurs between time t7 and t8. During cycle 1 of the synchronization signal 302, the variable 1006 transitions from variable level V2a to variable level V8a at time t0, transitions from variable level V8a to variable level zero at time t2.5, transitions from variable level zero to variable level V6a at time t5, and transitions from variable level V6a to variable level V2a at time t7.5. During cycle 2 of the synchronization signal 302, the variable 1006 transitions again from variable level V2a to variable level V8a at time t10, transitions from variable level V8a to variable level zero at time t12.5, transitions from variable level zero to variable level V6a at time t15, and transitions from variable level V6a to variable level V2a at time t17.5. Time t12.5 occurs between times t12 and t13. Similarly, time t17.5 occurs between times t17 and t18. Variable level V8a is an example of a variable level for state S4a of RF signal 912, variable level zero is an example of a variable level for state 0 of RF signal 912, variable level V6a is an example of a variable level for state S3a of RF signal 912, and variable level V2a is an example of a variable level for state S1a of RF signal 912.

[0269] Variable level V2a is greater than variable level 0. Also, variable level V6a is greater than variable level V2a, and variable level V8a is greater than variable level V6a. For example, the power value of variable level V6a is lower than the power value of variable level V8a. As another example, all power values ​​of variable level V6a are not greater than the power value of variable level V8a. As another example, the variable level has a maximum value and a minimum value. The maximum value is the largest of all values ​​of the variable level, and the minimum value is the smallest of all values ​​of the variable level. When the maximum value of the first variable level is less than the minimum value of the second variable level, the first variable level is lower than the second variable level, and when the minimum value of the first variable level is greater than the maximum value of the second variable level, the first variable level is higher than the second variable level.

[0270] In one embodiment, instead of implementing variable level V2a, variable 1006 has a variable level of zero. For example, variable 1006 has a variable level of zero from time t7.5 to time t10 and from t17.5 to time t20.

[0271] In one embodiment, the transition time is the time of the transition between two variable levels, and is the time period between the start time of the transition and the end time of the transition. For example, instead of transitioning from variable level V8a to variable level zero at time t2.5, variable 1006 begins its transition from variable level V8a at a first time, and ends its transition to variable level zero at a second time. The first time is before time t2.5 and between time t1 and t2.5, and the second time is after time t2.5 and between time t2.5 and t4. The time period of the transition is the transition time between the first time and the second time.

[0272] In one embodiment, in addition to the synchronization signal 302, a digital pulse signal is also received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 302 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal periodically transitions between four variable levels in the same manner as where the variable 1006 transitions between variable levels V8a, 0, V6a, and V2a. For example, during cycle 1 of the synchronization signal 302, the digital pulse signal transitions from logic level 1 to logic level 3 at time t0, transitions from logic level 3 to logic level 0 at time t2.5, transitions from logic level 0 to logic level 2 at time t5, and transitions from logic level 2 to logic level 1 at time t7.5. Logic level 3 is greater than logic level 2. For example, logic level 3 has a higher DC voltage than the DC voltage of logic level 2. Upon receiving the digital pulse signal, the DSP 204 identifies the time periods of the states S4a, the empty state, S3a, and S1a of the variable 1006 from the digital pulse signal, and generates an instruction signal having these time periods. For example, the time period of the state S4a of the variable 1006 is the same as the time period of the logic level 3 of the digital pulse signal, the time period of the state S0 of the variable 1006 is the same as the time period of the logic level 0 of the digital pulse signal, the time period of the state S3a of the variable 1006 is the same as the time period of the logic level 2 of the digital pulse signal, and the time period of the state S1a of the variable 1006 is the same as the time period of the logic level 1 of the digital pulse signal.

[0273] Fig. 10C is the RF signal 912 ( Fig. 9 ) is an embodiment of a graph 1008 of a variable 1010 versus time t. The variable 1010 is plotted on the y-axis and time t is plotted on the x-axis.

[0274] The variable 1010 periodically changes between the variable levels V8a, V6a, V4a, and V2a in synchronization with the synchronization signal 302. For example, the variable 1010 changes between the variable levels V8a, V6a, V4a, and V2a during cycle 1 of the synchronization signal 302, and changes between the variable levels V8a, V6a, V4a, and V2a again during cycle 2 of the synchronization signal 302. For example, the variable 1010 has a variable level of V8a during state S4a from time t0 to time t2.5, a variable level of V6a during state S3a from time t2.5 to time t5, a variable level of V4a during state S2a from time t5 to time t7.5, and a variable level of V2a during state S1a from time t7.5 to time t10. During cycle 1 of the synchronization signal 302, the variable 1010 transitions from variable level V2a to variable level V8a at time t0, from variable level V8a to variable level V6a at time t2.5, from variable level V6a to variable level V4a at time t5, and from variable level V4a to variable level V2a at time t7.5. During cycle 2 of the synchronization signal 302, the variable 1010 transitions again from variable level V2a to variable level V8a at time t10, from variable level V8a to variable level V6a at time t12.5, from variable level V6a to variable level V4a at time t15, and from variable level V4a to variable level V2a at time t17.5. Variable level V4a is an example of a variable level for state S2a of the RF signal 912.

[0275] Variable level V4a is greater than variable level V2a and less than variable level V6a. For example, the power value of variable level V4a is lower than the power value of variable level V6a and greater than the power value of variable level V2a. For another example, all power values ​​of variable level V4a are not greater than the power value of variable level V6a, and all power values ​​of variable level V2a are not greater than the power value of variable level V4a.

[0276] In one embodiment, instead of implementing variable level V2a, variable 1010 has a variable level of zero. For example, variable 1010 has a variable level of zero from time t7.5 to time t10 and from t17.5 to time t20.

[0277] Fig. 10D For illustrating the RF signal 912 ( Fig. 9 ) is an embodiment of a graph 1012 of a variable 1014 of time. The variable 1014 is plotted on the y-axis and time t is plotted on the x-axis.

[0278] The variable 1014 periodically changes between the variable levels V8a, V2a, V6a, and zero in synchronization with the synchronization signal 302. For example, the variable 1014 changes between the variable levels V8a, V2a, V6a, and zero during cycle 1 of the synchronization signal 302, and changes between the variable levels V8a, V2a, V6a, and zero again during cycle 2 of the synchronization signal 302. For example, the variable 1014 has a variable level of V8a during state S4a from time t0 to time t2.5, a variable level of V2a during state S1a from time t2.5 to time t5, a variable level of V6a during state S3a from time t5 to time t7.5, and a variable level of zero during state S0 from time t7.5 to time t10. During cycle 1 of the synchronization signal 302, the variable 1014 transitions from variable level zero to variable level V8a at time t0, from variable level V8a to variable level V2a at time t2.5, from variable level V2a to variable level V6a at time t5, and from variable level V6a to variable level zero at time t7.5. During cycle 2 of the synchronization signal 302, the variable 1014 transitions again from variable level zero to variable level V8a at time t10, from variable level V8a to variable level V2a at time t12.5, from variable level V2a to variable level V6a at time t15, and from variable level V6a to variable level zero at time t17.5.

[0279] Fig. 10E For illustrating the RF signal 912 ( Fig. 9 ) is an embodiment of a graph 1016 of a variable 1018 of time. The variable 1018 is plotted on the y-axis and time t is plotted on the x-axis.

[0280] The variable 1018 periodically changes between the variable levels V8a, V6a, V2a, and V4a in synchronization with the synchronization signal 302. For example, the variable 1018 changes between the variable levels V8a, V6a, V2a, and V4a during cycle 1 of the synchronization signal 302, and changes between the variable levels V8a, V6a, V2a, and V4a again during cycle 2 of the synchronization signal 302. For example, the variable 1018 has a variable level of V8a during state S4a from time t0 to time t2.5, a variable level of V6a during state S3a from time t2.5 to time t5, a variable level of V2a during state S1a from time t5 to time t7.5, and a variable level of V4a during state S2a from time t7.5 to time t10. During cycle 1 of the synchronization signal 302, the variable 1018 transitions from variable level V4a to variable level V8a at time t0, from variable level V8a to variable level V6a at time t2.5, from variable level V6a to variable level V2a at time t5, and from variable level V2a to variable level V4a at time t7.5. During cycle 2 of the synchronization signal 302, the variable 1018 transitions again from variable level V4a to variable level V8a at time t10, from variable level V8a to variable level V6a at time t12.5, from variable level V6a to variable level V2a at time t15, and from variable level V2a to variable level V4a at time t17.5.

[0281] In one embodiment, instead of implementing variable level V2a, variable 1018 has a variable level of zero. For example, variable 1018 has a variable level of zero from time t5 to time t7.5 and from t15 to time t17.5.

[0282] Fig.10F For illustrating the RF signal 912 ( Fig. 9 ) is an embodiment of a graph 1020 of a variable 1022 of time. The variable 1022 is plotted on the y-axis and time t is plotted on the x-axis.

[0283] The variable 1022 periodically changes between the variable levels V6a, V8a, V4a, and V2a in synchronization with the synchronization signal 302. For example, the variable 1022 changes between the variable levels V6a, V8a, V4a, and V2a during cycle 1 of the synchronization signal 302, and changes between the variable levels V6a, V8a, V4a, and V2a again during cycle 2 of the synchronization signal 302. For example, the variable 1022 has a variable level of V6a during state S3a from time t0 to time t2.5, a variable level of V8a during state S4a from time t2.5 to time t5, a variable level of V4a during state S2a from time t5 to time t7.5, and a variable level of V2a during state S1a from time t7.5 to time t10. During cycle 1 of the synchronization signal 302, the variable 1022 transitions from variable level V2a to variable level V6a at time t0, from variable level V6a to variable level V8a at time t2.5, from variable level V8a to variable level V4a at time t5, and from variable level V4a to variable level V2a at time t7.5. During cycle 2 of the synchronization signal 302, the variable 1022 transitions again from variable level V2a to variable level V6a at time t10, from variable level V6a to variable level V8a at time t12.5, from variable level V8a to variable level V4a at time t15, and from variable level V4a to variable level V2a at time t17.5.

[0284] Figure 10G For illustrating the RF signal 912 ( Fig. 9 ) is an embodiment of a graph 1024 of a variable 1026 of time. The variable 1026 is plotted on the y-axis and time t is plotted on the x-axis.

[0285] The variable 1026 periodically changes between the variable levels V4a, V6a, V8a, and V2a in synchronization with the synchronization signal 302. For example, the variable 1026 changes between the variable levels V4a, V6a, V8a, and V2a during cycle 1 of the synchronization signal 302, and changes between the variable levels V4a, V6a, V8a, and V2a again during cycle 2 of the synchronization signal 302. For example, the variable 1026 has a variable level of V4a during state S2a from time t0 to time t2.5, a variable level of V6a during state S3a from time t2.5 to time t5, a variable level of V8a during state S4a from time t5 to time t7.5, and a variable level of V2a during state S1a from time t7.5 to time t10. During cycle 1 of the synchronization signal 302, the variable 1026 transitions from variable level V2a to variable level V4a at time t0, transitions from variable level V4a to variable level V6a at time t2.5, transitions from variable level V6a to variable level V8a at time t5, and transitions from variable level V8a to variable level V2a at time t7.5. During cycle 2 of the synchronization signal 302, the variable 1026 transitions again from variable level V2a to variable level V4a at time t10, transitions from variable level V4a to variable level V6a at time t12.5, transitions from variable level V6a to variable level V8a at time t15, and transitions from variable level V8a to variable level V2a at time t17.5.

[0286] In one embodiment, instead of implementing variable level V2a, variable 1026 has a variable level of zero. For example, variable 1026 has a variable level of zero from time t7.5 to time t10 and from t17.5 to time t20.

[0287] Fig. 10H For illustrating the RF signal 912 ( Fig. 9 ) is an embodiment of a graph 1028 of a variable 1030 of time. The variable 1030 is plotted on the y-axis and time t is plotted on the x-axis.

[0288] The variable 1030 periodically changes between the variable levels V8a, V6a, V4a, V2a, and zero in synchronization with the synchronization signal 302. For example, the variable 1030 changes between the variable levels V8a, V6a, V4a, V2a, and zero during cycle 1 of the synchronization signal 302, and changes between the variable levels V8a, V6a, V4a, V2a, and zero again during cycle 2 of the synchronization signal 302. For example, the variable 1030 has a variable level of V8a during the state S4a from time t0 to time t2, a variable level of V6a during the state S3a from time t2 to time t4, a variable level of V4a during the state S2a from time t4 to time t6, a variable level of V2a during the state S1a stage from time t6 to time t8, and a variable level of 0 during the empty state from time t8 to time t10. During cycle 1 of the synchronization signal 302, the variable 1030 transitions from variable level zero to variable level V8a at time t0, from variable level V8a to variable level V6a at time t2, from variable level V6a to variable level V4a at time t4, from variable level V4a to variable level V2a at time t6, and from variable level V2a to variable level zero at time t8. During cycle 2 of the synchronization signal 302, the variable 1030 transitions again from variable level zero to variable level V8a at time t10, from variable level V8a to variable level V6a at time t12, from variable level V6a to variable level V4a at time t14, from variable level V4a to variable level V2a at time t16, and from variable level V2a to variable level zero at time t18.

[0289] It should be noted that although a step-down change in the variable level is shown in the graph 1028, in one embodiment, a step-up change in the variable level may occur. For example, during each cycle of the synchronization signal, the variable of the RF signal 912 may increase from zero to a variable level V2a, from a variable level V2a to a variable level V4a, from a variable level V4a to a variable level V6a, and from a variable level V6a to a variable level V8a.

[0290] Fig.10I For illustrating the RF signal 912 ( Fig. 9 ) is an embodiment of a graph 1032 of a variable 1034 of time. The variable 1034 is plotted on the y-axis and time t is plotted on the x-axis.

[0291] The variable 1034 periodically switches between the variable levels V18a, V16a, V14a, V12a, V10a, V8a, V6a, V4a, V2a and zero in synchronization with the synchronization signal 302. For example, the variable 1034 switches between the variable levels V18a, V16a, V14a, V12a, V10a, V8a, V6a, V4a, V2a and zero during cycle 1 of the synchronization signal 302, and switches again between the variable levels V18a, V16a, V14a, V12a, V10a, V8a, V6a, V4a, V2a and zero during cycle 2 of the synchronization signal 302. For example, variable 1034 has a variable level V18a during state S9a from time t0 to time t1, a variable level V16a during state S8a from time t1 to time t2, a variable level V14a during state S7a from time t2 to time t3, a variable level V12a during state S6a from time t3 to time t4, a variable level V10a during state S5a from time t4 to time t5, a variable level V8a during state S4a from time t5 to time t6, a variable level V6a during state S3a from time t6 to time t7, a variable level V4a during state S2a from time t7 to time t8, a variable level V2a during state S1a stage from time t8 to time t9, and a variable level zero during state S0 from time t9 to time t10. During cycle 1 of the synchronization signal 302, variable 1034 transitions from variable level zero to variable level V18a at time t0, from variable level V18a to variable level V16a at time t1, from variable level V16a to variable level V14a at time t2, from variable level V14a to variable level V12a at time t3, from variable level V12a to variable level V10a at time t4, from variable level V10a to variable level V8a at time t5, from variable level V8a to variable level V6a at time t6, from variable level V6a to variable level V4a at time t7, from variable level V4a to variable level V2a at time t8, and from variable level V2a to variable level zero at time t9.During cycle 2 of the synchronization signal 302, variable 1034 again transitions from variable level zero to variable level V18a at time t10, from variable level V18a to variable level V16a at time t11, from variable level V16a to variable level V14a at time t12, from variable level V14a to variable level V12a at time t13, from variable level V12a to variable level V10a at time t14, from variable level V10a to variable level V8a at time t15, from variable level V8a to variable level V6a at time t16, from variable level V6a to variable level V4a at time t17, from variable level V4a to variable level V2a at time t18, and from variable level V2a to variable level zero at time t19.

[0292] Variable level V10a is greater than variable level V8a. Also, variable level V12a is greater than variable level V10a, and variable level V14a is greater than variable level V12a. Variable level V16a is greater than variable level V14a, and variable level V18a is greater than variable level V16a. For example, the power value of variable level V14a is lower than the power value of variable level V16a. As another example, all power values ​​of variable level V14a are not greater than the power value of variable level V16a.

[0293] It should be noted that although a step-down change in the variable level is shown in the graph 1032, in one embodiment, a step-up change in the variable level may occur. For example, during each cycle of the synchronization signal, the variable of the RF signal 912 may increase from zero to a variable level V2a, from a variable level V2a to a variable level V4a, from a variable level V4a to a variable level V6a, from a variable level V6a to a variable level V8a, from a variable level V8a to a variable level V10a, and so on, to a variable level V18a.

[0294] Fig.10J FIG. 1 is a diagram of an embodiment of an RF generator 1070 having multiple power controllers and multiple automatic frequency tuners (AFTs). The RF generator 1070 is a source RF generator 102 or a bias RF generator 104 ( Figure 1 ) is an example. The RF generator 1070 further includes a DSP 204 and an RF power supply. The DSP 204 is an example of a receiver. The power controller includes a power controller PWR S(n-A) , another power controller PWR S(n-1) And so on until including the power controller PWR Sn . AFT includes the automatic frequency tuner AFT S(n-A) , Another automatic frequency tuner AFT S(n-1)etc. until including the automatic frequency tuner AFT Sn The automatic frequency tuner used here is also a frequency controller.

[0295] During state S(nA), the automatic frequency tuner AFT S(n-A) Tuning the frequency of the RF signal 220 generated by the RF power supply 222, or the power controller PWR S(n-A) The power of the RF signal 220 is modified, or both the frequency and the power are modified, where (nA) is an integer less than the integer n, and A is an integer. For example, when n is 4 or 5 or 10, (nA) is 1. For example, during state S(nA), the DSP 204 provides a control signal to the automatic frequency tuner AFT S(n-A) , to indicate the logic level (eg, voltage level) of the state S(nA). Upon receiving the control signal from the DSP 204, the automatic frequency tuner AFT S(n-A) From the automatic frequency tuner AFT S(n-A) The frequency level for state S(nA) is obtained from a database in a memory device of the automatic frequency tuner AFT. S(n-A) The frequency level for state S(nA) is provided to RF power supply 222. Upon receiving the frequency level for state S(nA), RF power supply 222 generates RF signal 220 having the frequency level during state S(nA). Similarly, during state S(nA), DSP 204 provides control signals to power controller PWR S(n-A) , to indicate the logic level of state S(nA). Upon receiving the control signal from DSP 204, the power controller PWR S(n-A) From the power controller PWR S(n-A) The power level PL for state S(nA) is obtained from the database in the memory device of S(n-A) . Power Controller PWR S(n-A) The power level PL to be used for state S (nA) S(n-A) is provided to the RF power supply 222. When receiving the power level PL for state S(nA) S(n-A) When the RF power source 222 generates a power level PL during the state S (nA) S(n-A) RF signal 220.

[0296] Similarly, during state S(n-1), the automatic frequency tuner AFT S(n-1) Tuning the frequency of the RF signal 220 generated by the RF power supply 222, or the power controller PWR S(n-1) The power of the RF signal 220 is modified, or both the frequency and the power are modified. Also, during state Sn, the automatic frequency tuner AFT SnTuning the frequency of the RF signal 220 generated by the RF power supply 222, or the power controller PWR Sn The power of the RF signal 220 is modified, or both the frequency and the power are modified.

[0297] The RF signal 220 is provided to the impedance matching circuit 216 via an output end (e.g., an RF output port) of the RF generator 1070, and the impedance matching circuit 216 generates a modified signal based on the RF signal 220 to provide the modified RF signal to the plasma chamber 112 ( Figure 1 ) electrode, such as a TCP electrode or a bottom electrode. The bottom electrode is located in a chuck of the plasma chamber 112. The electrode of the plasma chamber 112 is an example of a load.

[0298] RF signal 220 is a digital pulse signal having states S(nA) to Sn received by DSP 204 from host controller or host computer 106 ( Figure 1 ) or another processor of the controller, or when received from the analog-to-digital voltage control interface (ADVCI). The digital pulse signal is generated when Fig.10J The input end (e.g., input port) of the DSP 204 shown is received. When the DSP 204 is located in the RF generator 1070, the digital pulse signal is received by the input port of the RF generator 1070. The digital pulse signal is an example of an input signal and is generated by other processors or by the ADVCI. The duty cycle (e.g., duration) of each of the four states S(n-4) to Sn) is determined by the digital pulse signal. The four states occur during the clock cycle of the clock signal, which is Fig.10J Another input terminal (eg, another input port) of the processor shown is receiving a clock signal generated by another processor or by the ADVCI.

[0299] In one embodiment, a level (e.g., power level or frequency level) includes one or more values ​​or quantities within a predetermined range. For example, a first power level has one or more power values ​​within a predetermined range, and a second power level has one or more power values ​​within the predetermined range. The second power level does not include the first power level. For example, the power values ​​of the second power level are all different from the power values ​​of the first power level.

[0300] Figure 10K FIG. 1 is a diagram for explaining an embodiment of an RF signal having four states S(n-3), S(n-2), S(n-1) and Sn, which is used to explain the power level PL of the RF signal. S(n-3) , PL S(n-2) , PL S(n-1) and PL Sn For example, during state Sn, the source RF generator 102 or the bias RF generator 104 ( Figure 1 ) is the power level PL of the RF signal generated by the RF generator Sn The power level PL of the RF signal during the state S(n-1) is lower than S(n-1) Similarly, the power level PL of the RF signal during state S(n-1) is S(n-1) The power level PL of the RF signal during the state S(n-2) is lower than S(n-2) , and the power level PL of the RF signal during state S(n-2) S(n-2) The power level PL of the RF signal during the state S(n-3) is lower than S(n-3) .

[0301] Fig.10L is a diagram for explaining an implementation of another RF signal having four states S(n-3), S(n-2), S(n-1), and Sn. Fig.10L The RF signal shown is also a gradually decreasing signal, but except during the state S(n-1), the RF signal has a power level PL greater than during the state S(n-2). S(n-2) Higher power level PL S(n-1) .

[0302] Figure 10M is a diagram for explaining an embodiment of another RF signal having four states S(n-3), S(n-2), S(n-1), and Sn. Figure 10M The RF signal shown is also a gradually decreasing signal, but except during the state Sn, the RF signal has a power level PL greater than during the state S(n-1). S(n-1) Higher power level PL Sn .

[0303] Fig.10N is a diagram for explaining an implementation of yet another RF signal having four states S(n-3), S(n-2), S(n-1), and Sn. Fig.10N The RF signal shown is also a gradually decreasing signal, but except during state S(n-2), the RF signal has a power level PL greater than during state S(n-3). S(n-3) Higher power level PL S(n-2) .

[0304] Fig.10O FIG. 1 is a diagram for explaining another embodiment of an RF signal having four states S(n-3), S(n-2), S(n-1) and Sn. The RF signal has its power level PL S(n-3) To PL S(n-1) Step up, and from state S(n-1) to its power level PL S(n-1)The power level PL during the drop to state Sn Sn .

[0305] Power Level PL S(n-3) To PL Sn against Fig.10J The power level PL is repeated for each clock cycle of the clock signal received by the processor of the RF generator shown. S(n-3) To PL Sn Repeat multiple clock cycles. The clock signal is received from a clock source or from a processor of a host computer or host controller or ADVCI. The clock signal is generated by a clock source or by a processor of a host computer or a processor of a host controller or ADVCI. Similarly, the power level PL S(n-A) To PL Sn Repeat for states S(nA) to Sn occurring during the clock cycle. Power level PL S(n-A) To PL Sn Repeat for multiple clock cycles. Power level PL S(n-A) To PL Sn Occurs once during an instance of a clock cycle and repeats during subsequent instances of that clock cycle.

[0306] Attention Figures 10B-10I The RF signal shown in either of the above is generated by an RF generator (e.g., source RF generator 102 or bias RF generator 104 ( Figure 1 )) generates the envelope of the sinusoidal RF signal.

[0307] Figure 10P FIG. 1 is a diagram of an embodiment of a method for illustrating achieving a power level of zero during any of states S(nA) to Sn. Figure 10P As shown, instead of the RF signal having a power level of zero in state Sn, the RF signal has a power level of zero in another state, such as S2 or S3.

[0308] In one embodiment, the Figures 10K to 10P The implementations described above with respect to power also apply to frequency. For example, instead of or in addition to multiple power levels, multiple frequency levels may be implemented during states S(nA) to Sn.

[0309] It should be noted that in one embodiment, a power level of zero is achieved when the power level is zero. In one embodiment, a power level of zero is achieved when the power level is close to zero or substantially zero (e.g., within a preset range). An example of a default range value is a range between 0.1 Watt and 1 Watt. Another example of a default range is a range between 0.1 Watt and 0.25 Watt. Yet another example of a default range is a range between 0.1 Watt and 0.5 Watt.

[0310] Transformation Control

[0311] Fig.11A 1 is a diagram of an embodiment of a plasma system 1100 for illustrating the control of the slope of a state transition. The plasma system 1100 includes an RF generator 1102 and a host computer 106. The RF generator 1102 is a source RF generator 102 ( Figure 1 ) or bias RF generator 104 ( Figure 1 ). The RF generator 1102 includes the DSP 204, parameter controllers PRS1a to PRSna, and a plurality of transition parameter controllers PRST1a, PRST2a, PRST(n-1)a, and PRSTna, where n is an integer greater than three. For example, n is four or more. For example, the RF generator 1102 includes four transition parameter controllers, one of which is used for a state transition ST1a between parameter states S1a and S2a during a current cycle of the synchronization signal, another of which is used for a state transition ST2a between parameter states S2a and S3a during the current cycle of the synchronization signal, yet another of which is used for a state transition ST(n-1)a between parameter states S(n-1)a and Sna during the current cycle of the synchronization signal, and another of which is used for a state transition STna between parameter state Sna during the current cycle of the synchronization signal and parameter state S1a during a subsequent cycle of the synchronization signal. The current cycle is before the subsequent cycle. For example, there is no cycle of the synchronization signal between the current and subsequent cycles. As another example, the RF generator 1102 includes five transition parameter controllers.

[0312] The RF generator 1102 further includes frequency controllers FCS1a to FCSna and a plurality of conversion frequency controllers FCST1a, FCST2a, FCST(n-1)a, and FCSTna, wherein n is an integer greater than three. For example, n is four or more. For example, the RF generator 1102 includes four conversion frequency controllers, one of which is used for the state transition ST1a between the frequency states S1a and S2a during the current cycle of the synchronization signal, another of which is used for the state transition ST2a between the frequency states S2a and S3a during the current cycle of the synchronization signal, yet another of which is used for the state transition ST(n-1)a between the frequency states S(n-1)a and Sna during the current cycle of the synchronization signal, and another of which is used for the state transition STna between the frequency state Sna during the current cycle of the synchronization signal and the frequency state S1a during the subsequent cycle of the synchronization signal. For another example, the RF generator 1102 includes five conversion frequency controllers. The RF generator 1102 also includes a driver system 1104 and an RF power source 222 .

[0313] The DSP 204 is coupled to each of the parameter controllers PRS1a to PRSna of the RF generator 1102 and to each of the transition parameter controllers PRST1a to PRSTna of the RF generator 1102. The parameter controllers PRS1a to PRSna and the transition parameter controllers PRST1a to PRSTna are coupled to the driver system 1104, which is coupled to the RF power supply 222.

[0314] Furthermore, the DSP 204 is coupled to each of the frequency controllers FCS1a to FCSna of the RF generator 1102 and to each of the conversion frequency controllers FCST1a to FCSTna of the RF generator 1102. The frequency controllers FCS1a to FCSna and the conversion frequency controllers FCST1a to FCSTna are coupled to the driver system 1104. The functionality of the system 1100 is described below with reference to Fig. 11B illustrate.

[0315] Fig. 11B 1 is a diagram of an embodiment of a system 1100 for illustrating the functionality of the system 1100. The system 1100 includes an RF generator 1102 and a host computer 106. The RF generator 1102 includes a DSP 204, a parameter controller PRS(N±M)a, a transformation parameter controller PRSTa, and a parameter controller PRSNa, where N is an integer greater than zero, and N±M is an integer different from N. For example, when N is 1, N±M is 2 or 3 or 4, and when N is 3, N±M is 4 or 2 or 1. The integer N±M defines M, which is a positive integer. Examples of the parameter controller PRSNa include parameter controllers PRS1a or PRS2a or PRS3a or PRSna( Fig.11A ). Examples of the parameter controller PRS(N±M)a include the parameter controller PRS1a or PRS2a or PRS3a or PRSna ( Fig.11A ), and the parameter controller PRS(N±M)a is different from the parameter controller PRSNa. For example, when the parameter controller PRSNa is PRS4a, the parameter controller PRS(N±M)a is PRS2a or PRS1a.

[0316] Examples of the transition parameter controller PRSTa include parameter controllers PRST1a or PRST2a or PRST3a or PRST(n-1)a or PRSTna( Fig.11A). For example, when the parameter controller PRSNa is the parameter controller PRS1a, and the parameter controller PRS(N±M)a is the parameter controller PRS2a, the transition parameter controller PRSTa is PRST1a, which controls the transition between the states S1a and S2a of the parameter. For another example, when the parameter controller PRSNa is the parameter controller PRS3a, and the parameter controller PRS(N±M)a is the parameter controller PRS5a, the transition parameter controller PRSTa is PRST3a, which controls the transition between the states S3a and S5a of the parameter.

[0317] It should be noted that the RF generator 1102 includes any number of transition parameter controllers, such as the transition parameter controller PRSTa. For example, when the parameter changes from the state S4a of a previous cycle of the synchronization signal 146 to the state S1a of the current cycle, from the state S1a of the current cycle to the state S2a of the current cycle, from the state S2a of the current cycle to the state S3a of the current cycle, and from the state S3a of the current cycle to the state S4a of the current cycle, the RF generator 1102 includes four transition parameter controllers. The four transition parameter controllers include one for controlling the transition from the state S4a of the previous cycle of the synchronization signal 146 to the state S1a of the current cycle, another for controlling the transition from the state S1a of the current cycle to the state S2a of the current cycle, another for controlling the transition from the state S2a of the current cycle to the state S3a of the current cycle, and another for controlling the transition from the state S3a of the current cycle to the state S4a of the current cycle. The previous cycle of the synchronization signal 146 is before the current cycle of the synchronization signal 146.

[0318] The RF generator 1102 further includes a frequency controller FCS(N±M)a, a transition frequency controller FCSTa, and a frequency controller FCSNa, where M and N are defined above. Examples of the frequency controller FCSNa include frequency controllers FCS1a or FCS2a or FCS3a or FCSna ( Fig.11A ). Examples of the frequency controller FCS(N±M)a include frequency controller FCS1a or FCS2a or FCS3a or FCSna ( Fig.11A ), and the frequency controller FCS(N±M)a is different from the frequency controller FCSNa.

[0319] Examples of the transition frequency controller FCSTa include frequency controllers FCST1a or FCST2a or FCST3a or FCST(n-1)a or FCSTna( Fig.11A). For example, if the frequency controller FCSNa is the frequency controller FCS1a, and the frequency controller FCS(N±M)a is the frequency controller FCS2a, the transition frequency controller FCSTa is FCST1a, which controls the transition between the states S1a and S2a of the frequency. For another example, if the frequency controller FCSNa is the frequency controller FCS3a, and the frequency controller FCS(N±M)a is the frequency controller FCS5a, the transition frequency controller FCSTa is FCST3a, which controls the transition between the states S3a and S5a of the frequency.

[0320] It should be noted that the RF generator 1102 includes any number of transition frequency controllers, such as the transition frequency controller FCSTa. For example, when the frequency transitions from the state S4a of the previous cycle of the synchronization signal 146 to the state S1a of the current cycle, from the state S1a of the current cycle to the state S2a of the current cycle, from the state S2a of the current cycle to the state S3a of the current cycle, and from the state S3a of the current cycle to the state S4a of the current cycle, the RF generator 1102 includes four transition frequency controllers. The four transition frequency controllers include one for controlling the transition from the state S4a of the previous cycle of the synchronization signal 146 to the state S1a of the current cycle, another for controlling the transition from the state S1a of the current cycle to the state S2a of the current cycle, yet another for controlling the transition from the state S2a of the current cycle to the state S3a of the current cycle, and another for controlling the transition from the state S3a of the current cycle to the state S4a of the current cycle.

[0321] The DSP 204 is coupled to the parameter controllers PRS(N±M)a and PRSNa, and to the transition parameter controller PRSTa. Furthermore, the DSP 204 is coupled to the frequency controllers FCS(N±M)a and FCSNa, and to the transition frequency controller FCSTa. The parameter controllers PRS(N±M)a and PRSNa, the transition parameter controller PRSTa, the frequency controllers FCS(N±M)a and FCSNa, and the transition frequency controller FCSTa are coupled to the driver system 1104, which is coupled to the RF power supply 222.

[0322] The processor 118 provides the parameter levels for the states S(N±M)a and SNa and the synchronization signal 146 to the DSP 204 via the transmission cable system 214. In addition, the processor 118 provides one or more parameter values ​​for the state transition STa of the parameter to the DSP 204 via the transmission cable system 214. For example, the processor 118 provides one or more parameter values ​​to be achieved during the state transition ST1a of the parameter, one or more parameter values ​​to be achieved during the state transition ST2a of the parameter, one or more parameter values ​​to be achieved during the state transition ST(n-1)a of the parameter, and one or more parameter values ​​to be achieved during the state transition STna of the parameter.

[0323] The state transition STa of the parameter is a transition between the states S(N±M)a and SNa of the parameter. For example, the state transition STa of the parameter is a transition from the state S(N±M)a of the parameter to the state SNa of the parameter, or from the state SNa of the parameter to the state S(N±M)a of the parameter.

[0324] And, the processor 118 provides the frequency levels for the states S(N±M)a and SNa to the DSP 204 via the transmission cable system 214. In addition, the processor 118 provides the frequency values ​​for the state transition STa of the frequency to the DSP 204 via the transmission cable system 214. For example, the processor 118 provides one or more frequency values ​​to be achieved during the state transition ST1a of the frequency, one or more frequency values ​​to be achieved during the state transition ST2a of the frequency, one or more frequency values ​​to be achieved during the state transition ST(n-1)a of the frequency, and one or more frequency values ​​to be achieved during the state transition STna of the frequency.

[0325] The state transition STa of the frequency is a transition between the states S(N±M)a and SNa of the frequency. For example, the state transition STa of the frequency is a transition from the state S(N±M)a of the frequency to the state SNa of the frequency, or from the state SNa of the frequency to the state S(N±M)a of the frequency.

[0326] Upon receiving the parameter levels for the states S(N±M)a and SNa, the DSP 204 provides the parameter levels for the state S(N±M)a of the RF signal 1106 to the parameter controller PRS(N±M)a to store the parameter levels for the state S(N±M)a in a memory device of the parameter controller PRS(N±M)a. The RF signal 1106 is the RF signal 152 or the RF signal 168 ( Figure 1). And, upon receiving one or more parameter values ​​for the state transition STa of the parameter, the DSP 204 provides the one or more parameter values ​​for the state transition STa of the parameter of the RF signal 1106 to the transition parameter controller PRSTa to store the one or more parameter values ​​for the state transition STa in a memory device of the transition parameter controller PRSTa. An example of a parameter value during the state transition STa is an envelope of the parameter of the RF signal 1106 during the state transition STa, such as a zero-to-peak amplitude or a peak-to-peak amplitude. And, in response to receiving the parameter levels for the states S(N±M)a and SNa, the DSP 204 provides the parameter level for the state SNa of the RF signal 1106 to the parameter controller PRSNa to store the parameter level for the state SNa in a memory device of the parameter controller PRSNa.

[0327] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for the state S(N±M)a of the parameter to the parameter controller PRS(N±M)a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for the state S(N±M)a to the parameter controller PRS(N±M)a at the end of the time of transitioning from a state other than or in addition to the state S(N±M)a (e.g., the state S(N±M-1)a or the state S0) to the state S(N±M)a. The command signal for the state S(N±M)a transmitted to the parameter controller PRS(N±M)a includes a time period of the state S(N±M)a during each cycle of the parameter controller PRS(N±M)a to provide the parameter level for the state S(N±M)a to the drive system 1104. Upon receiving the command signal for state S(N±M)a, the parameter controller PRS(N±M)a retrieves the parameter level for state S(N±M)a from the memory device of the parameter controller PRS(N±M)a and transmits the parameter level for the time period of state S(N±M)a to the driver system 1104. For example, the parameter controller PRS(N±M)a transmits the parameter level for state S(N±M)a to the driver system 1104 at the end of the time of transition from a state different from state S(N±M)a to state S(N±M)a. After the time period of state S(N±M)a, during the cycle of the synchronization signal 146, the parameter controller PRS(N±M)a does not transmit the parameter level for state S(N±M)a to the driver system 1104.

[0328] Similarly, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for the state transition STa of the parameter to the transition parameter controller PRSTa during each cycle of the synchronization signal 146. For example, the DSP 204 transmits the command signal for the state transition STa to the transition parameter controller PRSTa at the beginning of the time of transitioning from the state S(N±M)a to the state SNa or from the state S0 to the state SNa. The command signal for the state transition STa transmitted to the transition parameter controller PRSTa includes a time period of the state transition STa during each cycle during which the transition parameter controller PRSTa will provide one or more parameter values ​​for the state transition STa to the driver system 1104. Upon receiving the command signal for the state transition STa, the transition parameter controller PRSTa retrieves one or more parameter values ​​for the state transition STa from the memory device of the transition parameter controller PRSTa and transmits the one or more parameter values ​​to the driver system 1104 for the time period of the state transition STa. For example, the transition parameter controller PRSTa transmits one or more parameter values ​​for the state transition STa to the driver system 1104 at the end of the time of the state S(N±M)a. After the time period of the state transition STa, during the cycle of the synchronization signal 146, the transition parameter controller PRSTa does not transmit one or more parameter values ​​for the state transition STa to the driver system 1104.

[0329] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for the state SNa to the parameter controller PRSNa during each cycle of the synchronization signal 146. For example, the DSP 204 transmits the command signal for the state SNa to the parameter controller PRSNa at the end of the time of transitioning from the state S(N±M)a to the state SNa. The command signal for the state SNa transmitted to the parameter controller PRSNa includes a time period of the state SNa during each cycle of the state SNa during which the parameter controller PRSNa will provide the parameter level for the state SNa to the drive system 1104. Upon receiving the command signal for the state SNa, the parameter controller PRSNa retrieves the parameter level for the state SNa from the memory device of the parameter controller PRSNa and transmits the parameter level to the drive system 1104 for the time period of the state SNa. For example, the parameter controller PRSNa transmits the parameter level for the state SNa to the drive system 1104 at the end of the time of transitioning from the state S(N±M)a to the state SNa. After the time period of state SNa, during the period of the synchronization signal 146 , the parameter controller PRSNa does not transmit the parameter level for state SNa to the drive system 1104 .

[0330] Similarly, upon receiving the frequency levels for the states S(N±M)a and SNa, the DSP 204 provides the frequency level for the state S(N±M)a of the frequency of the RF signal 1106 to the frequency controller FCS(N±M)a to store the frequency level for the state S(N±M)a in the memory device of the frequency controller FCS(N±M)a. And, upon receiving one or more frequency values ​​for the state transition STa of the frequency, the DSP 204 provides the one or more frequency values ​​for the state transition STa of the frequency of the RF signal 1106 to the transition frequency controller FCSTa to store the one or more frequency values ​​for the state transition STa in the memory device of the transition frequency controller FCSTa. An example of a frequency value during the state transition STa is an envelope of the frequency of the RF signal 1106 during the state transition STa, such as a zero-to-peak amplitude or a peak-to-peak amplitude. And, in response to receiving the frequency levels for states S(N±M)a and SNa, DSP 204 provides the frequency level for state SNa of RF signal 1106 to frequency controller FCSNa to store the frequency level for state SNa in a memory device of frequency controller FCSNa.

[0331] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for the state S(N±M)a of the frequency to the frequency controller FCS(N±M)a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for the state S(N±M)a to the frequency controller FCS(N±M)a at the end of the time of transitioning from a state other than or in addition to the state S(N±M)a (e.g., the state S(N±M-1)a or the state S0) to the state S(N±M)a. The command signal for the state S(N±M)a transmitted to the frequency controller FCS(N±M)a includes a time period during which the frequency controller FCS(N±M)a will provide the frequency level for the state S(N±M)a to the state S(N±M)a during each cycle of the driver system 1104. Upon receiving the command signal for the state S(N±M)a, the frequency controller FCS(N±M)a obtains the frequency level for the state S(N±M)a from the memory device of the frequency controller FCS(N±M)a and transmits the frequency level for the time period of the state S(N±M)a to the driver system 1104. For example, the frequency controller FCS(N±M)a transmits the frequency level for the state S(N±M)a to the driver system 1104 at the end of the time of transition from a state different from the state S(N±M)a to the state S(N±M)a. After the time period of the state S(N±M)a, during the cycle of the synchronization signal 146, the frequency controller FCS(N±M)a does not transmit the frequency level for the state S(N±M)a to the driver system 1104.

[0332] Similarly, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for the state transition STa of the frequency to the change frequency controller FCSTa during each cycle of the synchronization signal 146. For example, the DSP 204 transmits the command signal for the state transition STa to the change frequency controller FCSTa at the beginning of the time of transitioning from the state S(N±M)a to the state SNa or from the state S0 to the state SNa. The command signal for the state transition STa transmitted to the change frequency controller FCSTa includes a time period of the state transition STa during each cycle during which the change frequency controller FCSTa will provide one or more frequency values ​​for the state transition STa to the driver system 1104. Upon receiving the command signal for the state transition STa, the change frequency controller FCSTa obtains one or more frequency values ​​for the state transition STa from the memory device of the change frequency controller FCSTa and transmits the one or more frequency values ​​to the driver system 1104 for the time period of the state transition STa. For example, the transition frequency controller FCSTa transmits one or more frequency values ​​for the state transition STa to the driver system 1104 at the end of the time of the state S(N±M)a. After the time period of the state transition STa, during the cycle of the synchronization signal 146, the transition frequency controller FCSTa does not transmit one or more frequency values ​​for the state transition STa to the driver system 1104.

[0333] Upon receiving the synchronization signal 146, a command signal for state SNa is transmitted to the frequency controller FCSNa at the end of the time of transition from state S(N±M)a to state SNa during each cycle of the synchronization signal 146. The command signal for state SNa transmitted to the frequency controller FCSNa includes a time period of state SNa during each cycle of the frequency controller FCSNa to provide the frequency level for state SNa to the driver system 1104. Upon receiving the command signal for state SNa, the frequency controller FCSNa obtains the frequency level for state SNa from a memory device of the frequency controller FCSNa and transmits the frequency level to the driver system 1104 for the time period of state SNa. For example, the frequency controller FCSNa transmits the frequency level for state SNa to the driver system 1104 at the end of the time of transition from state S(N±M)a to state SNa. After the time period of state SNa, during the cycle of the synchronization signal 146, the frequency controller FCSNa does not transmit the frequency level for state SNa to the driver system 1104.

[0334] In response to receiving the parameter level for state S(N±M)a and the frequency level for state S(N±M)a, the driver system 1104 generates a drive signal for a time period of state S(N±M)a at the parameter level and state S(N±M)a at the frequency level, and transmits the drive signal to the RF power supply 222. For example, when the parameter level for state S(N±M)a is received at the end of a transition time of the parameter from state S(N±M-1)a or state S0 to state S(N±M)a, and the frequency level for state S(N±M)a is received at the end of a transition time of the frequency from state S(N±M-1)a or state S0 to state S(N±M)a, the driver system 1104 generates a drive signal for state S(N±M)a at the parameter level and state S(N±M)a at the frequency level for the time period of state S(N±M)a, and transmits the drive signal to the RF power supply 222. Upon receiving the driving signal for the state S(N±M)a from the driver system 1104, the RF power supply 222 generates the state S(N±M)a of the parameter and the state S(N±M)a of the frequency of the RF signal 1106. For example, upon receiving the driving signal for the state S(N±M)a of the parameter and the state S(N±M)a of the frequency from the driver system 1104, the RF power supply 222 generates the state S(N±M)a of the parameter and the state S(N±M)a of the frequency of the RF signal 1106. The state S(N±M)a of the parameter of the RF signal 1106 has the parameter level for the state S(N±M)a during the time period of the state S(N±M)a of the parameter. And, the state S(N±M)a of the frequency of the RF signal 1106 has the frequency level for the state S(N±M)a during the time period of the state S(N±M)a of the frequency.

[0335] Similarly, in response to receiving one or more parameter values ​​for the state transition STa and one or more frequency values ​​for the state transition STa, the driver system 1104 generates a drive signal for a time period of the state transition Sta of the parameter of the RF signal 1106 and the state transition STa of the frequency of the RF signal 1106, and transmits the drive signal to the RF power supply 222. For example, when one or more parameter values ​​for the state transition STa of the parameter are received at the end of the time of the state S(N±M)a or state S0 of the parameter, and one or more frequency values ​​for the state transition STa of the frequency are received at the end of the time of the state S(N±M)a or state S0 of the frequency, the driver system 1104 generates a drive signal for the state transition Sta of the parameter and the state transition STa of the frequency for the time period of the state transition STa of the frequency and the parameter, and transmits the drive signal to the RF power supply 222. When receiving the drive signal for the state transition STa of the frequency and the parameter from the driver system 1104, the RF power supply 222 generates the state transition Sta of the parameter of the RF signal 1106 and the state transition STa of the frequency. For example, upon receiving the driving signals for the state transition Sta of the parameter and the state transition STa of the frequency from the driver system 1104, the RF power supply 222 starts to make the RF signal 1106 transition from the state S(N±M)a of the parameter or the state S0 of the parameter to the state SNa of the parameter, and from the state S(N±M)a of the frequency or the state S0 of the frequency to the state SNa of the frequency. The state transition STa of the parameter of the RF signal 1106 has one or more parameter values ​​for the state transition STa during the time period of the state transition STa of the parameter. And, the state transition STa of the frequency of the RF signal 1106 has a frequency level for the state transition STa during the time period of the state transition STa of the frequency.

[0336] In response to receiving the parameter level for state SNa and the frequency level for state SNa, the driver system 1104 generates a drive signal for a time period of state SNa for the parameter level and state SNa for the frequency level, and transmits the drive signal to the RF power supply 222. For example, when the parameter level for state SNa is received at the end of the transition time of the parameter from state S(N±M)a or S0 to state SNa, and the frequency level for state SNa is received at the end of the transition time of the frequency from state S(N±M)a or S0 to state SNa, the driver system 1104 generates a drive signal for state SNa for the parameter level and state SNa for the frequency level for the time period of state SNa, and transmits the drive signal to the RF power supply 222. Upon receiving the drive signal for state SNa from the driver system 1104, the RF power supply 222 generates the state SNa for the parameter and the state SNa for the frequency of the RF signal 1106. For example, upon receiving a driving signal for a state SNa of a parameter and a state SNa of a frequency from the driver system 1104, the RF power supply 222 generates a state SNa of a parameter and a state SNa of a frequency of the RF signal 1106. The state SNa of the parameter of the RF signal 1106 has a parameter level for the state SNa during a time period of the state SNa of the parameter. Also, the state SNa of the frequency of the RF signal 1106 has a frequency level for the state SNa during a time period of the state SNa of the frequency.

[0337] In one embodiment, instead of the parameter controllers PRS(N±M)a and PRSNa, the transition parameter controller PRSTa, the frequency controllers FCS(N±M)a and FCSNa, and the transition frequency controller FCSTa, one or more controllers, such as one or more processors, are used to perform the functions described herein as performed by the parameter controllers PRS(N±M)a and PRSNa, the transition parameter controller PRSTa, the frequency controllers FCS(N±M)a and FCSNa, and the transition frequency controller FCSTa.

[0338] In one embodiment, instead of the DSP 204, the parameter controllers PRS(N±M)a and PRSNa, the transition parameter controller PRSTa, the frequency controllers FCS(N±M)a and FCSNa, and the transition frequency controller FCSTa, one or more controllers, such as one or more processors, are used to perform the functions described herein as performed by the DSP 204, the parameter controllers PRS(N±M)a and PRSNa, the transition parameter controller PRSTa, the frequency controllers FCS(N±M)a and FCSNa, and the transition frequency controller FCSTa.

[0339] Fig. 12Ais an embodiment of a graph 300 for illustrating a synchronization signal 302 .

[0340] Fig. 12B For illustrating the RF signal 1106 ( Fig.11A and 11B ) is an embodiment of a graph 1204 of a variable 1206 (e.g., frequency or parameter). The variable 1206 is plotted on the y-axis and time t is plotted on the x-axis.

[0341] The variable 1206 periodically switches between the variable levels V8a, V6a, V4a, and V2a in synchronization with the synchronization signal 302. For example, the variable 1206 switches between the variable levels V8a, V6a, V4a, and V2a during cycle 1 of the synchronization signal 302, and switches again between the variable levels V8a, V6a, V4a, and V2a during cycle 2 of the synchronization signal 302. For example, the variable 1206 has a variable level V8a during the variable state S4a of the RF signal 1106 from time t0 to time t1.5, one or more variable values ​​during the state transition ST3a from time t1.5 to time t2.5, a variable level V6a during the state S3a from time t2.5 to time t4, one or more variable values ​​during the state transition ST2a from time t4 to time t5, a variable level V4a during the state S2a from time t5 to time t6.5, one or more variable values ​​during the state transition ST1a from time t6.5 to time t7.5, a variable level V2a during the state S1a from time t7.5 to time t9, and one or more variable values ​​during the state transition ST4a from time t9 to time t10. It should be noted that time t1.5 is between time t1 and t2, and time t6.5 is between time t6 and t7.

[0342] During cycle 1 of the synchronization signal 302, the variable 1206 starts to transition from the variable level V8a to the variable level V6a at time t1.5, and ends the transition at time t2.5. Also, during cycle 1 of the synchronization signal 302, the variable 1206 starts to transition from the variable level V6a to the variable level V4a at time t4, and ends the transition at time t5. During cycle 1 of the synchronization signal 302, the variable 1206 starts to transition from the variable level V4a to the variable level V2a at time t6.5, and ends the transition at time t7.5. Also, during cycle 1 of the synchronization signal 302, the variable 1206 starts to transition from the variable level V2a to the variable level V8a at time t9, and ends the transition at time t10.

[0343] During cycle 2 of the synchronization signal 302, the variable 1206 starts to transition from the variable level V8a to the variable level V6a at time t11.5, and ends the transition at time t12.5. Also, during cycle 2 of the synchronization signal 302, the variable 1206 starts to transition from the variable level V6a to the variable level V4a at time t14, and ends the transition at time t15. During cycle 2 of the synchronization signal 302, the variable 1206 starts to transition from the variable level V4a to the variable level V2a at time t16.5, and ends the transition at time t17.5. Also, during cycle 2 of the synchronization signal 302, the variable 1206 starts to transition from the variable level V2a to the variable level V8a at time t19, and ends the transition at time t20. It should be noted that time t11.5 is between time t11 and t12, and time t16.5 is between time t16 and t17.

[0344] One or more variable values ​​of the state transition ST3a between the variable levels V8a and V6a are less than the variable level V8a and greater than the variable level V6a. Similarly, one or more variable values ​​of the state transition ST2a between the variable levels V6a and V4a are less than the variable level V6a and greater than the variable level V4a. Also, one or more variable values ​​of the state transition ST1a between the variable levels V4a and V2a are less than the variable level V4a and greater than the variable level V2a. One or more variable values ​​of the state transition ST4a between the variable levels V2a and V8a are less than the variable level V8a and greater than the variable level V2a.

[0345] In one embodiment, instead of transitioning to variable level V2a of state S1a, the variable of RF signal 1106 transitions to variable level zero.

[0346] In one embodiment, in addition to the synchronization signal 302, a digital pulse signal is also transmitted by the DSP 204 through the transmission cable system 214 ( Fig. 11B) is received from the processor 118. For example, the synchronization signal 302 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal periodically transitions between four logic levels 8, 6, 4, and 2 in the same manner in which the parameter 1206 transitions between the variable levels V8a, V6a, V4a, and V2a. For example, during cycle 1 of the synchronization signal 302, the digital pulse signal transitions from logic level 8 to logic level 6 at time t1.5 and ends the transition at time t2.5. Also, during cycle 1 of the synchronization signal 302, the digital pulse signal transitions from logic level 6 to logic level 4 at time t4 and ends the transition at time t5. During cycle 1 of the synchronization signal 302, the digital pulse signal transitions from logic level 4 to logic level 2 at time t6.5 and ends the transition at time t7.5. Also, during cycle 1 of the synchronization signal 302, the digital pulse signal transitions from logic level 2 to logic level 8 at time t9 and ends the transition at time t10. Logic level 8 is greater than logic level 6, and logic level 6 is greater than logic level 4. Logic level 4 is greater than logic level 2. For example, the DC voltage of logic level 8 is greater than the DC voltage of logic level 6, and the DC voltage of logic level 6 is greater than the DC voltage of logic level 4. The DC voltage of logic level 4 is greater than the DC voltage of logic level 2.

[0347] In an embodiment, during cycle 2 of the synchronization signal 302, the digital pulse signal transitions from logic level 8 to logic level 6 at time t11.5 and ends the transition at time t12.5. Furthermore, during cycle 2 of the synchronization signal 302, the digital pulse signal transitions from logic level 6 to logic level 4 at time t14 and ends the transition at time t15. During cycle 2 of the synchronization signal 302, the digital pulse signal transitions from logic level 4 to logic level 2 at time t16.5 and ends the transition at time t17.5. Furthermore, during cycle 2 of the synchronization signal 302, the digital pulse signal transitions from logic level 2 to logic level 8 at time t19 and ends the transition at time t20. Upon receiving the digital pulse signal, the DSP 204 identifies the time periods of the states S1a to S4a and the state transitions ST1a to ST4a of the variable 1206 from the digital pulse signal and generates a command signal having these time periods. For example, the time period of the state transition ST1a of variable 1206 is the same as the time period of the digital pulse signal transitioning from logic level 4 to logic level 2 of the digital pulse signal, and the time period of the state transition ST2a of variable 1206 is the same as the time period of the digital pulse signal transitioning from logic level 6 to logic level 4.

[0348] Fig. 12C For illustrating the RF signal 1106 ( Fig.11A and11B ) is an embodiment of a graph 1208 of a variable 1210 (e.g., frequency or parameter). The variable 1210 is plotted on the y-axis and time t is plotted on the x-axis.

[0349] The variable 1210 periodically switches between the variable levels V8a, V6a, V4a, and V2a in synchronization with the synchronization signal 302. For example, the variable 1210 switches between the variable levels V8a, V6a, V4a, and V2a during cycle 1 of the synchronization signal 302, and switches again between the variable levels V8a, V6a, V4a, and V2a during cycle 2 of the synchronization signal 302. For example, the variable 1210 has a variable level V8a during the variable state S4a of the RF signal 1106 from time t0 to time t1.5, one or more variable values ​​during the state transition ST3a from time t1.5 to time t3.5, a variable level V6a during the state S3a from time t3.5 to time t4, one or more variable values ​​during the state transition ST2a from time t4 to time t5, a variable level V4a during the state S2a from time t5 to time t6.5, one or more variable values ​​during the state transition ST1a from time t6.5 to time t7.5, a variable level V2a during the state S1a from time t7.5 to time t9, and one or more variable values ​​during the state transition ST4a from time t9 to time t10. It should be noted that time t3.5 is between time t3 and t4.

[0350] During cycle 1 of synchronization signal 302, variable 1210 begins to transition from variable level V8a to variable level V6a at time t1.5 and ends the transition at time t3.5. Also, during cycle 1 of synchronization signal 302, the remaining transitions of variable 1210 are consistent with those of variable 1206 ( Fig. 12B )same.

[0351] During cycle 2 of the synchronization signal 302, the variable 1210 begins to transition from the variable level V8a to the variable level V6a at time t11.5, and ends the transition at time t13.5. In addition, during cycle 2 of the synchronization signal 302, the remaining transitions of the variable 1210 are the same as those of the variable 1206. It should be noted that time t13.5 is between time t13 and t14. The slope of the state transition ST3a is greater than the slope of the state transition ST2a and the slope of the state transition ST1a.

[0352] In one embodiment, instead of transitioning to variable level V2a of state S1a, variable 1210 transitions to variable level zero.

[0353] In one implementation, the slope of the state transition ST3a is smaller than the slope of the state transition ST2a and the slope of the state transition ST1a.

[0354] In one embodiment, one or more of the state transitions ST1a to STna of the variables described herein have a slope different from the remaining one or more of the state transitions ST1a to STna. For example, the state transition ST1a has a slope different from the slope of the state transition ST2a, the slope of the state transition ST3a, and the slope of the state transition ST4a (e.g., a larger slope or a smaller slope). For example, the state transition ST1a has an angle larger than the angle of the state transition ST2a and the angle of the state transition ST3a and a smaller angle than the angle of the state transition ST4a.

[0355] Fig.12D t is used to illustrate the RF signal 1106 ( Fig.11A and 11B ) of a variable 1214 (e.g., frequency or parameter) of different transition types. The variable 1214 is plotted on the y-axis and time t is plotted on the x-axis.

[0356] The variable 1214 is synchronized with the synchronization signal 302 and periodically switches between the variable levels VRa and VSa, where R and S are real numbers and S is greater than R. For example, the variable 1214 switches between the variable levels VRa and VSa during cycle 1 of the synchronization signal 302 and switches between the variable levels VRa and VSa during cycle 2 of the synchronization signal 302 ( Fig. 12A ) again transitions between the variable levels VRa and VSa during the remaining cycles (e.g., cycle 2) of the RF signal 1106. For example, the variable 1214 has a variable level VSa during a state 1216 of the variable of the RF signal 1106 from time t1 to time t2.5, one or more variable values ​​during a state transition 1220 of the variable from time t2.5 to time t3.5, and a variable level VRa during a state 1218 from time t3.5 to time t5.

[0357] During state transition 1220, variable 1214 has multiple values ​​1222 and 1224 to define a negative linear slope of state transition 1220 between states 1216 and 1218. Values ​​1222 and 1224 are less than the value of variable level VSa and greater than the value of variable level VRa. It should be noted that variable 1214 can have more or less than two values ​​during state transition 1220.

[0358] In one implementation, during state transition 1220 , variable 1214 has multiple values ​​1226 and 1228 to define a slope of state transition 1220 between states 1216 and 1218 .

[0359] In one implementation, during state transition 1220, variable 1214 has multiple values ​​1230 and 1232 to define a concave slope of state transition 1220 between states 1216 and 1218. The convex slope and concave slope of variable 1214 are each examples of a curved slope.

[0360] Fig.12E For illustrating the RF signal 1106 ( Fig.11A and 11B ) of a variable 1252 (e.g., frequency or parameter) of different transition types. The variable 1252 is plotted on the y-axis and time t is plotted on the x-axis.

[0361] The variable 1252 is synchronized with the synchronization signal 302 and periodically switches between the variable levels VRa and VSa. For example, the variable 1252 switches between the variable levels VRa and VSa during cycle 1 of the synchronization signal 302 and switches between the variable levels VRa and VSa during cycle 2 of the synchronization signal 302. Fig. 12A ) again transitions between the variable levels VRa and VSa during the remaining cycles (e.g., cycle 2) of the RF signal 1106. For example, the variable 1214 has a variable level VRa during a state 1218 of the variable of the RF signal 1106 from time t1 to time t2.5, one or more variable values ​​during a state transition 1260 of the variable from time t2.5 to time t3.5, and a variable level VSa during a state 1216 from time t3.5 to time t5.

[0362] During state transition 1260, variable 1252 has multiple values ​​1262 and 1264 to define a positive linear ramp of state transition 1260 between states 1216 and 1218. Values ​​1262 and 1264 are less than the value of variable level VSa and greater than the value of variable level VRa. It should be noted that variable 1252 can have more or less than two values ​​during state transition 1260.

[0363] In one embodiment, during state transition 1260 , variable 1252 has multiple values ​​1266 and 1268 to define the slope of state transition 1260 between states 1216 and 1218 .

[0364] In one embodiment, during state transition 1260, variable 1252 has multiple values ​​1270 and 1272 to define a concave slope of state transition 1260 between states 1216 and 1218. The convex slope and concave slope of variable 1252 are each examples of a curved slope.

[0365] Fig.12F FIG. 1 is a diagram of an implementation scheme of a pulse shaping method. Fig.12FAs shown, the RF generator 1102 ( Fig. 11B ) generated by the RF signal 1106 ( Fig. 11B ) is changed to have a negative slope to reduce the pulse width for one or more of the states S(nA) to Sn. For example, instead of a vertical or substantially vertical transition from state S(n-1) to state Sn, a ramp-type transition with a negative slope is provided between states S(n-1) and Sn. Due to the negative slope, the power level PL of the RF signal 1106 during state S(n-1) is S(n-1) The pulse width is reduced. The power level used to achieve the ramp transition is provided from the host computer or host controller to the RF generator 1102 to achieve the ramp transition.

[0366] In one embodiment, a ramp transition between frequency levels occurs. For example, one frequency level transitions to another frequency level via a positive or negative ramp transition. The frequency levels during the ramp transition are provided from the host computer to the RF generator 1102 to generate an RF signal 1106 having these frequency levels.

[0367] Figure 12G FIG. 1 is a diagram showing another embodiment of a pulse shaping method. Figure 12G As shown, RF generator 1102 ( Fig. 11B ) generated by the RF signal 1106 ( Fig. 11B )The slope of the transition from state S(nA) to state S(n-A+1) is steeper (e.g., greater) than the slope of the transition of the RF signal 1106 from state S(n-1) to state Sn.

[0368] In one embodiment, the slope of the transition of the RF signal 1106 generated by the RF generator 1102 from state S(nA) to state S(n-A+1) is less steep (e.g., lower) than the slope of the transition of the RF signal 1106 from state S(n-1) to state Sn.

[0369] Fig.12H FIG. 1 is a diagram showing another embodiment of a pulse shaping method. Fig.12H , RF generator 1102 ( Fig. 11B ) generated by the RF signal 1106 ( Fig. 11B ) The slope of the transition from state S(nA) to state S(n-A+1) is curved, such as a semi-parabola or exponential change. Also, the slope of the transition of RF signal 1106 from state S(n-1) to state Sn is curved.

[0370] Fig.12I FIG. 1 is a diagram of another embodiment of a pulse shaping method, such as Fig.12I As shown, RF generator 1102 ( Fig. 11B) generated by the RF signal 1106 ( Fig. 11B )The slope of the transition from state S(nA) to state S(n-A+1) is curved, and the slope of the transition of RF signal 1106 from state S(n-1) to state Sn is linear.

[0371] Fig.12J FIG. 1 is a diagram of another embodiment of a pulse shaping method. Fig.12J As shown, the RF generator 1102 ( Fig. 11B ) generated by the RF signal 1106 ( Fig. 11B ) is modified to have a positive or negative slope to reduce the pulse width of the RF signal 1106 for one or more of the states S(nA) to Sn. For example, instead of a vertical or substantially vertical transition from state S(n-1) to state Sn, a ramped transition with a negative slope is provided between states S(nA) and S(n-A+1). Due to the negative slope, the power level PL of the RF signal 1106 during state S(nA) is S(n-A) As another example, instead of a vertical or substantially vertical transition from state S(n-1) to state Sn, a ramp transition with a positive slope is provided between state S(n-1) and Sn. Due to the positive slope, the power level PL of the RF signal 1106 during state Sn is Sn The pulse width is reduced.

[0372] Figure 12K FIG. 1 is a diagram for explaining another embodiment of a pulse shaping method. Figure 12K , RF generator 1102 ( Fig. 11B ) generated by the RF signal 1106 ( Fig. 11B ) The transition of the RF signal 1106 from state S(nA) to state S(n-A+1) has a linear slope, such as a negative straight slope, and the transition of the RF signal 1106 from state S(n-1) to state Sn has a curved slope, such as a concave slope. The curved slope has a positive slope.

[0373] Figure 12L FIG. 1 is a diagram for explaining another embodiment of a pulse shaping method. Figure 12L , RF generator 1102 ( Fig. 11B ) generated by the RF signal 1106 ( Fig. 11B ) The transition of the RF signal 1106 from state S(nA) to state S(n-A+1) has a linear slope, such as a negative straight slope, and the transition of the RF signal 1106 from state S(n-1) to state Sn has a curved slope, such as a convex slope. The curved slope has a positive slope.

[0374] EtherCAT Cable

[0375] Fig.13A 13 is a diagram of an embodiment of a system 1300, which is used to illustrate the transmission of information between various components of a plasma system via one or more Ethernet control automation technology (EtherCAT) cables. An example of an EtherCAT cable is an Ethernet cable. EtherCAT is an Ethernet-based protocol for real-time distributed control of information and is suitable for automation technology. When an EtherCAT frame or data packet passes through an EtherCAT slave, the EtherCAT slave reads the data addressed to it and processes the data on the fly. Similarly, when an EtherCAT frame passes through an EtherCAT slave, input data is inserted into the EtherCAT frame from the EtherCAT slave. The EtherCAT frame is not completely received by the EtherCAT slave before being processed, but processing begins as soon as possible. The transmission of input data from the EtherCAT slave is also performed with a minimum delay of a small bit time.

[0376] The system 1300 includes a host computer 106, a source RF generator 102, a bias RF generator 104, a source match 108, and a bias match 110, each of which is an example of a component of a plasma tool or a plasma system. The component of the plasma tool that transmits one or more EtherCAT frames is referred to herein as a master EtherCAT device, and the component of the plasma tool that receives one or more EtherCAT frames is referred to herein as a slave EtherCAT device. For example, each of the bias RF generator 104, the source match 108, and the bias match 110 is an example of a slave EtherCAT device, and the source RF generator is an example of a master EtherCAT device. Each of the source RF generator 102, the bias RF generator 104, the source match 108, and the bias match 110 is an example of a component of a plasma system. One or more EtherCAT frames are sometimes referred to herein as a pulse train.

[0377] The host computer 106 includes a processor 118 and a communication controller 1302. As used herein, examples of a communication controller include an ASIC, a PLD, a controller, and a processor.

[0378] Processor 118 is coupled to communication controller 1302. Communication controller 1302 is coupled to port 1308 of source RF generator 102 via EtherCAT cable 1304. As used herein, examples of Ethernet cables include twisted pair cables. For example, the Ethernet cable is 100BASE-TX TM or 100BASE-T4 TMThe EtherCAT cable 1306 is capable of transmitting data at a speed of more than 100 megabits per second (Mbps). In addition, another port 1310 of the source RF generator 102 is coupled to a port 1312 of the bias RF generator 104 via an EtherCAT cable 1306 .

[0379] The processor 118 transmits, for example, the synchronization signal 146 ( Figure 7 ), source RF generator variable information, and bias RF generator variable information are transmitted to the communication controller 1302. Examples of the timing information of the synchronization signal 146 include the time during each cycle of the synchronization signal 146 when the synchronization signal 146 changes its logic level (e.g., from 1 to 0 or from 0 to 1) and the number of cycles of the synchronization signal 146. The timing information also includes the logic levels 0 and 1 of the synchronization signal 146. Examples of the source RF generator variable information include variable levels for each state of the operation of the source RF generator 102, such as parameter levels or frequency levels. For example, the source RF generator variable information includes the power level and frequency level of the states S1a, S1b, and S1c of the variable of the RF signal 152 generated by the source RF generator 102. Examples of the bias RF generator variable information include variable levels for each state of the operation of the bias RF generator 104, such as parameter levels or frequency levels. For example, the bias RF generator variable information includes power levels and frequency levels for states S1 a to Sna of the variables of the RF signal 168 generated by the bias RF generator 104 .

[0380] The communication controller 1302 receives the processor data 1311 and applies the EtherCAT protocol to embed the processor data 1311, thereby generating one or more EtherCAT frames 1314 having the processor data 1311, and transmits the one or more EtherCAT frames 1314 to the port 1308 of the source RF generator 102 via the EtherCAT cable 1304. The communication controller of the source RF generator 102 receives the one or more EtherCAT frames 1314 via the port 1308, identifies the source RF generator variable information and the timing information of the synchronization signal 146 from the one or more EtherCAT frames 1314, and transmits the source RF generator variable information and the timing information to the DSP 204 of the source RF generator 102.

[0381] In addition, the communication controller of the source RF generator 102 transmits a request for information such as source RF generator measurement information to the DSP 204 of the source RF generator 102. Examples of source RF generator measurement information include factors determined or identified by the DSP 204 of the source RF generator 102. Examples of factors identified by the DSP 204 of the source RF generator 102 include references, such as complex voltage currents or complex voltages or complex powers or complex currents or complex impedances. The reference is measured by a sensor for each state of the RF signal 152. The sensor measuring the reference is located within the source RF generator 102, or is located outside the source RF generator 102 and coupled to the output terminal 154 of the source RF generator 102. The complex factor includes an amplitude and a phase. For example, a complex voltage includes an amplitude of the complex voltage and a phase of the complex voltage. Complex voltage and current include voltage amplitude, current amplitude, and a phase between voltage and current. The sensor measures the reference and provides the reference to the DSP 204 of the source RF generator 102. DSP 204 of source RF generator 102 identifies a reference and / or determines a frequency of the reference for each state of RF signal 152 from the measured reference. For example, DSP 204 of source RF generator 102 applies a Fourier transform to the value of the reference to determine the frequency of the reference. The frequency of the reference is an example of a factor.

[0382] Upon receiving the request for information, the DSP 204 of the source RF generator 102 provides the source RF generator measurement information to the communication controller of the source RF generator 102. Upon receiving the source RF generator measurement information, the communication controller of the source RF generator 102 embeds the source RF generator measurement information into one or more EtherCAT frames 1314 and transmits the one or more EtherCAT frames 1314 to the port 1312 of the bias RF generator 104 via the port 1310 of the source RF generator 102 and the EtherCAT cable 1306.

[0383] The communication controller of the bias RF generator 104 receives one or more EtherCAT frames 1314 via the port 1312 , identifies the bias RF generator variable information and the timing information of the synchronization signal 146 from the one or more EtherCAT frames 1314 , and transmits the bias RF generator variable information and the timing information to the DSP 204 of the bias RF generator 104 .

[0384] In addition, the communication controller of the bias RF generator 104 transmits a request for information such as bias RF generator measurement information to the DSP 204 of the bias RF generator 104. Examples of bias RF generator measurement information include factors determined or identified by the DSP 204 of the bias RF generator 104. Examples of factors identified by the DSP 204 of the bias RF generator 104 include a reference, such as a complex voltage and current or a complex voltage or a complex power or a complex current or a complex impedance. The reference is measured by a sensor for each state of the RF signal 168. The sensor that measures the reference is located within the bias RF generator 104, or is located outside the bias RF generator 104 and coupled to the output 160 of the bias RF generator 104. The sensor measures the reference and provides the reference to the DSP 204 of the bias RF generator 104. The DSP 204 of the bias RF generator 104 identifies the reference for each state of the RF signal 168 from the measured reference and determines the frequency of the reference. For example, the DSP 204 of the bias RF generator 104 applies a Fourier transform to the value of the reference to determine the frequency of the reference.

[0385] Upon receiving the request for information, the DSP 204 of the bias RF generator 104 provides the bias RF generator measurement information to the communication controller of the bias RF generator 104. Upon receiving the bias RF generator measurement information, the communication controller of the bias RF generator 104 embeds the bias RF generator measurement information within one or more EtherCAT frames 1314 and transmits the one or more EtherCAT frames 1314 to the port 1310 of the source RF generator 102 via the port 1312 of the bias RF generator 104 and the EtherCAT cable 1306. The communication controller of the source RF generator 102 receives the one or more EtherCAT frames 1314 via the port 1310 and transmits the one or more EtherCAT frames 1314 to the communication controller 1302 of the host computer 106 via the port 1308 and the EtherCAT cable 1304.

[0386] The communication controller 1302 of the host computer 106 applies the EtherCAT protocol to the one or more EtherCAT frames 1314 to obtain or extract source RF generator measurement information for each state of the variable of the source RF signal 152 and bias RF generator measurement information for each state of the variable of the bias RF signal 168 from the one or more EtherCAT frames 1314. The communication controller 1302 provides the source RF generator measurement information and the bias RF generator measurement information to the processor 118. The processor 118 determines whether to modify the variables of the source RF generator 102 during each state of the variable of the RF signal 152, or the variables of the bias RF generator 104 during each state of the variable of the RF signal 168, or a combination thereof based on the source RF generator measurement information or the bias RF generator measurement information or a combination thereof. Processor 118 controls states of variables of RF signal 152 generated by source RF generator 102 based on the state-modified variables of source RF generator 102, and / or controls states of variables of RF signal 168 generated by bias RF generator 104 based on the state-modified variables of bias RF generator 104.

[0387] It should be noted that in one embodiment, the one or more EtherCAT frames 1314 are not stored in the source RF generator 102, and the one or more EtherCAT frames 1314 are not stored in the bias RF generator 104. For example, the one or more EtherCAT frames 1314 are in a constant moving state in the memory device of the communication controller of the source RF generator 102, and the one or more EtherCAT frames 1314 are in a constant moving state in the memory device of the communication controller of the bias RF generator 104. For example, when the source RF generator variable information and the source RF generator measurement information are transmitted between the communication controller of the source RF generator 102 and the DSP 204 of the source RF generator 102, the one or more EtherCAT frames 1314 are moved in the memory device, such as from one register to another register in the register string of the communication controller of the source RF generator 102. As another example, when the bias RF generator variable information and the bias RF generator measurement information are transmitted between the communication controller of the bias RF generator 104 and the DSP 204 of the bias RF generator 104, one or more EtherCAT frames 1314 are moved within a memory device, such as from one register in a register string of the communication controller of the bias RF generator 104 to another register.

[0388] Fig. 13B1 is a diagram of an embodiment of a system 1350 for illustrating information transmission between various components of a plasma system via one or more EtherCAT cables. The system 1350 includes a host computer 106, a source RF generator 102, a bias RF generator 104, a source matching section 108, and a bias matching section 110. The communication controller 1302 is coupled to a port 1312 of the bias RF generator 104 via an EtherCAT cable 1306.

[0389] The processor 118 transmits the processor data 1311 to the communication controller 1302. The communication controller 1302 receives the processor data 1311 and applies the EtherCAT protocol to embed the timing information of the synchronization signal 146 and the source RF generator variable information of the processor data 1311 to generate one or more EtherCAT frames 1352 having the timing information of the synchronization signal 146 and the source RF generator variable information, and transmits the one or more EtherCAT frames 1352 to the port 1308 of the source RF generator 102 via the EtherCAT cable 1304. The communication controller of the source RF generator 102 receives the one or more EtherCAT frames 1352 via the port 1308, identifies the source RF generator variable information, and performs the same process as described above with reference to FIG. Fig.13A The same functions are described until the source RF generator measurement information is received from the DSP 204 of the source RF generator 102. When the source RF generator measurement information is received, the communication controller of the source RF generator 102 embeds the source RF generator measurement information into one or more EtherCAT frames 1352 and transmits the one or more EtherCAT frames 1352 to the communication controller 1302 of the host computer 106 via the port 1308 of the source RF generator 102 and the EtherCAT cable 1304.

[0390] In a similar manner, the communication controller 1302 receives the processor data 1311 and applies the EtherCAT protocol to embed the timing information of the synchronization signal 146 and the bias RF generator variable information of the processor data 1311, thereby generating one or more EtherCAT frames 1354 having the timing information of the synchronization signal 146 and the bias RF generator variable information, and transmits the one or more EtherCAT frames 1354 to the port 1312 of the bias RF generator 104 via the EtherCAT cable 1306. The communication controller of the bias RF generator 104 receives the one or more EtherCAT frames 1354 via the port 1312, identifies the bias RF generator variable information, and performs the same process as described above with reference to FIG. Fig.13AThe same functions are described until the bias RF generator measurement information is received from the DSP 204 of the bias RF generator 104. When the bias RF generator measurement information is received, the communication controller of the bias RF generator 104 embeds the bias RF generator measurement information into one or more EtherCAT frames 1354 and transmits the one or more EtherCAT frames 1354 to the communication controller 1302 of the host computer 106 via the port 1312 of the bias RF generator 104 and the EtherCAT cable 1306.

[0391] The communication controller 1302 of the host computer 106 applies the EtherCAT protocol to the one or more EtherCAT frames 1352 to obtain or extract the source RF generator measurement information from the one or more EtherCAT frames 1352. The communication controller 1302 provides the source RF generator measurement information to the processor 118.

[0392] Similarly, the communication controller 1302 of the host computer 106 applies the EtherCAT protocol to the one or more EtherCAT frames 1354 to obtain or extract the bias RF generator measurement information from the one or more EtherCAT frames 1354. The communication controller 1302 provides the bias RF generator measurement information to the processor 118. The processor 118 performs the same process as described above with reference to Fig.13A Describes the same functionality.

[0393] It should be noted that in one embodiment, one or more EtherCAT frames 1352 are not stored in the source RF generator 102, and one or more EtherCAT frames 1354 are not stored in the bias RF generator 104. For example, one or more EtherCAT frames 1352 are in a constant state of movement within a memory device of a communication controller of the source RF generator 102, and one or more EtherCAT frames 1354 are in a constant state of movement within a memory device of a communication controller of the bias RF generator 104. For example, when source RF generator variable information and source RF generator measurement information are transmitted between the communication controller of the source RF generator 102 and the DSP 204 of the source RF generator 102, the one or more EtherCAT frames 1352 are moved within the memory device, such as from one register to another register in a register string of the communication controller of the source RF generator 102. As another example, when the bias RF generator variable information and the bias RF generator measurement information are transmitted between the communication controller of the bias RF generator 104 and the DSP 204 of the bias RF generator 104, one or more EtherCAT frames 1354 are moved within a memory device, such as from one register in a register string of the communication controller of the bias RF generator 104 to another register.

[0394] Fig.14 1400. The EtherCAT frame 1400 is a diagram of an embodiment of an EtherCAT frame 1400. The EtherCAT frame 1400 is one or more EtherCAT frames 1314 ( Fig.13A ) is an example of any one of the following. And, the EtherCAT frame 1400 is one or more EtherCAT frames 1352 ( Fig. 13B ) and one or more EtherCAT frames 1354 ( Fig. 13B ) in any one of the examples.

[0395] In one embodiment, the terms frame and packet are used interchangeably herein. EtherCAT frame 1400 includes fields 1401 , 1403 , 1402 , 1404 , 1406 , 1408 , 1410 , 1412 , 1414 , 1416 , and 1418 .

[0396] Field 1401 contains a start frame delimiter that identifies the start of the EtherCAT frame 1400. Field 1402 contains the source address of the EtherCAT frame 1400. An example of a source address is the address of the communication controller of the host computer 106 that generates the EtherCAT frame 1400. Field 1403 of the EtherCAT frame 1400 contains the order in which the EtherCAT frame 1400 is to be propagated to the various components of the plasma system. An example of this order includes a sequence from the communication controller 1302 to the source RF generator 102 to the bias RF generator 104, from the bias RF generator 104 back to the source RF generator 102, and from the source RF generator 102 to the processor 118. Another example of this order includes a sequence from the communication controller 1302 to the source RF generator 102, and from the source RF generator 102 back to the communication controller 1302.

[0397] Field 1404 contains the destination address of the EtherCAT frame 1400. An example of the destination address is the address of the communication controller 1302 of the host computer 106, and the address of the communication controller 1302 is the final destination of the EtherCAT frame 1400.

[0398] Field 1406 contains the information identifying the source RF generator 102 ( Fig.13A) to distinguish the source RF generator 102 from other RF generators of the plasma system, such as a media access control (MAC) address. Field 1408 contains source RF generator variable information, and field 1410 contains source RF generator measurement information. The address identifying the source RF generator 102 is used by the communication controller of the source RF generator 102 to determine that data in field 1408 will be provided to the DSP 204 of the source RF generator 102, and to determine that data received from the DSP 204 of the source RF generator 102 will be stored in field 1410.

[0399] Field 1412 contains the identifier of the bias RF generator 104 ( Fig.13A ) to distinguish the bias RF generator 104 from other RF generators of the plasma system, such as a MAC address. Field 1414 contains bias RF generator variable information, and field 1416 contains bias RF generator measurement information. The address identifying the bias RF generator 104 is used by the communication controller of the bias RF generator 104 to determine that data in field 1414 will be provided to the DSP 204 of the bias RF generator 104, and to determine that data received from the DSP 204 of the bias RF generator 104 will be stored in field 1416.

[0400] Field 1418 contains a cyclic redundancy check (CRC) for one or more of fields 1408 and 1414. For example, the CRC is generated by communication controller 1302 ( Fig.13A ) is executed after receiving the EtherCAT frame 1400 to determine whether the source RF generator variable information transmitted by the communication controller 1302 in field 1408 matches the source RF generator variable information received by the communication controller 1302 in field 1408 to determine the validity of the EtherCAT frame 1400.

[0401] In one embodiment, fields 1406, 1408, and 1410 or fields 1412, 1414, and 1416 are not included in the EtherCAT frame 1400. For example, when the EtherCAT frame 1400 is one or more EtherCAT frames 1452 ( Fig. 13B ), the EtherCAT frame 1400 does not include fields 1412, 1414, and 1416 for biasing the RF generator 104.

[0402] In one embodiment, fields 1406, 1408, and 1410 or fields 1412, 1414, and 1416 are included in the EtherCAT frame 1400, but are empty. For example, when the EtherCAT frame 1400 is transmitted to the source RF generator 102, one or more EtherCAT frames 1452 ( Fig. 13B ), the EtherCAT frame 1400 does not include any data or information for biasing the RF generator 104 in fields 1412, 1414, and 1416.

[0403] Fig.15A 1 is a diagram of an embodiment of a system 1500 for illustrating information transmission between various components of a plasma system via one or more EtherCAT cables. The system 1500 includes a host computer 106, a source RF generator 102, a bias RF generator 104, a source match 108, and a bias match 110.

[0404] The port 1310 of the source RF generator 102 is coupled to the port 1502 of the source matching section 108 via the EtherCAT cable 1306. Also, the other port 1505 of the source matching section 108 is coupled to the port 1312 of the bias RF generator 104 via the EtherCAT cable 1504. The other port 1506 of the bias RF generator 104 is coupled to the port 1510 of the bias matching section 110 via the EtherCAT cable 1508.

[0405] Processor 118 transmits processor data 1501, which includes processor data 1302 ( Fig.13A ), and includes matching section data, such as bias matching section data or source matching section data, or a combination thereof. The processor data 1501 is transmitted to the communication controller 1302. An example of the source matching section data includes one or more specifications of one or more components of the source matching section 108, and an example of the bias matching section data includes one or more specifications of one or more components of the bias matching section 110. An example of the one or more specifications of one or more components of the source matching section 108 includes a capacitance value of a capacitor of the source matching section 108 and an inductance value of an inductor of the source matching section 108. An example of the one or more specifications of one or more components of the bias matching section 110 includes a capacitance value of a capacitor of the bias matching section 110 and an inductance value of an inductor of the bias matching section 110.

[0406] The communication controller 1302 receives the processor data 1501 and applies the EtherCAT protocol to embed the processor data 1501, thereby generating one or more EtherCAT frames 1512 having the processor data 1501, and transmits the one or more EtherCAT frames 1512 to the port 1308 of the source RF generator 102 via the EtherCAT cable 1304. The communication controller of the source RF generator 102 receives the one or more EtherCAT frames 1512 via the port 1308, identifies the source RF generator variable information and the timing information of the synchronization signal 146 from the one or more EtherCAT frames 1512, and transmits the source RF generator variable information and the timing information to the DSP 204 of the source RF generator 102.

[0407] In addition, the communication controller of the source RF generator 102 transmits a request for information such as source RF generator measurement information and source state information of the RF signal 152 to the DSP 204 of the source RF generator 102. Examples of the source state information of the RF signal 152 include timing information of the state of the RF signal 152 and / or timing information of state transitions. For example, the timing information of the state of the RF signal 152 includes the time when the RF signal 152 changes its variable level and the time the RF signal 152 stays at the variable level. For further explanation, refer to Fig. 10B The timing information of the state S4a of the RF signal 152 includes the time t0 when the variable 1006 of the RF signal 152 changes from the variable level V2a to the variable level V8a, the time period between the time t0 and t2.5 when the variable 1006 of the RF signal 152 is maintained at the variable level V8a, the time t2.5 when the variable 1006 of the RF signal 152 changes from the variable level V8a to the variable level zero, the time t5 when the variable 1006 of the RF signal 152 changes from the variable level zero to the variable level V6a, the time period between the time t5 and t7.5 when the variable 1006 of the RF signal 152 is maintained at the variable level V6a, the time t7.5 when the variable 1006 of the RF signal 152 changes from the variable level V6a to the variable level V2a, and the time period between the time t7.5 and t10 when the variable 1006 of the RF signal 152 is maintained at the variable level V2a.

[0408] For another example, refer to Fig. 12BThe timing information of the state S4a of the RF signal 152 includes the time t0 when the variable 1206 of the RF signal 152 changes from the variable level V2a to the variable level V8a and the time period between the time t0 and t1.5 when the variable 1206 of the RF signal 152 is maintained at the variable level V8a. The timing information of the state transition ST3a of the variable 1206 of the RF signal 152 includes the time t1.5 when the variable 1206 of the RF signal 152 starts to change from the variable level V8a to the variable level V6a and the time t2.5 when the variable 1206 of the RF signal 152 stops changing. Similarly, the timing information of the state transition ST2a of the variable 1206 of the RF signal 152 includes the time t4 when the variable 1206 of the RF signal 152 starts to transition from the variable level V6a to the variable level V4a and the time t5 when the variable 1206 of the RF signal 152 stops transitioning, the timing information of the state transition ST1a of the variable 1206 of the RF signal 152 includes the time t6.5 when the variable 1206 of the RF signal 152 starts to transition from the variable level V4a to the variable level V2a and the time t7.5 when the variable 1206 of the RF signal 152 stops transitioning, and the timing information of the state transition ST4a of the variable 1206 of the RF signal 152 includes the time t9 when the variable 1206 of the RF signal 152 starts to transition from the variable level V2a to the variable level V8a and the time t10 when the variable 1206 of the RF signal 152 stops transitioning.

[0409] Upon receiving the request for information, the DSP 204 of the source RF generator 102 provides the source RF generator measurement information and the source status information to the communication controller of the source RF generator 102. Upon receiving the source RF generator measurement information and the source status information, the communication controller of the source RF generator 102 embeds the source RF generator measurement information and the source status information into one or more EtherCAT frames 1512 and transmits the one or more EtherCAT frames 1512 to the port 1502 of the source matching section 108 via the port 1310 of the source RF generator 102 and the EtherCAT cable 1306.

[0410] The communication controller of the source matching section 108 receives one or more EtherCAT frames 1512 via the port 1502 of the source matching section 108, extracts source matching section data and source status information from the one or more EtherCAT frames 1512, and transmits the source matching section data and source status information to the processor of the source matching section 108. The processor of the source matching section 108 controls one or more components of the source matching section 108 according to the source matching section data and the source status information. For example, the processor of the source matching section 108 does not control the components of the source matching section 108 during one or more of the states S1a to Sna, but controls these components during the remaining parts of the states S1a to Sna. The processor of the source matching section 108 controls the components of the source matching section 108 to achieve the capacitance and inductance values ​​within the source matching section data.

[0411] In addition, the communication controller of the source matching section 108 transmits a request for information such as source matching measurement information to the processor of the source matching section 108. Examples of source matching measurement data include a reference measured by a sensor coupled to a component of the source matching section 108 or coupled to an output 158 ​​of the source matching section 108. The sensor is located inside the source matching section 108 or outside thereof. Upon receiving the request for information, the processor of the source matching section 108 provides the source matching measurement information to the communication controller of the source matching section 108. The communication controller of the source matching section 108 embeds the source matching measurement information into one or more EtherCAT frames 1512 and transmits the one or more EtherCAT frames 1512 to the port 1312 of the bias RF generator 104 via the port 1505 and the EtherCAT cable 1504.

[0412] The communication controller of the bias RF generator 104 receives one or more EtherCAT frames 1512 via the port 1312 , identifies the bias RF generator variable information and the timing information of the synchronization signal 146 from the one or more EtherCAT frames 1512 , and provides the bias RF generator variable information and the timing information to the DSP 204 of the bias RF generator 104 .

[0413] In addition, the communication controller of the bias RF generator 104 transmits a request for information such as bias RF generator measurement information and bias state information of the RF signal 168 to the DSP 204 of the bias RF generator 104. Examples of the bias state information of the RF signal 168 include timing information of the state of the RF signal 168 and / or timing information of state transitions. For example, the timing information of the state of the RF signal 168 includes the time when the RF signal 168 changes its variable level and the time the RF signal 168 stays at the variable level. For further explanation, refer to Fig. 10BThe timing information of the state S4a of the RF signal 168 includes the time t0 when the variable 1006 of the RF signal 168 changes from the variable level V2a to the variable level V8a, the time period between the time t0 and t2.5 when the variable 1006 of the RF signal 168 is maintained at the variable level V8a, the time t2.5 when the variable 1006 of the RF signal 168 changes from the variable level V8a to the variable level zero, the time t5 when the variable 1006 of the RF signal 168 changes from the variable level zero to the variable level V6a, the time period between the time t5 and t7.5 when the variable 1006 of the RF signal 168 is maintained at the variable level V6a, the time t7.5 when the variable 1006 of the RF signal 168 changes from the variable level V6a to the variable level V2a, and the time period between the time t7.5 and t10 when the variable 1006 of the RF signal 168 is maintained at the variable level V2a.

[0414] For another example, refer to Fig. 12B The timing information of the state S4a of the RF signal 168 includes the time t0 when the variable 1206 of the RF signal 168 changes from the variable level V2a to the variable level V8a and the time period between the time t0 and t1.5 when the variable 1206 of the RF signal 168 is maintained at the variable level V8a. The timing information of the state transition ST3a of the variable 1206 of the RF signal 168 includes the time t1.5 when the variable 1206 of the RF signal 168 starts to change from the variable level V8a to the variable level V6a and the time t2.5 when the variable 1206 of the RF signal 168 stops changing. Similarly, the timing information of the state transition ST2a of the variable 1206 of the RF signal 168 includes the time t4 when the variable 1206 of the RF signal 168 starts to transition from the variable level V6a to the variable level V4a and the time t5 when the variable 1206 of the RF signal 168 stops transitioning, the timing information of the state transition ST1a of the variable 1206 of the RF signal 168 includes the time t6.5 when the variable 1206 of the RF signal 168 starts to transition from the variable level V4a to the variable level V2a and the time t7.5 when the variable 1206 of the RF signal 168 stops transitioning, and the timing information of the state transition ST4a of the variable 1206 of the RF signal 168 includes the time t9 when the variable 1206 of the RF signal 168 starts to transition from the variable level V2a to the variable level V8a and the time t10 when the variable 1206 of the RF signal 168 stops transitioning.

[0415] Upon receiving the request for information, the DSP 204 of the bias RF generator 104 provides the bias RF generator measurement information and the bias status information to the communication controller of the bias RF generator 104. Upon receiving the bias RF generator measurement information and the bias status information, the communication controller of the bias RF generator 104 embeds the bias RF generator measurement information and the bias status information into one or more EtherCAT frames 1512 and transmits the one or more EtherCAT frames 1512 to the port 1510 of the bias matching section 110 via the port 1506 of the bias RF generator 104 and the EtherCAT cable 1508.

[0416] The communication controller of the bias matching section 110 receives one or more EtherCAT frames 1512 via the port 1510 of the bias matching section 110, extracts the bias matching section data and the bias state information from the one or more EtherCAT frames 1512, and transmits the bias matching section data and the bias state information to the processor of the bias matching section 110. The processor of the bias matching section 110 controls one or more components of the bias matching section 110 according to the bias matching section data and the bias state information. For example, the processor of the bias matching section 110 does not control the components of the bias matching section 110 during one or more of the states S1a to Sna, but controls these components during the rest of the states S1a to Sna. The processor of the bias matching section 110 controls the components of the bias matching section 110 to achieve the capacitance and inductance values ​​within the bias matching section data.

[0417] In addition, the communication controller of the bias match section 110 transmits a request for information, such as bias match measurement information, to the processor of the bias match section 110. Examples of bias match measurement data include a reference measured by a sensor coupled to a component of the bias match section 110 or coupled to the output 164 of the bias match section 110. The sensor is located within the bias match section 110 or external to it. Upon receiving the request for information, the processor of the bias match section 110 provides the bias match measurement information to the communication controller of the bias match section 110. The communication controller of the bias match section 110 embeds the bias match measurement information into one or more EtherCAT frames 1512 and transmits the one or more EtherCAT frames 1512 to the port 1506 of the bias RF generator 104 via the port 1510 and the EtherCAT cable 1508.

[0418] The communication controller of the bias RF generator receives one or more EtherCAT frames 1512 from the bias matching section 110 via port 1506, and transmits the one or more EtherCAT frames 1512 to the port 1505 of the source matching section 108 via port 1312 and the EtherCAT cable 1504. The communication controller of the source matching section 108 receives one or more EtherCAT frames 1512 from the bias RF generator 104 via port 1505, and transmits the one or more EtherCAT frames 1512 to the source RF generator 102 via port 1502, the EtherCAT cable 1306, and port 1310. The communication controller of the source RF generator 102 receives one or more EtherCAT frames 1512 via port 1310, and transmits the one or more EtherCAT frames 1512 to the communication controller 1302 of the host computer 106 via port 1308 and the EtherCAT cable 1304.

[0419] The communication controller 1302 of the host computer 106 applies the EtherCAT protocol to the one or more EtherCAT frames 1512 to obtain or extract the source RF generator measurement information and the bias RF generator measurement information from the one or more EtherCAT frames 1512. The communication controller 1302 provides the source RF generator measurement information and the bias RF generator measurement information to the processor 118.

[0420] Fig. 15B 1 is a diagram of an embodiment of a system 1550 for illustrating information transmission between various components of a plasma system via one or more EtherCAT cables. The system 1550 includes a host computer 106, a source RF generator 102, a bias RF generator 104, a source matching section 108, and a bias matching section 110. The communication controller 1302 is coupled to a port 1505 of the source matching section 108 via an EtehrCAT cable 1508, and the communication controller 1302 is coupled to a port 1510 of the bias matching section 110 via an EtherCAT cable 1504.

[0421] The processor 118 transmits the processor data 1501 to the communication controller 1302. The communication controller 1302 receives the processor data 1501 and applies the EtherCAT protocol to embed the timing information of the synchronization signal 146 and the source matching part information of the processor data 1501, thereby generating one or more EtherCAT frames 1552 having the timing information of the synchronization signal 146 and the source matching part information, and transmits the one or more EtherCAT frames 1552 to the port 1505 of the source matching part 108 via the EtherCAT cable 1508. The communication controller of the source matching part 108 receives the one or more EtherCAT frames 1552 via the port 1505, identifies the source matching part information, and performs the same as described above. Fig.15A The same functions are described until the source matching section measurement information is received from the processor of the source matching section 108. When the source matching section measurement information is received, the communication controller of the source matching section 108 embeds the source matching section measurement information into one or more EtherCAT frames 1552 and transmits the one or more EtherCAT frames 1552 to the communication controller 1302 of the host computer 106 via the port 1505 of the source matching section 108 and the EtherCAT cable 1508.

[0422] In a similar manner, the communication controller 1302 receives the processor data 1501 and applies the EtherCAT protocol to embed the timing information of the synchronization signal 146 and the offset matching part information of the processor data 1501, thereby generating one or more EtherCAT frames 1554 having the timing information of the synchronization signal 146 and the offset matching part information, and transmits the one or more EtherCAT frames 1554 to the port 1510 of the offset matching part 110 via the EtherCAT cable 1504. The communication controller of the offset matching part 110 receives the one or more EtherCAT frames 1554 via the port 1510, identifies the offset matching part information, and performs the same operation as described above with reference to FIG. Fig.15A The same functions are described until the bias match section measurement information is received from the processor of the bias match section 110. When the bias match section measurement information is received, the communication controller of the bias match section 110 embeds the bias match section measurement information into one or more EtherCAT frames 1554 and transmits the one or more EtherCAT frames 1554 to the communication controller 1302 of the host computer 106 via the port 1510 of the bias match section 110 and the EtherCAT cable 1504.

[0423] The communication controller 1302 of the host computer 106 applies the EtherCAT protocol to the one or more EtherCAT frames 1552 to obtain or extract the source matching section measurement information from the one or more EtherCAT frames 1552. The communication controller 1302 provides the source matching section measurement information to the processor 118. Upon receiving the source matching section measurement information, the processor 118 controls one or more of the source RF generator 102, the source matching section 108, the bias RF generator 104, and the bias matching section 110 based on the source matching section measurement information.

[0424] Similarly, the communication controller 1302 of the host computer 106 applies the EtherCAT protocol to the one or more EtherCAT frames 1554 to obtain or extract the bias matching section measurement information from the one or more EtherCAT frames 1554. The communication controller 1302 provides the bias matching section measurement information to the processor 118. Upon receiving the bias matching section measurement information, the processor 118 controls one or more of the source RF generator 102, the source matching section 108, the bias RF generator 104, and the bias matching section 110 based on the bias matching section measurement information.

[0425] It should be noted that in one embodiment, one or more EtherCAT frames 1552 are not stored in the source match section 108, and one or more EtherCAT frames 1554 are not stored in the bias match section 110. For example, one or more EtherCAT frames 1552 are in a constant moving state in the source match section 108, and one or more EtherCAT frames 1554 are in a constant moving state in the bias match section 110. For example, when the source match section data and the source match section measurement information are transmitted between the communication controller of the source match section 108 and the processor of the source match section 108, the one or more EtherCAT frames 1552 are moved in the memory device, such as from one register in the register string of the communication controller of the source match section 108 to another register. As another example, when the bias matching section data and the bias matching section measurement information are transmitted between the communication controller of the bias matching section 110 and the processor of the bias matching section 110, one or more EtherCAT frames 1554 are moved within the memory device, for example, from one register in the register string of the communication controller of the bias matching section 110 to another register.

[0426] Fig.16 1600 is a diagram of an embodiment of an EtherCAT frame 1600. The EtherCAT frame 1600 is one or more EtherCAT frames 1512 ( Fig.15A ) is an example of any one of the following. The EtherCAT frame 1600 is one or more EtherCAT frames 1552 ( Fig. 15B) is an example of any one of the following. And, the EtherCAT frame 1600 is one or more EtherCAT frames 1554 ( Fig. 15B ) in any one of the examples.

[0427] The EtherCAT frame 1600 includes a plurality of fields 1401, 1403, 1402, 1404, 1406, 1408, 1410, 1602, 1604, 1606, 1608, 1412, 1414, 1416, 1610, 1612, 1614, 1616, and 1418. Field 1401 includes a start frame delimiter that identifies the start of the EtherCAT frame 1600. Field 1402 includes a source address of the EtherCAT frame 1600. An example of a source address is the address of the host computer 106 that generates the EtherCAT frame 1600.

[0428] Field 1403 of the EtherCAT frame 1600 includes the order in which the EtherCAT frame 1600 is to be propagated to the various components of the plasma system. An example of the order in which the EtherCAT frame 1600 is to be propagated includes a sequence from the communication controller 1302 to the source RF generator 102 to the source matching section 108, from the source matching section 108 to the bias RF generator 104, from the bias RF generator 104 to the bias matching section 110, from the bias matching section 110 back to the bias RF generator 104, from the bias RF generator 104 to the source matching section 108, from the source matching section 108 to the source RF generator 102, and from the source RF generator 102 to the communication controller 1302. Another example of the order in which the EtherCAT frame 1600 is to be propagated includes a sequence from the communication controller 1302 to the source RF generator 102, and from the source RF generator 102 back to the communication controller 1302.

[0429] Field 1404 contains the destination address of the EtherCAT frame 1600. An example of the destination address is the address of the communication controller 1302 of the host computer 106, and the address of the communication controller 1302 is the final destination of the EtherCAT frame 1600.

[0430] Field 1602 contains source status information. The address identifying the source RF generator 102 is used by the communication controller of the source RF generator 102 to determine that data received from the DSP 204 of the source RF generator 102 is to be stored in field 1602.

[0431] Field 1604 contains the address of source matching unit 108, such as a MAC address, which identifies source matching unit 108 ( Fig.13A) to distinguish the source match 108 from other RF generators of the plasma system. Field 1606 contains source match data, and field 1608 contains source match measurement information. The address identifying the source match 108 is used by the communication controller of the source match 108 to determine that data in field 1606 will be provided to the processor of the source match 108, and to determine that data received from the processor of the source match 108 will be stored in field 1608.

[0432] Field 1610 contains bias status information. The address identifying the bias RF generator 104 is used by the communication controller of the bias RF generator 104 to determine that data received from the DSP 204 of the bias RF generator 104 is to be stored in field 1610.

[0433] Field 1612 contains the address of the offset matching unit 110, such as a MAC address, which identifies the offset matching unit 110 ( Fig.13A ) to distinguish the bias match section 110 from other RF generators of the plasma system. Field 1614 contains bias match section data, and field 1616 contains bias match section measurement information. The address identifying the bias match section 110 is used by the communication controller of the bias match section 110 to determine that the data in field 1614 will be provided to the processor of the bias match section 110, and to determine that the data received from the processor of the bias match section 110 will be stored in field 1616.

[0434] Field 1418 contains a CRC for one or more of fields 1408, 1410, 1602, 1606, 1608, 1414, 1416, 1610, 1614, and 1616. For example, the CRC is calculated by communication controller 1302 ( Fig.13A ) is executed after receiving the EtherCAT frame 1600 to determine whether the source RF generator variable information transmitted by the communication controller 1302 in field 1408 matches the source RF generator variable information received by the communication controller 1302 in field 1408, thereby determining the validity of the EtherCAT frame 1600.

[0435] In one embodiment, fields 1408, 1410 and 1602 or fields 1606 and 1608 or fields 1414, 1416 and 1610 or fields 1614 and 1616 or a combination thereof are not included in the EtherCAT frame 1600. For example, when the EtherCAT frame 1600 is transmitted to the source matching unit 108 ( Fig. 15B ) of one or more EtherCAT frames 1552 ( Fig. 15B), the EtherCAT frame 1600 does not include fields 1408, 1410, 1602, 1414, 1416, 1610, 1614, and 1616 for the source RF generator 102, the bias RF generator 104, and the bias matching section 110.

[0436] In one embodiment, fields 1408, 1410, and 1602 or fields 1606 and 1608 or fields 1414, 1416, and 1610 or fields 1614 and 1616 or a combination thereof are included in the EtherCAT frame 1600 but are empty. For example, when the EtherCAT frame 1600 is an example of any one of the one or more EtherCAT frames 1552 transmitted to the source matching section 108, the EtherCAT frame 1600 does not include any data or information for the source RF generator 102, the bias RF generator 104, and the bias matching section 110 in the fields 1408, 1410, 1602, 1414, 1416, 1610, 1614, and 1616.

[0437] In one embodiment, it should be noted that the address of a component of the plasma system described herein is the address of the communication controller of the component. For example, the MAC address of the source RF generator 102 is the address of the communication controller of the source RF generator 102, the MAC address of the bias RF generator 104 is the address of the communication controller of the bias RF generator 104, the MAC address of the source match 108 is the address of the communication controller of the source match 108, and the MAC address of the bias match 110 is the address of the communication controller of the bias match 110.

[0438] Fig.17 1 is a diagram for illustrating an embodiment of a system 1700 of an RF generator 1702 coupled to EtherCAT cables 1706 and 1708. The RF generator 1702 is either the source RF generator 102 or the bias RF generator 104 ( Fig.15A ). EtherCAT cable 1706 is an example of EtherCAT cable 1304 ( Fig.13A )、1306( Fig. 13B ) and 1504( Fig.15A ). EtherCAT cable 1708 is an example of EtherCAT cables 1306 and 1508 ( Fig.13A and 15A ) in any one of the examples.

[0439] RF generator 1702 includes communication controller 1704, DSP 204, RF power supply 222, and sensor 1710. Examples of sensor 1710 include complex voltage and current sensors, complex impedance sensors, complex power sensors, and complex voltage sensors. Figure 2 ) is an example of the RF generator 1702, except that in the RF generator 1702, the DSP 204 is coupled to the processor 118 of the host computer 106 via the communication controller 1704. In addition, the RF generator 702 ( Figure 7 )、802( Figure 8 ) and 902( Fig. 9 )、1102( Fig.11A ) is an example of an RF generator 1702, except that in the RF generator 1702, the DSP 204 is coupled to the processor 118 of the host computer 106 via the communication controller 1704.

[0440] The communication controller 1704 is coupled to the EtherCAT cable 1706 via a port 1714 of the communication controller 1704 and to the EtherCAT cable 1708 via another port 1716 of the communication controller 1704. The communication controller 1704 is also coupled to the DSP 204. The sensor 1710 is coupled to the DSP 204 and to the output 1712 of the RF generator 1702. The outputs 158 and 164 ( Figure 1 ) is an example of output terminal 1712.

[0441] The communication controller 1704 receives one or more EtherCAT frames 1712 from a component of the plasma system via port 1714. For example, the communication controller 1704 receives one or more EtherCAT frames 1314 ( Fig.13A ), or 1352( Fig. 13B ), or 1354( Fig. 13B ), or 1512( Fig.15A ). The communication controller 1704 processes the one or more EtherCAT frames 1712 to identify the address of the RF generator 1702. For example, the communication controller 1704 compares the address of the RF generator 1702 with the address of the RF generator 1702 pre-stored in the memory device of the communication controller 1704, and determines whether the two addresses match. When it is determined that the two addresses match, the communication controller 1704 identifies the address of the RF generator 1702 from the one or more EtherCAT frames 1712.

[0442] Once the address is identified, the communication controller 1704 identifies data to be extracted from the one or more EtherCAT frames 1712 and to be provided to the DSP 204. For example, the data to be provided to the DSP 204 of the RF generator 1702 is identified as being between the address of the RF generator 1702 in the one or more EtherCAT frames 1712 and the next address within the one or more EtherCAT frames 1712. Fig.14 In other words, the source RF generator variable information in field 1408 is between the source RF generator address in field 1406 and the bias RF generator address in field 1412. Examples of data to be provided to the DSP 204 include the source RF generator variable information in field 1408 or the bias RF generator variable information in field 1414. Once the data is identified, the communication controller 1704 extracts (e.g., obtains, reads, or copies) the data to be provided to the DSP 204 from one or more EtherCAT frames 1712 and transmits the data to the DSP 204.

[0443] The sensor 1710 measures a reference for one or more of the above conditions and provides the reference to the DSP 204. The DSP 204 provides the reference to the communication controller 1704, or calculates a factor from the reference and provides the factor to the communication controller 1704, or a combination thereof. In addition, the communication controller 1704 receives data from the DSP 204 and includes the data in a field, or in the case of the RF generator 1702, in a field 1712. For example, the communication controller 1704 receives the factor from the DSP 204 and embeds the factor in one or more EtherCAT frames 1712 and transmits the factor to a source component of the plasma system (e.g., the processor 118 or the source RF generator 102 or the source match 108) via the port 1714 and the EtherCAT cable 1706, or transmits the one or more EtherCAT frames 1712 to a destination component of the plasma system, such as the source match 108 or the bias RF generator 104, via the port 1716. For example, to transmit one or more EtherCAT frames 1712 to a component such as a source component or a destination component or any other component of a plasma system, the communication controller 1704 reads the sequence field 1403 of the one or more EtherCAT frames 1712 to identify the address of the component from the one or more EtherCAT frames 1712. By further example, to identify the address of the component, the communication controller 1704 compares the address of the destination component stored in the one or more EtherCAT frames 1712 with the component address pre-stored in the memory device of the communication controller 1704 and determines whether the two addresses match. Upon determining that the two addresses match, the communication controller 1704 identifies the address of the component from the one or more EtherCAT frames 1712 and transmits the one or more EtherCAT frames 1712 to the component. The source component is the component from which the RF generator 1702 receives the one or more EtherCAT frames 1712, and the destination component is the component to which the RF generator 1702 will transmit the one or more EtherCAT frames 1712. When one or more EtherCAT frames 1712 are transmitted to a destination component of the plasma system via port 1716 , the one or more EtherCAT frames 1712 are later received from the destination component via port 1716 and transmitted by communication controller 1704 to a source component via port 1714 .

[0444] In one embodiment, multiple sensors are associated with RF generator 1702. For example, another sensor is coupled to RF cable 138 or 142 ( Figure 1 ) and is also coupled to the DSP 204 to measure the reference and provide the reference to the DSP 204.

[0445] In one implementation, the system 1700 does not include the EtherCAT cable 1708 , and the communication controller 1704 does not include the port 1716 .

[0446] Fig.18 1800 is a diagram of an embodiment of a system 1800 for illustrating coupling to an RF generator 1702 ( Fig.17 ) and is coupled to the matching section 1802 of the EtherCAT cables 1806 and 1808. The RF cable 1804 is the RF cable 138 and 142 ( Figure 1 ) and 218( Figure 2 ) is an example of any one of the above. The matching unit 1802 is a source matching unit 108 ( Fig.15A ) or the offset matching section 110 ( Fig. 15B ). EtherCAT cable 1806 is an example of EtherCAT cable 1306 ( Fig.15A )、1508( Fig. 15B ) and 1504( Fig.15A and 15B ) is an example of any one of the following. EtherCAT cable 1808 is an example of EtherCAT cable 1504 ( Fig.15A ) example.

[0447] Matching unit 1802 includes a communication controller 1810, a processor 1812, a driver system 1814, a sensor system 1816, a circuit component system 1818, and a motor system 1820. An example of sensor system 1816 includes one or more sensors, such as sensor 1710 ( Fig.17 ). An example of driver system 1814 includes one or more drivers coupled to each other, such as one or more transistors. An example of circuit component system 1818 includes one or more circuit components coupled to each other, such as inductors and capacitors. An example of motor system 1820 includes one or more electric motors. Each electric motor is coupled to a corresponding circuit component of circuit component system 1818, such as an inductor or a capacitor.

[0448] The source match section 108 or the bias match section 110 is an example of a match section 1802, except that the match section 1802 includes a communication controller 1810 and a processor 1812. The communication controller 1810 is coupled to the EtherCAT cable 1806 via a port 1826 of the communication controller 1810, and is coupled to the EtherCAT cable 1808 via a port 1828 of the communication controller 1810. The communication controller 1810 is also coupled to the processor 1812. The processor 1812 is coupled to a sensor system 1816, and to a driver system 1814, which is coupled to a motor system 1820. The motor system 1820 is coupled to a circuit component system 1818, which is coupled to the RF cable 1804 and to the plasma chamber 112 via an RF transmission line 1822. The circuit component system 1818 is coupled to the sensor system 1816. For example, a first sensor of sensor system 1816 is coupled to a first circuit component of circuit component system 1818, and a second sensor of sensor system 1816 is coupled to a second circuit component of circuit component system 1818. RF transmission lines 140 and 144 ( Figure 1 ) are examples of RF transmission line 1822.

[0449] The communication controller 1810 receives one or more EtherCAT frames 1824 from a component of the plasma system via port 1826. For example, the communication controller 1810 receives one or more EtherCAT frames 1512 ( Fig.15A ), or 1552( Fig. 15B ), or 1554( Fig. 15B ). The communication controller 1810 processes one or more EtherCAT frames 1824 to identify the address of the matching unit 1802. For example, the communication controller 1810 compares the address of the matching unit 1802 with the address of the matching unit 1802 pre-stored in the memory device of the communication controller 1810, and determines whether the two addresses match. When it is determined that the two addresses match, the communication controller 1810 identifies the address of the matching unit 1802 from the one or more EtherCAT frames 1824.

[0450] Once the address is identified, the communication controller 1810 identifies data to be extracted from the one or more EtherCAT frames 1824 to be provided to the processor 1812. For example, the data to be provided to the processor 1812 of the matching portion 1802 is identified as being between the address of the matching portion 1802 in the one or more EtherCAT frames 1824 and the next address within the one or more EtherCAT frames 1824. Fig.16It is noted that the source matching section data in field 1606 is between the source matching section address in field 1604 and the bias RF generator address in field 1412. Examples of data to be provided to the processor 1812 include the source matching section data in field 1606 or the bias matching section data in field 1614. The communication controller 1810 extracts (e.g., reads, obtains, or copies) the data to be provided to the processor 1812 from one or more EtherCAT frames 1824, and transmits the data to the processor 1812.

[0451] The sensor system 1816 measures the reference at one or more outputs of one or more circuit components of the circuit component system 1818 and provides the reference to the processor 1812. The processor 1812 provides the reference to the communication controller 1810. In addition, the communication controller 1810 receives data from the processor 1812 and includes the data in a field, and in the case of the matching section 1802, in one or more EtherCAT frames 1824. For example, the communication controller 1810 receives the reference from the processor 1812 and embeds the reference in one or more EtherCAT frames 1824, and transmits the reference to a source component of the plasma system (e.g., the source RF generator 102 or the bias RF generator 104 or the host computer 106) via the port 1826 and the EtherCAT cable 1806, or transmits the one or more EtherCAT frames 1824 to a destination component of the plasma system, such as the bias RF generator 104, via the port 1828. For example, to transmit one or more EtherCAT frames 1824 to a component such as a source component or a destination component or any other component of a plasma system, the communication controller 1810 reads the sequence field 1403 of the one or more EtherCAT frames 1824 to identify the address of the destination from the one or more EtherCAT frames 1824. To further illustrate, to identify the address of the destination component, the communication controller 1810 compares the address of the destination component stored in the one or more EtherCAT frames 1824 with the address of the destination component pre-stored in the memory device of the communication controller 1810 and determines whether the two addresses match. When it is determined that the two addresses match, the communication controller 1810 identifies the address of the destination component from the one or more EtherCAT frames 1824 and transmits the one or more EtherCAT frames 1824 to the destination component.

[0452] The source component is the component from which the matching section 1802 receives one or more EtherCAT frames 1824, and the destination component is the component to which the matching section 1802 will transmit one or more EtherCAT frames 1824. When the one or more EtherCAT frames 1824 are transmitted to the destination component of the plasma system via port 1828, the one or more EtherCAT frames 1824 are later received from the destination component via port 1828 and transmitted to the source component by the communication controller 1810 via port 1826.

[0453] In one embodiment, multiple sensors are associated with the matching section 1802. For example, another sensor is coupled to a point on the RF transmission line 1804 and is also coupled to the processor 1812 to measure the reference and provide the reference to the processor 1812.

[0454] In one implementation, the system 1800 does not include the EtherCAT cable 1808 , and the communication controller 1810 does not include the port 1828 .

[0455] Fig.19A Another embodiment of an EtherCAT synchronization system 1920 such as a plasma system is described, wherein a plurality of EtherCAT cables are coupled between any two components of the EtherCAT synchronization system 1920. For example, one EtherCAT cable is coupled from an output port of a master controller to an input port of a source RF generator 102, another EtherCAT cable is coupled from another output port of the master controller to an input port of a bias RF generator 104, one EtherCAT cable is coupled from an output port of the source RF generator 102 to an input port of a source matching section 108, and one EtherCAT cable is coupled from an output port of the bias RF generator 104 to an input port of a bias matching section 110. Examples of master controllers include a host controller or a host computer 106 ( Figure 1 ) or ADVCI or another controller.

[0456] State information for the source RF generator 102 and the source matching section 108 is provided in pulse trains that are transmitted from the main controller to the source RF generator 102 and from the source RF generator 102 to the source matching section 108. For example, the states S(nA) to Sn duty cycle, power level and frequency level, and source matching section data of the variables of the RF signal 152 generated by the source RF generator 102 are provided in a pulse train transmitted from the main controller to the source RF generator 102, and the states S(nA) to Sn duty cycle of the variables are provided in a pulse train transmitted from the source RF generator 102 to the source matching section 108. Similarly, the states S(nA) to Sn duty cycle, power level and frequency level, and bias matching section data of the variables of the RF signal 168 are provided in a pulse train sent from the main controller to the bias RF generator 104, and the states S(nA) to Sn duty cycle are provided in other pulse trains sent from the bias RF generator 104 to the bias matching section 110.

[0457] Fig.19B An implementation of an EtherCAT synchronization system 1930 of, for example, a plasma system is described, wherein an EtherCAT cable is coupled between an output port of a master controller and an input port of a source RF generator 102, an EtherCAT cable is coupled between an output port of the source RF generator 102 and an input port of a bias RF generator 104, an EtherCAT cable is coupled between an output port of the source RF generator 102 and an input port of a source matching section 108, and an EtherCAT cable is coupled between an output port of the source matching section 108 and an input port of a bias matching section 110.

[0458] State information for the source RF generator 102, source match section 108, bias RF generator 104, and bias match section 110 is provided in a pulse train that is transmitted from the master controller to the source RF generator 102. For example, the states of the variables S(nA) to Sn duty cycle, power level and frequency level, source match section data, and bias match section data of the RF signals 152 and 168 are provided in a pulse train that is transmitted from the master controller to the source RF generator 102. The pulse train is forwarded from the source RF generator 102 to the bias RF generator 104. In addition, the pulse train is transmitted from the source RF generator 102 to the source match section and from the source match section 108 to the bias match section 110.

[0459] In one embodiment, an EtherCAT cable is coupled from the output port of the bias RF generator 104 to the input port of the source RF generator 102, and an EtherCAT cable is coupled from the output port of the bias matching section 110 to the input port of the source matching section 108. In this embodiment, instead of an EtherCAT cable coupling the main controller to the source RF generator 102, an EtherCAT cable is used that couples the output port of the main controller to the input port of the bias RF generator 104. In addition, an EtherCAT cable is coupled from the output port of the bias RF generator 104 to the input port of the bias matching section 110. Status information for the source RF generator 102, the source matching section 108, the bias RF generator 104, and the bias matching section 110 is provided in a pulse train that is transmitted from the main controller to the bias RF generator 104. For example, the pulse train is transmitted from the main controller to the bias RF generator 104 , forwarded from the bias RF generator 104 to the source RF generator 102 , forwarded from the bias RF generator 104 to the bias matching section 110 , and transmitted from the bias matching section 110 to the source matching section 108 .

[0460] Fig.19C An implementation of an EtherCAT synchronization system 1950 such as a plasma system is illustrated in which components are coupled in a daisy chain B. For example, an EtherCAT cable is coupled from an output port of a master controller to an input port of a source RF generator 102, an EtherCAT cable is coupled from an output port of the source RF generator 102 to an input port of a source matching section 108, an EtherCAT cable is coupled from an output port of the source matching section 108 to an input port of a bias matching section 110, and an EtherCAT cable is coupled from an output port of the bias matching section 110 to an input port of the bias RF generator 104.

[0461] The status information for the source RF generator 102, the source matching section 108, the bias RF generator 104, and the bias matching section 110 is provided in a pulse train that is transmitted from the main controller to the source RF generator 102. The pulse train is then transmitted from the source RF generator 102 to the source matching section 108, then from the source matching section 108 to the bias matching section 110, and from the bias matching section 110 to the bias RF generator 104.

[0462] Fig.19DAn implementation of an EtherCAT synchronization system 1960, such as a plasma system, is illustrated in which components are coupled in a daisy-chain fashion. For example, an EtherCAT cable is coupled from an output port of a master controller to an input port of a bias RF generator 104, an EtherCAT cable is coupled from an output port of the bias RF generator 104 to an input port of a bias matching section 110, an EtherCAT cable is coupled from an output port of the bias matching section 110 to an input port of a source matching section 108, and an E...

Claims

1. A method of transmitting information between a plurality of components of a plasma tool, comprising: receiving one or more Ethernet control automation technology (EtherCAT) frames at a radio frequency (RF) generator, wherein the RF generator is one of the plurality of components of the plasma tool; extracting, by the RF generator, a plurality of variable levels from the one or more EtherCAT frames; generating an RF signal by the RF generator, the RF signal having the plurality of variable levels during a clock cycle; identifying a destination address of the one or more EtherCAT frames; and The one or more EtherCAT frames are transmitted to another one of the plurality of components at the destination address.

2. The method of claim 1 , wherein the plurality of variable levels comprises a first variable level, a second variable level, a third variable level, and a fourth variable level, wherein during the clock cycle, the RF signal transitions from the first variable level to the second variable level, from the second variable level to the third variable level, and from the third variable level to the fourth variable level.

3. The method of claim 1 , further comprising identifying an address of the RF generator within one of the one or more EtherCAT frames, wherein the extracting comprises obtaining the plurality of variable levels from a field between a field having the address and a field having another address of the another one of the plurality of components.

4. The method of claim 1, wherein the other of the plurality of components comprises an impedance matching circuit coupled to the RF generator. The method of claim 1 , wherein each of the plurality of variable levels is a frequency level or a power level.

6. The method of claim 1 , wherein the one or more EtherCAT frames are received from a processor, the method further comprising: receiving the one or more EtherCAT frames from the other one of the plurality of components; and The one or more EtherCAT frames are transmitted to the processor.

7. The method of claim 1, wherein each of the one or more EtherCAT frames has a field for receiving measurement data from the RF generator and a field containing the plurality of variable levels provided to the RF generator.

8. A radio frequency (RF) generator, comprising: a communications controller configured to receive one or more Ethernet Control Automation Technology (EtherCAT) frames, wherein the RF generator is one of a plurality of components of a plasma tool, wherein the communication controller is configured to extract a plurality of variable levels from the one or more EtherCAT frames; and an RF power supply coupled to the communication controller, wherein the RF power supply is configured to generate an RF signal having the plurality of variable levels during a clock cycle, wherein the communication controller is configured to identify a destination address of the one or more EtherCAT frames, and Wherein the communication controller is configured to transmit the one or more EtherCAT frames to another one of the plurality of components at the destination address.

9. The RF generator of claim 8, wherein the plurality of variable levels include a first variable level, a second variable level, a third variable level, and a fourth variable level, wherein during the clock cycle, the RF signal transitions from the first variable level to the second variable level, from the second variable level to the third variable level, and from the third variable level to the fourth variable level.

10. The RF generator of claim 8, wherein the communication controller is configured to identify an address of the RF generator within one of the one or more EtherCAT frames, wherein to extract the plurality of variable levels, the communication controller is configured to obtain the plurality of variable levels from a field between a field having the address and a field having another address of the another one of the plurality of components.

11. The RF generator of claim 8, wherein the other of the plurality of components comprises an impedance matching circuit coupled to the RF generator.

12. The RF generator of claim 8, wherein each of the plurality of variable levels is a frequency level or a power level.

13. The RF generator of claim 8, wherein the one or more EtherCAT frames are received from a processor, wherein the communication controller is configured to: receiving the one or more EtherCAT frames from the other one of the plurality of components; and The one or more EtherCAT frames are transmitted to the processor.

14. The RF generator of claim 8, wherein the RF generator includes a processor coupled to the communication controller, wherein each of the one or more EtherCAT frames has a field for receiving data from the processor of the RF generator and a field including the plurality of variable levels provided to the processor of the RF generator.

15. An impedance matching circuit, comprising: a communications controller configured to receive one or more Ethernet Control Automation Technology (EtherCAT) frames; one or more components; as well as A processor is coupled to the one or more components and the communication controller when the communication controller is configured to transmit data from the one or more EtherCAT frames to the processor to control the one or more components.

16. The impedance matching circuit of claim 15, wherein the one or more EtherCAT frames are received from a component of a plasma system, wherein the communication controller is configured to: determining that an address stored in the one or more EtherCAT frames matches a pre-stored address of the impedance matching circuit; and Upon determining that the addresses stored within the one or more EtherCAT frames match the pre-stored addresses, data to be extracted from the one or more EtherCAT frames is identified.

17. The impedance matching circuit according to claim 15, wherein the communication controller is configured to: receiving a reference from the processor, wherein the reference is measured by a sensor; embedding the reference into the one or more EtherCAT frames; and The one or more EtherCAT frames are transmitted to a component coupled to the impedance matching circuit.

18. The impedance matching circuit according to claim 17, wherein the communication controller is configured to: determining that an address stored in the one or more EtherCAT frames matches a pre-stored address of the component coupled to the impedance matching circuit; and In response to determining that the addresses stored in the one or more EtherCAT frames match the pre-stored addresses, one or more EtherCAT frames are transmitted to the component coupled to the impedance matching circuit.

19. The impedance matching circuit of claim 18, wherein the component coupled to the impedance matching circuit is a source radio frequency (RF) generator, or a bias RF generator, or a host.

20. The impedance matching circuit of claim 15, wherein the data comprises state information received from a radio frequency (RF) generator, wherein the processor is configured to control the one or more components based on one of a plurality of states in the state information and not to control the one or more components based on the remaining states of the plurality of states in the state information.

21. A method comprising: receiving one or more Ethernet Control Automation Technology (EtherCAT) frames via the communication controller of the impedance matching circuit; as well as Data from the one or more EtherCAT frames is transmitted to a processor of the impedance matching circuit via the communication controller to control one or more components of the impedance matching circuit.

22. The method of claim 21 , wherein the one or more EtherCAT frames are received from a component of the plasma system, the method further comprising: determining, by the communication controller, that an address stored in the one or more EtherCAT frames matches a pre-stored address of the impedance matching circuit; as well as Upon determining that an address stored in one or more EtherCAT frames matches the pre-stored address, data to be extracted from the one or more EtherCAT frames is identified by the communication controller.

23. The method according to claim 21, further comprising: receiving a reference from the processor via the communication controller, wherein the reference is measured by a sensor; embedding, by the communications controller, the reference into the one or more EtherCAT frames; as well as The one or more EtherCAT frames are transmitted by the communication controller to a component coupled to the impedance matching circuit.

24. The method according to claim 23, further comprising: determining, by the communication controller, that an address stored in the one or more EtherCAT frames matches a pre-stored address of the component coupled to the impedance matching circuit; as well as In response to determining that the addresses stored in the one or more EtherCAT frames match the pre-stored addresses, one or more EtherCAT frames are transmitted, by the communication controller, to the component coupled to the impedance matching circuit.

25. The method of claim 24, wherein the component coupled to the impedance matching circuit is a source radio frequency (RF) generator, or a bias RF generator, or a host.

26. The method of claim 21, wherein the data comprises status information received from a radio frequency (RF) generator, the method further comprising: The one or more components are controlled by the processor based on one of the plurality of states in the state information, and the one or more components are not controlled based on the remaining states of the plurality of states in the state information.

27. An impedance matching circuit, comprising: processor; and a communications controller coupled to the processor, wherein the communications controller is configured to: receiving a reference from said processor; embedding the reference into one or more Ethernet Control Automation Technology (EtherCAT) frames; and The one or more EtherCAT frames are transmitted to a component coupled to the impedance matching circuit.

28. The impedance matching circuit of claim 27, wherein the communication controller is configured to: determining that an address stored in the one or more EtherCAT frames matches a pre-stored address of the component; and In response to determining that the address stored in the additional one or more EtherCAT frames matches the pre-stored address, the one or more EtherCAT frames are transmitted to the component.

29. The impedance matching circuit of claim 27, wherein the component is a source radio frequency (RF) generator, or a bias RF generator, or a host, wherein the reference is measured by a sensor, wherein the reference is a complex voltage current or a complex voltage or a complex power or a complex current.

30. The impedance matching circuit of claim 27, further comprising one or more components, wherein the processor is configured to control the one or more components based on one of a plurality of states and not to control the one or more components based on the remaining states of the plurality of states.

31. A method comprising: receiving, via a communications controller of the impedance matching circuit, a reference from a processor of the impedance matching circuit; embedding, by the communications controller, the reference into one or more Ethernet Control Automation Technology (EtherCAT) frames; as well as The one or more EtherCAT frames are transmitted, via the communication controller, to a component coupled to the impedance matching circuit.

32. The method of claim 31 further comprising: determining, by the communications controller, that an address stored in the one or more EtherCAT frames matches a pre-stored address of the component; as well as In response to determining that the address stored in the one or more EtherCAT frames matches the pre-stored address, one or more EtherCAT frames are transmitted to the component via the communication controller.

33. The method of claim 31, wherein the component is a source radio frequency (RF) generator, or a bias RF generator, or a host, wherein the reference is measured by a sensor, wherein the reference is a complex voltage current, or a complex voltage, or a complex power, or a complex current.

34. The method of claim 31 , further comprising: controlling, by the processor, one or more components of the impedance matching circuit based on one of a plurality of states; as well as Controlling the one or more components by the processor based on remaining states of the plurality of states is avoided.

35. A method of controlling conversion of a variable of a radio frequency (RF) signal, comprising: generating the RF signal; pulsing the RF signal to have a first state transition from a first variable level to a second variable level; as well as The RF signal is pulsed to have a second state transition from a second variable level to a third variable level, wherein the second state transition is of a different type than the first state transition.

36. The method of claim 35, wherein the second state transition is curved and the first state transition is linear.

37. The method of claim 35, wherein the first variable level is a first frequency level or a first parameter level, the second variable level is a second frequency level or a second parameter level, and the third variable level is a third frequency level or a third parameter level.

38. The method of claim 35, wherein the slope of the second state transition is different from the slope of the first state transition, wherein the first state transition has a negative slope and the second state transition has a negative slope.

39. The method of claim 35, wherein the slope of the second state transition is different from the slope of the first state transition, wherein the first state transition has a positive slope and the second state transition has a positive slope.

40. The method of claim 35, wherein the first variable level is greater than or less than the second variable level, and the second variable level is greater than or less than the third variable level.

41. A controller comprising: A processor configured to: controlling a radio frequency (RF) generator to generate an RF signal; controlling the RF generator to pulse the RF signal to have a first state transition from a first variable level to a second variable level; as well as controlling the RF generator to pulse the RF signal to have a second state transition from the second variable level to a third variable level, wherein the type of the second state transition is different from the type of the first state transition; as well as A memory device is coupled to the processor.

42. A controller according to claim 41, wherein the second state transition is curved and the first state transition is linear.

43. A controller according to claim 41, wherein the first variable level is a first frequency level or a first parameter level, the second variable level is a second frequency level or a second parameter level, and the third variable level is a third frequency level or a third parameter level.

44. The controller of claim 41, wherein the slope of the second state transition is different than the slope of the first state transition, wherein the first state transition has a negative slope and the second state transition has a negative slope.

45. The controller of claim 41, wherein the slope of the second state transition is different than the slope of the first state transition, wherein the first state transition has a positive slope and the second state transition has a positive slope.

46. ​​The controller of claim 41 , wherein the processor is configured to provide the RF generator with a first plurality of variable values ​​for the first state transition and a second plurality of variable values ​​for the second state transition, wherein the first plurality of variable values ​​are between the first variable level and the second variable level, and the second plurality of variable values ​​are between the second variable level and the third variable level.

47. The controller of claim 41, wherein the first variable level is greater than or less than the second variable level, and the second variable level is greater than or less than the third variable level.

48. A radio frequency (RF) generator comprising: a processor configured to receive a first plurality of variable values ​​for a first state transition and a second plurality of variable values ​​for a second state transition; as well as a radio frequency (RF) power source coupled to the processor to generate an RF signal having a first variable level, a second variable level, and a third variable level, Wherein, the processor is configured to control the RF power source to achieve the first state transition from the first variable level to the second variable level, and to achieve the second state transition from the second variable level to the third variable level.

49. The RF generator of claim 48, wherein the second state transition is curved and the first state transition is linear.

50. The RF generator of claim 48, wherein the first variable level is a first frequency level or a first parameter level, the second variable level is a second frequency level or a second parameter level, and the third variable level is a third frequency level or a third parameter level.

51. The RF generator of claim 48, wherein a slope of the second state transition is different than a slope of the first state transition, wherein the first state transition has a negative slope and the second state transition has a negative slope.

52. The RF generator of claim 48, wherein a slope of the second state transition is different than a slope of the first state transition, wherein the first state transition has a positive slope and the second state transition has a positive slope.

53. The RF generator of claim 48, wherein the first plurality of variable values ​​are between the first variable level and the second variable level, and the second plurality of variable values ​​are between the second variable level and the third variable level.

54. The RF generator of claim 48, wherein the first variable level is greater than or less than the second variable level, and the second variable level is greater than or less than the third variable level.

55. A method of calibrating a radio frequency (RF) generator, comprising: determining a first voltage value based on a first state of an RF signal generated by the RF generator when the RF generator is coupled to a known load; as well as In response to determining that the first voltage value is outside a preset range, at least one of a first power level and a first duty cycle is adjusted for the first state.

56. The method of claim 55, further comprising: determining a second voltage value based on a second state of the RF signal when the RF generator is coupled to the known load; as well as In response to determining that the second voltage value is outside the preset range, at least one of a second power level and a second duty cycle is adjusted for the second state.

57. The method of claim 56, wherein the RF signal has a first variable level during the first state and the RF signal has a second variable level during the second state, wherein the first variable level is greater than or less than the second variable level.

58. The method of claim 55, wherein the known load is a 50 ohm load, wherein the RF generator is coupled to the known load through an RF cable.

59. A controller for calibrating a radio frequency (RF) generator, comprising: A processor configured to: determining a first voltage value based on an occurrence of a first state of an RF signal generated by the RF generator when the RF generator is coupled to a known load; and In response to determining that the first voltage value is outside a preset range, adjusting at least one of a first power level and a first duty cycle; as well as A memory device is coupled to the processor.

60. The controller of claim 59, wherein the processor is configured to: determining a second voltage value based on occurrence of a second state of the RF signal when the RF generator is coupled to the known load; and In response to determining that the second voltage value is outside the preset range, at least one of a second power level and a second duty cycle is adjusted for the second state.

61. The controller of claim 60, wherein the RF signal has a first variable level during the first state and the RF signal has a second variable level during the second state, wherein the first variable level is greater than or less than the second variable level.

62. The controller of claim 59, wherein the known load is a 50 ohm load, wherein the RF generator is coupled to the known load by an RF cable.

63. A method for controlling an impedance matching circuit, comprising: transmitting timing information about a plurality of states to the impedance matching circuit; as well as A capacitance of a circuit component of the impedance matching circuit is modified during one of the plurality of states to reduce power reflected to a radio frequency (RF) generator to which the impedance matching circuit is coupled.

64. The method of claim 63, further comprising modifying a frequency or power level of the RF generator during one of the remaining states of the plurality of states to reduce reflected power during the plurality of states.

65. The method of claim 64, further comprising maintaining a frequency of an RF generator constant during the one of the plurality of states and the remaining of the plurality of states.

66. The method of claim 65, wherein reflected power during the plurality of states is minimized by maintaining a frequency of the RF generator constant.

67. The method of claim 63, wherein the impedance matching circuit is a source match or a bias match, wherein the source match is coupled to a transformer coupled plasma (TCP) coil of a plasma chamber and the bias match is coupled to an electrostatic chuck of the plasma chamber.

68. A controller comprising: A processor configured to: transmitting timing information about a plurality of states to the impedance matching circuit; as well as modifying a capacitance of a circuit component of the impedance matching circuit during one of the plurality of states to reduce power reflected to a radio frequency (RF) generator, wherein the impedance matching circuit is coupled to the RF generator; and A memory device is coupled to the processor.

69. The controller of claim 68, wherein the processor is configured to control the RF generator during one of the remaining states of the plurality of states to modify a frequency or a power level of the RF generator to reduce reflected power during the plurality of states.

70. The controller of claim 68, wherein the processor is configured to control the RF generator during the one of the plurality of states and the remaining of the plurality of states to maintain a frequency of the RF generator constant.

71. The controller of claim 70, wherein reflected power during the plurality of states is minimized by maintaining a frequency of the RF generator constant.

72. The controller of claim 68, wherein the impedance matching circuit is a source match or a bias match, wherein the source match is coupled to a transformer coupled plasma (TCP) coil of a plasma chamber and the bias match is coupled to an electrostatic chuck of the plasma chamber.

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