Wafer bearing structure, wafer alignment system and wafer alignment method

Abstract

The invention provides a wafer bearing structure, a wafer alignment system and a wafer alignment method, the surface of the wafer bearing structure is coated with a reflective material, a luminescent material or a fluorescent material, or the surface of the wafer bearing structure is provided with a light source, so that the edge of a wafer to be detected is obvious. The wafer to be detected is arranged on the wafer bearing structure capable of emitting light or reflecting light, accurate alignment of the wafer to be detected is achieved through the high identification degree of imaging, alignment can be conducted without setting identification patterns, and the wafer alignment method and device are suitable for alignment of control wafer type wafers without setting patterns; meanwhile, the optical characteristics of the surface of the wafer bearing structure are improved, other process equipment and structures do not need to be changed, and industrial popularization and application are facilitated; besides, alignment can be realized by performing image acquisition, processing and operation on the images of the wafer bearing structure and the to-be-detected wafer, operations such as additional transfer and the like do not need to be performed on the to-be-detected wafer or the wafer bearing structure, and the alignment process is stable in operation and high in reliability.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a wafer bearing structure, a wafer alignment system and a wafer alignment method. Background Art

[0002] During the semiconductor manufacturing process, the measuring machine is used to measure parameters such as the characteristic dimensions of the patterns in the semiconductor structure. The traditional measurement method is to place the wafer product to be measured on the measuring device through a transmission structure such as a robotic arm, and then move the wafer to be measured to a specific measurement position inside the measuring device through a moving unit inside the measuring device, and then measure at the specific measurement position. When the wafer to be measured is moved by the moving unit, an error of hundreds of microns may occur. In order to compensate and calibrate the error, the current method is to define various marking patterns in the wafer to be measured, and compensate for the movement error generated by the moving unit by recognizing the marking patterns, thereby ensuring the accuracy of the final measurement point.

[0003] The control chip is a silicon chip used to monitor the performance of the machine during the semiconductor manufacturing process. When the control chip is used to monitor the performance of the measuring device, after the transmission structure such as a robotic arm transfers the control chip to the measuring device, the mobile unit inside the measuring device directly moves the control chip to a specific measuring position. However, since the surface of the control chip has only a single film layer without any identification graphics, the movement error during the movement of the control chip cannot be compensated by the identification graphics, but can only rely on the stability of the machine itself, and it is easy to produce large alignment errors during the measurement process.

[0004] In the prior art, there is a method of using the markings on the product sheet and the projection of the measurement site to align the measurement position of the sheet. However, the alignment effect obtained by this operation is unstable, and the projection alignment process is complicated and difficult to implement.

[0005] Therefore, there is an urgent need for a wafer alignment system and a wafer alignment method that can accurately align the control wafer and is simple and easy to operate.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0007] In view of the above shortcomings of the prior art, an object of the present invention is to provide a wafer supporting structure, a wafer alignment system and a wafer alignment method, so as to solve the problems of large control chip alignment error and unstable operation in the prior art.

[0008] To achieve the above-mentioned purpose, the present invention provides a wafer supporting structure, the surface of which is a reflective material, a luminescent material or a fluorescent material, or the surface of which is coated with a reflective material, a luminescent material or a fluorescent material, or the surface of which is provided with a light source; when a wafer to be tested is carried on the surface of the wafer supporting structure, from the perspective of looking down at the wafer to be tested, the edges of the wafer to be tested are all within the area of ​​the reflective material, the luminescent material, the fluorescent material or the light source.

[0009] The present invention also provides a wafer alignment system, which comprises: a wafer bearing structure, an image acquisition module, an image processing module, a data calculation module and an alignment module;

[0010] The wafer supporting structure is the above-mentioned wafer supporting structure;

[0011] The wafer carrying structure is used to carry a wafer to be tested, and the wafer to be tested is a control wafer or a wafer provided with a pattern;

[0012] The image acquisition module is located above the wafer carrying structure, and is used to acquire the original image of the wafer carrying structure and the wafer to be tested; the image processing module is connected to the image acquisition module, and is used to process the original image;

[0013] The data calculation module is connected to the image processing module, and is used to calculate the position information of the wafer to be tested relative to the wafer supporting structure through the image obtained after the original image is processed by the image processing module;

[0014] The position information includes the center position information of the wafer to be tested and / or the position information of the notch groove on the wafer to be tested;

[0015] The alignment module moves and / or rotates the wafer to be tested to a preset position according to the position information obtained by the data operation module.

[0016] Optionally, when the surface of the wafer supporting structure is a reflective material or is coated with a reflective material, a light source is provided above the wafer supporting structure so that the image acquisition module can capture an original image of the wafer supporting structure.

[0017] The present invention also provides a wafer alignment method, the wafer alignment method comprising:

[0018] The image acquisition module acquires a first original image of a wafer supporting structure without a wafer to be tested, wherein the wafer supporting structure is the above-mentioned wafer supporting structure, and the wafer to be tested is a control wafer or a wafer provided with a pattern;

[0019] The image processing module and the data calculation module process and calculate the first original image to obtain the position of the first center of the wafer supporting structure;

[0020] The wafer to be tested is placed on the wafer supporting structure, the portion of the wafer supporting structure covered by the wafer to be tested is blocked, and the portion of the wafer supporting structure not blocked by the wafer to be tested reflects or emits light, and the image acquisition module obtains a second original image of the wafer supporting structure on which the wafer to be tested is placed;

[0021] The image processing module and the data calculation module process and calculate the second original image to obtain the position of the second center of the wafer to be tested;

[0022] The data operation module calculates and obtains the position offset between the first circle center and the second circle center;

[0023] The data calculation module calculates the position of the notch groove on the wafer to be tested;

[0024] The alignment module moves the wafer to be tested according to the position offset so that the first circle center overlaps with the second circle center; the alignment module rotates the wafer to be tested according to the position of the notch groove so that the position of the notch groove is aligned with the pre-alignment mark.

[0025] Optionally, the image processing module performs binarization processing on the first original image to obtain a first binarized image in which the wafer supporting structure is white and other parts are black, and the first binarized image uses pixels as image units; the data calculation module calculates the first binarized image to obtain the position of the first center of the wafer supporting structure;

[0026] And / or, the image processing module performs binarization processing on the second original image to obtain a second binarized image in which the wafer supporting structure is white and the wafer to be tested is black, and the second binarized image uses pixels as image units; the data calculation module calculates the second binarized image to obtain the position of the second center of the wafer supporting structure.

[0027] Optionally, before the image processing module performs binarization processing on the first original image and / or the second original image, the image processing module performs filtering processing on the first original image and / or the second original image and outputs a grayscale image.

[0028] Optionally, the method for obtaining the position of the first center of the circle is: establishing a plane coordinate system on the first binary image with a first direction and a second direction parallel to the wafer supporting structure and perpendicular to each other; the straight line containing the most white pixels when passing through the wafer supporting structure in the first direction is the first straight line, and the straight line containing the most white pixels when passing through the wafer supporting structure in the second direction is the second straight line, the point where the first straight line intersects the second straight line is the first center of the wafer supporting structure, and the coordinate value of the first center of the circle is obtained.

[0029] Optionally, the method for obtaining the position of the second center of the circle is: establishing a plane coordinate system on the second binary image with a first direction and a second direction parallel to the wafer supporting structure and perpendicular to each other; the straight line containing the most black pixels when passing through the wafer to be tested in the first direction is the third straight line, and the straight line containing the most black pixels when passing through the wafer to be tested in the second direction is the fourth straight line, the point where the third straight line intersects the fourth straight line is the second center of the wafer to be tested, and the coordinate value of the second center of the circle is obtained.

[0030] Optionally, the method for obtaining the position of the notch groove on the wafer to be tested is: the data calculation module obtains the pixel coordinates on the contour curve of the wafer to be tested in the second binary image, calculates the distance between the contour curve and the second center of the circle, and obtains the pixel coordinates with the minimum distance, which is the position of the notch groove on the wafer to be tested.

[0031] Optionally, the method by which the alignment module aligns the position of the notch with the pre-alignment mark is: after obtaining the position of the notch, calculate the deflection angle of the line between the notch and the second center of the circle and the line between the pre-alignment mark and the second center of the circle, and rotate the wafer to be tested in the opposite direction by the deflection angle with the second center of the circle as the rotation center to align the notch with the pre-alignment mark.

[0032] As described above, the wafer supporting structure, wafer alignment system and wafer alignment method of the present invention have the following beneficial effects:

[0033] The present invention sets the surface of the wafer bearing structure as a reflective or luminous material, so that there is a light difference between it and the original image of the wafer to be tested, so that the image of the wafer bearing structure has obvious recognition compared with the background area, so that the position of the wafer to be tested and the deflection angle of the notch groove can be easily distinguished and identified, and the error in the alignment process can be reduced or eliminated;

[0034] The present invention arranges the wafer to be tested on a wafer supporting structure that can emit light or reflect light, and uses the high recognition of imaging to achieve accurate alignment of the wafer to be tested. Alignment can be performed without setting identification patterns, and is suitable for alignment of control wafers that do not set patterns.

[0035] The present invention improves the optical properties of the surface of the wafer bearing structure without changing other process equipment and structures, which is convenient for industrial promotion and application.

[0036] The present invention can realize alignment by performing image acquisition, processing and calculation on the imaging of the wafer supporting structure and the wafer to be tested, without the need for additional operation steps such as transfer of the wafer to be tested or the wafer supporting structure, thereby making the alignment process stable and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Shown is a structural schematic diagram of providing a wafer supporting structure in step 1 of the wafer alignment method in embodiment 3 of the present invention.

[0038] Figure 2 It shows a structural schematic diagram of placing the wafer to be tested on the wafer supporting structure in step 3 of the wafer alignment method in the third embodiment of the present invention.

[0039] Figure 3 Shown is a schematic diagram of a method for obtaining a position offset in step 5 of the wafer alignment method in the third embodiment of the present invention.

[0040] Figure 4 Shown is a schematic diagram of the step flow in an optional example of a wafer alignment method in Embodiment 3 of the present invention.

[0041] Description of Figure Numbers

[0042] 1. Wafer supporting structure; 2. Wafer to be tested; 3. Notch; O1, first circle center; O2, second circle center. DETAILED DESCRIPTION

[0043] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0045] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0046] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0047] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0048] Embodiment 1:

[0049] The present invention provides a wafer supporting structure 1, the surface of the wafer supporting structure 1 is a reflective material, a luminescent material or a fluorescent material, or the surface of the wafer supporting structure 1 is coated with a reflective material, a luminescent material or a fluorescent material, or the surface of the wafer supporting structure 1 is provided with a light source; when a wafer 2 to be tested is supported on the surface of the wafer supporting structure, from the perspective of looking down at the wafer 2 to be tested, the edges of the wafer 2 to be tested are all within the area of ​​the reflective material, the luminescent material, the fluorescent material or the light source.

[0050] In the prior art, since there is no pattern or identification graphic on the surface of the control chip, the movement error of the control chip during the movement process cannot be compensated by the identification graphic, and can only rely on the stability of the machine itself, which is easy to produce large alignment errors during the measurement process. The present invention sets the surface of the wafer supporting structure 1 to emit light or reflect light, so that it can be distinguished from the wafer 2 to be tested placed on it and other surrounding objects during the subsequent imaging process, so that the image obtained by the wafer supporting structure 1 through image acquisition has obvious recognition compared to the background area and the image of the wafer 2 to be tested placed on it, and can be easily distinguished and identified, thereby achieving accurate alignment of the wafer 2 to be tested, wherein the wafer 2 to be tested can be a control chip without an identification pattern or a wafer with a pattern, so that the wafer supporting structure 1 can be suitable for the alignment of control chips without identification graphics.

[0051] Embodiment 2:

[0052] The present invention provides a wafer alignment system, which comprises: a wafer bearing structure 1, an image acquisition module, an image processing module, a data calculation module and an alignment module;

[0053] The wafer supporting structure 1 is the wafer supporting structure 1 described in the first embodiment;

[0054] The wafer supporting structure 1 is used to support a wafer 2 to be tested, and the wafer 2 to be tested is a control wafer or a wafer provided with a pattern;

[0055] The image acquisition module is located above the wafer supporting structure 1, and is used to acquire the original image of the wafer supporting structure 1 and the wafer to be tested 2; the image processing module is connected to the image acquisition module, and is used to process the original image;

[0056] The data calculation module is connected to the image processing module, and is used to calculate the position information of the wafer to be tested 2 relative to the wafer supporting structure 1 through the image obtained after the original image is processed by the image processing module;

[0057] The position information includes the center position information of the wafer 2 to be tested and / or the position information of the notch groove 3 on the wafer 2 to be tested;

[0058] The alignment module moves and / or rotates the wafer 2 to be tested to a preset position according to the position information obtained by the data operation module.

[0059] In one embodiment, when the surface of the wafer supporting structure 1 is a reflective material or is coated with a reflective material, a light source is provided above the wafer supporting structure 1 so that the image acquisition module can capture the original image of the wafer supporting structure 1 .

[0060] Specifically, when the surface of the wafer supporting structure 1 is made of reflective material or is coated with reflective material, an obvious light source is required to distinguish the original image of the wafer supporting structure 1 from surrounding objects and the wafer 2 to be tested; when the surface of the wafer supporting structure 1 is made of fluorescent material or is coated with fluorescent material, only a weak light source is required to produce an obvious bright area image on the wafer supporting structure 1 to distinguish it from other parts; and when the surface of the wafer supporting structure 1 is made of luminescent material, is coated with luminescent material or is provided with a light source, a bright area image can be produced on the wafer supporting structure 1 to distinguish it from other parts without providing additional lighting conditions.

[0061] The present invention sets the wafer supporting structure 1 as the wafer supporting structure 1 with a reflective or luminous surface in Example 1, and can use a simple and stable wafer alignment system to align the position of the wafer 2 to be tested. It is suitable for ordinary wafers with patterns, and is also suitable for the alignment of control wafers without identification patterns. The overall system has strong reliability, simple structure, and is easy to operate.

[0062] In one embodiment, the image acquisition module includes an image detector and an image collector. The image detector is used to detect bright light sources over a large range to determine the approximate range of the bright area emitted by the wafer supporting structure 1. The image collector is used to perform detailed and high-resolution acquisition of specific light and dark images within the confirmed approximate range to obtain a high-precision original image.

[0063] Embodiment three:

[0064] The present invention provides a wafer alignment method, the wafer alignment method comprising:

[0065] Step 1: The image acquisition module acquires a first original image of the wafer supporting structure 1 without the wafer 2 to be tested, wherein the wafer supporting structure 1 is the above-mentioned wafer supporting structure 1, and the wafer 2 to be tested is a control wafer or a wafer provided with a pattern;

[0066] Step 2: The image processing module and the data calculation module process and calculate the first original image to obtain the position of the first circle center O1 of the wafer supporting structure 1;

[0067] Step 3: placing the wafer 2 to be tested on the wafer supporting structure 1, the portion of the wafer supporting structure 1 covered by the wafer 2 to be tested is blocked, and the portion of the wafer supporting structure 1 not blocked by the wafer 2 to be tested reflects or emits light, and the image acquisition module obtains a second original image of the wafer supporting structure 1 on which the wafer 2 to be tested is placed;

[0068] Step 4: the image processing module and the data calculation module process and calculate the second original image to obtain the position of the second center O2 of the wafer 2 to be tested;

[0069] Step 5: The data operation module calculates and obtains the position offset between the first circle center O1 and the second circle center O2;

[0070] Step 6: The data calculation module calculates the position of the notch groove 3 on the wafer 2 to be tested;

[0071] Step 7: The alignment module moves the wafer 2 to be tested according to the position offset so that the first circle center O1 overlaps with the second circle center O2; the alignment module rotates the wafer 2 to be tested according to the position of the notch groove 3 so that the position of the notch groove 3 is aligned with the pre-alignment mark.

[0072] The wafer alignment method of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the wafer alignment method protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0073] First, if Figure 1 As shown, step 1 is performed, the image acquisition module acquires the first original image of the wafer supporting structure 1 without the wafer 2 to be tested, the wafer supporting structure 1 is the wafer supporting structure 1 described in Example 1, and the wafer 2 to be tested is a control wafer or a wafer with a pattern.

[0074] Then, step 2 is performed, in which the image processing module and the data calculation module process and calculate the first original image to obtain the position of the first circle center O1 of the wafer supporting structure 1.

[0075] In one embodiment, the image processing module performs binarization processing on the first original image to obtain a first binary image in which the wafer supporting structure 1 is white and the other parts are black, and the first binary image uses pixels as image units; the data calculation module calculates the first binary image to obtain the position of the first center O1 of the wafer supporting structure 1.

[0076] In one embodiment, before the image processing module performs binarization processing on the first original image, the image processing module performs filtering processing on the first original image and outputs a grayscale image.

[0077] In one embodiment, the method for obtaining the position of the first center O1 is: establishing a plane coordinate system on the first binary image with a first direction and a second direction parallel to the wafer supporting structure 1 and perpendicular to each other; the straight line containing the most white pixels when passing through the wafer supporting structure 1 in the first direction is the first straight line, and the straight line containing the most white pixels when passing through the wafer supporting structure 1 in the second direction is the second straight line, the point where the first straight line intersects the second straight line is the first center O1 of the wafer supporting structure 1, and the coordinate value of the first center O1 is obtained.

[0078] Specifically, Figure 1 As shown, the first direction is the X-axis direction, and the second direction is the Y-axis direction.

[0079] Then, if Figure 2As shown, step 3 is performed, the wafer to be tested 2 is placed on the wafer supporting structure 1, the portion of the wafer supporting structure 1 covered by the wafer to be tested 2 is blocked, and the portion of the wafer supporting structure 1 not blocked by the wafer to be tested 2 is reflective or luminous, and the image acquisition module obtains a second original image of the wafer supporting structure 1 on which the wafer to be tested 2 is placed.

[0080] Then, step 4 is performed, wherein the image processing module and the data calculation module process and calculate the second original image to obtain the position of the second center O2 of the wafer 2 to be tested.

[0081] In one embodiment, the image processing module performs binarization processing on the second original image to obtain a second binary image in which the wafer supporting structure 1 is white and the wafer to be tested 2 is black, and the second binary image uses pixels as image units; the data calculation module calculates the second binary image to obtain the position of the second center O2 of the wafer supporting structure 1.

[0082] In one embodiment, before the image processing module performs binarization processing on the second original image, the image processing module performs filtering processing on the second original image and outputs a grayscale image.

[0083] In one embodiment, when collecting the second original image, the outer portion of the outline of the wafer supporting structure 1 is cropped, and only the graphics of the wafer supporting structure 1 and the wafer to be tested 2 are retained, so that the subsequent data calculation module can perform high-precision and rapid calculations on the binary graphics.

[0084] In one embodiment, the method for obtaining the position of the second center O2 is: establishing a plane coordinate system on the second binary image with a first direction and a second direction parallel to the wafer supporting structure 1 and perpendicular to each other; the straight line containing the most black pixels when passing through the wafer 2 to be tested in the first direction is the third straight line, and the straight line containing the most black pixels when passing through the wafer 2 to be tested in the second direction is the fourth straight line, the point where the third straight line intersects the fourth straight line is the second center O2 of the wafer 2 to be tested, and the coordinate value of the second center O2 is obtained.

[0085] Next, step 5 is performed, wherein the data operation module calculates and obtains the position offset between the first circle center O1 and the second circle center O2.

[0086] In one embodiment, the method for the data calculation module to obtain the position offset is: using the second straight line where the first circle center O1 is located and the third straight line where the second circle center O2 is located as right-angled sides, and the first circle center O1 and the second circle center O2 as vertices to form a right triangle, and calculating the lengths of the two right-angled sides of the right triangle, such as Figure 3 As shown, the position offsets ΔX and ΔY of the first circle center O1 and the second circle center O2 in the first direction and the second direction are obtained respectively, and then the position offsets are reversely compensated to obtain the distance that the second circle center O2 needs to move.

[0087] Then, step 6 is performed, wherein the data calculation module calculates the position of the notch groove 3 on the wafer 2 to be tested.

[0088] In one embodiment, the method for obtaining the position of the notch groove 3 on the wafer 2 to be tested is as follows: the data calculation module obtains the pixel coordinates on the contour curve of the wafer 2 to be tested in the second binary image, calculates the distance between the contour curve and the second center of the circle O2, and obtains the pixel coordinates with the minimum distance, which is the position of the notch groove 3 on the wafer 2 to be tested.

[0089] Finally, step 7 is performed, the alignment module moves the wafer 2 to be tested according to the position offset so that the first circle center O1 overlaps with the second circle center O2; the alignment module rotates the wafer 2 to be tested according to the position of the notch groove 3 so that the position of the notch groove 3 is aligned with the pre-alignment mark.

[0090] In one embodiment, the method by which the alignment module aligns the position of the notch groove 3 with the pre-alignment mark is: after obtaining the position of the notch groove 3, calculate the deflection angle of the line between the notch groove 3 and the second circle center O2 and the line between the pre-alignment mark and the second circle center O2, and rotate the wafer 2 to be tested in the opposite direction by the deflection angle with the second circle center O2 as the rotation center, so that the notch groove 3 is aligned with the pre-alignment mark.

[0091] Specifically, the pre-alignment mark is a mark set in the measurement system when aligning the wafer 2 to be tested before loading the wafer 2 to be tested.

[0092] In one embodiment, the line connecting the pre-alignment mark and the first circle center O1 is parallel to the second direction. The second direction is as follows: Figure 2 In the Y direction of the circle, the pre-alignment mark is below the first circle center O1, that is, close to the positive direction of the Y axis. At this time, in a right triangle constructed with the second straight line of the first circle center O1 and the third straight line of the second circle center O2 as right angles and the first circle center O1 and the second circle center O2 as vertices, as shown in FIG. Figure 3 As shown, the deflection angle α between the hypotenuse L and the second straight line is the deflection angle between the line between the notch groove 3 and the second circle center O2 and the line between the pre-alignment mark and the second circle center O2. By rotating the center of the wafer 2 to be tested moved to the first circle center O1 in the opposite direction at a corresponding angle, the notch groove 3 on the wafer 2 to be tested can be aligned with the pre-alignment mark.

[0093] In one embodiment, Figure 4 As shown, the wafer alignment method includes:

[0094] When the wafer 2 to be tested is not placed on the wafer supporting structure 1, a first original image is collected; the first original image is binarized to make it a black and white image; a pixel coordinate system is established to determine the position of the first center O1 of the wafer supporting structure 1; when the wafer 2 to be tested is placed on the wafer supporting structure 1, a second original image is collected; the graphics other than the wafer supporting structure 1 and the wafer 2 to be tested are cropped; the wafer 2 to be tested and the wafer supporting structure 1 are binarized to be a black and white image; the coordinates of the second center O2 of the wafer 2 to be tested and the position coordinates of the notch groove 3 are determined in the pixel coordinate system; the alignment module moves the second center O2 to the first center O1, and the notch groove 3 to the pre-alignment mark, and the positioning is completed.

[0095] The present invention uses a wafer supporting structure 1 with a reflective or luminous surface for the alignment of the wafer 2 to be tested. The center position of the wafer 2 and the position of the notch groove 3 can be calculated from the binary image imaged thereof without setting an identification pattern on the wafer 2 to be tested. Therefore, it is suitable for the alignment of the control wafer. This process only involves the collection of images. Except for moving the wafer 2 to be tested to achieve alignment, no additional operations are performed on the wafer 2 to be tested and the wafer supporting structure 1. Therefore, the entire processing process is stable, simple and convenient, and will not cause major changes to the original operation process, which is beneficial to improving the alignment accuracy of the wafer 2 to be tested while maintaining process efficiency.

[0096] In summary, the wafer supporting structure, wafer alignment system and wafer alignment method of the present invention can achieve precise alignment of the wafer to be tested by placing the wafer to be tested on a luminous or reflective wafer supporting structure, and utilizing the high recognition of imaging. Alignment can be performed without setting identification graphics, and is suitable for the alignment of control wafers that do not set graphics. At the same time, the optical properties of the surface of the wafer supporting structure are improved, and there is no need to change other process equipment and structures, which is convenient for industrial promotion and application. In addition, alignment can be achieved by performing image acquisition, processing and calculation on the imaging of the wafer supporting structure and the wafer to be tested, and there is no need to perform additional transfer operations on the wafer to be tested or the wafer supporting structure, so that the alignment process is stable and reliable.

[0097] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0098] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A wafer supporting structure, characterized in that: The surface of the wafer supporting structure is a reflective material, a luminescent material or a fluorescent material, or the surface of the wafer supporting structure is coated with a reflective material, a luminescent material or a fluorescent material, or the surface of the wafer supporting structure is provided with a light source; when the wafer to be tested is carried on the surface of the wafer supporting structure, from the perspective of looking down at the wafer to be tested, the edges of the wafer to be tested are all within the area of ​​the reflective material, the luminescent material, the fluorescent material or the light source.

2. A wafer alignment system, characterized in that: The wafer alignment system comprises: a wafer carrying structure, an image acquisition module, an image processing module, a data calculation module and an alignment module; The wafer supporting structure is the wafer supporting structure described in claim 1; The wafer carrying structure is used to carry a wafer to be tested, and the wafer to be tested is a control wafer or a wafer provided with a pattern; The image acquisition module is located above the wafer carrying structure, and is used to acquire the original image of the wafer carrying structure and the wafer to be tested; the image processing module is connected to the image acquisition module, and is used to process the original image; The data calculation module is connected to the image processing module, and is used to calculate the position information of the wafer to be tested relative to the wafer supporting structure through the image obtained after the original image is processed by the image processing module; The position information includes the center position information of the wafer to be tested and / or the position information of the notch groove on the wafer to be tested; The alignment module moves and / or rotates the wafer to be tested to a preset position according to the position information obtained by the data operation module.

3. The wafer alignment system according to claim 2, characterized in that: When the surface of the wafer supporting structure is a reflective material or is coated with a reflective material, a light source is provided above the wafer supporting structure so that the image acquisition module can acquire an original image of the wafer supporting structure.

4. A wafer alignment method, characterized in that: The wafer alignment method comprises: The image acquisition module acquires a first original image of a wafer supporting structure without a wafer to be tested, wherein the wafer supporting structure is the wafer supporting structure described in claim 1, and the wafer to be tested is a control wafer or a wafer provided with a pattern; The image processing module and the data calculation module process and calculate the first original image to obtain the position of the first center of the wafer supporting structure; The wafer to be tested is placed on the wafer supporting structure, the portion of the wafer supporting structure covered by the wafer to be tested is blocked, and the portion of the wafer supporting structure not blocked by the wafer to be tested reflects or emits light, and the image acquisition module obtains a second original image of the wafer supporting structure on which the wafer to be tested is placed; The image processing module and the data calculation module process and calculate the second original image to obtain the position of the second center of the wafer to be tested; The data operation module calculates and obtains the position offset between the first circle center and the second circle center; The data calculation module calculates the position of the notch groove on the wafer to be tested; The alignment module moves the wafer to be tested according to the position offset so that the first circle center overlaps with the second circle center; the alignment module rotates the wafer to be tested according to the position of the notch groove so that the position of the notch groove is aligned with the pre-alignment mark.

5. The wafer alignment method according to claim 4, characterized in that: The image processing module performs binarization processing on the first original image to obtain a first binarized image in which the wafer supporting structure is white and other parts are black, and the first binarized image uses pixels as image units; the data calculation module calculates the first binarized image to obtain the position of the first center of the wafer supporting structure; And / or, the image processing module performs binarization processing on the second original image to obtain a second binarized image in which the wafer supporting structure is white and the wafer to be tested is black, and the second binarized image uses pixels as image units; The data operation module operates the second binary image to obtain the position of the second center of the wafer supporting structure.

6. The wafer alignment method according to claim 5, characterized in that: Before the image processing module performs binarization processing on the first original image and / or the second original image, the image processing module performs filtering processing on the first original image and / or the second original image and outputs a grayscale image.

7. The wafer alignment method according to claim 5, characterized in that: The method for obtaining the position of the first center of the circle is as follows: a plane coordinate system is established on the first binary image in a first direction and a second direction that are parallel to the wafer supporting structure and perpendicular to each other; a straight line containing the most white pixels when passing through the wafer supporting structure in the first direction is a first straight line, a straight line containing the most white pixels when passing through the wafer supporting structure in the second direction is a second straight line, a point where the first straight line intersects with the second straight line is a first center of the wafer supporting structure, and the coordinate value of the first center of the circle is obtained; 8. The wafer alignment method according to claim 5, characterized in that: The method for obtaining the position of the second center of the circle is: establishing a plane coordinate system on the second binary image with a first direction and a second direction parallel to the wafer supporting structure and perpendicular to each other; the straight line containing the most black pixels when passing through the wafer to be tested in the first direction is the third straight line, and the straight line containing the most black pixels when passing through the wafer to be tested in the second direction is the fourth straight line, the point where the third straight line intersects the fourth straight line is the second center of the wafer to be tested, and the coordinate value of the second center of the circle is obtained.

9. The wafer alignment method according to claim 5, characterized in that: The method for obtaining the position of the notch groove on the wafer to be tested is as follows: the data calculation module obtains the pixel coordinates on the contour curve of the wafer to be tested in the second binary image, calculates the distance between the contour curve and the second center of the circle, and obtains the pixel coordinates with the minimum distance, which is the position of the notch groove on the wafer to be tested.

10. The wafer alignment method according to claim 4, characterized in that: The method by which the alignment module aligns the position of the notch with the pre-alignment mark is as follows: after obtaining the position of the notch, calculating the deflection angle of the line between the notch and the second center of the circle and the line between the pre-alignment mark and the second center of the circle, and rotating the wafer to be tested in the opposite direction by the deflection angle with the second center of the circle as the rotation center so that the notch is aligned with the pre-alignment mark.

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