Hybrid power module, multi-phase full-bridge hybrid module, power conversion device, and vehicle

Abstract

The invention provides a hybrid power module, a multi-phase full-bridge hybrid module, a power conversion device and a vehicle. The hybrid power module comprises a substrate; the first direct-current connecting layer, the second direct-current connecting layer and the alternating-current connecting layer are located on the substrate; the upper bridge chip group is located on the first direct current connecting layer, the lower bridge chip group is located on the alternating current connecting layer, the upper bridge chip group comprises a first wide forbidden band chip group, and the lower bridge chip group comprises a second wide forbidden band chip group; the first wide bandgap chip set is connected with the alternating current connecting layer, the second wide bandgap chip set is connected with the second direct current connecting layer, the half-bridge hybrid power module is formed on one substrate, the manufacturing process is reduced, and the space utilization rate is improved. And the first wide bandgap chip group and the second wide bandgap chip group are arranged along the second direction, and each of the first wide bandgap chip group and the second wide bandgap chip group comprises a plurality of wide bandgap power chips arranged along the second direction, so that a relatively regular arrangement mode is formed, and the space utilization rate is further improved.

Description

Technical Field

[0001] The present application relates to the technical field of power conversion, and in particular to a hybrid power module, a multi-phase full-bridge hybrid module, a power conversion device and a vehicle. Background Art

[0002] Hybrid power modules composed of wide bandgap semiconductor power devices (e.g., silicon carbide metal oxide semiconductor field effect transistors, SiMOSFET) and silicon-based fully-controlled power semiconductor devices (e.g., silicon insulated gate bipolar transistors, Si IGBT) are increasingly widely used in power circuits. The wide bandgap semiconductor power devices are used to control the switching of the power circuit, and the silicon-based fully-controlled power semiconductor devices bear the main conduction current, thereby combining the advantages of the two devices to achieve the purpose of reducing switching losses and costs.

[0003] At present, a half-bridge hybrid power module is mainly composed of a plurality of different substrates. Different substrates are used to carry different devices. Different substrates need to be connected. There are too many manufacturing processes and the space utilization rate is low. Summary of the invention

[0004] The present application provides a hybrid power module, a multi-phase full-bridge hybrid module, a power conversion device and a vehicle, which are used to reduce the manufacturing process and improve space utilization.

[0005] In a first aspect, the present application provides a hybrid power module, comprising:

[0006] substrate;

[0007] a first DC connection layer, an AC connection layer, and a second DC connection layer located on the substrate;

[0008] and an upper bridge chipset located on the first DC connection layer, and a lower bridge chipset on the AC connection layer, wherein the upper bridge chipset includes a first wide bandgap chipset, and the lower bridge chipset includes a second wide bandgap chipset;

[0009] The first wide bandgap chipset is connected to the AC connection layer, and the second wide bandgap chipset is connected to the second DC connection layer;

[0010] The first wide bandgap chipset and the second wide bandgap chipset are arranged along a second direction, and both the first wide bandgap chipset and the second wide bandgap chipset include a plurality of wide bandgap power chips arranged along the second direction.

[0011] In some embodiments, the upper bridge chipset also includes a first silicon-based chipset, and the lower bridge chipset also includes a second silicon-based chipset. Each silicon-based power chip in the first silicon-based chipset is respectively connected in series with the silicon-based power chip in the second silicon-based chipset to form a half-bridge structure.

[0012] In some embodiments, the second wide bandgap chipset is connected in series with the wide bandgap power chips in the first wide bandgap chipset in a one-to-one correspondence to form a half-bridge circuit, and multiple wide bandgap power chips in the wide bandgap chipset are connected in parallel.

[0013] In some embodiments, the hybrid power module includes a second DC connection terminal located on the second DC connection layer, and the current path length between the wide bandgap power chip of each second wide bandgap chipset and the second DC connection terminal is the same.

[0014] In some embodiments, at least a portion of the AC connection layer is embedded in the first DC connection layer and is insulated from the first DC connection layer to connect the wide bandgap power chip in the first wide bandgap chipset.

[0015] In some embodiments, on the second DC connection layer, the second DC connection terminal is disposed close to the second wide bandgap chipset.

[0016] In some embodiments, the hybrid power module further includes a first DC connection terminal, which is located on the first DC connection layer, and the current path length between the wide bandgap power chip of each first wide bandgap chipset and the first DC connection terminal is the same.

[0017] In some embodiments, the first DC connection layer includes a first connection layer and a second connection layer connected to each other;

[0018] The first wide bandgap chipset is located on the first connection layer, and the first silicon-based chipset is located on the second connection layer.

[0019] In some embodiments, a recess is formed between the first connection layer and the second connection layer to accommodate at least a portion of the protruding structure of the AC connection layer. The at least a portion of the protruding structure is spaced apart from the first DC connection layer and is used to electrically connect multiple wide bandgap power chips in the first wide bandgap chipset.

[0020] In some embodiments, the arrangement of the plurality of wide bandgap power chips includes at least one of the following:

[0021] Each of the wide bandgap power chips is arranged flush with each other in the second direction;

[0022] Two adjacent wide bandgap power chips are staggered in a first direction;

[0023] Each of the wide bandgap power chips is arranged staggered in the first direction;

[0024] The first direction and the second direction are two directions perpendicular to each other on a plane.

[0025] In some embodiments, the first silicon-based chipset further includes a plurality of diode chips.

[0026] In some embodiments, the second silicon-based chipset further includes a plurality of diode chips.

[0027] In some embodiments, the plurality of diode chips in each of the first silicon-based chip groups are respectively connected in series with the plurality of diode chips in the second silicon-based chip group.

[0028] In some embodiments, the arrangement of the plurality of silicon-based power chips and the plurality of diode chips in any silicon-based chipset includes at least one of the following:

[0029] The silicon-based power chip and the diode chip are arranged crosswise in a first direction;

[0030] A first chip combination and a second chip combination are arranged in the first direction, the first chip combination includes a plurality of the silicon-based power chips arranged in the first direction, and the second chip combination includes a plurality of the diode chips arranged in the first direction;

[0031] A plurality of third chip combinations are arranged in the first direction, and the third chip combination includes the silicon-based power chip and the diode chip arranged in the second direction;

[0032] A plurality of fourth chip combinations and a plurality of fifth chip combinations are cross-arranged in the first direction, the fourth chip combination and the fifth chip combination include the silicon-based power chips and the diodes arranged in the second direction, and in the fourth chip combination and the fifth chip combination, the silicon-based power chips and the diodes are arranged in opposite directions;

[0033] The first direction and the second direction are two directions perpendicular to each other on a plane.

[0034] In some embodiments, the arrangement of the plurality of silicon-based power chips and the plurality of diodes in any silicon-based chipset includes at least one of the following:

[0035] The silicon-based power chip and the diode chip are arranged crosswise in the second direction;

[0036] A first chip combination and a second chip combination are arranged in the second direction, the first chip combination includes a plurality of the silicon-based power chips arranged in the second direction, and the second chip combination includes a plurality of the diode chips arranged in the second direction;

[0037] A plurality of third chip combinations are arranged in the second direction, and the third chip combination includes the silicon-based power chip and the diode chip arranged in the first direction;

[0038] A plurality of fourth chip combinations and a plurality of fifth chip combinations are cross-arranged in the second direction, the fourth chip combination and the fifth chip combination include the silicon-based power chips and the diodes arranged in the first direction, and in the fourth chip combination and the fifth chip combination, the arrangement directions of the silicon-based power chips and the diode chips are opposite.

[0039] In some embodiments, the hybrid power module comprises:

[0040] An upper bridge driving layer located on the substrate, the upper bridge driving layer comprising a first gate driving layer and a first emitter driving layer;

[0041] A gate of each of the wide bandgap power chips in the first wide bandgap chipset is connected to the first gate driving layer, and a source of each of the wide bandgap power chips in the first wide bandgap chipset is connected to the first source driving layer.

[0042] In some embodiments, the upper bridge chipset also includes: a second gate drive layer and a first emitter drive layer, the gate of each of the silicon-based power chips in the first silicon-based chipset is connected to the second gate drive layer, and the emitter of each of the silicon-based power chips in the first silicon-based chipset is connected to the first emitter drive layer.

[0043] In some embodiments, the hybrid power module comprises:

[0044] A lower bridge driving layer located on the substrate, the lower bridge driving layer comprising a third gate driving layer and a second emitter driving layer;

[0045] A gate of each of the wide bandgap power chips in the second wide bandgap chipset is connected to the third gate driving layer, and a source of each of the wide bandgap power chips in the second wide bandgap chipset is connected to the second source driving layer.

[0046] In some embodiments, the lower bridge chipset also includes a fourth gate drive layer and a second emitter drive layer, the gate of each of the silicon-based power chips in the second silicon-based chipset is connected to the fourth gate drive layer, and the emitter of each of the silicon-based power chips in the second silicon-based chipset is connected to the second emitter drive layer.

[0047] In some embodiments, the first source driving layer and the first emitter driving layer are the same driving layer.

[0048] In some embodiments, the hybrid power module comprises:

[0049] A first gate driving terminal is provided in the first gate driving layer, a second gate driving terminal is provided in the second gate driving layer, a first source driving terminal is provided in the first source driving layer, and a first emitter driving terminal is provided in the first emitter driving layer.

[0050] In some embodiments, the second source driving layer and the second emitter driving layer are the same driving layer.

[0051] In some embodiments, at least one of the first gate driving terminal, the second gate driving terminal, the first source driving terminal, and the first emitter driving terminal is led out perpendicularly to the substrate.

[0052] In some embodiments, the hybrid power module comprises:

[0053] A third gate driving terminal is provided in the third gate driving layer, a fourth gate driving terminal is provided in the fourth gate driving layer, a second source driving terminal is provided in the second source driving layer, and a second emitter driving terminal is provided in the second emitter driving layer.

[0054] In some embodiments, at least one of the third gate driving terminal, the fourth gate driving terminal, the second source driving terminal, and the second emitter driving terminal is led out perpendicularly to the substrate.

[0055] In some embodiments, the hybrid power module comprises:

[0056] Two first source driving layers connected to each other, at least one of the source driving layers being provided with a plurality of driving resistors;

[0057] The first end of each of the driving resistors is connected to each other and to the first gate driving layer, and the second end of each of the driving resistors is connected to the gate of one of the first wide bandgap power chips in the first wide bandgap chipset.

[0058] In some embodiments, the hybrid power module comprises:

[0059] Two second source driving layers are connected to each other, and at least one of the second source driving layers is provided with multiple driving resistors; the first end of each of the driving resistors is connected to each other and connected to the third gate driving layer, and the second end of each of the driving resistors is connected to the gate of one of the wide bandgap power chips in the second wide bandgap chipset.

[0060] In some embodiments, the first wide bandgap chipset includes a plurality of wide bandgap power chips;

[0061] The hybrid power module comprises an AC connection terminal located on the AC connection layer, and the current path lengths from each of the wide bandgap power chips in the first wide bandgap chipset to the AC connection terminal are the same.

[0062] In some embodiments, at least a portion of the structure of the AC connection layer embedded in the first DC connection layer includes an AC connection terminal, and the current path length from each of the wide bandgap power chips in the first wide bandgap chipset to the AC connection terminal is the same.

[0063] In some embodiments, the second DC connection layer is further connected with a second DC connection terminal, and the second DC connection terminal is led out along the first direction.

[0064] In some embodiments, the first DC connection layer is further connected with a first DC connection terminal, and the first DC connection terminal is led out along a first direction.

[0065] In some embodiments, the AC connection layer is further connected with an AC connection terminal, and the AC connection terminal is led out along the first direction.

[0066] In some embodiments, at least one of the first DC connection layer, the second DC connection layer, and the AC connection layer is a copper layer.

[0067] In some embodiments, the wide bandgap power chip includes a silicon carbide metal oxide semiconductor field effect transistor, or a gallium nitride high electron mobility transistor.

[0068] In some embodiments, the silicon-based power chip includes a silicon insulated gate bipolar transistor, or a silicon metal oxide semiconductor field effect transistor;

[0069] The diode chip includes a silicon fast recovery diode chip or a silicon carbide Schottky diode chip.

[0070] In a second aspect, the present application provides a multi-phase full-bridge hybrid module, comprising at least two of the above hybrid power modules.

[0071] In a third aspect, the present application provides a power conversion device, comprising at least one of the above-mentioned hybrid power modules.

[0072] In a fourth aspect, the present application provides a vehicle comprising the above-mentioned power conversion device.

[0073] The hybrid power module, multi-phase full-bridge hybrid module, power conversion device and vehicle provided by the present application include: a substrate; a first DC connection layer, a second DC connection layer and an AC connection layer located on the substrate; and an upper bridge chipset located on the first DC connection layer, a lower bridge chipset located on the AC connection layer, the upper bridge chipset includes a first wide bandgap chipset, and the lower bridge chipset includes a second wide bandgap chipset; the first wide bandgap chipset is connected to the AC connection layer, and the second wide bandgap chipset is connected to the second DC connection layer, thereby forming a half-bridge hybrid power module on a substrate, reducing the manufacturing process and improving space utilization. In addition, the first wide bandgap chipset and the second wide bandgap chipset are arranged along the second direction, and the first wide bandgap chipset and the second wide bandgap chipset both include a plurality of wide bandgap power chips arranged along the second direction, forming a more regular arrangement, and further improving space utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0075] Figure 1 A schematic diagram of the layout of a hybrid power module provided in one embodiment of the present application;

[0076] Figure 2 A schematic diagram of the layout of a hybrid power module provided in one embodiment of the present application;

[0077] Figure 3 A schematic diagram of the layout and connection of a hybrid power module provided in one embodiment of the present application;

[0078] Figure 4 A schematic diagram of the structure of a wide bandgap power chip provided in one embodiment of the present application;

[0079] Figure 5 A schematic diagram of a flow path of a wide bandgap chipset provided in an embodiment of the present application;

[0080] Figure 6 An equivalent circuit and a schematic diagram of a switching waveform of a hybrid power module provided in an embodiment of the present application;

[0081] Figure 7 A schematic diagram of the layout of a wide bandgap chipset provided in an embodiment of the present application;

[0082] Figure 8 A schematic diagram of the layout of a hybrid power module provided in another embodiment of the present application;

[0083] Fig. 9 A schematic diagram of the layout of a silicon-based chipset provided in one embodiment of the present application;

[0084] Fig.10 A schematic diagram of the layout of another hybrid power module provided in an embodiment of the present application;

[0085] Fig.11 A schematic diagram of the connection between the drive circuit and the drive terminals provided in one embodiment of the present application;

[0086] Fig.12 A schematic diagram of the layout of a hybrid power module provided in yet another embodiment of the present application;

[0087] Fig.13 A schematic diagram of a multi-phase hybrid power module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0088] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0089] In many fields such as automobiles and power systems, it is very important to reduce the power loss of power conversion devices such as inverters and frequency converters, and power semiconductor devices in power conversion devices such as inverters and frequency converters play an important role. The performance of traditional silicon-based power semiconductor devices is difficult to meet the current requirements for power switching devices in terms of blocking voltage, on-state current, operating frequency, high temperature, and high efficiency.

[0090] Silicon-based fully controlled power semiconductor devices represented by silicon insulated gate bipolar transistors (SiIGBT) have excellent performances such as simple control circuit, high voltage resistance, and large current bearing, and are widely used in power conversion devices such as inverters and frequency converters. However, when silicon-based fully controlled power semiconductor devices represented by silicon insulated gate bipolar transistors are turned off, the collector current decays slowly, that is, the tail current is obvious, and the tail current will increase its switching loss, especially when used as a high-frequency switch, the loss is even greater.

[0091] Wide bandgap semiconductor materials represented by silicon carbide have excellent physical properties such as large bandgap width, high saturated electron drift rate, and high thermal conductivity, which can greatly reduce the loss of power conversion devices such as inverters and frequency converters and improve conversion efficiency. However, wide bandgap semiconductor power devices represented by silicon carbide are relatively expensive.

[0092] Therefore, wide bandgap semiconductor power devices and silicon-based fully-controlled power semiconductor devices can be connected in parallel to form a hybrid power module. The switch of the hybrid power module can be controlled by the wide bandgap semiconductor power device, and the main conduction current can be taken by the silicon-based fully-controlled power semiconductor device, thereby combining the advantages of the two devices to achieve the purpose of reducing switching losses and costs.

[0093] At present, a half-bridge hybrid power module is mainly composed of a plurality of different substrates (e.g., ceramic substrates), and different substrates are used to carry different devices, such as the first substrate carries the wide bandgap semiconductor power device of the upper bridge, the second substrate carries the silicon-based fully-controlled power semiconductor device of the upper bridge, the third substrate carries the wide bandgap semiconductor power device of the lower bridge, and the fourth substrate carries the silicon-based fully-controlled power semiconductor device of the lower bridge. Different substrates need to be connected to form a half-bridge hybrid power module, which leads to too many manufacturing processes and low space utilization.

[0094] To this end, the present application proposes a hybrid power module, in which a first DC connection layer, a second DC connection layer and an AC connection layer are formed on a substrate, an upper bridge chipset is formed on the first DC connection layer, and a lower bridge chipset is formed on the AC connection layer, thereby reducing the manufacturing process and improving space utilization. In addition, the wide bandgap chipset in the upper bridge chipset and the wide bandgap chipset in the lower bridge chipset are arranged along the second direction, and the first wide bandgap chipset and the second wide bandgap chipset both include a plurality of wide bandgap power chips arranged along the second direction, forming a more regular arrangement, further improving space utilization.

[0095] The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0096] Figure 1 FIG. 1 shows a schematic diagram of the structure of a hybrid power module provided by an embodiment of the present application. Figure 1 As shown, the hybrid power module of this embodiment may include:

[0097] A substrate 20; a first DC connection layer 21, a second DC connection layer 23 and an AC connection layer 22 located on the substrate 20; and an upper bridge chipset 31 located on the first DC connection layer 21, and a lower bridge chipset 32 ​​located on the AC connection layer 22, wherein the upper bridge chipset 31 includes a first wide bandgap chipset 301, and the lower bridge chipset 32 ​​includes a second wide bandgap chipset 303. The first wide bandgap chipset 301 is connected to the AC connection layer 22, and the second wide bandgap chipset 303 is connected to the second DC connection layer 23. The first wide bandgap chipset 301 and the second wide bandgap chipset 303 are arranged along the second direction, and both the first wide bandgap chipset 301 and the second wide bandgap chipset 303 include a plurality of wide bandgap power chips 11 arranged along the second direction.

[0098] In the embodiment of the present application, the substrate 20 is used to carry the connection layer and the chipset. By forming the connection layer and the chipset on one substrate, the problem of too many manufacturing processes due to the need to connect multiple substrates is solved, the manufacturing process is reduced, and the chipset and the connection layer are formed on one substrate. By reasonably setting the position of the chipset and the connection layer on the substrate, the space utilization rate can be improved. In addition, in the embodiment of the present application, the wide bandgap chipset in the upper bridge chipset 31 and the wide bandgap chipset in the lower bridge chipset 32 ​​are arranged along the second direction, and the first wide bandgap chipset 301 and the second wide bandgap chipset 303 both include a plurality of wide bandgap power chips 11 arranged in the second direction, forming a more regular arrangement, further improving the space utilization rate.

[0099] For example, the substrate 20 may include a ceramic substrate, and the ceramic substrate may be, for example, an aluminum oxide substrate, a silicon nitride substrate, a zirconium oxide substrate, or the like.

[0100] In some embodiments, in combination Figure 2 and Figure 3 As shown, the upper bridge chipset 31 also includes the first silicon-based chipset 302, and the upper bridge chipset 31 is controlled to be turned on or off through the first wide bandgap chipset 301 and the first silicon-based chipset 302. The lower bridge chipset 32 ​​also includes the second silicon-based chipset 304, and the lower bridge chipset 32 ​​is controlled to be turned on or off through the second wide bandgap chipset 303 and the second silicon-based chipset 304.

[0101] Among them, the loss of power devices is divided into switching loss and conduction loss. Switching loss is the loss generated when the power device switches on and off, and conduction loss is the loss of current flowing for a long time after the device completes the turn-on process. Switching loss includes turn-on loss and turn-off loss. Turn-on loss is the loss generated when the power device is turned on, and turn-off loss is the loss generated when the power device is turned off. The wide bandgap chipset bears the switching action and switching loss, and the silicon-based chipset bears the conduction current. Since the wide bandgap power chip has low switching loss and the silicon-based power chip has low cost, it can achieve the purpose of reducing switching loss and cost.

[0102] For example, the first wide bandgap chipset 301 and the first silicon-based chipset 302 are located on the first DC connection layer 21, and the first DC connection layer 21 can be used to connect the positive electrode of the power supply, so that the first wide bandgap chipset 301 and the first silicon-based chipset 302 can be connected to the positive electrode of the power supply. The second wide bandgap chipset 303 and the second silicon-based chipset 304 are connected to the second DC connection layer 23, and the second DC connection layer 23 can be used to connect the negative electrode of the power supply, so that the lower bridge chipset 32 ​​can be connected to the negative electrode of the power supply; the first wide bandgap chipset 301 and the first silicon-based chipset 302 are connected to the AC connection layer 22, the second wide bandgap chipset 303 and the second silicon-based chipset 304 are located on the AC connection layer 22, and the AC connection layer 22 is used to connect the load, so that the upper bridge chipset 31 and the lower bridge chipset 32 ​​can be connected to the load.

[0103] For example, the second wide bandgap chipset 303 and the second silicon-based chipset 304 can be connected to the second DC connection layer 23 via bonding wires, and the first wide bandgap chipset 301 and the first silicon-based chipset 302 can be connected to the AC connection layer 22 via bonding wires, or other connection wires.

[0104] In practical applications, at least one of the first DC connection layer 21, the second DC connection layer 23 and the AC connection layer 22 is a copper layer. For example, the first DC connection layer 21 can be a positive DC copper layer, the second DC connection layer 23 can be a negative DC copper layer, and the AC connection layer 22 can be an AC copper layer.

[0105] Considering that parallel connection of power devices can share power, so that the device can withstand greater power and output greater current, the first wide bandgap chipset 301 and the second wide bandgap chipset 303 include a plurality of wide bandgap power chips 11 arranged in the second direction.

[0106] In some embodiments, the multiple wide bandgap power chips 11 in the first wide bandgap chipset 301 are connected in parallel to each other. Specifically, the multiple wide bandgap power chips 11 in the second wide bandgap chipset 303 are all located on the AC connection layer 23 and connected to the second DC connection layer 23, thereby realizing the parallel connection of the multiple wide bandgap power chips 11 in the second wide bandgap chipset 303. For example, each wide bandgap power chip 11 in the second wide bandgap chipset 303 can be connected to the second DC connection layer 23 through a bonding wire.

[0107] The multiple wide bandgap power chips 11 in the first wide bandgap chipset 301 are connected in parallel. Specifically, the multiple wide bandgap power chips 11 in the first wide bandgap chipset 303 are located on the first DC connection layer 21 and connected to the AC connection layer 22, thereby realizing the parallel connection of the multiple wide bandgap power chips 11 in the first wide bandgap chipset 301. For example, each wide bandgap power chip 11 in the first wide bandgap chipset 303 can be connected to the AC connection layer 22 through a bonding wire.

[0108] Furthermore, the second wide bandgap chipset 303 is connected in series one by one with the wide bandgap power chips 11 in the first wide bandgap chipset 301, and the corresponding two wide bandgap power chips 11 can form a half-bridge circuit. Moreover, since multiple half-bridge circuits are connected in parallel, a half-bridge circuit with a current specification amplified N times (the number of half-bridge circuits is N) can be formed, which is beneficial to improving the power level of the half-bridge power module.

[0109] In practical applications, wide bandgap power chips may include silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFET) or gallium nitride high electron mobility transistors (GaN HEMT).

[0110] Figure 4 (A) in FIG. 1 shows a schematic diagram of the structure of the wide bandgap power chip 11. The surface electrodes of the wide bandgap power chip 11 include a source 111, a gate 112, and a drain 113 at the bottom. Accordingly, the drain 113 of the wide bandgap power chip 11 in the second wide bandgap chip group 303 fits the AC connection layer 22, and the source 111 of the wide bandgap power chip 11 in the second wide bandgap chip group 303 is connected to the second DC connection layer 23. The drain of the wide bandgap power chip 11 in the first wide bandgap chip group 301 fits the first DC connection layer 21, and the source of the wide bandgap power chip 11 in the first wide bandgap chip group 301 is connected to the AC connection layer 22.

[0111] In some embodiments, the first silicon-based chipset 302 includes a plurality of silicon-based power chips 12, so that the upper bridge chipset 31 can output a larger current. The plurality of silicon-based power chips 12 in the first silicon-based chipset 302 are connected in parallel. Specifically, the plurality of silicon-based power chips 12 in the first silicon-based chipset 302 are all located on the first DC connection layer 21, and the plurality of silicon-based power chips 12 are connected to the AC connection layer 22, so as to realize the parallel connection of the plurality of silicon-based power chips 12 in the first silicon-based chipset 302. For example, the plurality of silicon-based power chips 12 in the first silicon-based chipset 302 can be connected to the AC connection layer 22 through bonding wires.

[0112] The second silicon-based chipset 304 includes a plurality of silicon-based power chips 12, so that the lower bridge chipset 32 ​​can output a larger current. The plurality of silicon-based power chips 12 in the second silicon-based chipset 304 are connected in parallel. Specifically, the plurality of silicon-based power chips 12 in the second silicon-based chipset 304 are all located on the AC connection layer 22, and the plurality of silicon-based power chips 12 are connected to the second DC connection layer 23, so as to realize the parallel connection of the plurality of silicon-based power chips 12 in the second silicon-based chipset 304. For example, the plurality of silicon-based power chips 12 in the second silicon-based chipset 304 can be connected to the second DC connection layer 23 through bonding wires.

[0113] Furthermore, each silicon-based power chip 12 in the first silicon-based chip group 302 is connected in series with each silicon-based power chip 12 in the second silicon-based chip group 304 to form a half-bridge structure.

[0114] In some embodiments, it is considered that the dynamic current sharing of the wide bandgap power chip 11 in the second wide bandgap chipset 303 is mainly affected by the current path. Therefore, when the hybrid power module includes a second DC connection terminal 42 located on the second DC connection layer 23, the current path length between each wide bandgap power chip 11 in the second wide bandgap chipset 303 and the second DC connection terminal 42 is the same, so that the multiple wide bandgap power chips 11 in the second wide bandgap chipset 303 can achieve a current sharing effect. The second DC connection terminal 42 is used to connect an external circuit, such as connecting the negative pole of a power supply.

[0115] In other embodiments, the first wide bandgap chipset 301 includes multiple wide bandgap power chips 11, the hybrid power module includes an AC connection terminal 43, and the current path length between each wide bandgap power chip 11 in the first wide bandgap chipset 301 and the AC connection terminal 43 is the same, so that the wide bandgap power chips 11 in the first wide bandgap chipset 301 can achieve a current sharing effect.

[0116] In some other embodiments, the hybrid power module includes a first DC connection terminal 41, which is located on the first DC connection layer 21, and the current path length between each wide bandgap power chip 11 in the first wide bandgap chipset 301 and the first DC connection terminal 41 is the same, further improving the current sharing effect of the wide bandgap power chips 11 in the first wide bandgap chipset 301.

[0117] It should be noted that the second DC connection terminal 42 and the AC connection terminal 43 are an area, the second DC connection terminal 42 is the connection area of ​​each wide bandgap power chip 11 in the second wide bandgap chipset 301, and the AC connection terminal 43 is the connection area of ​​each wide bandgap power chip 11 in the first wide bandgap chipset 301. The size, length, etc. of the second DC connection terminal 42 and the AC connection terminal 43 will affect the current path length. The current path lengths between each wide bandgap power chip 11 in the second wide bandgap chipset 303 and the second DC connection terminal 42 are the same, which may mean that the shortest current path lengths between the source of each wide bandgap power chip 11 in the second wide bandgap chipset 303 and the second DC connection terminal 42 are the same. The same here may be substantially the same, for example, the difference between the current path lengths of any two wide bandgap power chips 11 in the second wide bandgap chipset 303 to the second DC connection terminal 42 is within a preset difference range. The current path lengths between each wide bandgap power chip 11 in the first wide bandgap chipset 301 and the AC connection terminal 42 are the same, which may mean that the shortest current path lengths between each wide bandgap power chip 11 in the first wide bandgap chipset 301 and the AC connection terminal 43 are the same, for example, the difference between the current path lengths between any two wide bandgap power chips 11 in the first wide bandgap chipset 301 and the AC connection terminal 43 is within a preset difference range. The preset difference range can be determined according to actual conditions and is not limited here.

[0118] Similarly, the first DC connection terminal 41 is an area, which is the connection area of ​​each wide bandgap power chip 11 in the first wide bandgap chipset 301. The current path lengths between each wide bandgap power chip 11 in the first wide bandgap chipset 301 and the first DC connection terminal 41 are the same, which may mean that the shortest current path lengths between the drain of each wide bandgap power chip 11 in the first wide bandgap chipset 301 and the first DC connection terminal 41 are the same. The same here may be substantially the same, for example, the difference between the current path lengths from any two wide bandgap power chips 11 in the first wide bandgap chipset 301 to the first DC connection terminal 41 is within a preset difference range.

[0119] As an implementation manner, the second DC connection layer 23 is further connected with a second DC connection terminal, and the second DC connection terminal is led out along the first direction to connect an external load.

[0120] As an implementation manner, the first DC connection layer 21 is further connected with a first DC connection terminal, and the first DC connection terminal is led out along a first direction to be connected to an external power source.

[0121] As an implementation manner, the AC connection layer 22 is further connected with an AC connection terminal, and the AC connection terminal is led out along a first direction to connect to an external power source.

[0122] It can be understood that when the multiple wide bandgap power chips 11 are arranged in one direction and the current direction after the multiple wide bandgap power chips 11 are merged is perpendicular or nearly perpendicular to the arrangement direction of the multiple wide bandgap power chips 11, Figure 5 As shown in (A) in FIG. 1 , each wide bandgap power chip 11 has a current path of substantially the same length, that is, has a current path of substantially the same length, so that it can have good dynamic current sharing performance. When multiple wide bandgap power chips 11 are arranged in one direction, and the current direction after the multiple wide bandgap power chips 11 are converged is parallel to the arrangement direction of the multiple wide bandgap power chips 11, as shown in FIG. Figure 5 As shown in (B), each wide bandgap power chip 11 has a cocurrent path of different lengths, that is, has a current path length of different lengths, which may cause a problem of dynamic uneven current.

[0123] Therefore, in some examples, the multiple wide bandgap power chips 11 in the second wide bandgap chipset 303 are arranged along the second direction so that the current path lengths between the multiple wide bandgap power chips 11 in the second wide bandgap chipset 303 and the second DC connection terminal 42 are the same.

[0124] In other examples, multiple wide bandgap power chips 11 in the first wide bandgap chipset 301 are arranged along the second direction to make the current path of each wide bandgap power chip 11 in the first wide bandgap chipset 301 as similar as possible, thereby improving the current sharing effect of the first wide bandgap power chipset 301.

[0125] In some examples, the second silicon-based chipset 304 may further include a plurality of diode chips 13, and the silicon-based power chips 12 correspond one to one to the diode chips 13. Specifically, each diode chip 13 is connected in parallel with a silicon-based power chip 12 in the second silicon-based chipset 304 to bear reverse freewheeling and improve the reverse freewheeling capability of the module as a whole.

[0126] In other examples, the first silicon-based chipset 302 may also include a plurality of diode chips 13, and the silicon-based power chips 12 correspond to the diode chips 13 one by one. Specifically, each diode chip 13 is connected in parallel with a silicon-based power chip 12 in the first silicon-based chipset 302 to bear reverse freewheeling and improve the reverse freewheeling capability of the module as a whole.

[0127] Furthermore, the plurality of diode chips 13 in the first silicon-based chip group 302 are respectively connected in series with the plurality of diode chips in the second silicon-based chip group 304 to bear reverse freewheeling in the upper bridge and the lower bridge respectively.

[0128] In practical applications, the silicon-based power chip 12 may include a silicon insulated gate bipolar transistor or a silicon metal oxide semiconductor field effect transistor (Si MOSFET).

[0129] The diode chip 13 may be a silicon fast recovery diode chip (Silicon Fast Recovery Diode, SiRFD) or a silicon carbide Schottky barrier diode chip (Silicon Carbide Schottky Barrier Diode, SiCSBD).

[0130] Figure 4 (B) in the figure shows a schematic diagram of the structure of a silicon-based power chip, wherein the surface electrodes of the silicon-based power chip 12 include an emitter 121, a gate 122, and a collector 123 at the bottom. Accordingly, the collector of the silicon-based power chip 12 in the second silicon-based chip group 304 is bonded to the AC connection layer 22, and the emitter of the silicon-based power chip 12 in the second silicon-based chip group 304 is connected to the second DC connection layer 23. The collector of the silicon-based power chip 12 in the first silicon-based chip group 302 is bonded to the first DC connection layer 21, and the emitter of the silicon-based power chip 12 in the first silicon-based chip group 302 is connected to the AC connection layer 22.

[0131] Figure 4 (C) in the figure shows a schematic diagram of the structure of a diode chip, wherein the diode chip 13 includes an anode 131 at the top and a cathode 132 at the bottom. Accordingly, the cathode of the diode chip 13 of the second silicon-based chip group 304 is bonded to the AC connection layer 22, and the anode of the diode chip 13 of the second silicon-based chip group 304 is connected to the second DC connection layer 23. The cathode of the diode chip 13 in the first silicon-based chip group 302 is bonded to the first DC connection layer 21, and the anode of the diode chip 13 in the first silicon-based chip group 302 is connected to the AC connection layer 22.

[0132] In order to understand the influence of the DC connection terminal position on the commutation circuit of the wide bandgap power chip, the equivalent circuit considering the parasitic inductance of the hybrid power module is explained below. Figure 6As shown, the wide bandgap power chip 11 is turned on first, at this time the voltage drops, and the wide bandgap power chip 11 bears all the current, and then the silicon-based power chip 12 is turned on, the wide bandgap power chip 11 and the silicon-based power chip 12 exchange current, and finally the wide bandgap power chip 11 and the silicon-based power chip 12 each bear part of the current; during the shutdown process, the wide bandgap power chip 11 is turned off first, at this time the silicon-based power chip 12 and the wide bandgap power chip 11 exchange current, after the wide bandgap power chip 11 bears all the current, the wide bandgap power chip 11 is turned off, at this time the voltage rises, and a shutdown voltage spike appears at the same time.

[0133] Since the switching speed of the wide bandgap power chip 11 is faster and the switching speed of the silicon-based power chip 12 is slower, the voltage spike generated by the wide bandgap power chip 11 under the same inductance is much higher than the voltage spike generated by the silicon-based power chip 12. Therefore, the turn-off spike caused by the parasitic inductance in the switching commutation circuit of the wide bandgap power chip 11 is more serious. Reducing the length of the commutation circuit of the wide bandgap power chip 11 is the main problem.

[0134] Therefore, in some examples, on the second DC connection layer 23, the second DC connection terminal 42 is arranged close to the second wide bandgap chipset 303, that is, located on the side of the second wide bandgap chipset 303 away from the second silicon-based chipset 304, so that the second DC connection terminal 42 is close to the second wide bandgap chipset 303, thereby reducing the length of the commutation loop of the second wide bandgap chipset 303, reducing the parasitic inductance in the commutation loop, and thereby reducing the voltage shutdown spike generated by the wide bandgap power chip 11.

[0135] In other examples, the hybrid power module includes a first DC connection terminal 41, which is located on the first DC connection layer, and the first DC connection terminal is located on the side of the first wide bandgap chipset 301 away from the first silicon-based chipset 302, thereby reducing the commutation loop length of the first wide bandgap chip 301, reducing the parasitic inductance in the commutation loop, and thereby reducing the voltage shutdown spike generated by the wide bandgap power chip 11.

[0136] In the above examples, the arrangement of the multiple wide bandgap power chips 11 in the first wide bandgap chipset 301 and the multiple wide bandgap power chips 11 in the second wide bandgap chipset 303 includes at least one of the following:

[0137] Each wide bandgap power chip 11 is aligned in the second direction; two adjacent wide bandgap power chips 11 are staggered in the first direction;

[0138] Each wide bandgap power chip is staggered in a first direction;

[0139] The first direction and the second direction are two directions perpendicular to each other on a plane.

[0140] like Figure 7 As shown in (A), each wide bandgap power chip 11 is neatly arranged in sequence along the second direction, and the bonding wire is connected to the corresponding connection layer along the first direction. For example, when the multiple wide bandgap power chips 11 in the first wide bandgap chipset 301 are neatly arranged in sequence along the second direction, the bonding wire of each wide bandgap power chip 11 is connected to the AC connection layer 22 along the first direction; for another example, when the multiple wide bandgap power chips 11 in the second wide bandgap chipset 303 are neatly arranged in sequence along the second direction, the bonding wire of each wide bandgap power chip 11 is connected to the AC connection layer 22 along the first direction. This arrangement is more compact and helps to improve space utilization.

[0141] like Figure 7 As shown in (B), each wide bandgap power chip 11 is arranged in sequence in the second direction, and two adjacent wide bandgap power chips 11 are staggered in the first direction, and the bonding wires are connected to the corresponding connection layer along the first direction. This arrangement is an arrangement for heat dissipation optimization, which can further reduce thermal coupling and improve heat dissipation performance.

[0142] like Figure 7 In (C), each wide bandgap power chip 11 is arranged sequentially in the second direction, and each wide bandgap power chip 11 is staggered in the first direction, and the bonding wire is connected to the corresponding connection layer along the first direction. This arrangement is an arrangement for optimizing current sharing and heat dissipation, which can adjust the source current path of different wide bandgap power chips 11, improve current sharing performance, and reduce thermal coupling and improve heat dissipation performance.

[0143] In practical applications, different arrangements of the wide bandgap power chips 11 can be flexibly selected according to requirements to meet different performance requirements.

[0144] For example, Figure 8 As shown, when a plurality of wide bandgap power chips 11 in the first wide bandgap chipset 301 are arranged in the second direction, each wide bandgap power chip 11 in the first wide bandgap chipset 301 can be arranged in a staggered arrangement in the first direction to improve the current sharing performance of the first wide bandgap chipset 301 and have better heat dissipation performance. When a plurality of wide bandgap power chips 11 in the second wide bandgap chipset 303 are arranged in the second direction, adjacent wide bandgap power chips 11 in the second wide bandgap chipset 303 can be arranged in a staggered arrangement in the first direction to enable the second wide bandgap chipset 303 to have better heat dissipation performance.

[0145] In some embodiments, in combination Figure 3 and Fig. 9As shown, the arrangement of the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the first silicon-based chip group 302, and the arrangement of the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the second silicon-based chip group 304 may include at least one of the following;

[0146] A plurality of silicon-based power chips 12 and a plurality of diode chips 13 are cross-arranged in a first direction;

[0147] The first chip combination and the second chip combination are arranged in the first direction, the first chip combination includes a plurality of silicon-based power chips 12 arranged in the first direction, and the second chip combination includes a plurality of diode chips arranged in the first direction;

[0148] A plurality of third chip assemblies are arranged in the first direction, and the third chip assembly includes a silicon-based power chip 12 and a diode chip 13 arranged in the second direction;

[0149] A plurality of fourth chip combinations and a plurality of fifth chip combinations are cross-arranged in the first direction, the fourth chip combination and the fifth chip combination include silicon-based power chips 12 and diode chips 13 arranged in the second direction, and in the fourth chip combination and the fifth chip combination, the arrangement directions of the silicon-based power chips 12 and the diode chips 13 are opposite;

[0150] The first direction and the second direction are two directions perpendicular to each other on a plane.

[0151] like Fig. 9 In (A), the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the second chip combination are arranged crosswise in the first direction, and the bonding wires are connected to the corresponding connection layers along the second direction. For example, the bonding wires of the silicon-based power chips 12 and the diode chips 13 in the first silicon-based chip group 302 are connected to the AC connection layer 22 along the second direction; for another example, the bonding wires of the silicon-based power chips 12 and the diode chips 13 in the second silicon-based chip group 304 are connected to the second DC connection layer 23 along the second direction. This arrangement has a high heat dissipation performance and a small size along the second direction.

[0152] like Fig. 9 As shown in (B), the first chip combination and the second chip combination are arranged in sequence in the first direction, the first chip combination includes a plurality of silicon-based power chips 12 arranged in sequence in the first direction, and the second chip combination includes a plurality of diode chips 13 arranged in sequence in the first direction. In this arrangement, chips of the same type are adjacent to each other, and the bonding wires are connected to the corresponding connection layers along the second direction, which is convenient for driving the bonding wire connection, and the size along the second direction is small.

[0153] like Fig. 9As shown in (C), a plurality of third chip combinations are arranged in sequence in the first direction, and the second chip combination includes a silicon-based power chip 12 and a diode chip 13 arranged in sequence in the second direction. In this arrangement, a silicon-based power chip 12 and a diode chip 13 form a pair, and multiple pairs of chips are arranged along the first direction, so that chips of the same type are adjacent along the first direction, and the bonding wires are connected to the corresponding connection layer along the second direction, and the size along the first direction is small, and it is convenient to drive the bonding wire connection.

[0154] like Fig. 9 As shown in (D), multiple fourth chip combinations and multiple fifth chip combinations are arranged crosswise in the first direction, and the combination of silicon-based power chips 12 and diode chips 13 in the fourth chip combination is different from the combination of silicon-based power chips 12 and diode chips 13 in the fifth chip combination. Multiple pairs of chips are arranged along the wide bandgap power chip 11 so that chips of the same type are not adjacent to each other, and the bonding wires are connected to the corresponding connection layers along the second direction. This arrangement has a smaller size along the first direction and has a better heat dissipation effect.

[0155] In practical applications, different arrangements of the silicon-based power chip 12 and the diode chip 13 can be flexibly selected according to the needs. For example, the silicon-based power chip 12 has a slower switching speed and less parasitic inductance, but due to the lower thermal conductivity and larger size of the silicon-based power chip 12, the layout can be mainly considered from the perspective of heat dissipation and size.

[0156] As a way to achieve this, combining Figure 2 and Figure 3 As shown, the AC connection layer 22 may include two parts, a first part and a second part are connected to each other, the first part extends in a first direction, and the second part extends in a second direction. At this time, the first wide bandgap chipset 301 and the first silicon-based chipset 302 are located on both sides of the second part, thereby reducing the length of the bonding wire between the first wide bandgap chipset 301 and the AC connection layer 22.

[0157] In some embodiments, Fig.10 As shown, the first DC connection layer 21 includes a first connection layer 211 and a second connection layer 212 which are electrically connected to each other, the first wide bandgap chipset 301 is located on the first connection layer 211, and the first silicon-based chipset 302 is located on the second connection layer 312 to meet different scenario requirements.

[0158] In some examples, a first DC connection terminal 41 is formed on both the first connection layer 211 and the second connection layer 212, so that the first wide bandgap chipset 301 on the first connection layer 211 and the first silicon-based chipset 302 on the second connection layer 212 can receive an external voltage, such as a positive voltage. A second DC connection terminal 42 is formed on the second DC connection layer 23, so that the second wide bandgap chipset 303 and the second silicon-based chipset 304 on the AC connection layer 22 can receive an external voltage, such as a negative voltage.

[0159] As a way to achieve this, Fig.10 As shown, a recess is formed between the first connection layer 211 and the second connection layer 212 to accommodate a portion of the structure protruding from the AC connection layer 22. At least a portion of the protruding structure is spaced apart from the first DC connection layer 21 and is used to electrically connect multiple wide bandgap power chips 11 in the first wide bandgap chipset 301, thereby reducing the length of the bonding wires between the second wide bandgap chipset 303 and the second silicon-based chipset 304 and the second DC connection layer 23.

[0160] For example, the second DC connection layer 23 can be located between the first connection layer 211 and the second connection layer 212, that is, the first connection layer 211 and the second connection layer 212 are located on both sides of the second DC connection layer 23, and the second DC connection layer 23 extends in the second direction. At this time, the second wide bandgap chipset 303 and the second silicon-based chipset 304 are located on both sides of the second DC connection layer 23, thereby reducing the length of the bonding wires between the second wide bandgap chipset 303 and the second silicon-based chipset 304 and the second DC connection layer 23.

[0161] like Fig.10 As shown, the first part of the AC connection layer 22 extends between the first connection layer 211 and the second DC connection layer 23, thereby reducing the length of the bonding wire between the first wide bandgap chipset 301 and the AC connection layer 22. The second part of the AC connection layer 22 extends between the second DC connection layer 23 and the second connection layer 212, thereby reducing the length of the bonding wire between the first silicon-based chipset 302 and the AC connection layer 22.

[0162] In some examples, such as Fig.10 As shown, the first wide bandgap power chip 301 and the second wide bandgap chip group 302 each include a plurality of wide bandgap power chips 11, and each wide bandgap power chip 11 is arranged along the second direction to form a more regular arrangement to improve space utilization.

[0163] As an implementation, the arrangement of the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the first silicon-based chipset group 302, and the arrangement of the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the second silicon-based chipset group 304 may include at least one of the following:

[0164] A plurality of silicon-based power chips 12 and a plurality of diode chips 13 are cross-arranged in the second direction;

[0165] The first chip combination and the second chip combination are arranged in the second direction, the first chip combination includes a plurality of silicon-based power chips 12 arranged in the second direction, and the second chip combination includes a plurality of diode chips 13 arranged in the second direction;

[0166] A plurality of third chip assemblies are arranged in the second direction, and the third chip assembly includes silicon-based power chips 12 and diode chips 13 arranged in the first direction;

[0167] A plurality of fourth chip combinations and a plurality of fifth chip combinations are cross-arranged in the second direction, the fourth chip combination and the fifth chip combination include silicon-based power chips 12 and diode chips 13 arranged in the first direction, and in the fourth chip combination and the fifth chip combination, the arrangement directions of the silicon-based power chips 12 and the diode chips 13 are opposite;

[0168] The first direction and the second direction are two directions perpendicular to each other on a plane.

[0169] In some embodiments, in combination Figure 3 and Fig.11 As shown in (B) in FIG. 1 , the hybrid power module includes an upper bridge driving layer 24 located on a substrate 20, and the upper bridge driving layer 24 includes a first gate driving layer 241 and a first source driving layer 243. For example, the first gate driving layer 241 and the first source driving layer 243 may be copper layers.

[0170] The gate of the wide bandgap power chip 11 in the first wide bandgap chipset 301 is connected to the first gate drive layer 241, and the source of the wide bandgap power chip 11 in the first wide bandgap chipset 301 is connected to the first source drive layer 243, so that the voltage difference between the gate and the source of the wide bandgap power chip 11 in the first wide bandgap chipset 301 can be controlled, thereby controlling the wide bandgap power chip 11 in the first wide bandgap chipset 301 to be in an on or off state. For example, the gate of the wide bandgap power chip 11 in the first wide bandgap chipset 301 is connected to the first gate drive layer 241 through a bonding wire, and the source of the wide bandgap power chip 11 in the first wide bandgap chipset 301 is connected to the first source drive layer 243 through a bonding wire.

[0171] In some embodiments, the upper bridge driving layer 24 further includes a second gate driving layer 242 and a first emitter driving layer 244. For example, the second gate driving layer 242 and the first emitter driving layer 244 may be copper layers.

[0172] The gate of the silicon-based power chip 12 in the first silicon-based chipset group 302 is connected to the second gate driving layer 242, and the emitter of the silicon-based power chip 12 in the first silicon-based chipset group 302 is connected to the first emitter driving layer 244, so that the voltage difference between the gate and the emitter of the silicon-based power chip 12 in the first silicon-based chipset group 302 can be controlled, thereby controlling the silicon-based power chip 12 in the first silicon-based chipset group 302 to be in an on or off state. For example, the gate of the silicon-based power chip 12 in the first silicon-based chipset group 302 is connected to the second gate driving layer 242 through a bonding wire, and the emitter of the silicon-based power chip 12 in the first silicon-based chipset group 302 is connected to the first emitter driving layer 244 through a bonding wire. For example, when multiple wide bandgap power chips 11 in the first wide bandgap chipset 301 are arranged in the second direction, and each wide bandgap power chip 11 in the first wide bandgap chipset 301 is staggered in the first direction, the first gate drive layer 241 and the first source drive layer 243 can be set on the side of the first wide bandgap chipset 301 close to the first DC connection terminal 41, thereby shortening the bonding wires between the first wide bandgap chipset 301 and the driving layer, and shortening the bonding wires between the first wide bandgap chipset 301 and the AC connection layer 22.

[0173] Combination Figure 3 and Fig.11 As shown in (A), the first source drive layer 243 and the first emitter drive layer 244 can be the same drive layer, shortening the commutation circuit between the wide bandgap power chip 11 and the silicon-based power chip 12 in the hybrid module, reducing the parasitic inductance between the wide bandgap power chip 11 and the silicon-based power chip 12, and reducing the commutation time.

[0174] In some examples, combined Figure 3 and Fig.11 As shown, a first gate drive terminal 441 is formed in the first gate drive layer 241, a second gate drive layer 242 terminal is formed in the second gate drive layer 242, a first source drive terminal 443 is formed in the first source drive layer 243, and a first emitter drive terminal 444 is formed in the first emitter drive layer 244. The first gate drive terminal 441 and the first source drive terminal 443 are connected to an external circuit, so that the gate and source of the wide bandgap power chip 11 in the first wide bandgap chipset 301 can receive an external voltage, thereby controlling the wide bandgap power chip 11 of the first wide bandgap chipset 301 to be in an on or off state. The second gate drive terminal 442 and the first emitter drive terminal 444 are connected to an external circuit, so that the gate and emitter of the silicon-based power chip 12 in the first silicon-based chipset 302 can receive an external voltage, thereby controlling the silicon-based power chip 12 in the first silicon-based chipset 302 to be in an on or off state.

[0175] For example, when the first source driving layer 243 and the first emitter driving layer 244 are the same driving layer, the first source driving terminal 443 and the first emitter driving terminal 444 are the same driving terminal.

[0176] As an implementation manner, at least one of the first gate driving terminal 441 , the second gate driving terminal 442 , the first source driving terminal 443 and the first emitter driving terminal 444 is led out perpendicularly to the substrate 20 .

[0177] In other embodiments, in combination Figure 3 and Fig.11 As shown, the hybrid power module includes a lower bridge driving layer 25, and the lower bridge driving layer 25 includes a third gate driving layer 251 and a second source driving layer 253. For example, the third gate driving layer 251 and the second source driving layer 253 are copper layers.

[0178] The gate of the wide bandgap power chip 11 in the second wide bandgap chipset 303 is connected to the third gate drive layer 251, and the source of the wide bandgap power chip 11 in the second wide bandgap chipset 303 is connected to the second source drive layer 253, so that the voltage difference between the gate and the source of the wide bandgap power chip 11 in the second wide bandgap chipset 303 can be controlled, thereby controlling the wide bandgap power chip 11 in the second wide bandgap chipset 303 to be in an on or off state. For example, the gate of the wide bandgap power chip 11 in the second wide bandgap chipset 303 is connected to the third gate drive layer 251 through a bonding wire, and the source of the wide bandgap power chip 11 in the second wide bandgap chipset 303 is connected to the second source drive layer 253 through a bonding wire.

[0179] In some other embodiments, the lower bridge driving layer 25 further includes a fourth gate driving layer 252 and a second emitter driving layer 254. For example, the fourth gate driving layer 252 and the second emitter driving layer 254 are copper layers. The gate of the silicon-based power chip 12 in the second silicon-based chipset group 304 is connected to the fourth gate driving layer 252, and the emitter of the silicon-based power chip 12 in the second silicon-based chipset group 304 is connected to the second emitter driving layer 254, so that the voltage difference between the gate and the emitter of the silicon-based power chip 12 in the second silicon-based chipset group 304 can be controlled, thereby controlling the silicon-based power chip 12 in the second silicon-based chipset group 304 to be in an on or off state. For example, the gate of the silicon-based power chip 12 in the second silicon-based chipset group 304 is connected to the fourth gate driving layer 252 through a bonding wire, and the emitter of the silicon-based power chip 12 in the second silicon-based chipset group 304 is connected to the second emitter driving layer 254 through a bonding wire.

[0180] For example, when multiple wide bandgap power chips 11 in the second wide bandgap chipset 303 are arranged in the second direction, and adjacent wide bandgap power chips 11 in the first wide bandgap chipset 301 are staggered in the first direction, the third gate drive layer 251 and the second source drive layer 253 can be set on one side of the second wide bandgap chipset 303 principle second DC connection terminal 42, thereby shortening the bonding wire between the second wide bandgap chipset 303 and the drive layer, and shortening the bonding wire between the second wide bandgap chipset 303 and the second DC connection layer 23.

[0181] Combine 3 and Fig.11 As shown in (A), the second source drive layer 253 and the second emitter drive layer 254 can be the same drive layer, which further shortens the commutation circuit between the wide bandgap power chip 11 and the silicon-based power chip 12 in the hybrid module, reduces the parasitic inductance between the wide bandgap power chip 11 and the silicon-based power chip 12, and reduces the commutation time.

[0182] In some examples, a third gate drive terminal 451 is formed in the third gate drive layer 251, a fourth gate drive terminal 452 is formed in the fourth gate drive layer 252, a second source drive terminal 453 is formed in the second source drive layer 253, and a second emitter drive terminal 454 is formed in the second emitter drive layer 254. The third gate drive terminal 451 and the second source drive terminal 453 are connected to an external circuit, so that the gate and source of the wide bandgap power chip 11 in the second wide bandgap chipset 303 can receive an external voltage, thereby controlling the wide bandgap power chip 11 in the second wide bandgap chipset 303 to be in an on or off state. The fourth gate drive terminal 452 and the second emitter drive terminal 454 are connected to an external circuit, so that the gate and emitter of the silicon-based power chip 12 in the second silicon-based chipset 304 can receive an external voltage, thereby controlling the silicon-based power chip 12 in the second silicon-based chipset 304 to be in an on or off state.

[0183] For example, when the second source driving layer 253 and the second emitter driving layer 254 are the same driving layer, the second source driving terminal 453 and the second emitter driving terminal 454 are the same driving terminal.

[0184] As an implementation manner, at least one of the third gate driving terminal 451 , the fourth gate driving terminal 452 , the second source driving terminal 453 , and the second emitter driving terminal 454 is led out perpendicularly to the substrate 20 .

[0185] In some embodiments, Figure 3As shown, at least a portion of the structure of the AC connection layer 22 is embedded in the first DC connection layer 21 and is insulated from the first DC connection 23 to connect the wide bandgap power chip 11 in the first wide bandgap chipset 301 and shorten the connection line between the wide bandgap power chip 11 in the first wide bandgap chipset 301 and the AC connection layer 22. The embedding at intervals means that at least a portion of the structure of the AC connection layer 22 is embedded in the first DC connection layer 21, and at least a portion of the structure of the AC connection layer 22 embedded in the first DC connection layer 21 is non-contact and spaced from the first DC connection layer 21 to avoid short circuit. As an implementation method, as Figure 3 As shown, the upper bridge driving layer 24 is located on the substrate 20 and between at least a portion of the structure of the AC connection layer 22 embedded in the first DC connection layer 21 and a portion of the structure of the first DC connection layer 21, for example, between the first wide bandgap chipset 301 and the first silicon-based chipset 302, thereby reducing the length of the bonding wires between the first wide bandgap chipset 301 and the first silicon-based chipset 302 and the upper bridge driving layer 24.

[0186] The lower bridge driving layer 25 is located on the substrate 20 between the second wide bandgap chipset 303 and the second silicon-based chipset 304 , thereby reducing the length of the bonding wire between the second wide bandgap chipset 303 and the second silicon-based chipset 304 and the lower bridge driving layer 25 .

[0187] As an implementation method, at least a portion of the AC connection layer 22 that is embedded in the first DC connection layer 21 includes an AC connection terminal 43, and the current path length between each wide bandgap power chip 11 in the first wide bandgap chipset 301 and the AC connection terminal 43 is the same, so as to shorten the current path length between the wide bandgap power chip 11 in the first wide bandgap chipset 301 and the AC connection terminal 43, and at the same time improve the current sharing effect of the wide bandgap power chip 11 in the first wide bandgap chipset 301.

[0188] In some examples, such as Fig.12 As shown, the hybrid power module includes two first source drive layers 243 connected to each other, and a plurality of drive resistors 5 are formed in at least one first source drive layer 243. The first ends of each drive resistor 5 are connected to each other and to the first gate drive layer 241, and the second section of each drive resistor 5 is connected to the gate of a first chip in a first chipset. The drive resistor 5 can control the switching speed of the first wide bandgap chipset 301, thereby improving the dynamic current sharing performance of the upper bridge. The number of drive resistors 5 can be the same as or different from the number of wide bandgap power chips 11 in the first wide bandgap chipset 301. For example, the two first source drive layers 243 can be connected by bonding wires.

[0189] In other examples, the hybrid power module includes two second source drive layers 253 connected to each other, and a plurality of drive resistors are formed on at least one second source drive layer 253. The first end of each drive resistor is connected to each other and to the third gate drive layer 251; the second section of each drive resistor is connected to the gate of a wide bandgap power chip 11 in the second wide bandgap chipset 301. The drive resistor can control the switching speed of the second wide bandgap chipset 303, thereby improving the dynamic current sharing effect of the lower bridge. The number of drive resistors can be the same as or different from the number of wide bandgap power chips 11 in the second wide bandgap chipset 303. For example, the two second source drive layers 253 can be connected by bonding wires.

[0190] The hybrid power module provided in the present application is described above. The present application also provides a multi-phase full-bridge hybrid module, including at least two of the above-mentioned hybrid power modules.

[0191] like Fig.13 As shown, three hybrid power modules are connected together to form a three-phase full-bridge hybrid module. For example, the three hybrid power modules can be connected to the same heat dissipation substrate 6.

[0192] The present application also provides a power conversion device, comprising at least one of the above-mentioned hybrid power modules.

[0193] The present application also provides a vehicle, comprising the above-mentioned power conversion device.

[0194] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A hybrid power module, characterized in that: The hybrid power module comprises: substrate(20); A first DC connection layer (21), an AC connection layer (22), and a second DC connection layer (23) located on the substrate (20); and an upper bridge chipset (31) located on the first DC connection layer (21), and a lower bridge chipset (32) located on the AC connection layer (22), wherein the upper bridge chipset (31) includes a first wide bandgap chipset (301), and the lower bridge chipset (32) includes a second wide bandgap chipset (303); The first wide bandgap chipset (301) is connected to the AC connection layer (22), and the second wide bandgap chipset (303) is connected to the second DC connection layer (23); The first wide bandgap chipset (301) and the second wide bandgap chipset (303) are arranged along a second direction, and the first wide bandgap chipset (301) and the second wide bandgap chipset (303) both include a plurality of wide bandgap power chips (11) arranged along the second direction.

2. The hybrid power module according to claim 1, characterized in that: The upper bridge chipset (31) further includes a first silicon-based chipset (302), and the lower bridge chipset (32) further includes a second silicon-based chipset (304), and each silicon-based power chip in the first silicon-based chipset (302) is respectively connected in series with a silicon-based power chip in the second silicon-based chipset (304) to form a half-bridge structure.

3. The hybrid power module according to claim 1, characterized in that: The second wide bandgap chipset (303) is connected in series with the wide bandgap power chips (11) in the first wide bandgap chipset (301) in a one-to-one correspondence to form a half-bridge circuit, and a plurality of wide bandgap power chips (11) in the wide bandgap chipset are connected in parallel.

4. The hybrid power module according to claim 1, characterized in that: The hybrid power module comprises a second DC connection terminal (42) located on the second DC connection layer (23), and the current path length between the wide bandgap power chip (11) of each second wide bandgap chipset (303) and the second DC connection terminal (42) is the same.

5. The hybrid power module according to claim 1, characterized in that: At least a portion of the structure of the AC connection layer is embedded in the first DC connection layer (21) and is arranged in an insulated manner from the first DC connection layer (23) to connect the wide bandgap power chip (11) in the first wide bandgap chipset (301).

6. The hybrid power module according to claim 4, characterized in that: On the second DC connection layer (23), the second DC connection terminal (42) is arranged close to the second wide bandgap chipset (303).

7. The hybrid power module according to claim 1, characterized in that: The hybrid power module further comprises a first DC connection terminal (41), the first DC connection terminal (41) being located on the first DC connection layer (21), and the current path length between the wide bandgap power chip (11) of each of the first wide bandgap chipsets (301) and the first DC connection terminal (41) being the same.

8. The hybrid power module according to claim 2, characterized in that: The first DC connection layer (21) comprises a first connection layer (211) and a second connection layer (212) electrically connected to each other; The first wide bandgap chipset (301) is located on the first connection layer (211), and the first silicon-based chipset (302) is located on the second connection layer (212).

9. The hybrid power module according to claim 8, characterized in that: The first connection layer (211) and the second connection layer (212) are located on both sides of the second DC connection layer (23).

10. The hybrid power module according to claim 8, characterized in that: A recess is formed between the first connection layer (211) and the second connection layer (212) to accommodate at least a portion of the protruding structure of the AC connection layer; the at least a portion of the protruding structure is spaced apart from the first DC connection layer and is used to electrically connect a plurality of wide bandgap power chips (11) in the first wide bandgap chipset (301).

11. The hybrid power module according to any one of claims 1 to 10, characterized in that: The arrangement of the plurality of wide bandgap power chips (11) includes at least one of the following: Each of the wide bandgap power chips (11) is arranged flush in the second direction; Two adjacent wide bandgap power chips (11) are staggered in a first direction; Each of the wide bandgap power chips (11) is arranged in a staggered manner in the first direction; The first direction and the second direction are two directions perpendicular to each other on a plane.

12. The hybrid power module according to claim 2, characterized in that: The first silicon-based chip group (302) further includes a plurality of diode chips (13).

13. The hybrid power module according to claim 12, characterized in that: The second silicon-based chip group (304) further includes a plurality of diode chips (13).

14. The hybrid power module according to claim 13, characterized in that: The plurality of diode chips (13) of each of the first silicon-based chip groups (302) are respectively connected in series with the plurality of diode chips (13) of the second silicon-based chip group (304).

15. The hybrid power module according to claim 13, characterized in that: The arrangement of the plurality of silicon-based power chips (12) and the plurality of diode chips (13) in any one of the silicon-based chipsets includes at least one of the following: The silicon-based power chip (12) and the diode chip (13) are cross-arranged in a first direction; A first chip combination and a second chip combination are arranged in the first direction, the first chip combination includes a plurality of the silicon-based power chips (12) arranged in the first direction, and the second chip combination includes a plurality of the diode chips (13) arranged in the first direction; A plurality of third chip combinations are arranged in the first direction, the third chip combination comprising the silicon-based power chip (12) and the diode chip (13) arranged in the second direction; A plurality of fourth chip combinations and a plurality of fifth chip combinations are cross-arranged in the first direction, the fourth chip combination and the fifth chip combination include the silicon-based power chips (12) and the diode chips (13) arranged in the second direction, and in the fourth chip combination and the fifth chip combination, the silicon-based power chips (12) and the diode chips (13) are arranged in opposite directions; The first direction and the second direction are two directions perpendicular to each other on a plane.

16. The hybrid power module according to claim 13, characterized in that: The arrangement of the plurality of silicon-based power chips (12) and the plurality of diode chips (13) in any one of the silicon-based chip groups includes at least one of the following: The silicon-based power chip (12) and the diode chip (13) are arranged crosswise in the second direction; A first chip combination and a second chip combination are arranged in the second direction, the first chip combination includes a plurality of the silicon-based power chips (12) arranged in the second direction, and the second chip combination includes a plurality of the diode chips (13) arranged in the second direction; A plurality of third chip assemblies are arranged in the second direction, the third chip assemblies comprising the silicon-based power chips (12) and the diode chips (13) arranged in the first direction; A plurality of fourth chip combinations and a plurality of fifth chip combinations are cross-arranged in the second direction, the fourth chip combination and the fifth chip combination include the silicon-based power chips (12) and the diode chips (13) arranged in the first direction, and in the fourth chip combination and the fifth chip combination, the arrangement directions of the silicon-based power chips (12) and the diode chips (13) are opposite.

17. The hybrid power module according to claim 12, characterized in that: The hybrid power module comprises: An upper bridge driving layer (24) located on the substrate, the upper bridge driving layer (24) comprising a first gate driving layer (241) and a first source driving layer (243); The gate of each wide bandgap power chip (11) in the first wide bandgap chipset (301) is connected to the first gate drive layer (241), and the source of each wide bandgap power chip (11) in the first wide bandgap chipset (301) is connected to the first source drive layer (243).

18. The hybrid power module according to claim 17, characterized in that: The upper bridge driving layer (24) further comprises: a second gate driving layer (242) and a first emitter driving layer (244); the gate of each of the silicon-based power chips (12) in the first silicon-based chip group (302) is connected to the second gate driving layer (242); and the emitter of each of the silicon-based power chips (12) in the first silicon-based chip group (302) is connected to the first emitter driving layer (244).

19. The hybrid power module according to claim 13, characterized in that: The hybrid power module comprises: A lower bridge driving layer (25) located on the substrate, the lower bridge driving layer (25) comprising a third gate driving layer (251) and a second source driving layer (253); The gate of each wide bandgap power chip (11) in the second wide bandgap chipset (303) is connected to the third gate drive layer (251), and the source of each wide bandgap power chip (11) in the second wide bandgap chipset (303) is connected to the second source drive layer (253).

20. The hybrid power module according to claim 19, characterized in that: The lower bridge driving layer (25) further comprises a fourth gate driving layer (252) and a second emitter driving layer (254); the gate of each of the silicon-based power chips (12) in the second silicon-based chip group (304) is connected to the fourth gate driving layer (252); and the emitter of each of the silicon-based power chips (12) in the second silicon-based chip group (304) is connected to the second emitter driving layer (254).

21. The hybrid power module according to claim 18, characterized in that: The first source driving layer (243) and the first emitter driving layer (244) are the same driving layer.

22. The hybrid power module according to claim 18, characterized in that: The hybrid power module comprises: A first gate drive terminal (441) provided in the first gate drive layer (241), a second gate drive terminal (442) provided in the second gate drive layer (242), a first source drive terminal (443) provided in the first source drive layer (243), and a first emitter drive terminal (444) provided in the first emitter drive layer (244).

23. The hybrid power module according to claim 22, characterized in that: At least one of the first gate driving terminal (441), the second gate driving terminal (442), the first source driving terminal (443) and the first emitter driving terminal (444) is led out perpendicularly to the substrate.

24. The hybrid power module according to claim 20, characterized in that: The second source driving layer (253) and the second emitter driving layer (254) are the same driving layer.

25. The hybrid power module according to claim 20, characterized in that: The hybrid power module comprises: A third gate drive terminal (451) provided in the third gate drive layer (251), a fourth gate drive terminal (452) provided in the fourth gate drive layer (252), a second source drive terminal (453) provided in the second source drive layer (253), and a second emitter drive terminal (454) provided in the second emitter drive layer (254).

26. The hybrid power module according to claim 25, characterized in that: At least one of the third gate driving terminal (451), the fourth gate driving terminal (452), the second source driving terminal (453) and the second emitter driving terminal (454) is led out perpendicularly to the substrate.

27. The hybrid power module according to claim 17, characterized in that: The hybrid power module comprises: Two first source driving layers (243) connected to each other, at least one of the source driving layers (243) being provided with a plurality of driving resistors (5); The first end of each of the driving resistors (5) is connected to each other and to the first gate driving layer (241), and the second end of each of the driving resistors (5) is connected to the gate of one of the first wide bandgap power chips (11) in the first wide bandgap chipset (301).

28. The hybrid power module according to claim 19, characterized in that: The hybrid power module comprises: Two second source drive layers (253) are connected to each other, and at least one of the second source drive layers (253) is provided with a plurality of drive resistors (5); the first end of each of the drive resistors (5) is connected to each other and to the third gate drive layer (251), and the second end of each of the drive resistors (5) is connected to the gate of one of the wide bandgap power chips (11) in the second wide bandgap chipset (303).

29. The hybrid power module according to claim 5, characterized in that: At least a portion of the structure of the AC connection layer that is embedded in the first DC connection layer comprises an AC connection terminal (43), and the current path lengths from each of the wide bandgap power chips (11) in the first wide bandgap chipset (301) to the AC connection terminal (43) are the same.

30. The hybrid power module according to claim 1, characterized in that: The second DC connection layer (23) is also connected to a second DC connection terminal, and the second DC connection terminal is led out along the first direction.

31. The hybrid power module according to claim 1, characterized in that: The first DC connection layer (21) is also connected to a first DC connection terminal, which is led out along a first direction.

32. The hybrid power module according to claim 1, characterized in that: The AC connection layer (22) is also connected with an AC connection terminal, and the AC connection terminal is led out along a first direction.

33. The hybrid power module according to any one of claims 1 to 10, characterized in that: At least one of the first DC connection layer (21), the second DC connection layer (23) and the AC connection layer (22) is a copper layer.

34. The hybrid power module according to any one of claims 1 to 10, characterized in that: The wide bandgap power chip includes a silicon carbide metal oxide semiconductor field effect transistor or a gallium nitride high electron mobility transistor.

35. The hybrid power module according to claim 13, characterized in that: The silicon-based power chip includes a silicon insulated gate bipolar transistor or a silicon metal oxide semiconductor field effect transistor; The diode chip includes a silicon fast recovery diode chip or a silicon carbide Schottky diode chip.

36. A multi-phase full-bridge hybrid module, characterized in that: Comprising at least two hybrid power modules according to any one of claims 1-35.

37. A power conversion device, characterized in that: Comprising at least one hybrid power module according to any one of claims 1-35.

38. A vehicle, characterized in that: Includes the power conversion device as described in claim 37.

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