Hybrid power module, multi-phase full-bridge hybrid module, power conversion device, and vehicle

Abstract

The invention provides a hybrid power module, a multi-phase full-bridge hybrid module, a power conversion device and a vehicle. The hybrid power module comprises a substrate; the first direct-current connecting layer and the alternating-current connecting layer are located on the substrate, and the alternating-current connecting layer comprises a first alternating-current connecting layer and a second alternating-current connecting layer which are separately arranged on the two sides of the first direct-current connecting layer; the upper bridge chip set and the lower bridge chip set are arranged on the first direct-current connecting layer, one part of the lower bridge chip set is arranged on the first alternating-current connecting layer, and the other part of the lower bridge chip set is arranged on the second alternating-current connecting layer; and the chips in the upper bridge chip group are electrically connected with the alternating current connecting layer. According to the scheme, the power level can be well expanded, the switching loss and cost problems are considered, and the current sharing performance of the chip can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of power conversion, and in particular to a hybrid power module, a multi-phase full-bridge hybrid module, a power conversion device and a vehicle. Background Art

[0002] Hybrid power modules composed of wide bandgap semiconductor power devices (eg, silicon carbide metal oxide semiconductor field effect transistors, SiMOSFET) and silicon-based fully controlled power semiconductor devices (eg, silicon insulated gate bipolar transistors, Si IGBT) are gradually gaining widespread attention.

[0003] When a hybrid power module includes multiple devices connected in parallel, how to improve the current sharing performance of multiple devices in parallel is a more important issue. Summary of the invention

[0004] The present application provides a hybrid power module, a multi-phase full-bridge hybrid module, a power conversion device and a vehicle, which are used to improve the current sharing performance when multiple devices are connected in parallel.

[0005] In a first aspect, the present application provides a hybrid power module, the hybrid power module comprising:

[0006] substrate;

[0007] a first DC connection layer and an AC connection layer located on the substrate, wherein the AC connection layer comprises a first AC connection layer and a second AC connection layer separated and arranged on both sides of the first DC connection layer;

[0008] An upper bridge chipset, arranged on the first DC connection layer;

[0009] A lower bridge chipset, wherein a portion of the chips of the lower bridge chipset is arranged on the first AC connection layer, and another portion of the chips is arranged on the second AC connection layer;

[0010] The chips in the upper bridge chipset are electrically connected to the AC connection layer.

[0011] In some embodiments, the first DC connection layer is disposed between the first AC connection layer and the second AC connection layer, and the first AC connection layer and the second AC connection layer are electrically connected via leads or terminals.

[0012] In some embodiments, the lower bridge chipset includes a second wide bandgap chipset, the chips in the upper bridge chipset are electrically connected to the first AC connection layer, and the second wide bandgap chipset is disposed on the first AC connection layer.

[0013] In some embodiments, the lower bridge chipset further includes a second silicon-based chipset, and the second silicon-based chipset is disposed on the second AC connection layer.

[0014] In some embodiments, the upper bridge chipset includes a first wide bandgap chipset, the first wide bandgap chipset and the second wide bandgap chipset are arranged along a first direction, and the first wide bandgap chipset and the second wide bandgap chipset both include a plurality of wide bandgap power chips arranged along a second direction.

[0015] In some embodiments, the second wide bandgap chipset is connected in series with the wide bandgap power chips in the first wide bandgap chipset in a one-to-one correspondence.

[0016] In some embodiments, the upper bridge chipset further includes a first silicon-based chipset, and the silicon-based power chips in the first silicon-based chipset are respectively connected in series with the silicon-based power chips in the second silicon-based chipset in a one-to-one correspondence.

[0017] In some embodiments, the first AC connection layer includes a first AC connection terminal, and the current path lengths from each of the wide bandgap power chips in the first wide bandgap chipset to the first AC connection terminal are the same.

[0018] In some embodiments, the hybrid power module further includes a second DC connection layer, and the second wide bandgap chipset is electrically connected to the second DC connection layer.

[0019] In some embodiments, the hybrid power module includes a second DC connection terminal located on the second DC connection layer; and the current path length between each of the wide bandgap power chips in the second wide bandgap chipset and the second DC connection terminal is the same.

[0020] In some embodiments, the upper bridge chipset includes:

[0021] A first silicon-based chipset and a first wide bandgap chipset are arranged on the first DC connection layer along a first direction.

[0022] In some embodiments, the lower bridge chipset further includes:

[0023] A second silicon-based chipset, wherein the second silicon-based chipset and the second wide bandgap chipset are arranged in a first direction.

[0024] In some embodiments, on the second DC connection layer, the second DC connection terminal is disposed close to the second wide bandgap chipset.

[0025] In some embodiments, the first silicon-based chipset includes a plurality of silicon-based power chips and a plurality of diode chips, and the silicon-based power chips and the diode chips are connected in parallel in a one-to-one correspondence.

[0026] In some embodiments, the second silicon-based chipset includes a plurality of silicon-based power chips and a plurality of diode chips, and the silicon-based power chips and the diode chips are connected in parallel in a one-to-one correspondence.

[0027] In some embodiments, the second DC connection layer includes a first DC negative electrode connection layer and a second DC negative electrode connection layer, and the first DC negative electrode connection layer and the second DC negative electrode connection layer are connected.

[0028] In some embodiments, the first AC connection layer, the first DC connection layer and the second AC connection layer are disposed between the first DC negative electrode connection layer and the second DC negative electrode connection layer.

[0029] In some embodiments, the first AC connection layer is disposed close to the first DC negative electrode connection layer in a first direction, and the second AC connection layer is disposed close to the second DC negative electrode connection layer in the first direction.

[0030] In some embodiments, the first DC negative electrode connection layer and the second DC negative electrode connection layer enclose the first AC connection layer, the first DC connection layer and the second AC connection layer.

[0031] In some embodiments, the second DC negative connection layer is at least partially disposed close to the first DC connection layer.

[0032] In some embodiments, a current direction of the second DC negative connection layer is opposite to a current direction of the first DC connection layer.

[0033] In some embodiments, the second AC connection layer includes a second AC connection terminal, and the chip of the first silicon-based chipset is connected to the second AC connection terminal.

[0034] In some embodiments, on the second AC connection layer, the second AC connection terminal is disposed close to the first silicon-based chipset.

[0035] In some embodiments, the hybrid power module includes two first DC terminals, and the two first DC terminals are respectively located on the first DC negative electrode connection layer and the second DC negative electrode connection layer.

[0036] In some embodiments, the arrangement of the plurality of wide bandgap power chips includes at least one of the following:

[0037] Each of the wide bandgap power chips is aligned in the second direction;

[0038] Two adjacent wide bandgap power chips are staggered in a first direction;

[0039] The first direction and the second direction are two directions perpendicular to each other on a plane.

[0040] In some embodiments, a silicon-based chipset includes:

[0041] The arrangement of the plurality of silicon-based power chips and the plurality of diode chips includes at least one of the following:

[0042] The first chip combination, the second chip combination and the third chip combination are arranged sequentially in the second direction, the first chip combination includes at least one silicon-based power chip arranged sequentially in the second direction, the second chip combination includes at least one diode chip arranged sequentially in the second direction, and the third chip combination includes at least one silicon-based power chip arranged sequentially in the second direction;

[0043] A fourth chip combination, a fifth chip combination and a sixth chip combination are arranged sequentially in the second direction, the fourth chip combination includes at least one diode chip arranged sequentially in the second direction, the fifth chip combination includes at least one silicon-based power chip arranged sequentially in the second direction, and the sixth chip combination includes at least one diode chip arranged sequentially in the second direction;

[0044] A plurality of silicon-based power chips and a plurality of diode chips are cross-arranged in the second direction.

[0045] In some embodiments, the hybrid power module comprises:

[0046] A first gate driving layer and a first source driving layer located on the substrate;

[0047] A gate of each of the wide bandgap power chips in the first wide bandgap chipset is connected to the first gate driving layer, and a source of each of the wide bandgap power chips in the first wide bandgap chipset is connected to the first source driving layer.

[0048] In some embodiments, the hybrid power module comprises:

[0049] A second gate driving layer and a first emitter driving layer are located on the substrate; the gate of each of the silicon-based power chips in the first silicon-based chipset is connected to the second gate driving layer, and the emitter of each of the silicon-based power chips in the first silicon-based chipset is connected to the first emitter driving layer.

[0050] In some embodiments, the hybrid power module comprises:

[0051] A third gate driving layer and a second source driving layer are located on the substrate.

[0052] A gate of each of the wide bandgap power chips in the second wide bandgap chipset is connected to the third gate driving layer, and a source of each of the wide bandgap power chips in the second wide bandgap chipset is connected to the second source driving layer.

[0053] In some embodiments, the hybrid power module comprises:

[0054] A fourth gate driving layer and a second emitter driving layer are located on the substrate; the gate of each of the silicon-based power chips in the second silicon-based chipset is connected to the fourth gate driving layer, and the emitter of each of the silicon-based power chips in the second silicon-based chipset is connected to the second emitter driving layer.

[0055] In some embodiments, the hybrid power module comprises:

[0056] A first gate driving terminal is provided in the first gate driving layer and a first source driving terminal is provided in the first source driving layer.

[0057] In some embodiments, the hybrid power module comprises:

[0058] A second gate driving terminal is provided in the second gate driving layer and a first emitter driving terminal is provided in the first emitter driving layer.

[0059] In some embodiments, the hybrid power module comprises:

[0060] A third gate driving terminal is provided in the third gate driving layer and a second source driving terminal is provided in the second source driving layer.

[0061] In some embodiments, the hybrid power module comprises:

[0062] A fourth gate driving terminal is provided in the fourth gate driving layer and a second emitter driving terminal is provided in the second emitter driving layer.

[0063] In some embodiments, at least one of the first DC connection layer, the second DC connection layer, and the AC connection layer is a copper layer.

[0064] In some embodiments, the wide bandgap power chip includes a silicon carbide metal oxide semiconductor field effect transistor, or a gallium nitride high electron mobility transistor.

[0065] In some embodiments, the silicon-based power chip includes a silicon insulated gate bipolar transistor, or a silicon metal oxide semiconductor field effect transistor;

[0066] The diode chip includes a silicon fast recovery diode chip or a silicon carbide Schottky diode chip.

[0067] In a second aspect, the present application provides a multi-phase full-bridge hybrid module, comprising at least two of the above hybrid power modules.

[0068] In a third aspect, the present application provides a power conversion device, comprising at least one of the above-mentioned hybrid power modules.

[0069] In a fourth aspect, the present application provides a vehicle comprising the above-mentioned power conversion device.

[0070] The hybrid power module, multi-phase full-bridge hybrid module, power conversion device and vehicle provided by the present application include: a substrate; a first DC connection layer and an AC connection layer located on the substrate, the AC connection layer includes a first AC connection layer and a second AC connection layer separated and arranged on both sides of the first DC connection layer; an upper bridge chipset and a lower bridge chipset arranged on the first DC connection layer, a part of the chips of the lower bridge chips are arranged on the first AC connection layer, and another part of the chips are arranged on the second AC connection layer; the chips in the upper bridge chipset are electrically connected to the AC connection layer. The solution of the present application can better expand the power level, take into account the switching loss and cost issues, and can also provide the current sharing performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0072] Figure 1 A schematic diagram of the layout of a hybrid power module provided in one embodiment of the present application;

[0073] Figure 2 A schematic diagram of the layout of a hybrid power module provided in another embodiment of the present application;

[0074] Figure 3 A schematic diagram of the layout of a hybrid power module provided in yet another embodiment of the present application;

[0075] Figure 4 A schematic diagram of a flow path of a first chip provided in an embodiment of the present application;

[0076] Figure 5 A schematic diagram of the structure of a chip provided in one embodiment of the present application;

[0077] Figure 6 A schematic diagram of an AC terminal provided in an embodiment of the present application;

[0078] Figure 7An equivalent circuit and a schematic diagram of a switching waveform of a hybrid power module provided in an embodiment of the present application;

[0079] Figure 8 A schematic diagram of the layout of a first chipset provided in an embodiment of the present application;

[0080] Fig. 9 A schematic diagram of the layout of a hybrid power module provided in yet another embodiment of the present application;

[0081] Fig.10 A schematic diagram of the layout of a second chipset provided in an embodiment of the present application;

[0082] Fig.11 A schematic diagram of a multi-phase hybrid power module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0083] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0084] In many fields such as automobiles and power systems, it is very important to reduce the power loss of power conversion devices such as inverters and frequency converters, and power semiconductor devices in power conversion devices such as inverters and frequency converters play an important role. The performance of traditional silicon-based power semiconductor devices is difficult to meet the current requirements for power switching devices in terms of blocking voltage, on-state current, operating frequency, high temperature, and high efficiency.

[0085] Silicon-based fully controlled power semiconductor devices represented by silicon insulated gate bipolar transistors (SiIGBT) have excellent performances such as simple control circuit, high voltage resistance, and large current bearing, and are widely used in power conversion devices such as inverters and frequency converters. However, when silicon-based fully controlled power semiconductor devices represented by silicon insulated gate bipolar transistors are turned off, the collector current decays slowly, that is, the tail current is obvious, and the tail current will increase its switching loss, especially when used as a high-frequency switch, the loss is even greater.

[0086] Wide bandgap semiconductor materials represented by silicon carbide have excellent physical properties such as large bandgap width, high saturated electron drift rate, and high thermal conductivity, which can greatly reduce the loss of power conversion devices such as inverters and frequency converters and improve conversion efficiency. However, wide bandgap semiconductor power devices represented by silicon carbide are relatively expensive.

[0087] Therefore, wide bandgap semiconductor power devices and silicon-based fully-controlled power semiconductor devices can be connected in parallel to form a hybrid power module. The switch of the hybrid power module can be controlled by the wide bandgap semiconductor power device, and the main conduction current can be taken by the silicon-based fully-controlled power semiconductor device, thereby combining the advantages of the two devices to achieve the purpose of reducing switching losses and costs.

[0088] When a hybrid power module includes multiple devices connected in parallel, current sharing problems are likely to occur. How to improve the current sharing performance when multiple devices are connected in parallel is a more important issue.

[0089] To this end, the present application proposes a hybrid power module, in which the AC connection layer includes a first AC connection layer and a second AC connection layer, a part of the chips in the lower bridge chipset is arranged in the first AC connection layer, and another part of the chips is arranged in the second AC connection layer. This can better expand the power level, take into account switching losses and cost issues, and provide chip current sharing performance, thereby improving the electrical performance and reliability of the half-bridge power module. Moreover, since the hybrid power module is formed on a substrate, it can reduce the manufacturing process and improve space utilization.

[0090] The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0091] Figure 1-Figure 3 FIG. 1 is a schematic diagram showing the structure of a hybrid power module provided by an embodiment of the present application. Figure 1-Figure 3 As shown, the hybrid power module of this embodiment may include:

[0092] A substrate 20; a first DC connection layer 21 and an AC connection layer 22 located on the substrate 20, wherein the AC connection layer 22 includes a first AC connection layer 221 and a second AC connection layer 222 separated and arranged on both sides of the first DC connection layer 21;

[0093] The upper bridge chipset 31 is disposed on the first DC connection layer 21;

[0094] A lower bridge chipset 32, wherein a portion of the chips of the lower bridge chipset 32 ​​is disposed on the first AC connection layer 221, and another portion of the chips is disposed on the second AC connection layer 222;

[0095] The chips in the upper bridge chipset 31 are electrically connected to the AC connection layer 22 .

[0096] In the embodiment of the present application, the substrate 20 is used to carry the connection layer and the chipset. By forming the connection layer and the chipset on one substrate, the problem of too many manufacturing processes due to the need to connect multiple substrates is solved, and the manufacturing process is reduced. In addition, by forming the chipset and the connection layer on one substrate, the space utilization rate can be improved by reasonably setting the position of the chipset and the connection layer on the substrate. In addition, the upper bridge chipset and the lower bridge chipset are included, which can take into account the switching loss and cost issues. In addition, the lower bridge chipset includes multiple chips, which can better expand the power level.

[0097] For example, the substrate 20 may include a ceramic substrate, and the ceramic substrate may be, for example, an aluminum oxide substrate, a silicon nitride substrate, a zirconium oxide substrate, or the like.

[0098] It should be noted that the upper bridge chipset 31, the lower bridge chipset 32 ​​and the connection layer in the hybrid power module form a half-bridge structure, which is connected to the power supply and the load, and can convert the DC power supply into AC power supply for use by the load.

[0099] In some embodiments, the first DC connection layer 21 is disposed between the first AC connection layer 221 and the second AC connection layer 222, and the first AC connection layer 221 and the second AC connection layer 222 are electrically connected through leads or terminals to facilitate the connection between the chipset and the AC connection layer, shorten the length of the connection line, etc.

[0100] In some embodiments, the lower bridge chipset 32 ​​includes a second wide bandgap chipset 312 , and the second wide bandgap chipset 312 can bear the switching loss, thereby achieving the purpose of reducing the switching loss.

[0101] In some examples, the lower bridge chipset 32 ​​further includes a second silicon-based chipset 322 disposed on the second AC connection layer 222 . The lower bridge chipset 32 ​​is controlled to be turned on or off by the second silicon-based chipset 322 and the second wide bandgap chipset 312 .

[0102] Among them, the loss of power devices is divided into switching loss and conduction loss. Switching loss is the loss generated when the power device switches on and off, and conduction loss is the loss of current flowing for a long time after the device completes the turn-on process. Switching loss includes turn-on loss and turn-off loss. Turn-on loss is the loss generated when the power device is turned on, and turn-off loss is the loss generated when the power device is turned off. The wide bandgap chipset bears the switching action and switching loss, and the silicon-based chipset bears the conduction current. Since the wide bandgap power chip has low switching loss and the silicon-based power chip has low cost, it can achieve the purpose of reducing switching loss and cost.

[0103] In other examples, the upper bridge chipset 31 includes a first wide bandgap chipset 311, and the first wide bandgap chipset 311 can bear the switching loss, thereby achieving the purpose of reducing the switching loss. And the first wide bandgap chipset 311 and the second wide bandgap chipset 312 are arranged along the first direction to improve space utilization. In addition, the first wide bandgap chipset 311 and the second wide bandgap chipset 312 both include a plurality of wide bandgap power chips arranged along the second direction, so that the upper bridge chipset 31 and the lower bridge chipset 32 ​​can carry more power and output more current. For example, the first direction and the second direction are two directions that meet perpendicularly on a plane.

[0104] As an implementation method, the wide bandgap power chips 11 in the second wide bandgap chipset 312 and the first wide bandgap chipset 311 are connected in series one by one, and the corresponding two wide bandgap power chips 11 can form a half-bridge circuit. Moreover, since multiple half-bridge circuits are connected in parallel, a half-bridge circuit with a current specification amplified N times (the number of half-bridge circuits is N) can be formed, which is beneficial to improving the power level of the half-bridge power module.

[0105] In some other examples, the upper bridge chipset 31 further includes a first silicon-based chipset 321, and the upper bridge chipset 31 is controlled to be turned on or off through the first silicon-based chipset 321 and the first wide bandgap chipset 311. The first silicon-based chipset 321 can bear the conduction current and has a low cost, thereby achieving the purpose of reducing costs, and the first wide bandgap chipset 311 bears the switching loss, thereby achieving the purpose of reducing the switching loss and cost.

[0106] Furthermore, the chips in the first silicon-based chipset 321 are connected in series with the chips in the second silicon-based chipset 322 in a one-to-one correspondence to form a half-bridge structure.

[0107] In some embodiments, the first AC connection layer 221 includes a first AC connection terminal 431, and the current path length between each wide bandgap power chip 11 in the first wide bandgap chipset 311 and the first AC connection terminal 431 is the same. The first AC connection terminal 431 is an area, and the length, size, etc. of the first AC connection terminal 431 will affect the current path length. Therefore, the current path length between each wide bandgap power chip 11 in the first wide bandgap chipset 311 and the first AC connection terminal 431 is the same, and the shortest current path length from the source of each wide bandgap power chip 11 in the first wide bandgap chipset 311 to the first AC connection terminal 431 is the same. And the same here can be completely the same, or the current path length can be slightly different, for example, the difference between the current path lengths of any two wide bandgap power chips 11 in the first wide bandgap chipset 311 to the first AC connection terminal 431 is within a preset difference range, and the preset difference range can be determined according to actual conditions.

[0108] In some embodiments, the hybrid power module further includes a second DC connection layer 23 , and the second wide bandgap chipset 312 is electrically connected to the second DC connection layer 23 so as to lead out the lower bridge chipset 32 ​​.

[0109] It should be noted that the upper bridge chipset 31, the lower bridge chipset 32 ​​and the connection layer in the hybrid power module form a half-bridge structure, which is connected to the power supply and the load, and can convert the DC power supply into AC power supply for use by the load.

[0110] Specifically, the upper bridge chipset 31 is located on the first DC connection layer 21, and the first DC connection layer 21 can be used to connect the positive electrode of the power supply, so that the upper bridge chipset 31 can be connected to the positive electrode of the power supply; the lower bridge chipset 32 ​​is connected to the second DC connection layer 23, and the second DC connection layer 23 can be used to connect the negative electrode of the power supply, for example, through the second DC terminal 42 to connect the negative electrode of the power supply, so that the lower bridge chipset 32 ​​can be connected to the negative electrode of the power supply; the upper bridge chipset 31 is connected to the AC connection layer 22, the lower bridge chipset 32 ​​is located on the AC connection layer 22, and the AC connection layer 22 is used to connect the load, for example, through the AC terminal 43 to connect the load, so that the upper bridge chipset 31 and the lower bridge chipset 32 ​​can be connected to the load. For example, the lower bridge chipset 32 ​​can be connected to the second DC connection layer 23 through a bonding wire, and the upper bridge chipset 31 can be connected to the AC connection layer 22 through a bonding wire, or through other connection wires.

[0111] In practical applications, at least one of the first DC connection layer 21, the second DC connection layer 23 and the first AC connection layer 221, the second AC connection layer 222 is a copper layer. For example, the first DC connection layer 21 can be a positive DC copper layer, and the second DC connection layer 23 can be a negative DC copper layer.

[0112] As an implementation method, multiple wide bandgap power chips 11 in the first wide bandgap chipset 311 are connected in parallel. Specifically, multiple wide bandgap power chips 11 in the first wide bandgap chipset 311 are all located on the first DC connection layer 21, and multiple wide bandgap power chips 11 are connected to the AC connection layer 22, thereby realizing the parallel connection of multiple wide bandgap power chips 11 in the first wide bandgap chipset 311. For example, each wide bandgap power chip 11 in the first wide bandgap chipset 311 can be connected to the AC connection layer 22 through a bonding wire.

[0113] The multiple wide bandgap power chips 11 in the second wide bandgap chipset 312 are connected in parallel. Specifically, the multiple wide bandgap power chips 11 in the second wide bandgap chipset 312 are all located on the AC connection layer 22, and the multiple wide bandgap power chips 11 are connected to the second DC connection layer 23, thereby realizing the parallel connection of the multiple wide bandgap power chips 11 in the second wide bandgap chipset 312. For example, each wide bandgap power chip 11 in the second wide bandgap chipset 312 can be connected to the second DC connection layer 23 through a bonding wire.

[0114] Furthermore, the second wide bandgap chipset 312 corresponds one-to-one to and is connected to the wide bandgap power chips 11 in the first wide bandgap chipset 211. The corresponding two wide bandgap power chips 11 can form a half-bridge circuit. Moreover, since multiple half-bridge circuits are connected in parallel, a half-bridge circuit with a current specification amplified N times (the number of half-bridge circuits is N) can be formed, which is beneficial to improving the power level of the half-bridge power module.

[0115] In some embodiments, the hybrid power module includes a second DC connection terminal 42 located on the second DC connection layer 23, and the current path length between each wide bandgap power chip 11 in the second wide bandgap chipset 312 and the second DC connection terminal 42 is the same, thereby improving the current sharing performance of the lower bridge.

[0116] Among them, the second DC connection terminal 42 is an area, and the second DC connection terminal 42 is the connection area of ​​each wide bandgap power chip 11 in the second wide bandgap chipset 312. The length, size, etc. of the second DC connection terminal 42 will affect the current path length. Therefore, the current path length between each wide bandgap power chip 11 in the second wide bandgap chipset 312 and the second DC connection terminal 42 is the same, and the shortest current path length from the source of each wide bandgap power chip 11 in the second wide bandgap chipset 311 to the second DC connection terminal 42 may be the same. And the same here can be completely the same, or the current path length can be slightly different, for example, the difference between the current path lengths of any two wide bandgap power chips 11 in the second wide bandgap chipset 312 to the second DC connection terminal 42 is within a preset difference range, and the preset difference range can be determined according to actual conditions.

[0117] In practical applications, the wide bandgap power chip 11 may include a silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) or a gallium nitride high electron mobility transistor (GaN HEMT).

[0118] Figure 5 (A) in the figure shows a schematic diagram of the structure of a wide bandgap power chip, and the surface electrodes of the wide bandgap power chip 11 include a source 111, a gate 12, and a drain 113 at the bottom. Accordingly, the drain 113 of the wide bandgap power chip 11 in the second wide bandgap chip group 312 fits the AC connection layer 22, and the source 111 of the wide bandgap power chip 11 in the second wide bandgap chip group 312 is connected to the second DC connection layer 23. The drain of the wide bandgap power chip 11 in the first wide bandgap chip group 311 fits the first DC connection layer 21, and the source of the wide bandgap power chip 11 in the first wide bandgap chip group 311 is connected to the AC connection layer 22.

[0119] It should be noted that when the multiple wide bandgap power chips 11 are arranged in one direction, and the current direction after the multiple wide bandgap power chips 11 are merged is perpendicular to the arrangement direction of the multiple wide bandgap power chips 11, Figure 4 As shown in (A), each first chip has a current path of the same length, that is, has the same current path length, so that it can have good dynamic current sharing performance. When multiple wide bandgap power chips 11 are arranged in one direction, and the current direction after the multiple wide bandgap power chips 11 are merged is parallel to the arrangement direction of the multiple wide bandgap power chips 11, as shown in Figure 4 As shown in (B), each wide bandgap power chip 11 has a cocurrent path of different lengths, that is, has a current path length of different lengths, which may cause a problem of dynamic uneven current.

[0120] It can be understood that since the multiple wide bandgap power chips 11 in the first wide bandgap chipset 311 are arranged along the second direction, the current path lengths between the multiple wide bandgap power chips 11 in the first wide bandgap chipset 311 and the first AC connection terminal 43 are as similar as possible, thereby improving the current sharing performance of the upper bridge.

[0121] The multiple wide bandgap power chips 11 in the second wide bandgap chipset 312 are arranged along the second direction, so that the current path lengths between the multiple wide bandgap power chips 11 in the second wide bandgap chipset 312 and the second DC connection terminal 42 are as consistent as possible, thereby improving the current sharing performance of the lower bridge.

[0122] In some embodiments, in combination Figure 2 and Figure 3 As shown, the upper bridge chipset 31 includes a first silicon-based chipset 321 and a first wide bandgap chipset 311. On the first DC connection layer 21, the first silicon-based chipset 321 and the first wide bandgap chipset 311 are arranged along a first direction. The upper bridge chipset 31 is controlled to be turned on or off by the first silicon-based chipset 321 and the first wide bandgap chipset 311, thereby achieving the purpose of reducing switching loss and cost.

[0123] In other embodiments, the lower bridge chipset 32 ​​includes a second silicon-based chipset 322 and a second wide bandgap chipset 312, and the second silicon-based chipset 322 and the second wide bandgap chipset 312 are arranged in a first direction, and the lower bridge chipset 32 ​​is controlled to be turned on or off by the second silicon-based chipset 322 and the second wide bandgap chipset 312.

[0124] In some examples, the first silicon-based chipset 321 includes a plurality of silicon-based power chips 12, so that the upper bridge chipset 31 can output a larger current. The plurality of silicon-based power chips 12 in the first silicon-based chipset 321 are connected in parallel. Specifically, the plurality of silicon-based power chips 12 in the first silicon-based chipset 321 are all located on the first DC connection layer 21, and the plurality of silicon-based power chips 12 are connected to the AC connection layer 22, so as to realize the parallel connection of the plurality of silicon-based power chips 12 in the first silicon-based chipset 321. For example, the plurality of silicon-based power chips 12 in the first silicon-based chipset 321 can be connected to the AC connection layer 22 through bonding wires.

[0125] In addition, the first silicon-based chipset 321 may also include a plurality of diode chips 13, and the silicon-based power chips 12 and the diode chips 13 are connected in parallel one by one. Specifically, each diode 13 is connected in parallel with a silicon-based power chip 12 in the first silicon-based chipset 321 to bear reverse freewheeling and improve the reverse freewheeling capability of the module as a whole.

[0126] In other examples, the second silicon-based chipset 322 includes a plurality of silicon-based power chips 12, so that the lower bridge chipset 32 ​​can output a larger current. The plurality of silicon-based power chips 12 in the second silicon-based chipset 322 are connected in parallel. Specifically, the plurality of silicon-based power chips 12 in the second silicon-based chipset 322 are all located on the AC connection layer 22, and the plurality of silicon-based power chips 12 are connected to the second DC connection layer 23, so as to realize the parallel connection of the plurality of silicon-based power chips 12 in the second silicon-based chipset 322. For example, the plurality of silicon-based power chips 12 in the second silicon-based chipset 322 can be connected to the second DC connection layer 23 through bonding wires.

[0127] In addition, the second silicon-based chipset 322 may also include a plurality of diode chips 13, and the silicon-based power chips 12 and the diode chips 13 are connected in parallel one by one. Specifically, each diode chip 13 is connected in parallel with a silicon-based power chip 12 in the second silicon-based chipset 304 to bear reverse freewheeling and improve the reverse freewheeling capability of the module as a whole.

[0128] In practical applications, the silicon-based power chip 12 may include a silicon insulated gate bipolar transistor or a silicon metal oxide semiconductor field effect transistor (Si MOSFET).

[0129] The diode chip 13 may include a silicon fast recovery diode chip (Silicon Fast Recovery Diode, SiRFD) or a silicon carbide Schottky barrier diode chip (Silicon Carbide Schottky Barrier Diode, SiCSBD).

[0130] Figure 5 (B) in the figure shows a schematic diagram of the structure of a silicon-based power chip 12, the surface electrodes of the silicon-based power chip 12 include an emitter 121, a gate 122, and a collector 123 located at the bottom. Accordingly, the collector of the silicon-based power chip 12 in the second silicon-based chip group 322 is bonded to the AC connection layer 22, and the emitter of the silicon-based power chip 12 in the second silicon-based chip group 322 is connected to the second DC connection layer 23 via a bonding wire. The collector of the silicon-based power chip 12 in the first silicon-based chip group 321 is bonded to the first DC connection layer 22, and the emitter of the silicon-based power chip 12 in the first silicon-based chip group 321 is connected to the AC connection layer 22 via a bonding wire.

[0131] Figure 5 (C) in the figure shows a schematic diagram of the structure of a third chip, in which the diode chip 13 includes an anode 131 at the top and a cathode 132 at the bottom. Accordingly, the cathode of the diode chip 13 of the second silicon-based chip group 322 is bonded to the AC connection layer 22, and the anode of the diode chip 13 of the second silicon-based chip group 322 is connected to the second DC connection layer 23 via a bonding wire. The cathode of the diode chip 13 in the first silicon-based chip group 321 is bonded to the first DC connection layer 22, and the diode chip 13 in the first silicon-based chip group 321 is connected to the AC connection layer 22 via a bonding wire.

[0132] In some embodiments, in combination Figure 2 and Figure 3 As shown, the second DC connection layer 23 includes a first DC negative electrode connection layer 231 and a second DC negative electrode connection layer 232, and the first DC negative electrode connection layer 231 and the second DC negative electrode connection layer 232 are connected to facilitate the arrangement and shortening of the wiring from the chip to the connection layer.

[0133] In some examples, the first AC connection layer 221 , the first DC connection layer 21 , and the second AC connection layer 222 are disposed between the first DC negative electrode connection layer 231 and the second DC negative electrode connection layer 232 to shorten the connection line between each chip and the corresponding connection layer.

[0134] As an implementation method, the first AC connection layer 221 is arranged close to the first DC negative electrode connection layer 231 in the first direction to shorten the connection line from the wide bandgap power chip 11 in the second wide bandgap chipset group 312 to the AC connection layer, and the second AC connection layer 222 is arranged close to the second DC negative electrode connection layer 232 in the first direction to shorten the connection line from the silicon-based power chip 12 and the diode chip 13 in the second silicon-based chipset group 322 to the AC connection layer.

[0135] As another implementation method, the first DC negative electrode connection layer 231 and the second DC negative electrode connection layer 232 enclose the first AC connection layer 221, the first DC connection layer 21 and the second AC connection layer, which is convenient for setting and shortening the routing from the first wide bandgap chipset 311 to the first AC connection layer 221, and the routing from the first silicon-based chipset 321 to the second AC connection layer 222, and the routing from the second wide bandgap chipset 312 to the first DC negative electrode connection layer 231, and the routing from the second silicon-based chipset 322 to the second DC negative electrode connection layer 232.

[0136] For example, the first DC connection layer 21 and the second DC negative electrode connection layer 232 adopt a double “C” shape design, and the “C” shape of the second DC negative electrode connection layer 232 is located outside the “C” shape of the first DC connection layer 21. For example, the first DC negative electrode connection layer 231 and the second DC negative electrode connection layer 232 are connected by bonding wires.

[0137] As another implementation, the second DC negative electrode connection layer 232 is at least partially disposed close to the first DC connection layer 21 to shorten the wiring from the chip to the second DC negative electrode connection layer 232 .

[0138] For example, the current direction of the second DC negative electrode connection layer 232 is opposite to the current direction of the first DC connection layer 21, and the mutual inductance can be used to offset the parasitic inductance. For example, the current direction along the first direction in the second DC negative electrode connection layer 232 is opposite to the current direction along the first direction in the first DC connection layer 21.

[0139] In some examples, in order to lead out the first AC connection layer 221 and the second AC connection layer 222, the second AC connection layer 222 includes a second AC connection terminal 432, and the chip of the first silicon-based chipset 321 is connected to the second AC connection terminal 432, so that the first AC connection layer 221 and the second AC connection layer 222 can be led out through the first AC connection terminal 431 and the second AC connection terminal 432 respectively.

[0140] In order to understand the influence of the DC terminal position on the commutation circuit of the wide bandgap power chip, the equivalent circuit considering the parasitic inductance of the hybrid power module is explained below. Figure 7 As shown, the wide bandgap power chip 11 is turned on first, at this time the voltage drops, and the wide bandgap power chip 11 bears all the current, and then the silicon-based power chip 12 is turned on, the wide bandgap power chip 11 and the silicon-based power chip 12 exchange current, and finally the wide bandgap power chip 11 and the silicon-based power chip 12 each bear part of the current; during the shutdown process, the wide bandgap power chip 11 is turned off first, at this time the silicon-based power chip 12 and the wide bandgap power chip 11 exchange current, after the wide bandgap power chip 11 bears all the current, the wide bandgap power chip 11 is turned off, at this time the voltage rises, and a shutdown voltage spike appears at the same time.

[0141] Since the switching speed of the wide bandgap power chip 11 is faster and the switching speed of the silicon-based power chip 12 is slower, the voltage spike generated by the wide bandgap power chip 11 under the same inductance is much higher than the voltage spike generated by the silicon-based power chip 12. Therefore, the turn-off spike caused by the parasitic inductance in the switching commutation circuit of the wide bandgap power chip 11 is more serious, and reducing the commutation circuit length of the wide bandgap power chip 11 is the main problem.

[0142] Therefore, in some examples, on the second DC connection layer 23, the second DC connection terminal 42 is arranged close to the second wide bandgap chipset 312, for example, located on the side of the second wide bandgap chipset 312 away from the second silicon-based chipset 322, so as to reduce the length of the commutation loop of the second wide bandgap chipset 312, reduce the parasitic inductance in the commutation loop, and thereby reduce the voltage shutdown spike generated by the wide bandgap power chip 11.

[0143] In some other examples, the hybrid power module includes two first DC terminals 41 located on the first DC connection layer 21, the two first DC terminals 41 are respectively located on the first DC negative electrode connection layer 231 and the second DC negative electrode connection layer 232, and the two first DC terminals 41 are located on both sides of the second DC terminal 42 in the second direction, thereby improving the current sharing performance of multiple wide bandgap power chips 11 in the first wide bandgap chipset 311, and can reduce the commutation loop length of the wide bandgap power chip 11 in the first wide bandgap chipset 311 during the switching process, reduce the parasitic inductance between the wide bandgap power chip 11 in the first wide bandgap chipset 311 and the first DC terminal 41, and reduce the voltage shutdown spike. Among them, the first DC terminal 41 is used to connect an external circuit, such as connecting the positive electrode of a power supply, and the connection between the external circuit and the upper bridge chipset 31 can be achieved through the first DC terminal 41 and the first DC connection layer 21.

[0144] In some other examples, on the second AC connection layer 222 , the second AC connection terminal 43 is disposed close to the first silicon-based chipset 321 , so as to reduce the length of the commutation loop of the second silicon-based chipset 322 .

[0145] In some embodiments, Figure 8 As shown, the arrangement of the multiple wide bandgap power chips 11 in the first wide bandgap chipset 311 and the multiple wide bandgap power chips 11 in the second wide bandgap chipset 312 may include at least one of the following:

[0146] Each wide bandgap power chip 11 is aligned in the second direction;

[0147] Each wide bandgap power chip 11 is arranged in sequence in the second direction, and two adjacent wide bandgap power chips 11 are staggered in the first direction;

[0148] The first direction and the second direction are two directions perpendicular to each other on a plane.

[0149] like Figure 8 As shown in (A), each wide bandgap power chip 11 is neatly arranged in sequence along the second direction, and the bonding wire is connected to the corresponding connection layer along the first direction. For example, when the multiple wide bandgap power chips 11 in the first wide bandgap chipset 311 are neatly arranged in sequence along the second direction, the bonding wire of each wide bandgap power chip 11 is connected to the AC connection layer 22 along the first direction; for another example, when the multiple wide bandgap power chips 11 in the second wide bandgap chipset 312 are neatly arranged in sequence along the second direction, the bonding wire of each wide bandgap power chip 11 is connected to the AC connection layer 22 along the first direction. This arrangement is more compact and helps to improve space utilization.

[0150] like Figure 8As shown in (B), each wide bandgap power chip 11 is arranged in sequence in the second direction, and two adjacent wide bandgap power chips 11 are staggered in the first direction, and the bonding wires are connected to the corresponding connection layer along the first direction. This arrangement is an arrangement for heat dissipation optimization, which can further reduce thermal coupling and improve heat dissipation performance.

[0151] In practical applications, different arrangements of the wide bandgap power chips 11 can be flexibly selected according to requirements to meet different performance requirements.

[0152] For example, Fig. 9 As shown, when a plurality of wide bandgap power chips 11 in the first wide bandgap chipset 311 are arranged in the second direction, adjacent wide bandgap power chips 11 in the first wide bandgap chipset 311 may be arranged staggered in the first direction to reduce thermal coupling of the first wide bandgap chipset 311 and have better heat dissipation performance. When a plurality of wide bandgap power chips 11 in the second wide bandgap chipset 312 are arranged in the second direction, adjacent wide bandgap power chips 11 in the second wide bandgap chipset 312 may be arranged staggered in the first direction to enable the second wide bandgap chipset 312 to have better heat dissipation performance.

[0153] In some embodiments, Fig.10 As shown, the arrangement of the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the first silicon-based chip group 321, and the arrangement of the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the second silicon-based chip group 322 may include at least one of the following;

[0154] The first chip combination, the second chip combination and the third chip combination are sequentially arranged in the second direction, the first chip combination includes at least one silicon-based power chip 12 sequentially arranged in the second direction, the second chip combination includes at least one diode chip 13 sequentially arranged in the second direction, and the third chip combination includes at least one silicon-based power chip 12 sequentially arranged in the second direction;

[0155] The fourth chip combination, the fifth chip combination and the sixth chip combination are arranged sequentially in the second direction, the fourth chip combination includes at least one diode chip 13 arranged sequentially in the second direction, the fifth chip combination includes at least one silicon-based power chip 12 arranged sequentially in the second direction, and the sixth chip combination includes at least one diode chip 13 arranged sequentially in the second direction;

[0156] A plurality of silicon-based power chips 12 and a plurality of diode chips 13 are cross-arranged in the second direction;

[0157] The first direction and the second direction are two directions perpendicular to each other on a plane.

[0158] Due to the thermal coupling effect, the middle chip has a higher junction temperature in steady state under the same power loss conditions. The power loss of the silicon-based power chip 12 and the diode chip 13 depends on the driving control method of the silicon-based power chip 12 and the diode chip 13. Therefore, the loss of the silicon-based power chip 12 and the diode chip 13 can be evaluated during the design.

[0159] When the loss of the silicon-based power chip 12 is higher than that of the diode chip 13, the silicon-based power chip 12 can be arranged on both sides of the diode chip 13 in the second direction to reduce the temperature rise of the silicon-based power chip 12. Fig.10 As shown in (A), the first chip combination, the second chip combination and the third chip combination are arranged in sequence in the second direction, and the first chip combination and the third chip combination include silicon-based power chips 12, and the second chip combination includes diode chips 13.

[0160] When the loss of the silicon-based power chip 12 is lower than that of the diode chip 13, the diode chips 13 may be arranged on both sides of the silicon-based power chip 12 in the second direction to reduce the temperature rise of the diode chip 13. Fig.10 As shown in (B), the fourth chip combination, the fifth chip combination and the sixth chip combination are arranged in sequence in the second direction, and the fourth chip combination and the sixth chip combination include a diode chip 13, and the fifth chip combination includes a silicon-based power chip 12.

[0161] When the loss of the silicon-based power chip 12 is close to the loss of the diode chip 13, the silicon-based power chip 12 and the diode chip 13 may be arranged crosswise in the second direction, such as Fig.10 As shown in (C) in .

[0162] In practical applications, different arrangements of the silicon-based power chips 12 and the diode chips 13 can be flexibly selected according to requirements.

[0163] In some embodiments, in combination Figure 2 and Figure 3 As shown, the hybrid power module includes a first gate driving layer 241 and a first source driving layer 242 located on the substrate 20. For example, the first gate driving layer 241 and the first source driving layer 242 may be copper layers.

[0164] The gate of the wide bandgap power chip 11 in the first wide bandgap chipset group 311 is connected to the first gate drive layer 241 through a bonding wire, and the source of the wide bandgap power chip 11 in the first wide bandgap chipset group 311 is connected to the first source drive layer 242 through a bonding wire, so that the voltage difference between the gate and the source of the wide bandgap power chip 11 in the first wide bandgap chipset group 311 can be controlled, thereby controlling the wide bandgap power chip 11 in the first wide bandgap chipset group 311 to be in an on or off state.

[0165] In some other embodiments, the hybrid power module further includes a second gate driving layer 261 and a first emitter driving layer 262 located on the substrate 20. For example, the second gate driving layer 261 and the first emitter driving layer 262 may be copper layers.

[0166] The gate of the silicon-based power chip 12 in the first silicon-based chipset group 321 is connected to the second gate driving layer 261 via a bonding wire, and the emitter of the silicon-based power chip 12 in the first silicon-based chipset group 321 is connected to the first emitter driving layer 262 via a bonding wire, so that the voltage difference between the gate and the emitter of the silicon-based power chip 12 in the first silicon-based chipset group 321 can be controlled, thereby controlling the silicon-based power chip 12 in the first silicon-based chipset group 321 to be in an on or off state.

[0167] For example, when multiple wide bandgap power chips 11 in the first wide bandgap chipset 311 are arranged in the second direction, and multiple silicon-based power chips 12 and multiple diode chips 13 in the first silicon-based chipset 321 are arranged in the second direction, the first gate drive layer 241 and the first source drive layer 242 can be arranged between the first wide bandgap chipset 311 and the first silicon-based chipset 321, and the second gate drive layer 261 and the first emitter drive layer 262 can be arranged between the first silicon-based chipset 321 and the second AC connection layer 222 to shorten the bonding wires between the first wide bandgap chipset 311 and the driving layer, and shorten the bonding wires between the first silicon-based chipset 321 and the driving layer.

[0168] As an implementation method, the first source drive layer 242 and the first emitter drive layer 262 can be the same drive layer, shortening the commutation circuit between the wide bandgap power chip 11 and the silicon-based power chip 12 in the hybrid module, reducing the parasitic inductance between the wide bandgap power chip 11 and the silicon-based power chip 12, and reducing the commutation time.

[0169] In some examples, combined Figure 2 and Figure 3 As shown, a first gate drive terminal 441 is formed in the first gate drive layer 241, and a first source drive terminal 442 is formed in the first source drive layer 242. The first gate drive terminal 441 and the first source drive terminal 442 are connected to an external circuit, so that the gate and source of the wide bandgap power chip 11 in the first wide bandgap chipset 311 can receive an external voltage, thereby controlling the wide bandgap power chip 11 of the first wide bandgap chipset 311 to be in an on or off state.

[0170] In other examples, a second gate drive terminal 461 is formed in the second gate drive layer 261, and a first emitter drive terminal 462 is formed in the first emitter drive layer 262. An external circuit is connected through the second gate drive terminal 461 and the first emitter drive terminal 462, so that the gate and emitter of the silicon-based power chip 12 in the first silicon-based chipset group 321 can receive an external voltage, thereby controlling the silicon-based power chip 12 in the first silicon-based chipset group 321 to be in an on or off state.

[0171] For example, when the first source driving layer 242 and the first emitter driving layer 262 are the same driving layer, the first source driving terminal 442 and the first emitter driving terminal 462 are the same driving terminal.

[0172] In other embodiments, in combination Figure 2 and Figure 3 As shown, the hybrid power module includes a third gate driving layer 251 and a second source driving layer 252 located on the substrate 20. For example, the third gate driving layer 251 and the second source driving layer 252.

[0173] The gate of the wide bandgap power chip 11 in the second wide bandgap chipset group 312 is connected to the third gate drive layer 251 through a bonding wire, and the source of the wide bandgap power chip 11 in the second wide bandgap chipset group 312 is connected to the second source drive layer 252 through a bonding wire, so that the voltage difference between the gate and the source of the wide bandgap power chip 11 in the second wide bandgap chipset group 312 can be controlled, thereby controlling the wide bandgap power chip 11 in the second wide bandgap chipset group 312 to be in an on or off state.

[0174] In some other embodiments, the hybrid power module further includes a fourth gate driving layer 271 and a second emitter driving layer 272 located on the substrate 20. For example, the fourth gate driving layer 271 and the second emitter driving layer 272 may be copper layers.

[0175] The gate of the silicon-based power chip 12 in the second silicon-based chip group 322 is connected to the fourth gate driving layer 271 through a bonding wire, and the emitter of the silicon-based power chip 12 in the second silicon-based chip group 322 is connected to the second emitter driving layer 272 through a bonding wire, so that the voltage difference between the gate and emitter of the silicon-based power chip 12 in the second silicon-based chip group 322 can be controlled, thereby controlling the silicon-based power chip 12 in the second silicon-based chip group 322 to be in an on or off state.

[0176] For example, when multiple wide bandgap power chips 11 in the second wide bandgap chipset 312 are arranged in the second direction, and multiple silicon-based power chips 12 and multiple diode chips 13 in the second silicon-based chipset 311 are arranged in the second direction, the third gate drive layer 251 and the second source drive layer 252 can be arranged between the second wide bandgap chipset 312 and the first DC negative connection layer 231, and the fourth gate drive layer 271 and the fourth source drive layer 272 can be arranged between the first DC connection layer 21 and the second silicon-based chipset 322, thereby shortening the bonding wires between the second wide bandgap chipset 312 and the driving layer, and shortening the bonding wires between the second silicon-based chipset 322 and the driving layer.

[0177] As an implementation method, the second source drive layer 252 and the second emitter drive layer 272 can be the same drive layer, further shortening the commutation circuit between the wide bandgap power chip 11 and the silicon-based power chip 12 in the hybrid module, reducing the parasitic inductance between the wide bandgap power chip 11 and the silicon-based power chip 12, and reducing the commutation time.

[0178] In some examples, a third gate drive terminal 451 is formed in the third gate drive layer 251, and a second source drive terminal 452 is formed in the second source drive layer 252. An external circuit is connected through the third gate drive terminal 451 and the second source drive terminal 452, so that the gate and source of the wide bandgap power chip 11 in the second wide bandgap chipset 312 can receive an external voltage, thereby controlling the wide bandgap power chip 11 in the second wide bandgap chipset 312 to be in an on or off state.

[0179] In other examples, a fourth gate drive terminal 471 is formed in the fourth gate drive layer 271, and a second emitter drive terminal 472 is formed in the second emitter drive layer 272. The fourth gate drive terminal 271 and the second emitter drive terminal 272 are connected to an external circuit, so that the gate and emitter of the silicon-based power chip 12 in the second silicon-based chipset group 322 can receive an external voltage, thereby controlling the silicon-based power chip 12 in the second silicon-based chipset group 322 to be in an on or off state.

[0180] For example, when the second source driving layer 252 and the second emitter driving layer 272 are the same driving layer, the second source driving terminal 452 and the second emitter driving terminal 452 are the same driving terminal.

[0181] The hybrid power module provided in the present application is described above. The present application also provides a multi-phase full-bridge hybrid module, including at least two of the above hybrid power modules connected in parallel.

[0182] like Fig.11As shown, three hybrid power modules are placed together to form a three-phase full-bridge hybrid module. For example, the three hybrid power modules can be connected to the same heat dissipation substrate 6.

[0183] The present application also provides a power conversion device, comprising at least one of the above-mentioned hybrid power modules.

[0184] The present application also provides a vehicle, comprising the above-mentioned power conversion device.

[0185] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A hybrid power module, characterized in that: The hybrid power module comprises: substrate(20); A first DC connection layer (21) and an AC connection layer (22) located on the substrate (20), wherein the AC connection layer (22) comprises a first AC connection layer (221) and a second AC connection layer (222) which are separated and arranged on both sides of the first DC connection layer (21); An upper bridge chipset (31) is arranged on the first DC connection layer (21); A lower bridge chipset (32), wherein a portion of chips of the lower bridge chipset (32) are arranged on a first AC connection layer (221), and another portion of chips are arranged on a second AC connection layer (222); The chips in the upper bridge chipset (31) are electrically connected to the AC connection layer (22).

2. The hybrid power module according to claim 1, characterized in that: The first DC connection layer (21) is arranged between the first AC connection layer (221) and the second AC connection layer (222); the first AC connection layer (221) and the second AC connection layer (222) are electrically connected via leads or terminals.

3. The hybrid power module according to claim 1, characterized in that: The lower bridge chipset (32) comprises a second wide bandgap chipset (312), the chips in the upper bridge chipset (31) are electrically connected to the first AC connection layer (221), and the second wide bandgap chipset (312) is arranged on the first AC connection layer (221).

4. The hybrid power module according to claim 3, characterized in that: The lower bridge chipset (32) further comprises a second silicon-based chipset (322), wherein the second silicon-based chipset (322) is arranged on the second AC connection layer (222).

5. The hybrid power module according to claim 4, characterized in that: The upper bridge chipset (31) comprises a first wide bandgap chipset (311), the first wide bandgap chipset (311) and the second wide bandgap chipset (312) are arranged along a first direction, and the first wide bandgap chipset (311) and the second wide bandgap chipset (312) both comprise a plurality of wide bandgap power chips (11) arranged along a second direction.

6. The hybrid power module according to claim 5, characterized in that: The second wide bandgap chipset (312) is connected in series with the wide bandgap power chips in the first wide bandgap chipset (211) in a one-to-one correspondence.

7. The hybrid power module according to claim 5, characterized in that: The upper bridge chipset (31) further comprises a first silicon-based chipset (321), wherein the silicon-based power chips (12) in the first silicon-based chipset (321) are respectively connected in series with the silicon-based power chips (12) in the second silicon-based chipset (322) in a one-to-one correspondence.

8. The hybrid power module according to claim 5, characterized in that: The first AC connection layer (221) comprises a first AC connection terminal (431), and the current path lengths between each of the wide bandgap power chips (11) in the first wide bandgap chipset (311) and the first AC connection terminal (43) are the same.

9. The hybrid power module according to claim 5, characterized in that: The hybrid power module further comprises a second DC connection layer (23), and the second wide bandgap chipset (312) is electrically connected to the second DC connection layer (23).

10. The hybrid power module according to claim 9, characterized in that: The hybrid power module comprises a second DC connection terminal (42) located on the second DC connection layer (23); the current path length between each of the wide bandgap power chips (11) in the second wide bandgap chipset (312) and the second DC connection terminal (42) is the same.

11. The hybrid power module according to claim 1, characterized in that: The upper bridge chipset comprises: A first silicon-based chipset (321) and a first wide bandgap chipset (311), on the first DC connection layer (21), the first silicon-based chipset (321) and the first wide bandgap chipset (311) being arranged along a first direction.

12. The hybrid power module according to claim 4, characterized in that: The lower bridge chipset also includes: A second silicon-based chipset (322), wherein the second silicon-based chipset (322) and the second wide bandgap chipset (312) are arranged in a first direction.

13. The hybrid power module according to claim 10, characterized in that: On the second DC connection layer (23), the second DC connection terminal (42) is arranged close to the second wide bandgap chipset (312).

14. The hybrid power module according to claim 7, characterized in that: The first silicon-based chip group (321) comprises a plurality of silicon-based power chips (12) and a plurality of diode chips (13), and the silicon-based power chips (12) and the diode chips (13) are connected in parallel in a one-to-one correspondence.

15. The hybrid power module according to claim 4, characterized in that: The second silicon-based chip group (322) comprises a plurality of silicon-based power chips (12) and a plurality of diode chips (13), and the silicon-based power chips (12) and the diode chips (13) are connected in parallel in a one-to-one correspondence.

16. The hybrid power module according to claim 9, characterized in that: The second DC connection layer (23) comprises a first DC negative electrode connection layer (231) and a second DC negative electrode connection layer (232), and the first DC negative electrode connection layer (231) and the second DC negative electrode connection layer (232) are connected.

17. The hybrid power module according to claim 16, characterized in that: The first AC connection layer (221), the first DC connection layer (21), and the second AC connection layer (222) are arranged between the first DC negative electrode connection layer (231) and the second DC negative electrode connection layer (232).

18. The hybrid power module according to claim 17, characterized in that: The first AC connection layer (221) is arranged close to the first DC negative electrode connection layer (231) in a first direction, and the second AC connection layer (222) is arranged close to the second DC negative electrode connection layer (232) in the first direction.

19. The hybrid power module according to claim 17, characterized in that: The first DC negative electrode connection layer (231) and the second DC negative electrode connection layer (232) enclose the first AC connection layer (221), the first DC connection layer (21) and the second AC connection layer (222).

20. The hybrid power module according to claim 17, characterized in that: The second DC negative electrode connection layer (232) is at least partially disposed close to the first DC connection layer (21).

21. The hybrid power module according to claim 20, characterized in that: The current direction of the second DC negative electrode connection layer (232) is opposite to the current direction of the first DC connection layer (21).

22. The hybrid power module according to claim 7, characterized in that: The second AC connection layer (222) comprises a second AC connection terminal (432), and the chips of the first silicon-based chipset (321) are connected to the second AC connection terminal (432).

23. The hybrid power module according to claim 7, characterized in that: On the second AC connection layer (222), the second AC connection terminal (432) is arranged close to the first silicon-based chipset (321).

24. The hybrid power module according to claim 16, characterized in that: The hybrid power module comprises two first DC terminals (41), and the two first DC terminals (41) are respectively located on the first DC negative electrode connection layer (231) and the second DC negative electrode connection layer (232).

25. The hybrid power module according to claim 5, characterized in that: The arrangement of the plurality of wide bandgap power chips (11) includes at least one of the following: Each of the wide bandgap power chips (11) is aligned in the second direction; Two adjacent wide bandgap power chips (11) are staggered in a first direction; The first direction and the second direction are two directions perpendicular to each other on a plane.

26. The hybrid power module according to claim 14, characterized in that: Silicon chipset include: The arrangement of the plurality of silicon-based power chips (12) and the plurality of diode chips (13) includes at least one of the following: A first chip combination, a second chip combination and a third chip combination are arranged sequentially in a second direction, the first chip combination includes at least one silicon-based power chip (12) arranged sequentially in the second direction, the second chip combination includes at least one diode chip (13) arranged sequentially in the second direction, and the third chip combination includes at least one silicon-based power chip (12) arranged sequentially in the second direction; A fourth chip combination, a fifth chip combination and a sixth chip combination are arranged sequentially in the second direction, the fourth chip combination includes at least one diode chip (13) arranged sequentially in the second direction, the fifth chip combination includes at least one silicon-based power chip (12) arranged sequentially in the second direction, and the sixth chip combination includes at least one diode chip (13) arranged sequentially in the second direction; A plurality of silicon-based power chips (12) and a plurality of diode chips (13) are cross-arranged in the second direction.

27. The hybrid power module according to claim 5, characterized in that: The hybrid power module comprises: A first gate driving layer (241) and a first source driving layer (242) located on the substrate (20); The gate of each wide bandgap power chip (11) in the first wide bandgap chipset (311) is connected to the first gate drive layer (241), and the source of each wide bandgap power chip (11) in the first wide bandgap chipset (301) is connected to the first source drive layer (242).

28. The hybrid power module according to claim 7, characterized in that: The hybrid power module comprises: A second gate drive layer (261) and a first emitter drive layer (262) are located on the substrate (20); the gate of each of the silicon-based power chips (12) in the first silicon-based chip group (321) is connected to the second gate drive layer (261), and the emitter of each of the silicon-based power chips (12) in the first silicon-based chip group (321) is connected to the first emitter drive layer (262).

29. The hybrid power module according to claim 5, characterized in that: The hybrid power module comprises: A third gate driving layer (251), a second source driving layer (252), and The gate of each wide bandgap power chip (11) in the second wide bandgap chipset (312) is connected to the third gate drive layer (251), and the source of each wide bandgap power chip (11) in the second wide bandgap chipset (312) is connected to the second source drive layer (252).

30. The hybrid power module according to claim 7, characterized in that: The hybrid power module comprises: A fourth gate drive layer (271) and a second emitter drive layer (272) are located on the substrate (20); the gate of each of the silicon-based power chips (12) in the second silicon-based chip group (322) is connected to the fourth gate drive layer (271), and the emitter of each of the silicon-based power chips (12) in the second silicon-based chip group (322) is connected to the second emitter drive layer (272).

31. The hybrid power module according to claim 27, characterized in that: The hybrid power module comprises: A first gate driving terminal (441) is provided in the first gate driving layer (241) and a first source driving terminal (442) is provided in the first source driving layer (242).

32. The hybrid power module according to claim 28, characterized in that: The hybrid power module comprises: A second gate drive terminal (461) is provided in the second gate drive layer (261) and a first emitter drive terminal (462) is provided in the first emitter drive layer (262).

33. The hybrid power module according to claim 29, characterized in that: The hybrid power module comprises: A third gate driving terminal (451) is provided in the third gate driving layer (251) and a second source driving terminal (252) is provided in the second source driving layer (252).

34. The hybrid power module according to claim 30, characterized in that: The hybrid power module comprises: A fourth gate driving terminal (471) provided in the fourth gate driving layer (271) and a second emitter driving terminal (472) provided in the second emitter driving layer (272).

35. The hybrid power module according to claim 9, characterized in that: At least one of the first DC connection layer (21), the second DC connection layer (23) and the AC connection layer (22) is a copper layer.

36. The hybrid power module according to claim 5, characterized in that: The wide bandgap power chip includes a silicon carbide metal oxide semiconductor field effect transistor or a gallium nitride high electron mobility transistor.

37. The hybrid power module according to claim 14 or 15, characterized in that: The silicon-based power chip includes a silicon insulated gate bipolar transistor or a silicon metal oxide semiconductor field effect transistor; The diode chip includes a silicon fast recovery diode chip or a silicon carbide Schottky diode chip.

38. A multi-phase full-bridge hybrid module, characterized in that: The hybrid power module comprises at least two hybrid power modules according to any one of claims 1 to 37.

39. A power conversion device, characterized in that: Comprising at least one hybrid power module as claimed in any one of claims 1 to 37.

40. A vehicle, characterized in that: Includes the power conversion device as described in claim 39.

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