A semiconductor device structure and its manufacturing method and chip

Abstract

The present invention discloses a semiconductor device structure, a method for preparing the same, and a chip, belonging to the field of semiconductor device technology. The semiconductor device structure comprises a gold-silver alloy bump and an UBM layer, wherein the UBM layer is composed of a seed layer, a diffusion barrier layer, and an adhesion layer, or a diffusion barrier layer and an adhesion layer; the diffusion barrier layer is composed of a single platinum group element and / or an alloy containing a platinum group element, preferably platinum, rhodium, iridium, or an alloy thereof; the bottom of the gold-silver alloy bump is connected to the seed layer or the diffusion barrier layer, and the adhesion layer is connected to the chip electrode. By improving the UBM layer, the present invention enhances the bonding reliability between the gold-silver alloy bump and the UBM layer. The resulting semiconductor device structure can pass high-end chip reliability testing, enabling the use of gold-silver alloy instead of gold in flip-chip production.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices and relates to a semiconductor device structure and a preparation method thereof and a chip. Background Art

[0002] Flip-chip technology is primarily divided into two categories. One involves reflow solder, which can include tin, tin-lead alloys, tin-silver alloys, and gold-tin alloys. While lead-free soldering materials are currently well-established, solder becomes liquid at high temperatures and, under pressure, can cause bridging between adjacent solder bumps, making it unsuitable for fine-pitch flip-chip applications. The other approach involves bonding using pure gold bumps, which are electrically connected to the substrate via hot-press soldering or anisotropic conductive adhesive. While gold bumps offer excellent reliability and prevent bridging between adjacent gold bumps, their material cost is very high. With the price of gold rising, developing new alternative materials is a hot topic. Given the excellent properties of gold bumps, such as oxidation resistance, sulfurization resistance, hardness, roughness, and solderability, there are few viable alternatives to gold. Among these, gold-silver alloys offer one of the most promising solutions.

[0003] TWI469288B discloses electroplated gold-silver bumps, addressing the issue of preventing silver oxidation. The top or side surfaces of the gold-silver bumps are electroplated or chemically plated with one of gold, palladium, copper, or nickel to prevent silver oxidation, with copper and nickel being more susceptible to oxidation than silver. TW201044527A discloses electroplated gold-silver bumps containing at least 80% silver, followed by a protective layer formed on the gold and silver surfaces by replacing or reducing the gold to prevent silver oxidation. TW201019440A discloses that the silver bumps can be made of pure silver or a silver alloy, and the silver alloy of these silver bumps can contain at least 80% silver. A layer of pure gold or a gold alloy is then plated on the silver alloy surface to address the issue of anti-oxidation.

[0004] CN117542818B significantly improves the silver's anti-oxidation and anti-sulfurization properties by increasing the gold content in the gold-silver bumps to over 60%. This approach addresses the oxidation and anti-sulfurization issues of the gold-silver bumps by first preparing a gold-silver alloy with a gold content of 20% to 50% as a connecting layer in the same electroplating bath at a low current density, and then applying a very thin protective layer with a gold content of over 60% on the bump surface at a high current density. To address the potential for poor soldering caused by silver oxidation, CN118398588B selectively removes metallic silver from the bump surface through electrochemical etching to form a nano-mesoporous gold structure. This approach addresses the oxidation and anti-sulfurization issues of the gold-silver bumps without compromising the hardness of the bump itself.

[0005] Although the above solutions propose solutions to problems such as the hardness of gold and silver bumps, and poor soldering due to oxidation or sulfidation, they do not mention the bonding strength between the gold and silver bumps and different metal layers during the manufacturing process. After bump preparation, the bumps need to undergo various reliability tests, such as TCT (Temperature Cycle Test): -65℃ (15min) ~150℃ (15min), more than 700 cycles, PCT (Pressure Cooker Test): 121℃, 100% RH, 2atm, 168 hrs, THT (Temperature Humidity Test): 85℃ / 85% RH, 1000 hrs, HTST (High Temperature Storage Life Test): 150℃, 1000 hrs, LTST (Low Temperature Storage Life Test): -65℃, 1000 hrs, etc. to verify the bonding strength between the bumps and the UBM (Under Bump Metal). Specifically, a push shear test can be performed on the bumps that have undergone reliability testing to check whether the underlying UBM layer is exposed.

[0006] Most reliability failures occur due to poor bonding between the bump and the UBM layer, so the choice of UBM material metal is very important for the bonding strength. CN105895604B mentions the preparation of the bump, wherein the material of the electroplated conductive bump is selected from gold, copper, nickel, silver or their alloys, and the UBM material is selected from titanium / copper, titanium tungsten / gold or silver-containing alloys. CN116564916A mentions that the UBM layers used for the gold bump are titanium layer, titanium tungsten layer and gold layer from near to far from the electrode pad. By changing the UBM layer structure, adding the titanium layer and reducing the thickness of the titanium tungsten layer, the bonding strength of the bump is increased. US20230369270A1 In order to solve the reliability problem of bump-bonded IC devices at high temperatures, the bump material is selected from gold, copper or non-conductive materials, and the UBM layer is formed by a titanium / gold stack. US20190214357A1 mentions the low manufacturing yield of the bump structure encountered in flip-chip technology when creating bumps on the chip to connect to the substrate. This yield was improved by developing an additional etching process. The bump material used is gold, and the UBM material is a titanium-tungsten alloy. US10629444B2 describes a new bump structure, which is considered a replacement for gold bumps in display driver IC packaging. The bump material used is a three-layer copper-nickel-gold (Cu-Nickel-Au) structure. The UBM layer includes a Ti layer and a Cu layer on the Ti layer, or a TiW layer and a Cu layer on the TiW layer. TW200633093A provides a method for manufacturing a metal bump composed of gold (Au), and the metal layer is composed of a titanium-tungsten alloy (TiW) metal layer and a gold (Au) metal layer. US6664128B2 provides a bump manufacturing process, wherein the material forming the conductive layer is selected from aluminum, titanium, titanium-tungsten alloy, chromium, gold, silver and copper, wherein the UBM layer includes a layer selected from the following group: aluminum / nickel-vanadium / copper layer, titanium / nickel-vanadium / copper layer, titanium-tungsten / nickel-vanadium / copper layer and chromium / nickel-vanadium / copper layer.

[0007] To address the problem of gold-silver alloy bumps and existing UBM layers failing high-temperature cycling reliability testing, CN119340299A proposes a thermal expansion coefficient difference between the gold-silver alloy bumps and the adhesive layer of less than 9 ppm / K. This approach can address the bonding issues encountered during high-temperature cycling reliability testing (350 cycles) of semiconductor devices. However, for some high-end DDICs (Display Driver ICs), the high-temperature cycling tests are more stringent, with cycles reaching 700 or even 1,000 cycles or more, and it is still difficult to completely eliminate the possibility of interface failure.

[0008] There is an urgent need to improve the bonding reliability between the gold-silver alloy bumps and the UBM layer, to ensure that semiconductor devices based on the gold-silver alloy bumps pass high-end chip reliability tests, and to lay the foundation for using gold-silver alloy to replace gold in the preparation of flip-chips. Summary of the Invention

[0009] The present invention aims to provide a semiconductor device structure, a method for fabricating the same, and a chip. By improving the UBM layer, the bond reliability between the gold-silver alloy bump and the UBM layer is enhanced. The resulting semiconductor device structure can pass high-end chip reliability testing and enable the use of gold-silver alloys in place of pure gold in flip-chip fabrication. After intensive research, the inventors discovered that the failure mechanism of the gold-silver alloy is that during reliability testing, silver atoms in the gold-silver alloy migrate through the gold seed layer to the adhesion layer (titanium or titanium-tungsten alloy) at high temperatures. However, the bonding strength between silver and titanium or titanium-tungsten alloy is poor, resulting in separation at the interface even without applied force.

[0010] According to diffusion theory, diffusion between metals is explained by vacancies or interstitial mechanisms. Diffusion is also influenced by crystal structure. When two metals have the same crystal structure and similar lattice constants, the interfacial energy is relatively low, and the interfacial bonding strength is high, diffusion is likely to occur easily. Otherwise, when the lattice structures and lattice constants differ significantly, the interfacial energy is relatively high, the interfacial bonding strength is weak, and diffusion is more difficult. As shown in Table 1, gold and silver both have a face-centered cubic structure. The atomic radius of silver is 1.44 Å and the lattice constant is 4.086 Å, while the atomic radius of gold is 1.44 Å and the lattice constant is 4.078 Å. This increases the chance of diffusion, which also explains why gold-silver alloys are prone to interfacial failure at high temperatures. To prevent silver from diffusing from the bump through the gold seed layer into the adhesion layer, which would degrade the bonding strength, a diffusion layer material is needed to prevent silver from diffusing into the adhesion layer. This diffusion layer material also possesses the properties of a precious metal to prevent oxidation during the material preparation process, which could lead to a decrease in interfacial bonding strength.

[0011] Table 1 Crystal structure, lattice constant and atomic radius of different precious metals

[0012]

[0013] The inventors have found that platinum group metals are a good choice. As shown in Table 1, the lattice constants of platinum group elements are close to those of gold and silver, and the interfacial binding energy is low and the binding force is strong. When diffusion occurs, since the atomic radius of silver atoms is larger than that of platinum group elements, these metals diffuse toward silver, thereby blocking the diffusion of silver atoms into the adhesion layer.

[0014] Based on this important discovery, the present invention proposes corresponding solutions, which are as follows:

[0015] The primary aspect of the present invention is to provide a semiconductor device structure comprising a gold-silver alloy bump and an UBM layer, wherein the UBM layer is composed of a seed layer, a diffusion barrier layer, and an adhesion layer, or a diffusion barrier layer and an adhesion layer; the diffusion barrier layer is composed of a single element of a platinum group element and / or an alloy containing a platinum group element; and the device structure, from top to bottom, is as follows: the bottom of the gold-silver alloy bump is connected to the seed layer, which is connected to the diffusion barrier layer, which is connected to the adhesion layer, which is connected to the chip electrode; or the bottom of the gold-silver alloy bump is connected to the diffusion barrier layer, which is connected to the seed layer, which is connected to the adhesion layer, which is connected to the chip electrode; or the bottom of the gold-silver alloy bump is connected to the diffusion barrier layer, which is connected to the adhesion layer, which is connected to the chip electrode. By adding a diffusion barrier layer between the gold-silver bump and the adhesion layer, silver atoms are prevented from migrating to the adhesion layer interface, thereby resolving the problem of interface failure caused by silver diffusion from the bump to the adhesion layer. The advantage of doing this is that UBM materials can be prepared simultaneously by magnetron sputtering or evaporation plating, and the bonding force between interfaces is better; compared with the use of electroplating and other methods to prepare the barrier layer, equipment investment is reduced, and cross-contamination between different plating solutions is avoided; the thickness of the metal diffusion layer film prepared by magnetron sputtering or evaporation plating is more uniform and controllable, thereby shortening the subsequent etching time and increasing the production rate and chip yield.

[0016] Preferably, the diffusion barrier layer is composed of one or more of platinum, rhodium, iridium and alloys thereof.

[0017] Furthermore, the thickness of the seed layer is 0-500 nm (the thickness of 0 means the seed layer is removed), the thickness of the adhesion layer is 10-1000 nm, and the thickness of the diffusion barrier layer is 10-1000 nm.

[0018] Furthermore, the seed layer is gold or a gold alloy.

[0019] Furthermore, the adhesion layer is titanium or a titanium alloy, preferably titanium-tungsten or titanium-nitrogen alloy.

[0020] Furthermore, the thickness of the gold-silver alloy bump is 5-20 μm.

[0021] Furthermore, the gold content of the gold-silver alloy bump is 10-60 wt%. If the gold content is too low, the hardness, roughness, and oxidation and sulfidation resistance of the gold-silver alloy bump will be significantly different from those of the gold bump. If the gold content is too high, the hardness will be too high and defects such as gold nodules will easily form. Secondly, it will be difficult to reduce costs.

[0022] Another aspect of the present invention is to provide a method for preparing the above-mentioned semiconductor device structure, comprising the following steps:

[0023] S1. An adhesion layer, a diffusion barrier layer, and a seed layer are sequentially formed on a chip wafer by physical vapor deposition (e.g., evaporation or magnetron sputtering) to obtain a UBM layer; or an adhesion layer, a seed layer, and a diffusion barrier layer are sequentially formed on a chip wafer by physical vapor deposition (e.g., evaporation or magnetron sputtering) to obtain a UBM layer; or an adhesion layer and a diffusion barrier layer are sequentially formed on a chip wafer by physical vapor deposition (e.g., evaporation or magnetron sputtering) to obtain a UBM layer;

[0024] S2 applies photoresist and exposes the area to be plated;

[0025] S3 prepares gold-silver alloy bumps by electroplating using a gold-silver electroplating solution;

[0026] S4 removes excess photoresist and UBM layer.

[0027] The key to the fabrication method provided by the present invention lies in adding a diffusion barrier layer above the adhesion layer. The diffusion barrier layer can be located above or below the gold seed layer. The specific operations involved, including physical vapor deposition of the adhesion layer, diffusion barrier layer, and seed layer, photoresist coating, and electroplating of the gold-silver alloy bumps, can all employ existing technical solutions.

[0028] Another aspect of the present invention is to provide a chip, which includes the semiconductor device structure provided by the present invention.

[0029] Furthermore, the chip is a liquid crystal driver chip, a memory chip, a logic chip or a radio frequency power chip.

[0030] The technical solution provided by the present invention solves the technical problem that gold-silver alloy bumps and existing UBM layers cannot pass high-low temperature cycle reliability tests. The obtained semiconductor device structure and corresponding chip can pass various reliability tests, making it feasible to replace pure gold bumps with gold-silver alloys, thereby significantly reducing the production cost of flip chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a FIB-SEM (focused ion beam scanning electron microscope) photo of the interface of a semiconductor device constructed with gold-silver alloy bumps with different gold contents after annealing at 280°C for 8 hours.

[0032] Figure 2 This is a semiconductor device constructed with gold-silver alloy bumps with a gold content of 45%, and FIB-SEM photos of the interface after annealing at 280°C for different times.

[0033] Figure 3 It is a schematic diagram of the semiconductor device structure provided by the present invention.

[0034] Figure 4 It is a FIB-SEM interface image of the semiconductor device structure of Example 1 and Comparative Example 1 annealed at 280° C. for 12 hours.

[0035] Reference numerals: 101 - wafer substrate, 102 - electrode, 103 - passivation layer, 104 - adhesion layer, 105 - diffusion barrier layer or seed layer, 106 - seed layer or diffusion barrier layer, 107 - gold-silver alloy bump. DETAILED DESCRIPTION

[0036] The following is a clear and complete description of the technical solution of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0037] In their previous work, the inventors discovered that semiconductor devices constructed with existing gold-silver alloy bumps have difficulty passing reliability tests for high-end chips, such as DDIC. To uncover the failure mechanism of semiconductor devices constructed with existing gold-silver alloy bumps, the inventors conducted the following research.

[0038] DDIC reliability tests, such as TCT (-65°C (15 min) to 150°C (15 min), 700 cycles or even more than 1000 cycles) and HTST (150°C, 1000 hrs), are time-consuming. To accelerate material development, inventors have developed a new method based on the time-temperature equivalence effect, simulating device failure by shortening the time under high-temperature conditions.

[0039] Semiconductor devices were constructed using gold-silver alloy bumps with different gold contents. The semiconductor devices included gold-silver alloy bumps and UBM layers. The gold contents in the gold-silver alloys were 20%, 45%, and 100% (pure gold), respectively. The UBM layer included an adhesion layer and a seed layer. The adhesion layer was a TiW alloy with a thickness of 320nm; the seed layer was pure gold with a thickness of 80nm. These three semiconductor devices were annealed at 280°C for 8 hours, and the interface morphology of the gold-silver alloy bumps and the UBM layer was observed using FIB-SEM. The results are shown in Figure 2. Figure 1 As shown. Figure 1 It can be seen that the interface between the gold-silver alloy bump with a gold content of 20% and the UBM layer has separated, while the interface between the gold content of 45% and pure gold has not separated.

[0040] A semiconductor device was constructed using a gold-silver alloy bump with a 45% gold content. The device consisted of a gold-silver alloy bump and an UBM layer. The UBM layer consisted of an adhesion layer and a seed layer. The adhesion layer was a TiW alloy with a thickness of 320nm; the seed layer was pure gold with a thickness of 80nm. Annealing at 280°C for 4h, 8h, and 12h, respectively, was performed to investigate the failure mechanism by studying the changes in the interface structure during the annealing process. The results are shown in the figure below. Figure 2 As shown. Figure 2 After 4 hours of annealing, the interface had not separated, but a discontinuous layer (indicated by the white arrow) was present at the interface. This layer gradually disappeared with increasing annealing time. After annealing at 280°C for 12 hours, separation occurred at the edge of the interface. Because the layer was located above the adhesion layer and was very thin, it can be concluded that it was a gold seed layer. With increasing annealing time, silver gradually diffused into the gold, eventually forming a uniform gold-silver alloy. Due to the weak bonding between silver and TiW, the interface failed after 12 hours of annealing.

[0041] To verify the diffusion of silver atoms in gold, the inventors designed an experiment to verify this. They first electroplated an 8μm thick layer of a 20% gold-content gold-silver alloy onto a wafer, then deposited a 1μm thick layer of pure gold. Using EDX, they measured the gold and silver content of the original pure gold layer after silver diffused into the gold layer under different annealing conditions. The detection voltage was 20kV, so the detection depth was approximately 400-500nm. The results are shown in Table 2.

[0042] Table 2 Gold and silver contents in the original pure gold coating after silver diffusion under different annealing conditions

[0043]

[0044] As shown in Table 2, no silver atoms were detected in the gold layer without annealing. However, as the annealing time increased from 8 hours to 24 hours, the detectable silver atoms in the gold layer increased from 8.55% to 15.4%. This experiment demonstrates the rapid diffusion of silver in gold at 280°C. Based on these experiments, the strong interface bonding between the gold atoms and the TiW layer in the adhesion layer prevented separation after annealing at 280°C. However, the weak interface bonding between the silver atoms and the TiW layer in the adhesion layer led to the diffusion of more silver atoms through the gold seed layer to the adhesion layer interface, ultimately leading to device interface failure.

[0045] Next, a semiconductor device with a diffusion barrier layer added to the UBM layer is prepared and reliability testing is carried out. Example 1

[0046] A semiconductor device structure, such as Figure 3As shown, the bottom layer is a silicon-based wafer substrate 101, on which transistors are deployed. The external connection lines of the transistors are aluminum or copper electrodes 102. On both sides of the electrodes are passivation layers 103. The passivation layer materials can be silicon dioxide or silicon nitride, and their main function is to protect and isolate the circuits. They are prepared by evaporation or magnetron sputtering. Above the electrodes is the UBM layer, and from bottom to top are adhesion layer 104, diffusion barrier layer 105, and seed layer 106. Adhesion layer 104 is made of titanium and has a thickness of 250nm; diffusion barrier layer 105 is made of platinum and has a thickness of 50nm; seed layer 106 is made of gold and has a thickness of 50nm; and gold-silver alloy bumps 107 have a gold content of 20wt% and a thickness of 9μm.

[0047] The detailed fabrication process is as follows. A Ti adhesion layer is first deposited on a pre-fabricated 12-inch liquid crystal driver chip wafer using magnetron sputtering under the following conditions: vacuum of 2.3 mTorr, bias of 90 V, power of 5 kW, and sputtering time of 200 s. A Pt diffusion barrier layer is then deposited using a Pt target in the same chamber under the following conditions: vacuum of 2.1 mTorr, bias of 60 V, power of 2 kW, and sputtering time of 120 s. Finally, an Au seed layer is deposited using an Au target in the same chamber under the following conditions: vacuum of 2.7 mTorr, bias of 60 V, power of 2 kW, and sputtering time of 150 s. The wafer is then cooled by nitrogen gas and removed. JSR 121 photoresist is then spin-coated on the wafer, exposing the areas to be plated. The photoresist is applied to a 20 μm height. After plasma cleaning, a gold-silver conductive metal layer was deposited using a gold-silver alloy electroplating solution at a temperature of 30°C, a pH of 9.0, a current density of 0.5 ASD, and a plating time of 36 minutes. The resulting bump height was approximately 9 μm, and the gold content by weight was 20%. Finally, the photoresist and UBM layers were removed. Reliability testing involved annealing at 280°C for 12 hours, and the interface morphology was observed using a FIB-SEM. Example 2

[0048] A semiconductor device structure, the overall structure is the same as that of Example 1, except that the UBM structure, from bottom to top, consists of a 320nm TiW adhesion layer, an 80nm Au seed layer, and a 100nm Pt diffusion barrier layer; the gold-silver alloy bump has a gold content of 60wt% and a thickness of 5μm. The overall preparation process is similar to that of Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly with the UBM structure. Example 3

[0049] A semiconductor device structure, the overall structure being identical to that of Example 1, differing in that the UBM structure, from bottom to top, comprises a 320nm TiW adhesion layer, an 80nm Au seed layer, and a 100nm Pt-Rh alloy diffusion barrier layer; the gold-silver alloy bump has a gold content of 10wt% and a thickness of 20μm. The overall preparation process is similar to that of Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly with the UBM structure. Example 4

[0050] A semiconductor device structure, the overall structure being identical to that of Example 1, differing in that the UBM structure, from bottom to top, comprises a 320 nm thick TiW adhesion layer, a 100 nm thick platinum-iridium alloy diffusion barrier layer, and a 50 nm thick Au seed layer. The overall preparation process is similar to that of Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly with the UBM structure. Example 5

[0051] A semiconductor device structure, the overall structure being identical to that of Example 1, differing in that the UBM structure, from bottom to top, comprises a 100 nm Ti adhesion layer, a 100 nm Ir diffusion barrier layer, and a 50 nm Au seed layer. The overall preparation process is similar to that of Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly with the UBM structure. Example 6

[0052] A semiconductor device structure, the overall structure being identical to that of Example 1, differing in that the UBM structure, from bottom to top, comprises a 1000 nm Ti adhesion layer, a 500 nm Au seed layer, and a 50 nm Ir diffusion barrier layer. The overall preparation process is similar to that of Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly with the UBM structure. Example 7

[0053] A semiconductor device structure, the overall structure being identical to that of Example 1, differing in that the UBM structure, from bottom to top, comprises a 100 nm Ti adhesion layer, an 80 nm Au seed layer, and a 100 nm Rh diffusion barrier layer. The overall preparation process is similar to that of Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly with the UBM structure. Example 8

[0054] A semiconductor device structure, the overall structure being identical to that of Example 1, differing in that the UBM structure, from bottom to top, comprises a 100 nm Ti adhesion layer, a 50 nm Rh diffusion barrier layer, and a 500 nm Au seed layer. The overall preparation process is similar to that of Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly with the UBM structure. Example 9

[0055] A semiconductor device structure, the overall structure being identical to that of Example 1, differing in that the UBM structure, from bottom to top, comprises a 100 nm Ti adhesion layer and a 100 nm Rh diffusion barrier layer. The overall preparation process is similar to that of Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly with the UBM structure. Example 10

[0056] A semiconductor device structure, the overall structure of which is the same as that of Example 1, except that the UBM structure, from bottom to top, consists of a 10 nm Ti adhesion layer and a 1000 nm Pd diffusion barrier layer. The overall preparation process is similar to that of Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly with the UBM structure. Example 11

[0057] A semiconductor device structure, the overall structure of which is the same as that of Example 1, except that the UBM structure, from bottom to top, consists of a 100 nm TiN adhesion layer and a 10 nm Pt diffusion barrier layer. The overall preparation process is similar to that of Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly with the UBM structure. Example 12

[0058] A semiconductor device structure, the overall structure being identical to that of Example 1, differing in that the UBM structure, from bottom to top, comprises a 100 nm TiW adhesion layer and a 100 nm Ir diffusion barrier layer. The overall preparation process is similar to that of Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly with the UBM structure.

[0059] The results show that the device prepared in the above embodiment does not undergo interface separation even after annealing at 280°C for 12 hours. Therefore, forming a diffusion barrier layer with a single substance or alloy of platinum group elements can solve the problem of poor bonding of the device after reliability testing due to the diffusion of silver into the UBM adhesion layer.

[0060] Comparative Example 1

[0061] A semiconductor device structure, the overall structure is the same as that of Example 1, except that: the UBM layer is an adhesion layer 104 and a seed layer 106 from bottom to top, that is, compared with Example 1, the UBM layer does not have a diffusion barrier layer 105, and the interface is separated after annealing at 280°C for 12h. Figure 4 shown.

[0062] Although the embodiments of the present invention have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention without departing from the principles and intent of the present invention. The scope of protection of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device structure comprising a gold-silver alloy bump and a UBM layer, characterized in that: The semiconductor device structure is used for bump bonding flip-chips, and the gold content in the gold-silver alloy bump is 10-45wt%; the UBM layer is composed of a seed layer, a diffusion barrier layer and an adhesion layer, or composed of a diffusion barrier layer and an adhesion layer; the diffusion barrier layer is composed of a single substance of a platinum group element and / or an alloy containing a platinum group element, and prevents silver atoms in the gold-silver alloy bump from migrating to the adhesion layer interface; the device structure from top to bottom is as follows: the bottom of the gold-silver alloy bump is connected to the seed layer, the seed layer is connected to the diffusion barrier layer, the diffusion barrier layer is connected to the adhesion layer, and the adhesion layer is connected to the chip electrode; or the bottom of the gold-silver alloy bump is connected to the diffusion barrier layer, the diffusion barrier layer is connected to the seed layer, the seed layer is connected to the adhesion layer, and the adhesion layer is connected to the chip electrode; or the bottom of the gold-silver alloy bump is connected to the diffusion barrier layer, the diffusion barrier layer is connected to the adhesion layer, and the adhesion layer is connected to the chip electrode.

2. The semiconductor device structure according to claim 1, wherein: The diffusion barrier layer is composed of one or more of platinum, rhodium, iridium or alloys thereof.

3. The semiconductor device structure according to claim 1, wherein The thickness of the seed layer is 0-500 nm, the thickness of the adhesion layer is 10-1000 nm, and the thickness of the diffusion barrier layer is 10-1000 nm.

4. The semiconductor device structure according to claim 1, wherein: The seed layer material is gold or a gold alloy.

5. The semiconductor device structure according to claim 1, wherein: The adhesion layer material is titanium or titanium alloy.

6. The semiconductor device structure according to claim 5, wherein: The adhesion layer material is titanium, titanium-tungsten or titanium-nitrogen alloy.

7. The semiconductor device structure according to claim 1, wherein: The thickness of the gold-silver alloy bump is 5-20 μm.

8. The method for preparing a semiconductor device structure according to any one of claims 1 to 7, wherein: The following steps are involved: S1. Sequentially preparing an adhesion layer, a diffusion barrier layer, and a seed layer on a chip wafer by physical vapor deposition to obtain a UBM layer; or sequentially preparing an adhesion layer, a seed layer, and a diffusion barrier layer on a chip wafer by physical vapor deposition to obtain a UBM layer; or sequentially preparing an adhesion layer and a diffusion barrier layer on a chip wafer by physical vapor deposition to obtain a UBM layer; S2 applies photoresist and exposes the area to be plated; S3 prepares gold-silver alloy bumps by electroplating using a gold-silver electroplating solution; S4 removes excess photoresist and UBM layer.

9. A chip, characterized in that: The chip includes the semiconductor device structure according to any one of claims 1 to 7.

10. The chip according to claim 9, characterized in that The chip is a liquid crystal driver chip, a memory chip, a logic chip or a radio frequency power chip.

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