Chip packaging structure, preparation method thereof and electronic equipment

Abstract

The invention relates to a chip packaging structure and a preparation method thereof, and electronic equipment, the chip packaging structure comprises a substrate layer, and a rewiring layer and a chip stacking layer which are sequentially arranged on the substrate layer, and the chip stacking layer comprises at least one group of chip stacking units; the chip stacking unit comprises a first chip and at least one second chip located between the first chip and the rewiring layer, and the first chip and the second chip are at least partially overlapped in the thickness direction of the substrate layer; the chip packaging structure further comprises at least one first through hole penetrating through each second chip, the first through hole is filled with a conductive column, any chip is connected with the conductive column in the adjacent second chip, and the first chip is electrically connected with the second chip and / or the rewiring layer through the conductive column. According to the invention, mutual communication between the plurality of stacked chips and / or between the plurality of chips and the rewiring layer is realized through a through hole process, so that high-density integration of the chips is realized, and the requirements of high-performance chips are met.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure and a preparation method thereof, and an electronic device. Background Art

[0002] With the development of artificial intelligence (AI) chips and high-performance computing (HPC) technology, chip transistor integration has reached 100 billion, and it is expected to reach 1 trillion transistor integration by 2030. However, the current chip packaging technology cannot meet the needs of high-performance chips. For example, the chip-on-wafer-on-substrate (CoWos) process of a wafer foundry uses wafer packaging, but it is very difficult to increase the size of the wafer. The current maximum diameter of the wafer is about 300 millimeters (mm), which cannot meet the needs of high-performance chips. Summary of the invention

[0003] The embodiments of the present application provide a chip packaging structure and a preparation method thereof, and an electronic device, which realize interconnection between multiple stacked chips and / or between multiple chips and a redistribution layer through a through-hole process, thereby achieving high-density integration of chips and meeting the needs of high-performance chips.

[0004] In order to achieve the above object, according to a first aspect of the present application, a chip packaging structure is provided, comprising:

[0005] basal layer;

[0006] a redistribution layer, disposed on one side of the base layer; and

[0007] a chip stacking layer, arranged on a side of the redistribution layer away from the base layer, and comprising at least one group of chip stacking units; the chip stacking unit comprises a first chip and at least one second chip located between the first chip and the redistribution layer, the first chip and the second chip being arranged to at least partially overlap in a thickness direction of the base layer;

[0008] Among them, the chip packaging structure also includes at least one first through hole passing through each of the second chips, the first through hole is filled with a conductive column, any chip is connected to the conductive column in the adjacent second chip, and the first chip is electrically connected to the second chip and / or the redistribution layer through the conductive column.

[0009] In some embodiments, a first conductive connection layer is provided between the first chip and the adjacent second chip, and the first conductive connection layer is connected to the conductive pillar in the adjacent second chip;

[0010] A second conductive connection layer is provided between the second chip close to the redistribution layer and the redistribution layer, and the second conductive connection layer includes a first conductive connection portion and a second conductive connection portion which are located between the corresponding second chip and the redistribution layer and are spaced apart; the first conductive connection portion is electrically connected to the adjacent second chip and the redistribution layer, respectively, and the second conductive connection portion is electrically connected to the conductive column in the adjacent second chip and the redistribution layer, respectively.

[0011] In some embodiments, a plurality of second chips are stacked in sequence in the thickness direction of the base layer and arranged between the redistribution layer and the first chip, and a third conductive connection layer is provided between any two adjacent second chips; the third conductive connection layer is connected to the conductive columns in adjacent second chips.

[0012] In some embodiments, the redistribution layer includes a resistance region, a capacitance region, and an inductance region located between the base layer and the chip stacking layer; at least one resistance element is formed in the resistance region, at least one capacitance element is formed in the capacitance region, and at least one inductance element is formed in the inductance region;

[0013] The resistor element and the capacitor element are both located in the redistribution layer, and the inductor element is at least partially located in the redistribution layer; the resistor element, the capacitor element and the inductor element are respectively electrically connected to the first chip and / or the second chip in at least one group of the chip stacking units.

[0014] In some embodiments, the chip packaging structure further includes a heat dissipation component and a second through hole penetrating the first chip;

[0015] The heat dissipation component includes a first heat dissipation layer covering the side of the first chip facing away from the second chip, a first thermally conductive column filled in the second through hole, and a second heat dissipation layer covering the side of the second chip adjacent to the first chip facing away from the redistribution layer, wherein both ends of the first thermally conductive column are respectively connected to the first heat dissipation layer and the second heat dissipation layer.

[0016] In some embodiments, a plurality of the second chips are stacked in sequence in the thickness direction of the base layer and arranged between the redistribution layer and the first chip, the chip packaging structure further includes a third through hole penetrating at least part of the second chip, the heat dissipation assembly further includes a second heat-conducting column filled in the third through hole, and the second heat dissipation layer is arranged on a side of each of the second chips away from the redistribution layer;

[0017] In any two adjacent second chips, the third through hole is at least arranged in the second chip on a side close to the first chip, and both ends of the second heat-conducting column are respectively connected to the adjacent second heat dissipation layer.

[0018] In some embodiments, the first heat dissipation layer entirely covers a side of the first chip facing away from the second chip.

[0019] In some embodiments, the second chip includes a circuit area and at least one heat dissipation area adjacent to the circuit area, the conductive column is located in the circuit area, the second heat dissipation layer is located in the heat dissipation area, and the first thermally conductive column and the second heat dissipation layer are overlapped.

[0020] In some embodiments, the first heat dissipation layer includes a first heat conductive layer and a first adhesive layer located between the first heat conductive layer and the first chip; the first heat conductive column includes a second adhesive layer filled in the sidewall and the bottom of the first through hole and a second heat conductive layer surrounded by the second adhesive layer; the second heat dissipation layer includes a third heat conductive layer and a third adhesive layer located between the third heat conductive layer and the second chip;

[0021] The first heat conducting layer is connected to the second heat conducting layer, the first adhesive layer is connected to the second adhesive layer, and the second adhesive layer is connected to the second heat conducting layer.

[0022] In some embodiments, the first adhesion layer, the second adhesion layer, and the third adhesion layer are made of the same material and are selected from metal copper;

[0023] The first heat-conducting layer, the second heat-conducting layer and the third heat-conducting layer are made of the same material, which is selected from molybdenum, titanium or an alloy thereof.

[0024] In some embodiments, the redistribution layer includes a first wiring layer, a first dielectric layer, a second wiring layer, a second dielectric layer, a third wiring layer, and a third dielectric layer stacked sequentially on a side of the base layer close to the chip stacking layer;

[0025] The capacitor element comprises a first electrode and a second electrode which are at least partially overlapped; the first electrode is located in any one of the first wiring layer, the second wiring layer and the third wiring layer, and the second capacitor is located in any one of the first wiring layer, the second wiring layer and the third wiring layer which is different from the first electrode; the second electrode is electrically connected to the first chip and / or the second chip in at least one group of the chip stacking units;

[0026] The resistor element is located in any one of the first wiring layer, the second wiring layer and the third wiring layer, and a side of the resistor element away from the base layer is electrically connected to the first chip and / or the second chip in at least one group of the chip stacking units;

[0027] The inductor element includes a spiral coil, a portion of which is located in at least one of the first wiring layer, the second wiring layer and the third wiring layer, and another portion of which penetrates the base layer and extends to a side of the base layer away from the redistribution layer; one end of the spiral coil is electrically connected to the first chip and / or the second chip in at least one group of the chip stacking units.

[0028] In some embodiments, each coil of the spiral coil is at least located on a side of the base layer away from the redistribution layer, in the first wiring layer and the second wiring layer, and at least penetrates the base layer and the first dielectric layer;

[0029] The surface of the spiral coil located on the side of the base layer away from the redistribution layer is covered with a protection layer.

[0030] In some embodiments, the chip packaging structure further includes at least one soldering portion located on a side of the base layer away from the redistribution layer, at least one first plug penetrating the base layer, at least one second plug penetrating the first dielectric layer, at least one third plug penetrating the second dielectric layer, and at least one fourth plug penetrating the third dielectric layer;

[0031] The first wiring layer includes a plurality of first signal bonding portions, at least part of which is connected to the first plug, and at least part of which is connected to the second plug; the second wiring layer includes a plurality of second signal bonding portions, at least part of which is connected to the second plug, and at least part of which is connected to the third plug; the third wiring layer includes a plurality of third signal bonding portions, at least part of which is connected to the third plug, and at least part of which is connected to the fourth plug;

[0032] The first plunger is aligned and connected to the welding part, and the fourth plunger is connected to the first conductive connection part or the second conductive connection part; the welding part is electrically connected to the first conductive connection part or the second conductive connection part through the first plunger, the first signal bonding part, the second plunger, the second signal bonding part, the third plunger, the third signal bonding part and the fourth plunger in sequence.

[0033] In some embodiments, the chip packaging structure further includes at least one welding portion located on a side of the base layer away from the redistribution layer;

[0034] The thickness of the welding portion is greater than the thickness of any one of the redistribution layers, and is greater than the sum of the thicknesses of the inductor element and the protective layer located on a side of the base layer away from the redistribution layer.

[0035] In some embodiments, the first electrode is located in the first wiring layer, the second electrode is located in the second wiring layer, the first electrode is connected to the second signal bonding portion through the second plug, and the second electrode is electrically connected to the first conductive connection portion or the second conductive connection portion through the third plug, the third signal bonding portion and the fourth plug in sequence;

[0036] The resistor element is located in the second wiring layer, a side of the resistor element close to the base layer is connected to a first signal bonding portion through a second plug, a side of the resistor element away from the base layer is connected to two third signal bonding portions through a third plug, and one of the third signal bonding portions is electrically connected to the first conductive connecting portion or the second conductive connecting portion through a fourth plug;

[0037] The spiral coil of the inductor element is located on the side of the base layer away from the redistribution layer, in the first wiring layer and the second wiring layer, and penetrates the base layer and the first dielectric layer; the spiral coil includes a signal transmission end located in the second wiring layer, and the signal transmission end is electrically connected to the first conductive connecting part or the second conductive connecting part through a third plug, a third signal bonding part and a fourth plug in sequence.

[0038] In some embodiments, the first chip and the second chip each include any one of a glass-based chip and a silicon-based chip, and the base layer includes any one of a glass substrate and a silicon substrate.

[0039] According to a second aspect of the present application, a method for preparing a chip packaging structure is provided, comprising:

[0040] Prepare at least one group of chip stacking units; the chip stacking unit comprises a first chip and at least one second chip stacked on one side of the first chip, each of the second chips is provided with a first through hole penetrating the second chip, the first through hole is filled with a conductive column, any chip is connected to the conductive column in the adjacent second chip, a first welding layer is provided on the side of the second chip located on the surface layer away from the first chip, and the conductive column is connected to the first welding layer;

[0041] Providing a base layer, and sequentially forming a stacked redistribution layer and a second welding layer on one side of the base layer; and

[0042] The first welding layer and the second welding layer are welded so that the at least one group of chip stacking units are welded on the side of the redistribution layer away from the base layer to form a chip stacking layer electrically connected to the redistribution layer; the first chip is electrically connected to the second chip and / or the redistribution layer through the conductive column.

[0043] In some embodiments, the manufacturing process of the chip stacking unit includes:

[0044] Providing a first chip, and forming at least one second through hole penetrating the first chip on the first chip;

[0045] A first heat dissipation layer and a third welding layer are respectively formed on opposite sides of the first chip, and a first heat-conducting column is filled in the second through hole; the third welding layer includes a first heat-conducting welding portion and a first conductive welding portion, and two ends of the first heat-conducting column are respectively connected to the first heat dissipation layer and the first heat-conducting welding portion;

[0046] Providing a second chip, and forming at least one first through hole penetrating the second chip on the second chip;

[0047] forming a fourth welding layer and a fifth welding layer on opposite sides of the second chip respectively, and filling the conductive column in the first through hole; the fourth welding layer comprises a second thermal conductive welding portion and a second conductive welding portion, and the second conductive welding portion is connected to the conductive column; and

[0048] The third welding layer and the fourth welding layer are welded to connect the first thermal conductive welding portion and the second thermal conductive welding portion, and the first conductive welding portion and the second conductive welding portion, to form a chip stacking unit.

[0049] In some embodiments, providing a base layer and sequentially forming a stacked redistribution layer and a second welding layer on one side of the base layer comprises the following steps:

[0050] Providing a base layer; the base layer comprises a first surface and a second surface arranged opposite to each other;

[0051] A first wiring layer and a first dielectric layer are stacked on the first surface of the base layer, and at least one welding portion and a partial structure of at least one inductor element are formed on the second surface of the base layer; the first wiring layer includes a plurality of first signal bonding portions, the welding portion is connected to one of the first signal bonding portions through a through hole penetrating the base layer, and the inductor element also penetrates the base layer and is located in the first wiring layer;

[0052] A second wiring layer, a second dielectric layer, a third wiring layer and a third dielectric layer are sequentially formed on the first dielectric layer to form the redistribution layer; the second wiring layer is electrically connected to the first wiring layer through a through hole penetrating the first dielectric layer, the third wiring layer is electrically connected to the second wiring layer through a through hole penetrating the second dielectric layer, at least one resistor element and at least one capacitor element are further formed in the redistribution layer, and the inductor element may also be located in the second wiring layer and penetrate the first dielectric layer; and

[0053] A second welding layer is formed on the third dielectric layer; the second welding layer is electrically connected to the third wiring layer through a through hole penetrating the third dielectric layer.

[0054] According to a third aspect of the present application, an electronic device is also provided, and the electronic device includes the chip packaging structure described above.

[0055] In the chip packaging structure and preparation method thereof, and the electronic device of the embodiment of the present application, a first through hole penetrating the second chip is formed on the second chip by a through hole process, and a conductive column is filled in the first through hole, so as to realize the electrical connection between the first chip (top chip) and the second chip (bottom chip) and / or realize the electrical connection between the first chip (top chip) and the redistribution layer. The present application can integrate multiple chips in three dimensions to form a chip stacking unit, and can integrate multiple groups of chip stacking units containing multi-layer chips on the same base layer provided with a redistribution layer, which is conducive to reducing the area occupied by a single chip on the base layer, thereby realizing high-density integration of chips. At the same time, multiple chips in each chip stacking unit can be interconnected through conductive columns, and any chip in each chip stacking unit can be interconnected with the redistribution layer through at least one conductive column. Therefore, the embodiment of the present application realizes high-density interconnection of chips while realizing high-density integration of chips, meeting the needs of high-performance chips.

[0056] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0058] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0059] Figure 1 is a schematic cross-sectional structure diagram of a chip packaging structure provided in an embodiment of the present application;

[0060] Figure 2 is a schematic cross-sectional structure diagram of another chip packaging structure provided in an embodiment of the present application;

[0061] Figure 3 is a top view of a first chip provided in an embodiment of the present application;

[0062] Figure 4 is a top view of a second chip provided in an embodiment of the present application;

[0063] Figure 5 is a top view of another second chip provided in an embodiment of the present application;

[0064] Figure 6 It is a schematic flow chart of a method for preparing a chip packaging structure provided in an embodiment of the present application;

[0065] Figure 7 is a schematic diagram of a cross-sectional structure of a first chip before welding provided in an embodiment of the present application;

[0066] Figure 8 is a schematic diagram of a cross-sectional structure of a second chip before welding provided in an embodiment of the present application;

[0067] Fig. 9 is a schematic diagram of a cross-sectional structure of another second chip provided in an embodiment of the present application when it is not welded;

[0068] Fig.10 yes Figure 7 The first chip in Figure 8 A schematic cross-sectional structure diagram of a chip stacking unit formed after the second chip in the chip is welded;

[0069] Fig.11 yes Figure 7 The first chip in Fig. 9 A schematic cross-sectional structure diagram of another chip stacking unit formed after the second chip in the chip is welded;

[0070] Fig.12 is a schematic cross-sectional structure diagram of forming a first wiring layer, a first dielectric layer and a contact portion on opposite sides of a base layer by using a through hole and a double-sided process according to an embodiment of the present application;

[0071] Fig.13 is Fig.12 A schematic diagram of a cross-sectional structure of a redistribution layer and a second welding layer formed on the basis of the above;

[0072] Fig.14 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application.

[0073] Explanation of reference numerals: 1. chip packaging structure; 2. base layer; 3. redistribution layer; 3a. first wiring layer; 3b. first dielectric layer; 3c. second wiring layer; 3d. second dielectric layer; 3e. third wiring layer; 3f. third dielectric layer; 4. chip stacking layer; 5. chip stacking unit; 6. first chip; 7 (7'), second chip; 8. first through hole; 9. conductive column; 10. first conductive connection layer; 11. second conductive connection layer; 11a. first conductive connection portion; 11b. second conductive connection portion connection portion; 12, third conductive connection layer; 13, conductive layer; 14, adhesion layer; 15, resistance area; 16, capacitance area; 17, inductance area; 18, resistance element; 19, capacitance element; 19a, first electrode; 19b, second electrode; 20, inductance element; 20a, spiral coil; 201a, first part; 201b, second part; 201c, third part; 201d, fourth part; 201e, fifth part; 21, second through hole; 22, heat dissipation component; 22a, first heat dissipation layer ; 22b, first heat-conducting column; 22c, second heat-dissipating layer; 22d, second heat-conducting column; 23, third through hole; 24, circuit area; 25, heat-dissipating area; 26, first heat-conducting layer; 27, first adhesive layer; 28, second adhesive layer; 29, second heat-conducting layer; 30, third heat-conducting layer; 31, third adhesive layer; 32, protective layer; 33, welding part; 34, first plunger; 35, second plunger; 36, third plunger; 37, fourth plunger; 38, first signal bonding part; 39, second signal bonding part; 40. The third signal bonding part; 41. The first welding layer; 41a. The third conductive welding part; 41b. The fourth conductive welding part; 42. The second welding layer; 42a. The fifth conductive welding part; 42b. The sixth conductive welding part; 43. The third welding layer; 43a. The first thermal conductive welding part; 43b. The first conductive welding part; 44. The fourth welding layer; 44a. The second thermal conductive welding part; 44b. The second conductive welding part; 45. The first surface; 46. The second surface; 47. The electronic device; 48. The device body. DETAILED DESCRIPTION

[0074] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0075] like Figure 1 and Figure 2 As shown, an embodiment of the present application provides a chip packaging structure 1, which includes a base layer 2, a redistribution layer 3 and a chip stacking layer 4. The redistribution layer 3 is arranged on one side of the base layer 2; the chip stacking layer 4 is arranged on the side of the redistribution layer 3 away from the base layer 2, and includes at least one group of chip stacking units 5. The chip stacking unit 5 includes a first chip 6, and at least one second chip 7 (7') located between the first chip 6 and the redistribution layer 3, and the first chip 6 and the second chip 7 (7') are at least partially overlapped in the thickness direction of the base layer 2.

[0076] Among them, the chip packaging structure 1 also includes at least one first through hole 8 that passes through each second chip 7 (7'), and the first through hole 8 is filled with a conductive column 9. Any chip is connected to the conductive column 9 in the adjacent second chip 7 (7'), and the first chip 6 is electrically connected to the second chip 7 (7') and / or the redistribution layer 3 through the conductive column 9.

[0077] In the embodiment of the present application, a first through hole 8 penetrating the second chip 7 (7') is formed on the second chip 7 (7') by a through hole process, and a conductive column 9 is filled in the first through hole 8, thereby realizing the electrical connection between the first chip 6 (top chip) and the second chip 7 (7') (bottom chip), or realizing the electrical connection between the first chip 6 (top chip) and the redistribution layer 3. In the embodiment of the present application, multiple chips can be three-dimensionally integrated to form a chip stacking unit 5, and multiple groups of chip stacking units 5 containing multi-layer chips can be integrated on the same base layer 2 provided with a redistribution layer 3, which is conducive to reducing the area occupied by a single chip on the base layer 2, thereby realizing high-density integration of chips. At the same time, multiple chips in each chip stacking unit 5 can realize signal interconnection through the conductive column 9, and any chip in each chip stacking unit 5 can realize signal interconnection with the redistribution layer 3 through at least one conductive column 9. Therefore, the embodiment of the present application realizes high-density chip interconnection while realizing high-density chip integration, meeting the demand for high-performance chips.

[0078] In some embodiments, the first chip 6 and the second chip 7 ( 7 ′) are both glass-based chips; of course, in other embodiments, the first chip 6 and the second chip 7 ( 7 ′) may also be silicon-based chips.

[0079] When the first chip 6 and the second chip 7 ( 7 ′) are both glass-based chips, the first through hole 8 can be formed by a glass hole opening process, making it easier to open a hole on the second chip 7 ( 7 ′).

[0080] In some embodiments, Figure 1 and Figure 2 As shown, a first conductive connection layer 10 is provided between the first chip 6 and the adjacent second chip 7 (7'), and the first conductive connection layer 10 is connected to the conductive column 9 in the adjacent second chip 7 (7'). A second conductive connection layer 11 is provided between the second chip 7 near the redistribution layer 3 and the redistribution layer 3, and the second conductive connection layer 11 includes a first conductive connection portion 11a and a second conductive connection portion 11b that are located between the corresponding second chip 7 and the redistribution layer 3 and are spaced apart. The first conductive connection portion 11a is electrically connected to the adjacent second chip 7 and the redistribution layer 3, respectively, and the second conductive connection portion 11b is electrically connected to the conductive column 9 in the adjacent second chip 7 and the redistribution layer 3, respectively.

[0081] It can be understood that the first chip 6 and the adjacent second chip 7 (7') are electrically connected through the first conductive connection layer 10, and can also be electrically connected through the first conductive connection layer 10 and the conductive column 9; the first chip 6 can be electrically connected to the redistribution layer 3 through the first conductive connection layer 10, the conductive column 9 in at least one second chip 7 (7') and the second conductive connection; the second chip 7 close to the redistribution layer 3 can be electrically connected to the redistribution layer 3 through the first conductive connection portion 11a.

[0082] It should be noted that the number and type of the conductive connection parts between each group of chip stacking units 5 and the redistribution layer 3 can be the same or different, and this embodiment of the present application does not limit this. Figure 1 The chip packaging structure 1 in FIG. 1 integrates two groups of chip stacking units 5. The chip stacking unit 5 on the left is connected to the redistribution layer 3 through the first conductive connection portion 11a and the second conductive connection portion 11b, while the chip stacking unit 5 on the right is connected to the redistribution layer 3 only through the second conductive connection portion 11b. Correspondingly, when manufacturing the second chip 7, the following can be manufactured: Figure 8 He Ru Fig. 9 The two second chips 7 shown, Figure 8 The second chip 7 and Fig. 9 The second chips 7 shown are respectively applied in different chip stacking units 5 .

[0083] In a specific embodiment, if Figure 1 As shown, there is only one second chip 7 between the first chip 6 and the redistribution layer 3, and the first chip 6 can be electrically connected to the redistribution layer 3 through the first conductive connection layer 10, the conductive pillars 9 in the second chip 7 and the second conductive connection part 11b in sequence.

[0084] In another specific embodiment, Figure 2 As shown, a plurality of second chips (for example, a second chip 7 and a second chip 7') are stacked in sequence in the thickness direction of the base layer 2 between the redistribution layer 3 and the first chip 6, and a third conductive connection layer 12 is provided between any two adjacent second chips 7 and 7'; the third conductive connection layer 12 is connected to the conductive column 9 in the adjacent second chip 7 (7').

[0085] It can be understood that when the number of second chips 7 (7') is multiple, the first chip 6 can be electrically connected to the redistribution layer 3 in sequence through the first conductive connection layer 10, the conductive pillars 9 in multiple second chips 7 (7'), the third conductive connection layer 12, and the second conductive connection part 11b; and the second chip 7' located in the middle position can be electrically connected to the redistribution layer 3 in sequence through the conductive pillars 9 in at least one second chip 7 (7'), at least one third conductive connection layer 12, and the second conductive connection part 11b.

[0086] In some embodiments, the first conductive connection layer 10, the second conductive connection layer 11 and the third conductive connection layer 12 are all conductive connection layers formed by welding the welding layer. It can be understood that the first chip 6 and the adjacent second chip 7 (7'), any two adjacent second chips 7 (7') and the redistribution layer 3 and the adjacent second chip 7 are all connected by welding.

[0087] In a specific embodiment, the first conductive connection layer 10 , the second conductive connection layer 11 and the third conductive connection layer 12 are all composed of a conductive layer 13 and an adhesive layer 14 , and the adhesive layer 14 is located between the conductive layer 13 and the corresponding chip.

[0088] In some embodiments, the conductive pillar 9 is also composed of a conductive layer 13 and an adhesion layer 14 . Specifically, the conductive pillar 9 is composed of an adhesion layer 14 formed on the sidewall of the first through hole 8 and a conductive layer 13 surrounded by the adhesion layer 14 .

[0089] In a specific embodiment, the material of the conductive layer 13 includes metal copper, but is not limited thereto; the material of the adhesion layer 14 includes molybdenum, titanium or an alloy thereof, but is not limited thereto.

[0090] In some embodiments, Figure 1 and Fig.13As shown, the redistribution layer 3 includes a resistance area 15, a capacitance area 16 and an inductance area 17 located between the base layer 2 and the chip stacking layer 4. At least one resistance element 18 is formed in the resistance area 15, at least one capacitance element 19 is formed in the capacitance area 16, and at least one inductance element 20 is formed in the inductance area 17. The resistance element 18 and the capacitance element 19 are both located in the redistribution layer 3, and the inductance element 20 is at least partially located in the redistribution layer 3; the resistance element 18, the capacitance element 19 and the inductance element 20 are respectively electrically connected to the first chip 6 and / or the second chip 7 (7') in at least one group of chip stacking units 5.

[0091] The embodiment of the present application integrates the resistor element 18, the capacitor element 19 and the inductor element 20 in the redistribution layer 3, avoiding the additional welding of the external resistor element 18, the capacitor element 19 and the inductor element 20 on the base layer 2, reducing the subsequent welding process and the packaging area, which is beneficial to reducing the overall volume of the chip packaging structure 1.

[0092] In some embodiments, Figure 1 and Figure 2 As shown, the chip packaging structure 1 further includes a heat dissipation component 22 and a second through hole 21 penetrating the first chip 6. The heat dissipation component 22 includes a first heat dissipation layer 22a covering the side of the first chip 6 away from the second chip 7 (7'), a first heat-conducting column 22b filled in the second through hole 21, and a second heat dissipation layer 22c covering the side of the second chip 7 (7') adjacent to the first chip 6 away from the redistribution layer 3, and both ends of the first heat-conducting column 22b are respectively connected to the first heat dissipation layer 22a and the second heat dissipation layer 22c.

[0093] In the embodiment of the present application, a second through hole 21 is formed on the first chip 6 through a hole-opening process, and a first heat-conducting column 22b is filled in the second through hole 21. At the same time, the second heat dissipation layer 22c on the second chip 7 (7') of the lower layer is connected to the first heat dissipation layer 22a on the outer side of the first chip 6 of the top layer through the first heat-conducting column 22b, so that the heat generated by the second chip 7 (7') of the lower layer can be effectively discharged, and the second chip 7 (7') can be prevented from overheating during use, thereby solving the heat dissipation problem caused by high-density interconnection of multiple chips and multi-layer chip packaging.

[0094] In some embodiments, Figure 2As shown, a plurality of second chips 7 (for example, the second chip 7 and the second chip 7') are sequentially stacked and arranged between the redistribution layer 3 and the first chip 6 in the thickness direction of the base layer 2, the chip packaging structure 1 further includes a third through hole 23 penetrating at least part of the second chip 7 (7'), the heat dissipation assembly 22 further includes a second heat-conducting column 22d filled in the third through hole 23, and the second heat dissipation layer 22c is arranged on the side of each second chip 7 (7') away from the redistribution layer 3. In any two adjacent second chips 7 (7'), the third through hole 23 is at least arranged in the second chip 7 (7') on the side close to the first chip 6, and the two ends of the second heat-conducting column 22d are respectively connected to the adjacent second heat dissipation layer 22c.

[0095] It can be understood that when there are multiple second chips, a third through hole 23 can be formed on the second chip 7' through a hole opening process, and the third through hole 23 is filled with a second thermally conductive column 22d, so that two adjacent second chips 7 (7') can be connected to the first thermally conductive column 22b through the second thermally conductive column 22d and the second heat dissipation layer 22c, so that the heat generated by each layer of the second chip 7 (7') can be effectively discharged.

[0096] It should be noted that the third through hole 23 may not be provided on the second chip 7 adjacent to the redistribution layer 3, but the present invention is not limited thereto. For example, when the redistribution layer 3 also needs to dissipate heat, the third through hole 23 may be provided on the second chip 7 adjacent to the redistribution layer 3, and the second heat-conducting column 22d may be filled. In the embodiment of the present application, only the example of not providing the third through hole 23 on the second chip 7 adjacent to the redistribution layer 3 is used for explanation.

[0097] In some embodiments, Figure 3 As shown, the first heat dissipation layer 22a covers the entire side of the first chip 6 away from the second chip 7, so that the heat dissipation area is maximized, which is beneficial to improving the heat dissipation effect.

[0098] In some embodiments, Figure 4 and Figure 5 As shown, the second chip 7 (7') includes a circuit area 24 and at least one heat dissipation area 25 adjacent to the circuit area 24, the conductive column 9 is located in the circuit area 24, the second heat dissipation layer 22c is located in the heat dissipation area 25, and the first heat conductive column 22b is overlapped with the second heat dissipation layer 22c. It can be understood that in addition to the point circuit area 24 for transmitting signals and power connection, at least one heat dissipation area 25 can be set in the second chip 7 (7') for heat dissipation connection with the upper chip.

[0099] In a specific embodiment, the heat dissipation area 25 is disposed around the circuit area 24 , that is, the heat dissipation area 25 on the second chip 7 ( 7 ′) is located at the edge, but not limited thereto.

[0100] It should be noted that Figure 4 The second chip 7 shown in the figure does not have the third through hole 23, so Figure 4 The second chip 7 shown can be applied to Figure 1 In the chip packaging structure 1 shown; Figure 5 The second chip 7' shown in the figure is provided with a third through hole 23, so Figure 5 The second chip 7' shown can be applied to Figure 2 In the chip packaging structure 1 shown.

[0101] In some embodiments, the first heat dissipation layer 22a includes a first heat conducting layer 26, a first adhesive layer 27 located between the first heat conducting layer 26 and the first chip 6, the first heat conducting column 22b includes a second adhesive layer 28 filled in the sidewall and bottom of the first through hole 8, and a second heat conducting layer 29 surrounded by the second adhesive layer 28; the second heat dissipation layer 22c includes a third heat conducting layer 30, and a third adhesive layer 31 located between the third heat conducting layer 30 and the second chip 7. The first heat conducting layer 26 and the second heat conducting layer 29 are connected, the first adhesive layer 27 and the second adhesive layer 28 are connected, and the second adhesive layer 28 and the second heat conducting layer 29 are connected.

[0102] It can be understood that the adhesive layer 14 can enhance the connection tightness between the thermal conductive layer and the chip, which is beneficial to improving the heat dissipation effect.

[0103] In a specific embodiment, the first heat conducting layer 26, the second heat conducting layer 29 and the third heat conducting layer 30 are made of the same material. For example, the first heat conducting layer 26, the second heat conducting layer 29 and the third heat conducting layer 30 are made of copper metal with good heat dissipation performance, but are not limited thereto.

[0104] In a specific embodiment, the first adhesive layer 27, the second adhesive layer 28 and the third adhesive layer 31 are made of the same material. For example, the first adhesive layer 27, the second adhesive layer 28 and the third adhesive layer 31 are made of molybdenum, titanium or an alloy thereof, but are not limited thereto.

[0105] It can be understood that the first adhesion layer 27 and the second adhesion layer 28 can be formed in the same process, and the first heat-conducting layer 26 and the second heat-conducting layer 29 can be formed in the same process, which is conducive to simplifying the process.

[0106] In some embodiments, the second heat-conducting pillar 22 d and the first heat-conducting pillar 22 b have the same material and structure, but are not limited thereto.

[0107] It is understandable that the materials of the heat-conducting layer (e.g., the first heat-conducting layer 26, the second heat-conducting layer 29, and the third heat-conducting layer 30), the conductive connecting layer (e.g., the first conductive connecting layer 10, the second conductive connecting layer 11, and the third conductive connecting layer 12), the conductive column 9, and the heat-conducting column (e.g., the first heat-conducting column 22b and the second heat-conducting column 22d) in the embodiment of the present application can be the same, thereby simplifying the manufacturing process. Of course, in other embodiments, in order to take into account both high thermal conductivity and high electrical conductivity, the materials of the heat-conducting layer, the conductive connecting layer, the conductive column 9, and the heat-conducting column can be different.

[0108] In some embodiments, Figure 1 As shown, the redistribution layer 3 includes a first wiring layer 3a, a first dielectric layer 3b, a second wiring layer 3c, a second dielectric layer 3d, a third wiring layer 3e and a third dielectric layer 3f which are sequentially stacked on the side of the base layer 2 close to the chip stacking layer 4.

[0109] It should be noted that the first wiring layer 3a, the second wiring layer 3c and the third wiring layer 3e are conductive connection layers, and the first dielectric layer 3b, the second dielectric layer 3d and the third dielectric layer 3f are insulating layers. It can be understood that the number of wiring layers and dielectric layers in the redistribution layer 3 is not limited to three layers, and the number of layers can be increased according to the needs of the circuit structure.

[0110] In some embodiments, the materials of the first wiring layer 3a, the second wiring layer 3c and the third wiring layer 3e are the same, and are the same as the materials of the first conductive connection layer 10, the second conductive connection layer 11 and the third conductive connection layer 12. That is to say, the first wiring layer 3a, the second wiring layer 3c and the third wiring layer 3e can also be composed of a conductive layer 13 and an adhesive layer 14. Among them, the adhesive layer 14 in the first wiring layer 3a is located between the corresponding conductive layer 13 and the first dielectric layer 3b, the adhesive layer 14 in the second wiring layer 3c is located between the corresponding conductive layer 13 and the second dielectric layer 3d, and the adhesive layer 14 in the third wiring layer 3e is located between the corresponding conductive layer 13 and the third dielectric layer 3f.

[0111] It can be understood that the wiring layer and the conductive connection layer may be made of the same material to simplify the manufacturing process.

[0112] In some embodiments, the capacitor element 19 includes a first electrode 19a and a second electrode 19b that are at least partially overlapped; the first electrode 19a is located in any one of the first wiring layer 3a, the second wiring layer 3c and the third wiring layer 3e, and the second capacitor is located in any one of the first wiring layer 3a, the second wiring layer 3c and the third wiring layer 3e that is different from the first electrode 19a. The second electrode 19b is electrically connected to the first chip 6 and / or the second chip 7 (7') in at least one group of chip stacking units 5. Integrating the capacitor element 19 in the rewiring layer 3 can avoid additional welding of the external capacitor element 19 on the base layer 2, which is beneficial to reducing the area and volume of the chip packaging structure 1.

[0113] In some embodiments, the resistor element 18 is located in any one of the first wiring layer 3a, the second wiring layer 3c and the third wiring layer 3e, and the side of the resistor element 18 facing away from the base layer 2 is electrically connected to the first chip 6 and / or the second chip 7 (7') in at least one group of chip stacking units 5. Integrating the resistor element 18 in the redistribution layer 3 can avoid additional welding of the external resistor element 18 on the base layer 2, which is beneficial to reducing the area and volume of the chip packaging structure 1.

[0114] In some embodiments, the inductor element 20 includes a spiral coil 20a, a portion of which is located in at least one of the first wiring layer 3a, the second wiring layer 3c, and the third wiring layer 3e, and another portion of which penetrates the base layer 2 and extends to the side of the base layer 2 away from the redistribution layer 3. One end of the spiral coil 20a is electrically connected to the first chip 6 and / or the second chip 7 (7') in at least one group of chip stacking units 5. Integrating the inductor element 20 in the redistribution layer 3 can avoid additional welding of the external inductor element 20 on the base layer 2, which is beneficial to reducing the area and volume of the chip packaging structure 1.

[0115] In some embodiments, each coil of the spiral coil 20a is at least located on the side of the substrate layer 2 away from the redistribution layer 3, in the first wiring layer 3a and the second wiring layer 3c, and at least penetrates the substrate layer 2 and the first dielectric layer 3b. The surface of the spiral coil 20a located on the side of the substrate layer 2 away from the redistribution layer 3 is covered with a protective layer 32. The protective layer 32 is used to isolate the inductor element 20 exposed to the outside to prevent oxidation.

[0116] It can be understood that the spiral coil 20 a of the inductor element 20 in the embodiment of the present application penetrates the base layer 2 and is partially embedded in the redistribution layer 3 .

[0117] In one specific embodiment, the material of the protection layer 32 is selected from ink of a specific color.

[0118] In some embodiments, the chip packaging structure 1 further includes at least one welding portion 33 located on the side of the base layer 2 away from the redistribution layer 3, and the thickness of the welding portion 33 is greater than the thickness of any wiring layer in the redistribution layer 3, and greater than the sum of the thicknesses of the inductor element 20 and the protective layer 32 located on the side of the base layer 2 away from the redistribution layer 3. This design can prevent welding from being mistakenly welded to a position that does not require welding (such as the position where the inductor element 20 is located), thereby facilitating the improvement of welding yield.

[0119] In some embodiments, in combination Figure 1 , Fig.12 and Fig.13 As shown, the chip packaging structure 1 further includes at least one first plug 34 penetrating the base layer 2, at least one second plug 35 penetrating the first dielectric layer 3b, at least one third plug 36 penetrating the second dielectric layer 3d, and at least one fourth plug 37 penetrating the third dielectric layer 3f. The first wiring layer 3a includes a plurality of first signal bonding portions 38, at least some of which are connected to the first plug 34, and at least some of which are connected to the second plug 35. The second wiring layer 3c includes a plurality of second signal bonding portions 39, at least some of which are connected to the second plug 35, and at least some of which are connected to the third plug 36. The third wiring layer 3e includes a plurality of third signal bonding portions 40, at least some of which are connected to the third plug 36, and at least some of which are connected to the fourth plug 37.

[0120] The first plunger 34 is aligned and connected to the soldering portion 33, and the fourth plunger 37 is connected to the first conductive connection portion 11a or the second conductive connection portion 11b. The soldering portion 33 is electrically connected to the first conductive connection portion 11a or the second conductive connection portion 11b through the first plunger 34, the first signal bonding portion 38, the second plunger 35, the second signal bonding portion 39, the third plunger 36, the third signal bonding portion 40 and the fourth plunger 37 in sequence.

[0121] It can be understood that each soldering portion 33 is electrically connected to the first conductive connection portion 11a or the second conductive connection portion 11b through the redistribution layer 3, thereby achieving electrical connection with the first chip 6 and / or the second chip 7, thereby achieving signal input or output. In addition, the soldering portion 33 is used to connect the chip packaging structure 1 with other electronic devices or circuit structures.

[0122] In some embodiments, the first plug 34 and the first wiring layer 3a can be formed in the same process, the second plug 35 and the second wiring layer 3c can be formed in the same process, the third plug 36 and the third wiring layer 3e can be formed in the same process, and the fourth plug 37 and the second welding layer 42 described below can be formed in the same process.

[0123] In a specific embodiment, Fig.13 As shown, the first electrode 19a is located in the first wiring layer 3a, the second electrode 19b is located in the second wiring layer 3c, the first electrode 19a is connected to a second signal bonding portion 39 through a second plug 35, and the second electrode 19b is electrically connected to the first conductive connection portion 11a or the second conductive connection portion 11b through a third plug 36, a third signal bonding portion 40 and a fourth plug 37 in sequence. The resistor element 18 is located in the second wiring layer 3c, the side of the resistor element 18 close to the base layer 2 is connected to a first signal bonding portion 38 through a second plug 35, the side of the resistor element 18 away from the base layer 2 is connected to two third signal bonding portions 40 through a third plug 36, and one of the third signal bonding portions 40 is electrically connected to the first conductive connection portion 11a or the second conductive connection portion 11b through a fourth plug 37. The spiral coil 20a of the inductor element 20 is located on the side of the base layer 2 away from the redistribution layer 3, in the first wiring layer 3a and the second wiring layer 3c, and penetrates the base layer 2 and the first dielectric layer 3b. The spiral coil 20a includes a signal transmission end located in the second wiring layer 3c, and the signal transmission end is electrically connected to the first conductive connection part 11a or the second conductive connection part 11b through a third plunger 36, a third signal bonding part 40 and a fourth plunger 37 in sequence.

[0124] In a specific embodiment, if Fig.13 As shown, each coil includes a first portion 201a located on the side of the base layer 2 away from the redistribution layer 3, two second portions 201b penetrating the base, two third portions 201c located on the first wiring layer 3a, two fourth portions 201d penetrating the first dielectric layer 3b, and two fifth portions 201e located on the second wiring layer 3c; the two second portions 201b are respectively connected to the two ends of the first portion 201a, the two third portions 201c are respectively connected to the two second portions 201b one by one, the two fourth portions 201d are respectively connected to the two third portions 201c one by one, and the two fifth portions 201e are respectively connected to the two fourth portions 201d one by one. The first portion 201a, the second portion 201b, the third portion 201c, the fourth portion 201d, and the fifth portion 201e are connected to form a coil that vertically penetrates the base layer 2 and the first dielectric layer 3b.

[0125] Of course, in other embodiments, the spiral coil 20a of the inductor element 20 may also be formed in only one of the first wiring layer 3a, the second wiring layer 3c and the third wiring layer 3e.

[0126] It can be understood that through the double-sided through-hole process, a welding layer and a redistribution layer 3 are respectively arranged on the opposite sides of the base layer 2, and a capacitor area 16, a resistor area 15 and an inductor area 17 are formed, and the capacitor element 19, the resistor element 18 and the inductor element 20 are integrated inside the chip packaging structure 1, avoiding the additional welding of external resistor elements 18, capacitor elements 19 and inductor elements 20 on the base layer 2, reducing the subsequent welding process, and reducing the packaging area, which is beneficial to reducing the overall volume of the chip packaging structure 1.

[0127] In some embodiments, the substrate layer 2 includes any one of a glass substrate and a silicon substrate.

[0128] In a specific embodiment, the base layer 2 is a glass substrate. Since the glass substrate has the advantages of large size, good heat dissipation, low dielectric constant and dielectric loss, the embodiment of the present application can realize large-size, high-performance inductance, high-frequency application, lower dielectric loss and energy-saving chip packaging.

[0129] In the embodiment of the present application, on the one hand, a first through hole 8 penetrating the second chip 7 (7') is formed on the second chip 7 (7') by a through hole process, and a conductive column 9 is filled in the first through hole 8, so as to realize the electrical connection between the first chip 6 (top chip) and the second chip 7 (7') (bottom chip) and / or realize the electrical connection between the first chip 6 (top chip) and the redistribution layer 3, thereby realizing high-density chip integration and high-density chip interconnection. On the other hand, a second through hole 21 is formed on the first chip 6 by a hole opening process, and a first heat-conducting column 22b is filled in the second through hole 21. At the same time, the second heat dissipation layer 22c on the lower second chip 7 (7') is connected to the first heat dissipation layer 22a on the outer side of the top first chip 6 by the first heat-conducting column 22b, so that the heat generated by the lower second chip 7 (7') can be effectively discharged, and the second chip 7 (7') can be prevented from overheating during use, thereby solving the heat dissipation problem caused by multi-chip high-density interconnection and multi-layer chip packaging. On the other hand, through the double-sided through-hole process, a welding layer and a redistribution layer 3 are respectively arranged on the opposite sides of the base layer 2, and a capacitor area 16, a resistor area 15 and an inductor area 17 are formed, and the capacitor element 19, the resistor element 18 and the inductor element 20 are integrated inside the chip packaging structure 1, avoiding the additional welding of external resistor elements 18, capacitor elements 19 and inductor elements 20 on the base layer 2, reducing the subsequent welding process, and reducing the packaging area, which is beneficial to reducing the overall volume of the chip packaging structure 1.

[0130] Therefore, the embodiment of the present application can realize high-density chip integration and interconnection on a smaller substrate layer 2, and can solve the heat dissipation problem caused by high-density interconnection of multiple chips and multi-layer chip packaging, thereby meeting the needs of high-performance chips.

[0131] like Figures 6 to 13 As shown, the embodiment of the present application further provides a method for preparing the chip packaging structure 1 described in the aforementioned embodiment, and the preparation method includes steps S601 to S603.

[0132] S601: Prepare at least one group of chip stacking units; the chip stacking unit includes a first chip and at least one second chip stacked on one side of the first chip, each second chip is provided with a first through hole penetrating the second chip, the first through hole is filled with a conductive column, any chip is connected to the conductive column in the adjacent second chip, and the second chip located on the surface layer is provided with a first welding layer on the side facing away from the first chip, and the conductive column is connected to the first welding layer.

[0133] like Fig.10 and Fig.11 As shown, the chip stacking unit 5 includes a first chip 6 and at least one second chip 7 stacked on one side of the first chip 6, each second chip 7 is provided with a first through hole 8 penetrating the second chip 7, the first through hole 8 is filled with a conductive column 9, any chip is connected to the conductive column 9 in the adjacent second chip 7, and the second chip 7 located on the surface layer is provided with a first welding layer 41 on the side facing away from the first chip 6, and the conductive column 9 is connected to the first welding layer 41.

[0134] It can be understood that the embodiment of the present application does not limit the number of chip stacking units 5 .

[0135] In some embodiments, in step S601, the manufacturing process of each chip stacking unit 5 includes the following steps:

[0136] like Figure 7 As shown, a first chip 6 is provided, and at least one second through hole 21 penetrating the first chip 6 is formed on the first chip 6;

[0137] like Figure 7 As shown, a first heat dissipation layer 22a and a third welding layer 43 are formed on opposite sides of the first chip 6, and a first heat-conducting column 22b is filled in the second through hole 21; the third welding layer 43 includes a first heat-conducting welding portion 43a and a first conductive welding portion 43b, and two ends of the first heat-conducting column 22b are connected to the first heat dissipation layer 22a and the first heat-conducting welding portion 43a, respectively;

[0138] like Figure 8 or Fig. 9 As shown, a second chip 7 is provided, and at least one first through hole 8 penetrating the second chip 7 is formed on the second chip 7;

[0139] like Figure 8 or Fig. 9As shown, a fourth welding layer 44 and a first welding layer 41 are formed on opposite sides of the second chip 7, and a conductive column 9 is filled in the first through hole 8; the fourth welding layer 44 includes a second thermal conductive welding portion 44a and a second conductive welding portion 44b, and the second conductive welding portion 44b is connected to the conductive column 9; and

[0140] like Fig.10 or Fig.11 As shown, the third welding layer 43 and the fourth welding layer 44 are welded to connect the first thermal conductive welding portion 43a and the second thermal conductive welding portion 44a, and the first conductive welding portion 43b and the second conductive welding portion 44b, to form a chip stacking unit 5.

[0141] It can be understood that the first conductive welding part 43b and the second conductive welding part 44b are welded to form the first conductive connection layer 10 described in the above embodiment, and the first thermal conductive welding part 43a and the second thermal conductive welding part 44a are welded to form the second heat dissipation layer 22c. The relevant description of the first conductive connection layer 10 and the second heat dissipation layer 22c can refer to the above embodiment and will not be repeated here. Fig.10 and Fig.11 The difference between the two chip stacking units 5 shown is only the different structures of the first welding layer 44 . The two chip stacking units 5 can be arranged in the same chip packaging structure 1 .

[0142] In some embodiments, the first chip 6 and the second chip 7 are both glass-based chips; of course, in other embodiments, the first chip 6 and the second chip 7 may also be silicon-based chips.

[0143] When both the first chip 6 and the second chip 7 are glass-based chips, the first through hole 8 can be formed by a glass hole drilling process, making it easier to drill a hole on the second chip 7 .

[0144] It should be noted that the embodiment of the present application will take the case where the number of second chips 7 is one as an example to illustrate the preparation process of the chip stacking unit 5. When the number of second chips 7 is multiple, a similar process is used to set through holes on the second chip 7 (7') to achieve signal connection and / or heat dissipation connection between the upper and lower chips.

[0145] The embodiment of the present application adopts a stacking method to open holes in the chip, thereby realizing the connection of internal electrical signals and heat dissipation connections, and achieving the effect of effective heat dissipation of internal chips or bottom chips while realizing signal interconnection of multi-layer chips.

[0146] S602: providing a base layer, and sequentially forming a stacked redistribution layer and a second welding layer on one side of the base layer.

[0147] like Fig.12 and Fig.13As shown, a redistribution layer 3 and a second welding layer 42 which are stacked are sequentially formed on one side of the base layer 2 .

[0148] In some embodiments, S602 includes the following steps:

[0149] like Fig.12 As shown, a base layer 2 is provided; the base layer 2 includes a first surface 45 and a second surface 46 disposed opposite to each other;

[0150] like Fig.12 As shown, a first wiring layer 3a and a first dielectric layer 3b are stacked on a first surface 45 of the base layer 2, and at least one welding portion 33 and a partial structure of at least one inductor element 20 are formed on a second surface 46 of the base layer 2; the first wiring layer 3a includes a plurality of first signal bonding portions 38, and the welding portion 33 is connected to a first signal bonding portion 38 through a through hole penetrating the base layer 2, and the inductor element 20 also penetrates the base layer 2 and is located on the first wiring layer 3a;

[0151] like Fig.13 As shown, a second wiring layer 3c, a second dielectric layer 3d, a third wiring layer 3e and a third dielectric layer 3f are sequentially formed on the first dielectric layer 3b to form a redistribution layer 3; the second wiring layer 3c is electrically connected to the first wiring layer 3a through a through hole penetrating the first dielectric layer 3b, and the third wiring layer 3e is electrically connected to the second wiring layer 3c through a through hole penetrating the second dielectric layer 3d. At least one resistor element 18 and at least one capacitor element 19 are also formed in the redistribution layer 3, and the inductor element 20 may also be located in the second wiring layer 3c and penetrate the first dielectric layer 3b; and

[0152] like Fig.13 As shown, a second welding layer 42 is formed on the third dielectric layer 3f; the second welding layer 42 is electrically connected to the third wiring layer 3e through a through hole penetrating the third dielectric layer 3f.

[0153] In some embodiments, the substrate layer 2 includes any one of a glass substrate and a silicon substrate.

[0154] In a specific embodiment, the base layer 2 is a glass substrate. Since the glass substrate has the advantages of large size, good heat dissipation, low dielectric constant and dielectric loss, the embodiment of the present application can realize large-size, high-performance inductance, high-frequency application, lower dielectric loss and energy-saving chip packaging.

[0155] In some embodiments, the surface of the inductor element 20 located on the second surface 46 of the substrate layer 2 is covered by the protective layer 32. In a specific embodiment, the protective layer 32 is ink of a specific color.

[0156] Since the connection areas on both the upper and lower sides of the base layer 2 with the redistribution layer 3 are covered with welding layers, and the inductance area 17 is covered with a protective layer 32, the connection areas between the base layer 2 and the redistribution layer 3 can be effectively isolated, thereby achieving an anti-oxidation effect.

[0157] The structures of the redistribution layer 3 and the soldering portion 33 may refer to the description of the aforementioned embodiments and will not be elaborated here.

[0158] The embodiment of the present application adopts a double-sided through-hole process to realize the production of the welding part 33, the resistor element 18, the capacitor element 19 and the inductor element 20, and integrates the resistor element 18, the capacitor element 19 and the inductor element 20 in the redistribution layer 3, thereby avoiding the additional welding of the external resistor element 18, the capacitor element 19 and the inductor element 20 on the base layer 2, reducing the subsequent welding process and the packaging area, which is beneficial to reducing the overall volume of the chip packaging structure 1.

[0159] S603: Weld the first welding layer and the second welding layer so that at least one group of chip stacking units is welded on the side of the redistribution layer away from the base layer to form a chip stacking layer electrically connected to the redistribution layer; the first chip is electrically connected to the second chip and / or the redistribution layer through the conductive column.

[0160] It can be understood that after the first welding layer 41 and the second welding layer 42 are welded, Figure 1 The second conductive connection layer 11 is shown.

[0161] Specifically, Fig.10 As shown, the first welding layer 41 includes a third conductive welding portion 41a and a fourth conductive welding portion 41b, and the second welding layer 42 includes a fifth conductive welding portion 42a and a sixth conductive welding portion 42b which are aligned with the third conductive welding portion 41a and the fourth conductive welding portion 41b. The third conductive welding portion 41a is connected to the conductive column 9 in the second chip 7, and the fourth conductive welding portion 41b is connected to the second chip 7. After the third conductive welding portion 41a and the fifth conductive welding portion 42a are welded, the second conductive connection portion 11b described in the aforementioned embodiment is formed, and after the fourth conductive welding portion 41b and the sixth conductive welding portion 42b are welded, the first conductive connection portion 11a described in the aforementioned embodiment is formed.

[0162] like Fig.11 As shown, the bottom of the second chip 7 in another group of chip stacking units 5 is only provided with the third conductive welding portion 41 a , but the present invention is not limited thereto.

[0163] It can be understood that the number of conductive welding parts (conductive connecting parts) between each group of chip stacking units 5 and the redistribution layer 3 can be the same or different, and the embodiment of the present application does not limit this.

[0164] In the embodiment of the present application, high-density chip integration and interconnection can be achieved on a smaller substrate layer 2 through through-hole and double-sided processes, and the heat dissipation problem caused by high-density interconnection of multiple chips and multi-layer chip packaging can be solved, thereby meeting the needs of high-performance chips.

[0165] like Fig.14 As shown, the embodiment of the present application further provides an electronic device 47, which includes a device body 48 and at least one chip packaging structure 1 provided in the above embodiments. The chip packaging structure 1 is electrically connected to the device body 48.

[0166] It can be understood that the chip packaging structure 1 can be electrically connected to other electronic devices or circuit structures in the device body 48 through the contact portion 33 arranged at the bottom of the base layer 22, so as to achieve signal connection.

[0167] In some embodiments, the electronic device 47 may be a display device or an AI smart product, which is not limited in this application.

[0168] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0169] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0170] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0171] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A chip packaging structure, characterized in that: include: basal layer; A redistribution layer is disposed on one side of the base layer; as well as a chip stacking layer, arranged on a side of the redistribution layer away from the base layer, and comprising at least one group of chip stacking units; the chip stacking unit comprises a first chip and at least one second chip located between the first chip and the redistribution layer, the first chip and the second chip being arranged to at least partially overlap in a thickness direction of the base layer; Among them, the chip packaging structure also includes at least one first through hole passing through each of the second chips, the first through hole is filled with a conductive column, any chip is connected to the conductive column in the adjacent second chip, and the first chip is electrically connected to the second chip and / or the redistribution layer through the conductive column.

2. The chip packaging structure according to claim 1, characterized in that: A first conductive connection layer is provided between the first chip and the adjacent second chip, and the first conductive connection layer is connected to the conductive column in the adjacent second chip; A second conductive connection layer is provided between the second chip close to the redistribution layer and the redistribution layer, and the second conductive connection layer includes a first conductive connection portion and a second conductive connection portion which are located between the corresponding second chip and the redistribution layer and are spaced apart; the first conductive connection portion is electrically connected to the adjacent second chip and the redistribution layer, respectively, and the second conductive connection portion is electrically connected to the conductive column in the adjacent second chip and the redistribution layer, respectively.

3. The chip packaging structure according to claim 2, characterized in that: A plurality of the second chips are stacked in sequence in the thickness direction of the base layer and arranged between the redistribution layer and the first chip, and a third conductive connection layer is arranged between any two adjacent second chips; The third conductive connection layer is connected to the conductive pillar in the adjacent second chip.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The redistribution layer includes a resistance region, a capacitance region and an inductance region located between the base layer and the chip stacking layer; at least one resistance element is formed in the resistance region, at least one capacitance element is formed in the capacitance region, and at least one inductance element is formed in the inductance region; The resistance element and the capacitance element are both located in the redistribution layer, and the inductance element is at least partially located in the redistribution layer; The resistance element, the capacitance element, and the inductance element are electrically connected to the first chip and / or the second chip in at least one group of the chip stacking units, respectively.

5. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a heat dissipation component and a second through hole penetrating the first chip; The heat dissipation component includes a first heat dissipation layer covering the side of the first chip facing away from the second chip, a first thermally conductive column filled in the second through hole, and a second heat dissipation layer covering the side of the second chip adjacent to the first chip facing away from the redistribution layer, wherein both ends of the first thermally conductive column are respectively connected to the first heat dissipation layer and the second heat dissipation layer.

6. The chip packaging structure according to claim 5, characterized in that: A plurality of second chips are stacked in sequence in the thickness direction of the base layer and arranged between the redistribution layer and the first chip, the chip packaging structure further comprises a third through hole penetrating at least part of the second chips, the heat dissipation assembly further comprises a second heat-conducting column filled in the third through hole, and the second heat dissipation layer is arranged on a side of each second chip away from the redistribution layer; In any two adjacent second chips, the third through hole is at least arranged in the second chip on a side close to the first chip, and both ends of the second heat-conducting column are respectively connected to the adjacent second heat dissipation layer.

7. The chip packaging structure according to claim 5, characterized in that: The first heat dissipation layer entirely covers a side of the first chip that is away from the second chip.

8. The chip packaging structure according to claim 5, characterized in that: The second chip includes a circuit area and at least one heat dissipation area adjacent to the circuit area, the conductive column is located in the circuit area, the second heat dissipation layer is located in the heat dissipation area, and the first heat conductive column and the second heat dissipation layer are overlapped.

9. The chip packaging structure according to claim 5, characterized in that: The first heat dissipation layer includes a first heat-conducting layer and a first adhesive layer located between the first heat-conducting layer and the first chip; the first heat-conducting column includes a second adhesive layer filled in the sidewall and the bottom of the first through hole and a second heat-conducting layer surrounded by the second adhesive layer; the second heat dissipation layer includes a third heat-conducting layer and a third adhesive layer located between the third heat-conducting layer and the second chip; The first heat conducting layer is connected to the second heat conducting layer, the first adhesive layer is connected to the second adhesive layer, and the second adhesive layer is connected to the second heat conducting layer.

10. The chip packaging structure according to claim 9, characterized in that: The first adhesion layer, the second adhesion layer and the third adhesion layer are made of the same material and are selected from metal copper; The first heat-conducting layer, the second heat-conducting layer and the third heat-conducting layer are made of the same material, which is selected from molybdenum, titanium or an alloy thereof.

11. The chip packaging structure according to claim 4, characterized in that: The redistribution layer comprises a first wiring layer, a first dielectric layer, a second wiring layer, a second dielectric layer, a third wiring layer and a third dielectric layer which are sequentially stacked on a side of the base layer close to the chip stacking layer; The capacitor element includes a first electrode and a second electrode that are at least partially overlapped; the first electrode is located in any one of the first wiring layer, the second wiring layer and the third wiring layer, and the second capacitor is located in any one of the first wiring layer, the second wiring layer and the third wiring layer that is different from the first electrode; The second electrode is electrically connected to the first chip and / or the second chip in at least one group of the chip stacking units; The resistor element is located in any one of the first wiring layer, the second wiring layer and the third wiring layer, and a side of the resistor element away from the base layer is electrically connected to the first chip and / or the second chip in at least one group of the chip stacking units; The inductor element includes a spiral coil, a portion of which is located in at least one of the first wiring layer, the second wiring layer and the third wiring layer, and another portion of which penetrates the base layer and extends to a side of the base layer away from the redistribution layer; one end of the spiral coil is electrically connected to the first chip and / or the second chip in at least one group of the chip stacking units.

12. The chip packaging structure according to claim 11, characterized in that: Each coil of the spiral coil is at least located on a side of the base layer away from the redistribution layer, in the first wiring layer and the second wiring layer, and at least penetrates the base layer and the first dielectric layer; The surface of the spiral coil located on the side of the base layer away from the redistribution layer is covered with a protection layer.

13. The chip packaging structure according to claim 11, characterized in that: The chip packaging structure further includes at least one welding portion located on a side of the base layer away from the redistribution layer, at least one first plug penetrating the base layer, at least one second plug penetrating the first dielectric layer, at least one third plug penetrating the second dielectric layer, and at least one fourth plug penetrating the third dielectric layer; The first wiring layer includes a plurality of first signal bonding portions, at least part of which is connected to the first plug, and at least part of which is connected to the second plug; the second wiring layer includes a plurality of second signal bonding portions, at least part of which is connected to the second plug, and at least part of which is connected to the third plug; the third wiring layer includes a plurality of third signal bonding portions, at least part of which is connected to the third plug, and at least part of which is connected to the fourth plug; The first plunger is aligned and connected to the welding part, and the fourth plunger is connected to the first conductive connection part or the second conductive connection part; the welding part is electrically connected to the first conductive connection part or the second conductive connection part through the first plunger, the first signal bonding part, the second plunger, the second signal bonding part, the third plunger, the third signal bonding part and the fourth plunger in sequence.

14. The chip packaging structure according to claim 12, characterized in that: The chip packaging structure further comprises at least one welding portion located on a side of the base layer away from the redistribution layer; The thickness of the welding portion is greater than the thickness of any one of the redistribution layers, and is greater than the sum of the thicknesses of the inductor element and the protective layer located on a side of the base layer away from the redistribution layer.

15. The chip packaging structure according to claim 13, characterized in that: The first electrode is located in the first wiring layer, the second electrode is located in the second wiring layer, the first electrode is connected to the second signal bonding portion through the second plug, and the second electrode is electrically connected to the first conductive connecting portion or the second conductive connecting portion through the third plug, the third signal bonding portion and the fourth plug in sequence; The resistor element is located in the second wiring layer, a side of the resistor element close to the base layer is connected to a first signal bonding portion through a second plug, a side of the resistor element away from the base layer is connected to two third signal bonding portions through a third plug, and one of the third signal bonding portions is electrically connected to the first conductive connecting portion or the second conductive connecting portion through a fourth plug; The spiral coil of the inductor element is located on the side of the base layer away from the redistribution layer, in the first wiring layer and the second wiring layer, and penetrates the base layer and the first dielectric layer; the spiral coil includes a signal transmission end located in the second wiring layer, and the signal transmission end is electrically connected to the first conductive connecting part or the second conductive connecting part through a third plug, a third signal bonding part and a fourth plug in sequence.

16. The chip packaging structure according to claim 1, characterized in that: The first chip and the second chip each include any one of a glass-based chip and a silicon-based chip, and the base layer includes any one of a glass substrate and a silicon substrate.

17. A method for preparing a chip packaging structure, characterized in that: include: Prepare at least one group of chip stacking units; the chip stacking unit comprises a first chip and at least one second chip stacked on one side of the first chip, each of the second chips is provided with a first through hole penetrating the second chip, the first through hole is filled with a conductive column, any chip is connected to the conductive column in the adjacent second chip, a first welding layer is provided on the side of the second chip located on the surface layer away from the first chip, and the conductive column is connected to the first welding layer; Providing a base layer, and sequentially forming a stacked redistribution layer and a second welding layer on one side of the base layer; as well as The first welding layer and the second welding layer are welded so that the at least one group of chip stacking units are welded on the side of the redistribution layer away from the base layer to form a chip stacking layer electrically connected to the redistribution layer; the first chip is electrically connected to the second chip and / or the redistribution layer through the conductive column.

18. The method for preparing a chip packaging structure according to claim 17, characterized in that: The manufacturing process of the chip stacking unit includes: Providing a first chip, and forming at least one second through hole penetrating the first chip on the first chip; A first heat dissipation layer and a third welding layer are respectively formed on opposite sides of the first chip, and a first heat-conducting column is filled in the second through hole; the third welding layer includes a first heat-conducting welding portion and a first conductive welding portion, and two ends of the first heat-conducting column are respectively connected to the first heat dissipation layer and the first heat-conducting welding portion; Providing a second chip, and forming at least one first through hole penetrating the second chip on the second chip; forming a fourth welding layer and a fifth welding layer on opposite sides of the second chip respectively, and filling the conductive column in the first through hole; the fourth welding layer comprises a second thermal conductive welding portion and a second conductive welding portion, and the second conductive welding portion is connected to the conductive column; and The third welding layer and the fourth welding layer are welded to connect the first thermal conductive welding portion and the second thermal conductive welding portion, and the first conductive welding portion and the second conductive welding portion, to form a chip stacking unit.

19. The method for preparing a chip packaging structure according to claim 17, characterized in that: The method of providing a base layer and sequentially forming a stacked redistribution layer and a second welding layer on one side of the base layer comprises the following steps: Providing a base layer; the base layer comprises a first surface and a second surface arranged opposite to each other; A first wiring layer and a first dielectric layer are stacked on the first surface of the base layer, and at least one welding portion and a partial structure of at least one inductor element are formed on the second surface of the base layer; the first wiring layer includes a plurality of first signal bonding portions, the welding portion is connected to one of the first signal bonding portions through a through hole penetrating the base layer, and the inductor element also penetrates the base layer and is located in the first wiring layer; A second wiring layer, a second dielectric layer, a third wiring layer and a third dielectric layer are sequentially formed on the first dielectric layer to form the redistribution layer; the second wiring layer is electrically connected to the first wiring layer through a through hole penetrating the first dielectric layer, the third wiring layer is electrically connected to the second wiring layer through a through hole penetrating the second dielectric layer, at least one resistor element and at least one capacitor element are further formed in the redistribution layer, and the inductor element may also be located in the second wiring layer and penetrate the first dielectric layer; and A second welding layer is formed on the third dielectric layer; the second welding layer is electrically connected to the third wiring layer through a through hole penetrating the third dielectric layer.

20. An electronic device, characterized in that: A chip packaging structure comprising any one of claims 1 to 16.

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