Power supply circuit and undershoot suppression circuit thereof

Abstract

The invention provides a power supply circuit and an undershoot suppression circuit thereof. The power supply circuit generates an output voltage. The undershoot suppression circuit includes a rising edge determination circuit, a falling edge determination circuit, and a pulse generation circuit. The rising edge decision circuit detects a difference voltage between the output voltage and a reference voltage, and outputs a clock control signal of a first voltage level when the difference voltage is greater than a critical voltage. The falling edge decision circuit detects the output voltage and outputs a reset signal of a first voltage level when the output voltage is not less than the reference voltage. The pulse generator generates an undershoot suppression pulse according to a clock control signal of a first voltage level and a reset signal of the first voltage level, so that the output voltage is close to the reference voltage. The undershoot suppression circuit can automatically control the output period of the undershoot suppression pulse according to the voltage level of the output voltage. Therefore, the power supply circuit adopting the undershoot suppression circuit has the advantages of automatically optimizing the transient response capability of the load and the like.

Description

Technical Field

[0001] The present application relates to an undershoot suppression circuit, and more particularly to an undershoot suppression circuit applied to a power supply circuit. Background Art

[0002] With the development of semiconductor technology, the ability of power supply circuits to respond to load transients has become increasingly important. Some related technologies set threshold values, and after the output voltage change (e.g., rising or falling slope) provided to the load exceeds the set threshold value, corresponding operations are performed to meet the load requirements. However, these related technologies require testing the power supply circuit to determine whether the set threshold value can effectively respond to the load transient. If it is determined after testing that the currently set threshold value cannot effectively respond to the load transient, the threshold value needs to be reset and tested again. Therefore, it is necessary to propose a new way to solve the above problems. Summary of the invention

[0003] One aspect of the present application is an undershoot suppression circuit for a control circuit of at least one power stage circuit. The control circuit is used to control at least one power stage circuit to generate an output voltage at an output node electrically coupled to the at least one power stage circuit. The undershoot suppression circuit includes a rising edge determination circuit, a falling edge determination circuit, and a pulse generation circuit. The rising edge determination circuit is used to output a clock control signal to detect a difference voltage between an output voltage and a reference voltage, and to control the clock control signal to have a first voltage level when the difference voltage is greater than a critical voltage. The falling edge determination circuit is used to output a reset signal to detect the output voltage, and to control the reset signal to have a first voltage level when the output voltage is not less than a reference voltage. The pulse generation circuit is electrically coupled to the rising edge determination circuit and the falling edge determination circuit, to receive the clock control signal and the reset signal, and to generate an undershoot suppression pulse according to the clock control signal having a first voltage level and the reset signal having a first voltage level, so that the output voltage approaches the reference voltage.

[0004] In some embodiments, the rising edge determination circuit includes a difference calculation circuit and a comparison circuit. The difference calculation circuit is used to receive the output voltage and the reference voltage, and to generate the difference voltage according to the reference voltage and the output voltage. The comparison circuit is electrically coupled to the difference calculation circuit, and is used to receive and compare the difference voltage and the threshold voltage to generate the clock control signal having the first voltage level or a second voltage level different from the first voltage level.

[0005] In some embodiments, the falling edge determination circuit includes a comparison circuit for receiving and comparing the output voltage and the reference voltage to generate the reset signal having the first voltage level or a second voltage level different from the first voltage level.

[0006] In some embodiments, the pulse generating circuit includes a flip-flop circuit. The flip-flop circuit includes a data input terminal, a clock input terminal, a reset terminal, and a data output terminal, wherein the data input terminal is used to receive an enable signal having the first voltage level, the clock input terminal is used to receive the clock control signal, the reset terminal is used to receive the reset signal, and the data output terminal is used to output an undershoot suppression signal. The flip-flop circuit first switches the voltage level of the undershoot suppression signal to the first voltage level of the enable signal in response to the clock control signal having the first voltage level, maintains the voltage level of the undershoot suppression signal at the first voltage level in response to the clock control signal having a second voltage level different from the first voltage level, and resets the voltage level of the undershoot suppression signal to the second voltage level in response to the reset signal having the first voltage level, so as to generate the undershoot suppression pulse.

[0007] In some embodiments, the control circuit is further used to control the at least one power stage circuit to generate an output current at the output end, and the voltage level of the reference voltage decreases as the magnitude of the output current increases. The control circuit is also used to simultaneously enable the at least one power stage circuit to increase the output current during the output of the undershoot suppression pulse, so that the output voltage approaches the reference voltage.

[0008] One aspect of the present application is a power supply circuit. The power supply circuit includes a control signal generating circuit, a plurality of power stage circuits, and an undershoot suppression circuit. The control signal generating circuit is used to output a plurality of control signals. The plurality of power stage circuits are electrically coupled to the control signal generating circuit and the output node of the power supply circuit, and are used to receive a plurality of control signals, wherein the control signal generating circuit is used to enable the plurality of power stage circuits in sequence through a plurality of control signals, so that an output voltage is generated at the output node. The undershoot suppression circuit is electrically coupled to the output node and the control signal generating circuit, is used to detect the output voltage, and is used to receive a reference voltage and a critical voltage. In response to detecting that the output voltage is less than the reference voltage and that the difference between the output voltage and the reference voltage exceeds the critical voltage, the undershoot suppression circuit generates an undershoot suppression pulse to the control signal generating circuit, so that the output voltage approaches the reference voltage. In response to detecting that the output voltage is not less than the reference voltage, the undershoot suppression circuit stops generating the undershoot suppression pulse to the control signal generating circuit.

[0009] In some embodiments, the undershoot suppression circuit includes: a difference calculation circuit, used to receive the output voltage and the reference voltage, and used to generate a difference voltage according to the difference between the reference voltage and the output voltage; a first comparison circuit, electrically coupled to the difference calculation circuit, used to receive and compare the difference voltage and the critical voltage to generate a clock control signal; a second comparison circuit, used to receive and compare the output voltage and the reference voltage to generate a reset signal; and a flip-flop circuit, including a data input terminal, a clock input terminal, a reset terminal and a data output terminal, wherein the data input terminal is used to receive an enable signal having a first voltage level, the clock input terminal is used to receive the clock control signal, the reset terminal is used to receive the reset signal, and the data output terminal is used to output an undershoot suppression signal.

[0010] In some embodiments, when the difference voltage is greater than the critical voltage, the first comparison circuit generates the clock control signal having the first voltage level, and the flip-flop circuit switches the voltage level of the undershoot suppression signal to the first voltage level of the enable signal in response to the clock control signal having the first voltage level to generate the undershoot suppression pulse.

[0011] In some embodiments, when the difference voltage is not greater than the critical voltage, the first comparison circuit generates the clock control signal having a second voltage level different from the first voltage level, and the flip-flop circuit maintains the voltage level of the undershoot suppression signal at the first voltage level in response to the clock control signal having the second voltage level to generate the undershoot suppression pulse.

[0012] In some embodiments, when the output voltage is not less than the reference voltage, the second comparison circuit generates the reset signal having the first voltage level, and the flip-flop circuit switches the undershoot suppression signal from the first voltage level to a second voltage level different from the first voltage level in response to the reset signal having the first voltage level to stop generating the undershoot suppression pulse.

[0013] In summary, the rising edge of the undershoot suppression pulse is determined by detecting whether the difference voltage between the reference voltage and the output voltage is greater than the critical voltage, and the falling edge of the undershoot suppression pulse is determined by the undershoot suppression circuit detecting whether the output voltage is not less than the reference voltage. The undershoot suppression circuit of the present application can automatically control the output period of the undershoot suppression pulse according to the voltage level of the output voltage. Therefore, compared with some related technologies that need to set different parameters for different targets and adjust the parameters through repeated tests in order to make a suitable response to load transients, the power supply circuit using the undershoot suppression circuit of the present application can have the advantages of automatically optimizing the load transient response capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1The invention is a circuit block diagram of a power supply circuit according to some embodiments of the present application.

[0015] Figure 2 FIG. 4 is a circuit block diagram of an undershoot suppression circuit according to some embodiments of the present application.

[0016] Figure 3 The figure is a circuit diagram of an undershoot suppression circuit according to some embodiments of the present application.

[0017] Figure 4 FIG. 4 is a signal timing diagram of an undershoot suppression circuit according to some embodiments of the present application.

[0018] Figure 5 FIG. 4 is a signal timing diagram of an undershoot suppression signal and a control signal according to some embodiments of the present application.

[0019] Figure 6 FIG. 4 is a signal timing diagram of an undershoot suppression signal and a control signal according to some embodiments of the present application.

[0020] Figure 7 FIG. 4 is a signal timing diagram of an undershoot suppression signal and a control signal according to some embodiments of the present application. DETAILED DESCRIPTION

[0021] The following embodiments are described in detail with reference to the accompanying drawings, but the specific embodiments described are only used to explain the present case and are not used to limit the present case. The description of the structural operation is not used to limit the order of its execution. Any structure recombined by the elements to produce a device with equal functions is within the scope of the present invention.

[0022] The terms used throughout the specification and claims generally have the ordinary meanings of each term used in the art, in the context of this disclosure, and in the specific context, unless otherwise noted.

[0023] As used herein, “coupled” or “connected” may refer to direct physical or electrical contact between two or more elements, or indirect physical or electrical contact between two or more elements, or may refer to mutual operation or action between two or more elements.

[0024] In the following embodiments, if only a component or signal symbol is used without specifying the index of the component or signal symbol, it means that the component or signal symbol refers to any unspecified one of the component group or signal group to which it belongs. For example, the power stage circuit 11 refers to one or more unspecified ones of the power stage circuits 11[1] to 11[8].

[0025] See also Figure 1 , Figure 1FIG. 1 is a circuit block diagram of a power supply circuit 100 according to some embodiments of the present application. In some embodiments, the power supply circuit 100 includes a plurality of power stage circuits 11[1] to 11[8] and a control circuit 13. The power supply circuit 100 is electrically coupled to a load circuit 10 via an output node Nout and is used to supply power to the load circuit 10. Specifically, the load circuit 10 may be a processing circuit such as a central processing unit (CPU) or an application-specific integrated circuit (ASIC).

[0026] like Figure 1 As shown, the plurality of power stage circuits 11[1]-11[8] are electrically coupled to the control circuit 13, and the plurality of output terminals of the plurality of power stage circuits 11[1]-11[8] are electrically coupled to the output node Nout of the power supply circuit 100. In addition, the control circuit 13 is also electrically coupled to the output node Nout. For illustration purposes, Figure 1 The embodiment of the present invention depicts eight power stage circuits 11 [1] to 11 [8], but the number of the power stage circuits 11 of the present application is not limited thereto and can be any integer.

[0027] In some embodiments, each power stage circuit 11 is used to receive an input voltage Vin and to receive a corresponding control signal PWM from a control circuit 13. Specifically, the control signal PWM may be a pulse width modulation (PWM) signal. Accordingly, each power stage circuit 11 is used to operate a transistor switch (not shown) inside the power stage circuit 11 according to the corresponding control signal PWM. For example, Figure 1 As shown, the power stage circuit 11[1] operates according to the control signal PWM[1], and the power stage circuit 11[2] operates according to the control signal PWM[2]. Similarly, the power stage circuit 11[8] operates according to the control signal PWM[8].

[0028] In some embodiments, such as Figure 1As shown, the control circuit 13 includes a control signal generating circuit 130 and an undershoot suppression circuit 132. The control signal generating circuit 130 is electrically coupled to a plurality of power stage circuits 11[1] to 11[8]. The control signal generating circuit 130 is used to output a plurality of control signals PWM[1] to PWM[8], and to sequentially enable the plurality of power stage circuits 11[1] to 11[8] through the plurality of control signals PWM[1] to PWM[8] (i.e., to allow each power stage circuit 11 to operate its internal transistor switch according to the corresponding control signal PWM), so as to generate an output voltage Vout at the output node Nout obtained by converting the input voltage Vin. In addition, an output current Iout is also generated at the output node Nout. Specifically, the output current Iout may be the sum of a plurality of currents generated by the plurality of power stage circuits 11[1] to 11[8].

[0029] In some practical applications, the load circuit 10 may require a larger operating current due to a temporary change in the task, that is, the power supply circuit 100 needs to increase the value of the output current Iout. Due to some non-ideal factors, the multiple power stage circuits 11[1]~11[8] cannot immediately increase the output current Iout to the operating current value required by the load circuit 10. Therefore, the capacitor element (not shown) electrically coupled to the output node Nout in the power supply circuit 100 will discharge to compensate for the shortage of the output current Iout. In addition, the discharge of the aforementioned capacitor element causes the output voltage Vout to undershoot.

[0030] In view of this, in some embodiments, the control circuit 13 is used to improve the undershoot phenomenon of the output voltage Vout through the operation of the undershoot suppression circuit 132. Figure 1 As shown, the undershoot suppression circuit 132 is electrically coupled to the output node Nout and the control signal generating circuit 130. The undershoot suppression circuit 132 is used to receive the reference voltage VDAC and the threshold voltage Vth, and to detect the output voltage Vout on the output node Nout. In some embodiments, the undershoot suppression circuit 132 performs corresponding operations according to the value of the output voltage Vout.

[0031] In detail, in some embodiments, the output voltage Vout is significantly reduced due to the change of the load circuit 10 (i.e., the output voltage Vout undershoots), and the undershoot suppression circuit 132 detects that the output voltage Vout is reduced to less than the reference voltage VDAC, and detects that the difference between the output voltage Vout and the reference voltage VDAC exceeds the threshold voltage Vth. Accordingly, the undershoot suppression circuit 132 generates an undershoot suppression pulse USP to the control signal generating circuit 130. By triggering the undershoot suppression pulse USP, the control signal generating circuit 130 simultaneously enables the multiple power stage circuits 11[1]~11[8] through multiple control signals PWM. It should be understood that the control signal generating circuit 130 does not continuously and simultaneously enable the multiple power stage circuits 11[1]~11[8] during the output of the undershoot suppression pulse USP. Specifically, the control signal generating circuit 130 can pre-set the same duty ratio for each control signal PWM so as to simultaneously enable and disable the plurality of power stage circuits 11[1] to 11[8] according to the preset duty ratio during the output period of the undershoot suppression pulse USP. This operation will be described in detail in the following paragraphs. Figure 5 Further explanation: It is worth noting that by enabling the multiple power stage circuits 11 [1] to 11 [8] simultaneously, the output current Iout increases, and the output voltage Vout approaches the reference voltage VDAC.

[0032] In some embodiments, the output voltage Vout is increased by the multiple power stage circuits 11[1]-11[8] being enabled simultaneously, and the undershoot suppression circuit 132 detects that the output voltage Vout rises to reach the reference voltage VDAC (i.e., the output voltage Vout is not less than the reference voltage VDAC, which indicates that the undershoot phenomenon of the output voltage Vout is improved). Accordingly, the undershoot suppression circuit 132 stops generating the undershoot suppression pulse USP to the control signal generating circuit 130. Correspondingly, the control signal generating circuit 130 returns to sequentially enabling the multiple power stage circuits 11[1]-11[8] through the multiple control signals PWM[1]-PWM[8].

[0033] It can be seen from the above embodiments that when the output voltage Vout undershoots, the undershoot suppression circuit 132 triggers the control signal generating circuit 130 to simultaneously enable the multiple power stage circuits 11[1]-11[8] to improve the undershoot phenomenon of the output voltage Vout.

[0034] Then match them in order Figure 2 and Figure 3 The circuit configuration of the undershoot suppression circuit 132 is described. Figure 2 , Figure 2FIG. 1 is a circuit block diagram of an undershoot suppression circuit 132 according to some embodiments of the present application. In some embodiments, the undershoot suppression circuit 132 includes a rising edge determination circuit 21, a falling edge determination circuit 23, and a pulse generation circuit 25. Figure 2 As shown, the rising edge determination circuit 21 is used to receive the output voltage Vout, the reference voltage VDAC and the threshold voltage Vth, and to output the clock control signal CCS. The falling edge determination circuit 23 is used to receive the output voltage Vout and the reference voltage VDAC, and to output the reset signal RSTS. In addition, the pulse generation circuit 25 is electrically coupled to the rising edge determination circuit 21 and the falling edge determination circuit 23, and is used to receive the clock control signal CCS and the reset signal RSTS, and to output the undershoot suppression signal USS to Figure 1 The control signal generating circuit 130 in.

[0035] In some embodiments, the rising edge determination circuit 21 is used to detect the difference voltage Vdiff between the output voltage Vout and the reference voltage VDAC. Specifically, the difference voltage Vdiff is the reference voltage VDAC minus the output voltage Vout. The rising edge determination circuit 21 is also used to control the voltage level of the clock control signal CCS according to the comparison result of the difference voltage Vdiff and the threshold voltage Vth. The falling edge determination circuit 23 is used to detect the output voltage Vout, and to control the voltage level of the reset signal RSTS according to the comparison result of the output voltage Vout and the reference voltage VDAC. The pulse generation circuit 25 is used to control the voltage level of the undershoot suppression signal USS through the voltage level of the clock control signal CCS and the voltage level of the reset signal RSTS to generate the undershoot suppression pulse USP.

[0036] See also Figure 3 , Figure 3FIG. 1 is a circuit block diagram of an undershoot suppression circuit 132 according to some embodiments of the present application. In some embodiments, the undershoot suppression circuit 132 includes a difference calculation circuit 211, a comparison circuit 213, a comparison circuit 231, and a flip-flop circuit 251. The difference calculation circuit 211 is used to receive an output voltage Vout and a reference voltage VDAC to generate a difference voltage Vdiff according to the output voltage Vout and the reference voltage VDAC. The non-inverting input terminal of the comparison circuit 213 is electrically coupled to the output terminal of the difference calculation circuit 211 to receive the difference voltage Vdiff, and the inverting input terminal of the comparison circuit 213 is used to receive the threshold voltage Vth. The non-inverting input terminal of the comparison circuit 231 is used to receive the output voltage Vout, and the inverting input terminal of the comparison circuit 231 is used to receive the reference voltage VDAC. The flip-flop circuit 251 includes a data input terminal D, a reset terminal RST, a clock input terminal (located between the data input terminal D and the reset terminal RST), and a data output terminal Q. The flip-flop circuit 251 is electrically coupled to the output terminal of the comparison circuit 213 through the clock input terminal to receive the clock control signal CCS, is electrically coupled to the output terminal of the comparison circuit 231 through the reset terminal RST to receive the reset signal RSTS, and is electrically coupled to the output terminal of the comparison circuit 231 through the data output terminal Q to receive the reset signal RSTS. Figure 1 The control signal generating circuit 130 in the embodiment outputs the undershoot suppression signal USS to the control signal generating circuit 130. In addition, the data input terminal D of the flip-flop circuit 251 is used to receive the enable signal EN having the first voltage level VH.

[0037] In some embodiments, the difference calculation circuit 211 is used to generate a difference voltage Vdiff according to the difference between the reference voltage VDAC and the output voltage Vout (i.e., the result of subtracting the output voltage Vout from the reference voltage VDAC). The comparison circuit 213 is used to compare the difference voltage Vdiff with the threshold voltage Vth to generate a clock control signal CCS. The comparison circuit 231 is used to compare the output voltage Vout with the reference voltage VDAC to generate a reset signal RSTS. In addition, the flip-flop circuit 251 is used to control the voltage level of the undershoot suppression signal USS according to the clock control signal CCS and the reset signal RSTS to generate an undershoot suppression pulse USP.

[0038] Specifically, Figure 3 In the embodiment of the present invention, the difference calculation circuit 211 may be implemented by a subtractor, the comparison circuit 213 and the comparison circuit 231 may be implemented by comparators, and the flip-flop circuit 251 may be implemented by a D-type flip-flop.

[0039] By the above Figure 2 and Figure 3As can be seen from the description, the difference calculation circuit 211 and the comparison circuit 213 can be used to implement the rising edge determination circuit 21, the comparison circuit 231 can be used to implement the falling edge determination circuit 23, and the flip-flop circuit 251 can be used to implement the pulse generation circuit 25. However, the present invention is not limited to this, that is, the present invention does not exclude the use of other methods to implement the rising edge determination circuit 21, the falling edge determination circuit 23 and the pulse generation circuit 25.

[0040] Then match Figure 2 , Figure 3 and Figure 4 The operation of each circuit in the undershoot suppression circuit 132 is further described. Figure 4 , Figure 4 The signal timing diagram of the undershoot suppression circuit 132 is shown according to some embodiments of the present application. In some embodiments, before a time T1, due to a sudden increase in the demand for working current of the load circuit 10, the aforementioned capacitor element begins to discharge, so that the output current Iout begins to increase and the output voltage Vout begins to undershoot.

[0041] In some embodiments, the reference voltage VDAC is determined according to the value of the output current Iout. Specifically, the voltage level of the reference voltage VDAC can be calculated by substituting the output current Iout into the following formula (1), wherein VN in the formula (1) is a preset voltage value (e.g., 0.9 volts), and Rload in the formula (1) is an equivalent resistance value of the load circuit 10 (e.g., 1 milliohm (mΩ)).

[0042] VDAC=VN-Iout×Rload…(1)

[0043] Depend on Figure 4 It can be seen that before time T1, the decrease in the output voltage Vout per unit time is greater than the reference voltage VDAC (at Figure 4 Therefore, in some embodiments, at time T1, the output voltage Vout decreases to a value lower than the reference voltage VDAC, and the difference between the two (i.e., the difference voltage Vdiff) is greater than the critical voltage Vth. Accordingly, at time T1, Figure 3 The comparison circuit 213 generates a clock control signal CCS having a first voltage level VH.

[0044] In some embodiments, such as Figure 3 As shown, since the clock input terminal of the flip-flop circuit 251 receives the clock control signal CCS having the first voltage level VH, the flip-flop circuit 251 outputs the data received by the data input terminal D through the data output terminal Q. In other words, Figure 4As shown, at time T1 , the flip-flop circuit 251 switches the voltage level of the undershoot suppression signal USS to the first voltage level VH of the enable signal EN in response to the clock control signal CCS having the first voltage level VH, so as to generate the undershoot suppression pulse USP.

[0045] After time T1, if Figure 1 In the embodiment, the control signal generating circuit 130 is triggered by the undershoot suppression pulse USP, and multiple power stage circuits 11[1]-11[8] are simultaneously enabled through multiple control signals PWM[1]-PWM[8] to increase the output current Iout and the output voltage Vout. Figure 4 It can be seen that by enabling multiple power stage circuits 11[1] to 11[8] simultaneously, the drop in the output voltage Vout per unit time is reduced. In addition, from the above formula (1), it can be seen that since VN and Rload in formula (1) are substantially fixed values, the voltage level of the reference voltage VDAC decreases as the value of the output current Iout increases. The result is as follows: Figure 4 Therefore, the output voltage Vout will slowly approach the reference voltage VDAC.

[0046] In some embodiments, such as Figure 4 As shown, at time T2, the difference voltage Vdiff generated by subtracting the output voltage Vout from the reference voltage VDAC is not greater than the critical voltage Vth. Figure 3 The comparison circuit 213 generates a clock control signal CCS having a second voltage level VL. Specifically, the second voltage level VL is different from the first voltage level VH. For example, the first voltage level VH is greater than the second voltage level VL.

[0047] In some embodiments, such as Figure 3 As shown in FIG. 2 , since the clock input terminal of the flip-flop circuit 251 receives the clock control signal CCS having the second voltage level VL, the flip-flop circuit 251 will maintain the output state of the data output terminal Q. In other words, Figure 4 As shown, at time T2, the flip-flop circuit 251 maintains the voltage level of the undershoot suppression signal USS at the first voltage level VH in response to the clock control signal CCS having the second voltage level VL to generate the undershoot suppression pulse USP. Accordingly, the control signal generating circuit 130 continues to simultaneously enable the multiple power stage circuits 11[1]-11[8] through the multiple control signals PWM[1]-PWM[8] to allow the output voltage Vout to continue to approach the reference voltage VDAC.

[0048] In some embodiments, such as Figure 4As shown, at time T3, the output voltage Vout rises to reach the reference voltage VDAC (ie, the output voltage Vout is not less than the reference voltage VDAC). Figure 3 The comparison circuit 231 generates a reset signal RSTS having a first voltage level VH.

[0049] In some embodiments, such as Figure 3 As shown, since the reset terminal RST of the flip-flop circuit 251 receives the reset signal RSTS having the first voltage level VH, the flip-flop circuit 251 forces the data output terminal Q to enter a reset state. Figure 4 As shown, at time T3, the flip-flop circuit 251 switches the voltage level of the undershoot suppression signal USS from the first voltage level VH to the second voltage level VL in response to the reset signal RSTS having the first voltage level VH, so as to stop generating the undershoot suppression pulse USP. Accordingly, the control signal generating circuit 130 returns to sequentially enabling the multiple power stage circuits 11[1]-11[8] through the multiple control signals PWM[1]-PWM[8].

[0050] As can be seen from the above-mentioned embodiments, the rising edge determination circuit 21 is used to control the clock control signal CCS to have the first voltage level VH when the difference voltage Vdiff is greater than the critical voltage Vth. The falling edge determination circuit 23 is used to control the reset signal RSTS to have the first voltage level VH when the output voltage Vout is not less than the reference voltage VDAC. The pulse generation circuit 25 is used to first switch the undershoot suppression signal USS from the second voltage level VL to the first voltage level VH in response to the clock control signal CCS having the first voltage level VH, and then switch the undershoot suppression signal USS from the first voltage level VH to the second voltage level VL again in response to the reset signal RSTS having the first voltage level VH, so as to generate the undershoot suppression pulse USP.

[0051] That is, when the output voltage Vout is detected to be undershooting (i.e., the difference voltage Vdiff between the reference voltage VDAC and the output voltage Vout is detected to be greater than the threshold voltage Vth), the undershoot suppression circuit 132 can generate an undershoot suppression pulse USP to trigger the control signal generating circuit 130 to simultaneously enable the plurality of power stage circuits 11[1] to 11[8] until the output voltage Vout is detected to reach or track the reference voltage VDAC. In this way, the undershoot phenomenon of the output voltage Vout can be improved.

[0052] Further explanation, such as Figure 4As shown, the output period P1 of the undershoot suppression pulse USP is between the time T1 when the clock control signal CCS switches from the second voltage level VL to the first voltage level VH and the time T3 when the reset signal RSTS switches from the second voltage level VL to the first voltage level VH.

[0053] It should be understood that the rising edge determination circuit 21 is also used to control the clock control signal CCS to have a second voltage level VL when the difference voltage Vdiff is not greater than the threshold voltage Vth (for example, before time T1 or after time T2). In addition, the falling edge determination circuit 23 is also used to control the reset signal RSTS to have a second voltage level VL when the output voltage Vout is less than the reference voltage VDAC (for example, between time T1 and time T3).

[0054] In the above embodiment, if Figure 4 As shown, the reference voltage VDAC changes according to the value of the output current Iout. For example, the greater the value of the output current Iout, the smaller the reference voltage VDAC. However, the present invention is not limited thereto. For example, in some embodiments, the reference voltage VDAC has a fixed voltage level.

[0055] See also Figure 5 , Figure 5 FIG. 1 is a timing diagram of an undershoot suppression signal USS and a plurality of control signals PWM[1] to PWM[8] according to some embodiments of the present application. Figure 1 In the description of the embodiments, the plurality of control signals PWM[1]-PWM[8] are respectively used to control the operation of the plurality of power stage circuits 11[1]-11[8]. In some embodiments, before the undershoot suppression pulse USP is generated, the control signal generating circuit 130 has sequentially enabled the power stage circuit 11[1] and the power stage circuit 11[2] through the enable pulse P[1] of the control signal PWM[1] and the enable pulse P[2] of the control signal PWM[2], but has not yet enabled the remaining power stage circuits 11[3]-11[8]. That is, when the undershoot suppression pulse USP is just generated, the power stage circuit 11[1] has been in the disabled state (i.e., has not received the enable pulse P[1]) for a period of time, but the power stage circuit 11[2] has just been in the disabled state (i.e., has not received the enable pulse P[2]) for a short time.

[0056] In some embodiments, such as Figure 5As shown, during the output of the undershoot suppression pulse USP, the control signal generating circuit 130 adjusts the voltage levels of the multiple control signals PWM[1]~PWM[8] according to the aforementioned preset duty cycle, so that the multiple control signals PWM[1]~PWM[8] simultaneously generate at least one supplementary pulse P'. In this way, the multiple power stage circuits 11[1]~11[8] will be alternately enabled and disabled at the same time to increase the output current Iout and improve the undershoot phenomenon of the output voltage Vout. In addition, after the undershoot suppression pulse USP stops being generated, the control signal generating circuit 130 returns to enabling the multiple power stage circuits 11[1]~11[8] in sequence. In some embodiments, Figure 5 The rising edge and the falling edge of the undershoot suppression pulse USP may not overlap with the enable pulse and the supplementary pulse, or may be aligned with the rising edge and the falling edge of the supplementary pulse, respectively.

[0057] See also Figure 6 , Figure 6 The timing diagram of the undershoot suppression signal USS and a plurality of control signals PWM[1]-PWM[8] is illustrated according to some embodiments of the present application. In some embodiments, when the undershoot suppression pulse USP is just generated, the control signal generating circuit 130 is enabling the power stage circuit 11[1] and the power stage circuit 11[2] in sequence through the enable pulse P[1] of the control signal PWM[1] and the enable pulse P[2] of the control signal PWM[2], but has not yet enabled the remaining power stage circuits 11[3]-11[8].

[0058] In some embodiments, such as Figure 6As shown, in the initial stage of outputting the undershoot suppression pulse USP, the control signal generating circuit 130 maintains the enable pulses P[1]-P[2] according to the aforementioned preset duty cycle, and adjusts the voltage levels of a portion of the control signals PWM[3]-PWM[8] according to the aforementioned preset duty cycle, so that the portion of the control signals PWM[3]-PWM[8] simultaneously generate the supplementary pulses P'. During the remaining output period of the undershoot suppression pulse USP, the control signal generating circuit 130 adjusts the voltage levels of the plurality of control signals PWM[1]-PWM[8] according to the aforementioned preset duty cycle based on the timing relationship between the enable pulses P[1]-P[2] and the supplementary pulses P'[3]-P'[8], so that the plurality of control signals PWM[1]-PWM[8] generate at least one supplementary pulse P'. In this way, the multiple power stage circuits 11[3] to 11[8] will be enabled and disabled alternately at the same time. When the power stage circuit 11[2] is slightly ahead of the multiple power stage circuits 11[3] to 11[8] in timing, it will also be enabled and disabled alternately. When the power stage circuit 11[1] is slightly ahead of the power stage circuit 11[2] in timing, it will also be enabled and disabled alternately. This will increase the output current Iout and improve the undershoot of the output voltage Vout. In addition, if Figure 5 In the embodiment, after the undershoot suppression pulse USP stops being generated, the control signal generating circuit 130 returns to sequentially enabling the multiple power stage circuits 11[1]-11[8] instead of enabling the multiple power stage circuits 11[1]-11[8] simultaneously. In some embodiments, Figure 6 The rising edge and the falling edge of the undershoot suppression pulse USP can overlap the enable pulse and the supplement pulse respectively.

[0059] See also Figure 7 , Figure 7 1 is a timing diagram of an undershoot suppression signal USS and a plurality of control signals PWM[1]-PWM[8] according to some embodiments of the present application. Figure 7 An embodiment similar to Figure 6 Embodiment of the invention. Figure 7 Example and Figure 6 The difference between the embodiments is that the control signal generating circuit 130 extends the output period of the enable pulses P[1]-P[2] and the supplementary pulses P'[3]-P'[8] at the initial stage of the output of the undershoot suppression pulse USP, so as to increase the proportion of the power stage circuit 11 being enabled during the output period of the undershoot suppression pulse USP. Specifically, the output period of the enable pulse P[1] is extended by the period TE, the output period of the enable pulse P[2] is extended by the period TE', and the output period of the supplementary pulses P'[3]-P'[8] is extended by the period TE", wherein the lengths of the period TE, the period TE' and the period TE" may be different. In some embodiments, Figure 7The rising edge and the falling edge of the undershoot suppression pulse USP can overlap the enable pulse and the supplement pulse respectively. Figure 7 The remaining description of the embodiment Figure 6 The description of the embodiments is similar and will not be repeated here.

[0060] In the above-mentioned embodiments, the control signal generating circuit 130 enables the multiple power stage circuits 11[1] to 11[8] simultaneously through the multiple control signals PWM[1] to PWM[8] according to the undershoot suppression pulse USP, but the present application is not limited thereto. For example, in some embodiments, the control signal generating circuit 130 can enable a portion of the multiple power stage circuits 11[1] to 11[8] simultaneously. It can be seen that the control signal generating circuit 130 can enable all or part of the power stage circuits 11 simultaneously according to the undershoot suppression pulse USP. In addition, in some embodiments, the control signal generating circuit 130 can adjust the voltage levels of the multiple control signals PWM according to the undershoot suppression pulse USP to simultaneously generate multiple supplementary pulses P', but it is not necessary to output all of the multiple supplementary pulses P' generated simultaneously. In other words, the multiple supplementary pulses P' generated simultaneously can be partially output and partially not output.

[0061] From the above-mentioned implementation of the present application, it can be known that the rising edge of the undershoot suppression pulse USP is determined by detecting whether the difference voltage Vdiff between the reference voltage VDAC and the output voltage Vout is greater than the critical voltage Vth, and the falling edge of the undershoot suppression pulse USP is determined by detecting whether the output voltage Vout is not less than the reference voltage VDAC through the undershoot suppression circuit 132. The undershoot suppression circuit 132 of the present application can automatically control the output period P1 of the undershoot suppression pulse USP according to the voltage level of the output voltage Vout. Therefore, compared with some related technologies that need to set different parameters for different targets and adjust the parameters through repeated tests in order to make a suitable response to the load transient, the power supply circuit 100 using the undershoot suppression circuit 132 of the present application can have the advantages of automatically optimizing the load transient response capability.

[0062] Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the following claims.

[0063]

Explanation of symbols

[0064] 10: Load circuit

[0065] 11: Power stage circuit

[0066] 13: Control circuit

[0067] 21: Rising edge determination circuit

[0068] 23: Falling edge determination circuit

[0069] 25: Pulse generating circuit

[0070] 100: Power supply circuit

[0071] 130: Control signal generating circuit

[0072] 132: Undershoot suppression circuit

[0073] 211: Difference calculation circuit

[0074] 213,231: Comparison circuit

[0075] 251: Flip-flop circuit

[0076] CCS: Clock control signal

[0077] D: Data input terminal

[0078] EN: Enable signal

[0079] Iout: output current

[0080] Nout: output node

[0081] P1: Output period

[0082] P: Enable pulse

[0083] P': Supplementary pulse

[0084] PWM: control signal

[0085] Q: Data output terminal

[0086] RST: Reset terminal

[0087] RSTS: reset signal

[0088] T1, T2, T3: time

[0089] TE,TE',TE": period

[0090] USP: Undershoot Suppression Pulse

[0091] USS: Undershoot Suppression Signal

[0092] VDAC: reference voltage

[0093] VH: First voltage level

[0094] VL: Second voltage level

[0095] Vdiff: difference voltage

[0096] Vin: Input voltage

[0097] Vout: output voltage

[0098] Vth: threshold voltage.

Claims

1. An undershoot suppression circuit, applicable to a control circuit of at least one power stage circuit, the control circuit is used to control the at least one power stage circuit to generate an output voltage at an output node electrically coupled to the at least one power stage circuit, and the undershoot suppression circuit is characterized in that it comprises: A rising edge determination circuit is used to output a clock control signal, to detect a voltage difference between the output voltage and a reference voltage, and to control the clock control signal to have a first voltage level when the voltage difference is greater than a critical voltage; A falling edge determination circuit is used to output a reset signal, detect the output voltage, and control the reset signal to have the first voltage level when the output voltage is not less than the reference voltage; as well as The pulse generating circuit is electrically coupled to the rising edge determining circuit and the falling edge determining circuit, and is used to receive the clock control signal and the reset signal, and to generate an undershoot suppression pulse according to the clock control signal having the first voltage level and the reset signal having the first voltage level, so that the output voltage approaches the reference voltage.

2. The undershoot suppression circuit according to claim 1, characterized in that: The rising edge determination circuit comprises: A difference calculation circuit is used for receiving the output voltage and the reference voltage, and for generating the difference voltage according to the reference voltage and the output voltage; as well as The comparison circuit is electrically coupled to the difference calculation circuit, and is used for receiving and comparing the difference voltage and the threshold voltage to generate the clock control signal having the first voltage level or a second voltage level different from the first voltage level.

3. The undershoot suppression circuit according to claim 1, characterized in that: The falling edge determination circuit comprises: The comparison circuit is used for receiving and comparing the output voltage and the reference voltage to generate the reset signal having the first voltage level or a second voltage level different from the first voltage level.

4. The undershoot suppression circuit according to claim 1, characterized in that: The pulse generating circuit comprises: A flip-flop circuit, comprising a data input terminal, a clock input terminal, a reset terminal and a data output terminal, wherein the data input terminal is used to receive an enable signal having the first voltage level, the clock input terminal is used to receive the clock control signal, the reset terminal is used to receive the reset signal, and the data output terminal is used to output an undershoot suppression signal; The flip-flop circuit first switches the voltage level of the undershoot suppression signal to the first voltage level of the enable signal in response to the clock control signal having the first voltage level, maintains the voltage level of the undershoot suppression signal at the first voltage level in response to the clock control signal having a second voltage level different from the first voltage level, and resets the voltage level of the undershoot suppression signal to the second voltage level in response to the reset signal having the first voltage level to generate the undershoot suppression pulse.

5. The undershoot suppression circuit according to claim 1, characterized in that: The control circuit is further used to control the at least one power stage circuit to generate an output current at the output end, and the voltage level of the reference voltage decreases as the value of the output current increases; The control circuit is also used to enable the at least one power stage circuit to increase the output current during the output period of the undershoot suppression pulse, so that the output voltage approaches the reference voltage.

6. A power supply circuit, characterized in that: Include: A control signal generating circuit, used for outputting a plurality of control signals; A plurality of power stage circuits are electrically coupled to the control signal generating circuit and the output node of the power supply circuit and are used to receive the control signals, wherein the control signal generating circuit is used to sequentially enable the power stage circuits through the control signals so that an output voltage is generated at the output node; as well as An undershoot suppression circuit is electrically coupled to the output node and the control signal generating circuit, and is used to detect the output voltage and receive a reference voltage and a threshold voltage; The undershoot suppression circuit generates an undershoot suppression pulse to the control signal generating circuit in response to detecting that the output voltage is less than the reference voltage and the difference between the output voltage and the reference voltage exceeds the critical voltage, so that the output voltage approaches the reference voltage; When the undershoot suppression circuit detects the output voltage being not less than the reference voltage, the undershoot suppression circuit stops generating the undershoot suppression pulse to the control signal generating circuit.

7. The power supply circuit according to claim 6, characterized in that: The undershoot suppression circuit comprises: A difference calculation circuit is used for receiving the output voltage and the reference voltage, and for generating a difference voltage according to the difference between the reference voltage and the output voltage; A first comparison circuit is electrically coupled to the difference calculation circuit, and is used to receive and compare the difference voltage and the threshold voltage to generate a clock control signal; A second comparison circuit, used for receiving and comparing the output voltage and the reference voltage to generate a reset signal; as well as The flip-flop circuit includes a data input terminal, a clock input terminal, a reset terminal and a data output terminal, wherein the data input terminal is used to receive an enable signal having a first voltage level, the clock input terminal is used to receive the clock control signal, the reset terminal is used to receive the reset signal, and the data output terminal is used to output an undershoot suppression signal.

8. The power supply circuit according to claim 7, characterized in that: When the difference voltage is greater than the critical voltage, the first comparison circuit generates the clock control signal having the first voltage level, and the flip-flop circuit switches the voltage level of the undershoot suppression signal to the first voltage level of the enable signal in response to the clock control signal having the first voltage level to generate the undershoot suppression pulse.

9. The power supply circuit according to claim 7, characterized in that: When the difference voltage is not greater than the critical voltage, the first comparison circuit generates the clock control signal having a second voltage level different from the first voltage level, and the flip-flop circuit maintains the voltage level of the undershoot suppression signal at the first voltage level in response to the clock control signal having the second voltage level to generate the undershoot suppression pulse.

10. The power supply circuit according to claim 7, characterized in that: When the output voltage is not less than the reference voltage, the second comparison circuit generates the reset signal having the first voltage level, and the flip-flop circuit switches the undershoot suppression signal from the first voltage level to a second voltage level different from the first voltage level in response to the reset signal having the first voltage level to stop generating the undershoot suppression pulse.

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