Power supply capable of adaptively adjusting voltage stabilization feedback compensation bandwidth range

Abstract

The power supply comprises a noise suppression circuit, an active power factor correction circuit, an active clamping flyback conversion circuit, a voltage stabilization feedback compensation circuit and a control circuit. The active power factor correction circuit and the active clamping flyback conversion circuit convert the AC voltage into an output voltage required by the operation of the load device, and the voltage stabilization feedback compensation circuit provides voltage stabilization feedback compensation for the output voltage. The active clamping flyback conversion circuit switches the operation mode according to the instant output load of the power supply, and the control circuit controls the operation of the voltage stabilization feedback compensation circuit according to the operation mode of the active clamping flyback conversion circuit. And the equivalent capacitance of the voltage-stabilizing feedback loop is adjusted according to different output loads so as to provide a corresponding voltage-stabilizing feedback compensation bandwidth range.

Description

Technical Field

[0001] The present invention relates to a power supply, and in particular to a power supply with adaptive adjustment of voltage regulation feedback compensation bandwidth. Background Art

[0002] Different components in a computer system require different operating voltages, so power supplies are commonly used to convert AC indoor power into DC to drive different components through transformation, rectification and filtering. With the rise of environmental awareness, countries have set energy-saving specifications for consumer electronics, office equipment, home appliances and external power supplies. For example, the U.S. Energy Star is a certification program jointly sponsored by the U.S. Department of Energy and the Environmental Protection Agency (EPA). It has clear definitions and energy-saving specifications for power supplies with different rated output power in various states and under different load operations.

[0003] For example, for power supplies with an output power greater than 70W and their overall system configuration, the US Energy Star standard requires that their rated power factor (power factor) must be greater than 0.9. Therefore, the design architecture of a high-power power supply is usually divided into a boost-type front-stage circuit and a buck-type rear-stage circuit. The front-stage circuit of a high-power power supply can be a boost power factor corrector (boost PFC), which is responsible for improving the power factor of the AC power supply end; the rear-stage circuit of a high-power power supply can use a buck-type flyback converter (flyback converter), which is responsible for converting the high voltage (e.g. 400V) output by the boost power factor corrector into a low voltage (e.g. 19.5V) to supply load devices such as laptops.

[0004] In order to meet the increasingly stringent energy-saving specifications, power supplies are usually designed with a voltage regulation feedback compensation architecture to reduce power consumption. However, power supplies in the prior art only design a single voltage regulation feedback compensation bandwidth for the maximum load rate, and cannot achieve low-loss optimization when running in other modes. Therefore, a power supply with an adaptive adjustment of the voltage regulation compensation bandwidth range is needed. Summary of the invention

[0005] The present invention provides a power supply with an adaptively adjustable voltage regulation compensation bandwidth, which is used to convert an AC voltage into an output voltage to supply power to a load device, and includes a noise suppression circuit, a boost type active power factor correction circuit, an active clamp flyback conversion circuit, a voltage regulation feedback compensation circuit and a control circuit. The noise suppression circuit is used to filter out the noise in the AC voltage to provide a processed AC voltage. The boost type active power factor correction circuit is used to convert the processed AC voltage into a DC voltage, and then convert the DC voltage into a pulsating DC voltage. The active clamp flyback conversion circuit is used to convert the pulsating DC voltage into the output voltage and provide a detection voltage related to the output voltage. The voltage regulation feedback compensation circuit is used to selectively perform voltage regulation feedback compensation on the output voltage with a first voltage regulation feedback compensation bandwidth or a second voltage regulation feedback compensation bandwidth. The control circuit is used to output a first control signal that periodically switches between a first enable potential and a first disable potential to control the operation of the boost-type active power factor correction circuit; output a second control signal that periodically switches between a second enable potential and a second disable potential to control the operation of the active clamp flyback conversion circuit; determine a current operation mode of the active clamp flyback conversion circuit according to the detection voltage; when it is determined that the active clamp flyback conversion circuit is operating in a first mode according to the detection voltage, control the voltage regulation feedback compensation circuit to perform voltage regulation feedback compensation on the output voltage with the first voltage regulation feedback compensation bandwidth range; and when it is determined that the active clamp flyback conversion circuit is operating in a second mode according to the detection voltage, control the voltage regulation feedback compensation circuit to perform voltage regulation feedback compensation on the output voltage with the second voltage regulation feedback compensation bandwidth range. Wherein, when the active clamp flyback conversion circuit operates in the first mode, a first real-time output load of the power supply is greater than a second real-time output load of the power supply when the active clamp flyback conversion circuit operates in the second mode, and the first voltage regulation feedback compensation bandwidth range is greater than the second voltage regulation feedback compensation bandwidth range. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a functional block diagram of a power supply with adaptive adjustment of voltage regulation compensation bandwidth according to an embodiment of the present invention.

[0007] Figure 2 FIG. 4 is a schematic diagram of an implementation of a power supply capable of adaptively adjusting a voltage regulation compensation bandwidth according to an embodiment of the present invention.

[0008] Figure 3A FIG. 4 is a schematic diagram of related signals when the active clamp flyback converter circuit in the power supply according to an embodiment of the present invention operates in a continuous conduction mode.

[0009] Figure 3BFIG. 4 is a schematic diagram of related signals when the active clamp flyback converter circuit in the power supply according to an embodiment of the present invention operates in a quasi-resonant mode.

[0010] Figure 3C FIG. 4 is a schematic diagram of related signals when the active clamp flyback converter circuit in the power supply according to an embodiment of the present invention operates in the burst mode.

[0011] Figure 4A-4C Schematic diagram of an equivalent circuit of a voltage stabilizing feedback compensation circuit of a power converter in different operating modes according to an embodiment of the present invention.

[0012] Figure 5 FIG. 4 is a schematic diagram of a voltage regulation compensation bandwidth range provided by a power converter for different operation modes according to an embodiment of the present invention.

[0013] The reference numerals are described as follows:

[0014] 10: Noise suppression circuit

[0015] 12: Rectifier

[0016] 20: Boost type active power factor correction circuit

[0017] 30: Active clamp flyback conversion circuit

[0018] 40: Voltage stabilization feedback compensation circuit

[0019] 42: Light Emitting Diode

[0020] 44: Phototransistor

[0021] 50: Control circuit

[0022] 100: Power supply

[0023] L1, L2: Live wire pins

[0024] N1, N2: Neutral pins

[0025] NP: Primary side winding and number of turns

[0026] NS: Secondary winding and number of turns

[0027] NX: Auxiliary winding and number of turns

[0028] NC1-NC3: Windings and turns of coupled inductors

[0029] GND1, GND2: Ground potential

[0030] FG: Ground terminal

[0031] TR: Transformer

[0032] Q1, Q2: power switches

[0033] Q3, Q4: Auxiliary switch

[0034] PC: Linear Optocoupler

[0035] TL: Voltage Regulator

[0036] A: Anode terminal of the voltage regulator

[0037] K: cathode terminal of the regulator

[0038] R: Reference terminal of the voltage regulator

[0039] CO1, CO2: Energy storage capacitors

[0040] CX: X capacitor

[0041] CY1, CY2: Y capacitors

[0042] CC: Compensation capacitor

[0043] CB: Feedback capacitor

[0044] LC1, LC2: common mode inductors

[0045] LX1, LX2: bandwidth limiting inductors

[0046] LTC: Coupled Inductors

[0047] DO1: Boost diode

[0048] DO2: Output diode

[0049] D1-D4: diodes

[0050] LM1: boost inductor

[0051] LM2: Magnetizing inductor

[0052] V IN : DC voltage

[0053] V OUT : Output voltage

[0054] V AC : AC voltage

[0055] V AC ': AC voltage after processing

[0056] V FB : Feedback voltage

[0057] V REF : Reference voltage

[0058] VO1, VO2: pulsating DC voltage

[0059] Vs: Detection voltage

[0060] Rs: Detection resistor

[0061] I C : Compensation current

[0062] I FB : Feedback current

[0063] I OUT : Output current

[0064] RO1, RO2: voltage divider resistors

[0065] RP: Startup resistor

[0066] Rs: Detection resistor

[0067] GD1-GD4: control signal

[0068] P1-P6: Pins DETAILED DESCRIPTION

[0069] Figure 1 The functional block diagram of a power supply 100 with adaptive adjustment of voltage regulation compensation bandwidth in an embodiment of the present invention. The power supply 100 includes a noise suppression circuit 10, a boost type active power factor correction circuit 20, an active clamp flyback conversion circuit 30, a voltage regulation feedback compensation circuit 40, and a control circuit 50. The noise suppression circuit 10 can receive an AC voltage V AC , and filter the AC voltage V AC The common mode noise and / or differential mode noise in the circuit can provide a processed AC voltage V AC '. The boost active power factor correction circuit 20 can process the AC voltage V AC The active clamp flyback converter circuit 30 can convert the pulsating DC voltage VO1 into an output voltage V OUT To supply power to the load device (not shown) Figure 1 ), and provides the relevant output voltage V OUT The voltage regulator feedback compensation circuit 40 can detect the output voltage V OUT state to provide a corresponding feedback voltage V FB , and according to the operation mode of the active clamp flyback converter circuit 30, the output voltage V OUT Provide voltage regulation feedback compensation. The control circuit 50 can be based on the feedback voltage V FBThe detection voltage VS is used to control the operation of the boost active power factor correction circuit 20, the active clamp flyback conversion circuit 30, and the voltage regulation feedback compensation circuit 40 to perform voltage conversion and voltage regulation feedback compensation, and the voltage regulation feedback compensation range is adaptively adjusted according to the operation mode of the active clamp flyback conversion circuit 30 to reduce power consumption.

[0070] Figure 2 The noise suppression circuit 10 can be connected to a mains supply terminal through a live pin L1 and a neutral pin N1 to receive an AC voltage V AC , and then output the processed AC voltage V through a live wire pin L2 and a neutral wire pin N2 AC However, the implementation of the transmission interface between the noise suppression circuit 10 and the mains power supply terminal does not limit the scope of the present invention.

[0071] exist Figure 2 In the illustrated embodiment, the noise suppression circuit 10 includes common mode inductors LC1-LC2, coupled inductors LTC, X capacitors CX, and Y capacitors CY1 and CY2. The coupled inductor LTC includes three windings (represented by the number of turns NC1-NC3, respectively), wherein windings NC1 and NC3 are arranged on the first side of the magnetic core, and winding NC2 is arranged on the second side of the magnetic core. In the coupled inductor LTC, the first end of the winding NC1 is coupled to the first input end (live pin L1) of the noise suppression circuit 10, and the second end is coupled to the first output end (live pin L2) of the noise suppression circuit 10; the first end of the winding NC2 is coupled to the second input end (neutral pin N1) of the noise suppression circuit 10, and the second end is coupled to the second output end (neutral pin N2) of the noise suppression circuit 10; the first end and the second end of the winding NC3 are coupled to the voltage regulation feedback compensation circuit 40. The first end of the common mode inductor LC1 is coupled to the first end of the winding NC1 in the coupled inductor LTC, and the second end thereof is coupled to the second end of the winding NC1 in the coupled inductor LTC. The first end of the common mode inductor LC2 is coupled to the first end of the winding NC2 in the coupled inductor LTC, and the second end thereof is coupled to the second end of the winding NC2 in the coupled inductor LTC. The first end of the X capacitor CX is coupled between the live pin L1 and the first end of the common mode inductor LC1, and the second end thereof is coupled between the neutral pin N1 and the first end of the common mode inductor LC2. The first end of the Y capacitor CY1 is coupled between the live pin L2 and the second end of the common mode inductor LC1, and the second end thereof is coupled to a ground terminal FG. The first end of the Y capacitor CY2 is coupled between the neutral pin N2 and the second end of the common mode inductor LC2, and the second end thereof is coupled to the ground terminal FG.

[0072] AC voltage V supplied by the mains ACThere may be differential mode noise or common mode noise in the circuit. Differential mode noise generally refers to the voltage noise between the live wire pin L1 and the neutral wire pin N1 between the frequency of 10KHz-30MHz, which is not conducted to the ground terminal FG. Common mode noise generally refers to the voltage noise between the frequency of 10KHz-30MHz that is conducted to the ground terminal FG through the live wire pin L1 or the neutral wire pin N1 of the power supply. In the present invention, the noise suppression circuit 10 can filter out the AC voltage V through the X capacitor CX. AC The differential mode noise in the circuit can be filtered out by Y capacitor CY. AC In the present invention, the noise suppression circuit 10 can also filter out the AC voltage V through the common mode inductors LC1-LC2. AC The common mode noise in the circuit 10 is filtered out, and the value of the common mode inductor LC1-LC2 is determined by the frequency band of the noise to be filtered out. In one embodiment, the value of the common mode inductor LC1 is equal to the value of the common mode inductor LC2 to achieve optimal noise filtering. However, the implementation of the noise suppression circuit 10 does not limit the scope of the present invention.

[0073] exist Figure 2 In the embodiment shown, the boost active power factor correction circuit 20 includes a rectifier 12, a power switch Q1, a boost diode DO1, a storage capacitor CO1, and a boost inductor LM1, which can convert the processed AC voltage V AC ' is converted into a pulsating DC voltage VO1. In the embodiment of the present invention, the rectifier 12 may be a bridge rectifier, which includes rectifier diodes D1-D4, coupled to the live pin L2 and the common mode inductor N2 to receive the processed AC voltage V AC ', and the processed AC voltage V AC 'Converted into a DC voltage V IN However, the implementation of the rectifier 12 does not limit the scope of the present invention.

[0074] The first terminal of the boost inductor LM1 is coupled to the rectifier 12 to receive the DC voltage V IN , and the second end is selectively coupled to the ground potential GND1 through the power switch Q1, which can store the DC voltage V INThe first end of the energy storage capacitor CO1 is coupled to the pulsating DC voltage VO1, and the second end is coupled to the ground potential GND1, which can store the energy of the pulsating DC voltage VO1. The anode of the boost diode DO1 is coupled to the second end of the boost inductor LM1, and the cathode is coupled to the first end of the energy storage capacitor CO1. The first end of the power switch Q1 is coupled between the second end of the boost inductor LM1 and the anode of the boost diode DO1, and the second end is coupled to the ground potential GND1. The control end receives a control signal GD1, and can perform high-frequency switching according to the control signal GD1 to allow the boost inductor LM1 to store and release energy, so that the input current follows the input voltage, thereby improving the power factor and reducing current harmonics.

[0075] In the boost type active power factor correction circuit 20, the boost inductor LM1, the boost diode DO1, the energy storage capacitor CO1 and the power switch Q1 can achieve the purpose of boosting. AC When the power switch Q1 is turned on, the second end of the boost inductor LM1 is coupled to the ground potential GND1. At this time, the boost inductor LM1 responds to the DC voltage V IN The change in the voltage will generate an induced voltage, and then convert the electrical energy into magnetic energy for storage. When the power switch Q1 is turned off, the ground loop of the boost inductor LM1 is disconnected, and the magnetic energy stored in it will be converted into electrical energy, allowing a large current to pass through the boost diode DO1 to charge the energy storage capacitor CO1. After multiple rapid switching of the power switch Q1, the DC voltage V IN To provide a pulsating DC voltage VO1.

[0076] exist Figure 2 In the embodiment shown, the active clamp flyback converter circuit 30 includes a transformer TR, a power switch Q2, a magnetizing inductor LM2, a storage capacitor CO2, a detection resistor Rs, and an output diode DO2. The active clamp flyback converter circuit 30 can receive a pulsating DC voltage VO1 at its input terminal and provide an output voltage V at its output terminal. OUT. The transformer TR includes a primary winding (represented by the number of turns NP), a secondary winding (represented by the number of turns NS) and an auxiliary winding (represented by the number of turns NX), wherein the auxiliary winding NX is arranged on the primary side of the transformer TR, the non-pointed end of the primary winding NP is selectively coupled to the ground potential GND1 via the power switch Q2, and the point-marked end of the secondary winding NS is coupled to the ground potential GND2. The first end of the magnetizing inductor LM2 is coupled to the point-marked end of the primary winding NP in the transformer TR, and the second end is coupled to the non-pointed end of the primary winding NP in the transformer TR. The first end of the power switch Q2 is coupled to the non-pointed end of the primary winding NP in the transformer TR, the second end is coupled to the ground potential GND1, and the control end receives a control signal GD2. The anode of the output diode DO2 is coupled to the non-pointed end of the secondary winding NS in the transformer TR, and the cathode is coupled to the output end (output voltage V OUT ). A first terminal of the energy storage capacitor CO2 is coupled to the cathode of the output diode DO2, and a second terminal thereof is coupled to the ground potential GND2. OUT The first end of the detection resistor Rs is coupled to the second end of the energy storage capacitor CO2, and the second end is coupled to the ground potential GND2, which can store the output current I OUT energy to provide a corresponding detection voltage Vs.

[0077] The pulsating DC voltage VO1 output by the boost active power factor correction circuit 20 is the input voltage of the active clamp flyback conversion circuit 30. The power switch Q2 can perform high-frequency switching according to the control signal GD2 to allow the excitation inductor LM2 to store and release energy. The transformer TR can sense the energy corresponding to the pulsating DC voltage VO1 stored in the primary side winding NP to the secondary side winding NS to provide a pulsating DC voltage VO2. When the output diode DO2 is forward biased, the pulsating DC voltage VO2 can be transmitted to the output end of the power supply 100, and the energy storage capacitor CO2 can store the energy of the secondary side winding NS to supply the output voltage V OUT When the output diode DO2 is not forward biased, the power transmission path of the power supply 100 will be cut off, and the output end of the power supply 100 has no output (V OUT =0V).

[0078] exist Figure 2 In the embodiment shown, the voltage regulator feedback compensation circuit 40 includes a compensation capacitor CC, a feedback capacitor CB, bandwidth limiting inductors LX1-LX2, voltage divider resistors RO1 and RO2, a start-up resistor RP, auxiliary switches Q3-Q4, a linear optocoupler PC, and a voltage regulator TL. The voltage divider resistors RO1 and RO2 are connected in series to the output voltage V OUTand ground potential GND2, a related output voltage V can be established on the voltage divider resistor RO2 OUT A reference voltage V REF , where V REF =V OUT *RO2 / (RO1+RO2). The reference terminal R of the voltage regulator TL is coupled between the voltage dividing resistors RO1 and RO2 to receive the reference voltage V REF , the anode terminal A is coupled to the ground potential GND2, and the cathode terminal K is coupled to the linear optical coupler PC, where V KA represents the voltage between the cathode terminal K and the anode terminal A of the voltage regulator TL. The first terminal of the compensation capacitor CC is coupled to the cathode terminal K of the voltage regulator TL, and the second terminal thereof is coupled to the reference terminal R of the voltage regulator TL. The voltage regulator TL can adjust the compensation current I flowing through the cathode terminal K and the anode terminal A according to the state of the reference terminal R. C In more detail, the voltage regulator TL receives the reference voltage V at its reference terminal R REF When an error occurs, the compensation capacitor CC coupled between the cathode terminal K of the voltage regulator TL and the reference terminal R can adjust the gain of the voltage regulator TL accordingly, so that the compensation current I C The value can reflect the reference voltage V REF The value of the output voltage V OUT The value of .

[0079] The linear optocoupler PC includes a light emitting diode 42 and a photosensitive transistor 44, which can perform electrical-optical-electrical conversion between the primary side and the secondary side of the transformer TR. The light emitting diode 42 is coupled between the first input terminal and the second input terminal of the linear optocoupler PC, and its anode is coupled to the first terminal of the energy storage capacitor CO2 (i.e., coupled to the output voltage V OUT ), and the cathode is coupled to the cathode terminal K of the voltage regulator TL. The phototransistor 44 is coupled between the first output terminal and the second output terminal of the linear optical coupler PC, and its first terminal is coupled to the control circuit 50, and its second terminal is coupled to the feedback capacitor CB. The first terminal of the feedback capacitor CB is coupled to the second terminal of the phototransistor 44, and the second terminal is coupled to the ground potential GND1. Due to the compensation current I flowing through the light emitting diode 42 C Related output voltage V OUT The linear optocoupler PC can use the light emitting diode 42 on the input side to sense the output voltage V OUT The change in the output voltage V OUT The changing amount of electrical energy is converted into light energy, which is then received by the photosensitive transistor 44 on the output side and converted into a feedback current I FB , and then charge the feedback capacitor CB to provide the corresponding feedback voltage V FB .

[0080] The first end of the bandwidth-limiting inductor LX1 is selectively coupled to the first end of the compensation capacitor CC through the auxiliary switch Q3, and the second end thereof is coupled to the second end of the compensation capacitor CC. The first end of the bandwidth-limiting inductor LX2 is selectively coupled to the first end of the bandwidth-limiting inductor LX1 through the auxiliary switch Q4, and the second end thereof is coupled to the second end of the bandwidth-limiting inductor LX1. The first end of the auxiliary switch Q3 is coupled to the first end of the bandwidth-limiting inductor LX1, the second end thereof is coupled to the first end of the compensation capacitor CC, and the control end thereof receives a control signal GD3. The first end of the auxiliary switch Q4 is coupled to the first end of the bandwidth-limiting inductor LX2, the second end thereof is coupled to the first end of the bandwidth-limiting inductor LX1, and the control end thereof receives a control signal GD4.

[0081] By changing the states of the auxiliary switches Q3 and Q4, the present invention can adjust the equivalent capacitance value of the voltage stabilizing feedback compensation loop provided by the voltage stabilizing feedback compensation circuit 40. When the auxiliary switches Q3 and Q4 are both turned off, the connection between the bandwidth limiting inductors LX1 and LX2 and the voltage stabilizing feedback compensation loop is disconnected, and the equivalent capacitance value of the voltage stabilizing feedback compensation loop is only determined by the value of the compensation capacitor CC; when the auxiliary switch Q3 is turned on and the auxiliary switch Q4 is turned off, the bandwidth limiting inductor LX1 is connected in parallel to the compensation capacitor CC, and the equivalent capacitance value of the voltage stabilizing feedback compensation loop is determined by the parallel structure of the compensation capacitor CC and the bandwidth limiting inductor LX1; when the auxiliary switches Q3 and Q4 are both turned on, the bandwidth limiting inductors LX1 and LX2 are connected in parallel to the compensation capacitor CC, and the equivalent capacitance value of the voltage stabilizing feedback compensation loop is determined by the parallel structure of the compensation capacitor CC, the bandwidth limiting inductor LX1, and the bandwidth limiting inductor LX2.

[0082] exist Figure 2 In the illustrated embodiment, the first end of the bandwidth limiting inductor LX1 may be coupled to the first end of the winding NC3 of the coupled inductor LTC in the noise suppression circuit 10, and the second end thereof may be coupled to the second end of the winding NC3; the first end of the bandwidth limiting inductor LX2 may be coupled to the first end of the auxiliary winding NX of the transformer TR in the active clamp flyback converter circuit 30, and the second end thereof may be coupled to the second end of the auxiliary winding NX. In another embodiment, the first end of the bandwidth limiting inductor LX1 may be coupled to the first end of the auxiliary winding NX of the transformer TR in the active clamp flyback converter circuit 30, and the second end thereof may be coupled to the second end of the auxiliary winding NX; the first end of the bandwidth limiting inductor LX2 may be coupled to the first end of the winding NC3 of the coupled inductor LTC in the noise suppression circuit 10, and the second end thereof may be coupled to the second end of the winding NC3.

[0083] exist Figure 2In the illustrated embodiment, the control circuit 50 may be a microcontroller unit (MCU), which includes pins P1 to P6, wherein the pin P1 is used to output a control signal GD1 that switches between a first enable potential and a first disable potential at a high frequency to a control end of the power switch Q1, the pin P2 is used to output a control signal GD2 that switches between a second enable potential and a second disable potential at a high frequency to a control end of the power switch Q2, the pin P3 is used to output a control signal GD3 having a third enable potential or a third disable potential to a control end of the auxiliary switch Q3, the pin P4 is used to output a control signal GD4 having a fourth enable potential or a fourth disable potential to a control end of the auxiliary switch Q4, the pin P5 is coupled to the active clamp flyback converter circuit 30 to receive the detection voltage Vs, and the pin P6 is coupled to the voltage regulation feedback compensation circuit 40 to receive the feedback voltage V FB .

[0084] like Figure 1 and Figure 2 As shown, when the power supply 100 is connected to the mains, the noise suppression circuit 10 can filter out the AC voltage V AC noise in the circuit and provide a processed AC voltage V AC The rectifier 12 of the boost active power factor correction circuit 20 can process the AC voltage V AC 'Converted into DC voltage V IN , and the control circuit 50 outputs a control signal GD1 that switches between the first enable potential and the first disable potential at high frequency to the control end of the power switch Q1 through the pin P1, so that the power switch Q1 can perform high-frequency switching between the on and off states, thereby allowing the boost inductor LM1 to periodically store and release energy to provide a boosted pulsating DC voltage VO1 on the primary side of the transformer TR. Then, the control circuit 50 outputs a control signal GD2 that switches between the second enable potential and the second disable potential at high frequency to the control end of the power switch Q2 through the pin P2, so that the power switch Q2 can perform high-frequency switching between the on and off states, thereby periodically inducing the primary side energy of the transformer TR to the secondary side to provide an output voltage V OUT At the same time, the related output voltage V OUT The output current I OUT The current will flow to the ground potential GND2 through the detection resistor RS and establish a detection voltage VS on the detection resistor RS. The control circuit 50 receives the detection voltage VS through the pin P5 and thus knows the output current I OUT The instantaneous state.

[0085] As described above, the voltage regulator feedback compensation circuit 40 monitors the output voltage V through the voltage divider resistors RO1 and RO2, the feedback capacitor CC / the bandwidth limiting inductor LX1 / the bandwidth limiting inductor LX2, the linear optocoupler PC and the voltage regulator TL. OUT The instantaneous state of the FB The control circuit 50 receives the feedback voltage V through the pin P6. FB , and then the feedback voltage V FB The duty cycle of the control signal GD2 is adjusted by pulse width modulation to achieve a stable output voltage V OUT function.

[0086] In the present invention, the active clamp flyback converter circuit 30 will drive the load (not shown) according to the Figure 1 and Figure 2 )The required output current I OUT The instantaneous current value is used to switch its operation mode, and the detection voltage Vs can reflect the output current I OUT The instantaneous current value (Vs = I OUT *Rs). In the present invention, the control circuit 50 provides control signals GD3 and GD4 according to the current operation mode of the active clamp flyback converter circuit 30, and then adjusts the equivalent capacitance of the voltage regulation feedback loop for different output loads to provide a corresponding voltage regulation feedback compensation bandwidth. For the purpose of illustration, it is assumed that the active clamp flyback converter circuit 30 of the present invention can operate in three modes: continuous conduction mode (CCM), quasi resonant mode (QRM) and burst mode (BRM).

[0087] Figure 3A FIG. 1 is a schematic diagram of related signals when the active clamp flyback converter circuit 30 operates in the continuous conduction mode according to an embodiment of the present invention. Figure 3A In the waveform diagram shown above, the vertical axis shows the control signal GD2 of the power switch Q2, and the horizontal axis represents time. Figure 3A In the waveform diagram below, the vertical axis shows the current I flowing through the magnetizing inductor. LM2 , and the horizontal axis represents time. When the instantaneous output load of the power supply 100 is at its maximum load I OMAX Under the condition of 75%-100% of the above, the active clamp flyback converter circuit 30 needs to operate in the continuous conduction mode to provide an output voltage V with a larger average energy. OUT In continuous conduction mode, the current I flowing through the magnetizing inductor is LM2It will continue to operate in a state greater than zero, and the switching frequency of the power switch Q2 is designed to be a larger 120K-165KHz.

[0088] Figure 3B FIG. 1 is a schematic diagram of related signals when the active clamp flyback converter circuit 30 operates in the quasi-resonant mode in an embodiment of the present invention. Figure 3B In the waveform diagram shown above, the vertical axis shows the control signal GD2 of the power switch Q2, and the horizontal axis represents time. Figure 3B In the waveform diagram shown below, the vertical axis shows the voltage VDS of the power switch Q2 (the voltage difference between the first terminal and the second terminal of the power switch Q2), and the horizontal axis represents time. OMAX Under the condition of 15%-75% of the power supply voltage, the active clamp flyback converter circuit 30 operates in the quasi-resonant mode to improve the overall power conversion efficiency. In the quasi-resonant mode, the power switch Q2 can achieve flexible switching of zero voltage conduction, and its switching frequency is designed to be 65K-100KHz.

[0089] Figure 3C FIG. 1 is a schematic diagram of related signals when the active clamp flyback converter circuit 30 operates in the burst mode according to an embodiment of the present invention. Figure 3C In the waveform diagram shown above, the vertical axis shows the control signal GD2 of the power switch Q2 in normal mode, and the horizontal axis represents time. Figure 3C In the waveform diagram shown below, the vertical axis shows the control signal GD2' of the power switch Q2 in the burst mode, and the horizontal axis represents time. OMAX When the active clamp flyback converter circuit 30 is less than 15% of the switching loss, the active clamp flyback converter circuit 30 will operate in the burst mode to reduce switching loss and meet the light load power consumption requirements of energy efficiency. In the burst mode, the power switch Q2 will not switch in every cycle and reduce the switching duty cycle. Its switching frequency is designed to be less than 15KHz.

[0090] Figure 4A-4C Schematic diagram of an equivalent circuit of the voltage stabilizing feedback compensation circuit 40 of the power converter 100 in different operation modes according to an embodiment of the present invention. Figure 5 FIG. 1 is a schematic diagram of the voltage regulation compensation bandwidth range provided by the power converter 100 for different operation modes according to an embodiment of the present invention.

[0091] When the active clamp flyback converter circuit 30 operates in the continuous conduction mode, the switching frequency of the power switch Q2 is the largest, so the required compensation bandwidth range is also relatively the largest. When the control circuit 50 determines that the active clamp flyback converter circuit 30 is currently operating in the continuous conduction mode based on the detection voltage Vs received by its pin P5, it will output a control signal GD3 with a third disable potential through its pin P3 and a control signal GD4 with a fourth disable potential through its pin P4 to turn off the auxiliary switches Q3 and Q4. In this case, the voltage regulation compensation path provided by the voltage regulation feedback compensation circuit 40 only includes a single compensation capacitor CC (such as Figure 4A As shown), that is, the equivalent capacitance value of the voltage regulation feedback compensation loop can be adjusted to the maximum value, thereby providing the maximum compensation bandwidth range BW1 (as shown Figure 5 shown).

[0092] When the active clamp flyback converter circuit 30 operates in the burst mode, the switching frequency of the power switch Q2 is the smallest, so the required compensation bandwidth range is relatively the smallest. When the control circuit 50 determines that the active clamp flyback converter circuit 30 is currently operating in the burst mode based on the detection voltage Vs received by its pin P5, it will output a control signal GD3 with a third enable potential through its pin P3 to turn on the auxiliary switch Q3, and output a control signal GD4 with a fourth disable potential through its pin P4 to turn off the auxiliary switch Q4. In this case, the voltage regulation compensation path provided by the voltage regulation feedback compensation circuit 40 will include a parallel combination of the compensation capacitor CC and the bandwidth limiting inductor LX1, such as Figure 4C The bandwidth-limiting inductor LX1 can offset the effect of the compensation capacitor CC, that is, it can adjust the equivalent capacitance value of the voltage-stabilizing feedback compensation loop to the minimum value, thereby providing a minimum compensation bandwidth range BW3, as shown in FIG. Figure 5 shown.

[0093] When the active clamp flyback converter circuit 30 operates in the quasi-resonant mode, the switching frequency of the power switch Q2 operates in the middle region, so the required compensation bandwidth range can also be designed to the middle region. When the control circuit 50 determines that the active clamp flyback converter circuit 30 is currently operating in the quasi-resonant mode based on the detection voltage Vs received by its pin P5, it will output a control signal GD3 with a third enable potential through its pin P3 and a control signal GD4 with a fourth enable potential through its pin P4 to simultaneously turn on the auxiliary switches Q3 and Q4. In this case, the voltage regulation compensation path provided by the voltage regulation feedback compensation circuit 40 will include a parallel combination of the compensation capacitor CC, the bandwidth limiting inductor LX1 and the bandwidth limiting inductor LX2, such as Figure 4BAs is known to those with common knowledge in the relevant field, when two sets of inductors are connected in parallel, their total inductance value will decrease. Therefore, the parallel limited bandwidth inductors LX1 and LX2 can offset the effect of the compensation capacitor CC to a lesser extent, that is, the equivalent capacitance value of the voltage regulation feedback compensation loop can be adjusted to an intermediate value, thereby providing an intermediate compensation bandwidth range BW2 between the maximum compensation bandwidth range BW1 and the minimum compensation bandwidth range BW3, as shown in FIG. Figure 5 shown.

[0094] In the embodiment of the present invention, the power switches Q1-Q2 and the auxiliary switches Q3-Q4 may be metal-oxide-semiconductor field-effect transistors (MOSFET), bipolar junction transistors (BJT), or other elements with similar functions. For N-type transistors, the enable potential is a high potential, while the disable potential is a low potential; for P-type transistors, the enable potential is a low potential, while the disable potential is a high potential. However, the types of the power switches Q1-Q2 and the auxiliary switches Q3-Q4 do not limit the scope of the present invention.

[0095] In summary, in the power supply 100 of the present invention, the boost type active power factor correction circuit 20 can improve the power factor of the AC power supply end, the buck type active clamp flyback conversion circuit 30 can convert the voltage output by the boost type active power factor correction circuit 20 into the output voltage required for the operation of the load device, and the voltage stabilization feedback compensation circuit 40 can provide voltage stabilization feedback compensation for the output voltage. The active clamp flyback conversion circuit 30 switches its operation mode according to the instantaneous output load of the power supply 100, and the control circuit 50 controls the operation of the voltage stabilization feedback compensation circuit 40 according to the current operation mode of the active clamp flyback conversion circuit 30, thereby adjusting the equivalent capacitance of the voltage stabilization feedback loop according to different output loads to provide a corresponding voltage stabilization feedback compensation bandwidth range, so that low loss optimization can be achieved in different modes.

[0096] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A power supply with adaptive adjustment of voltage regulation compensation bandwidth, used to convert an AC voltage into an output voltage to supply power to a load device, comprising: a noise suppression circuit for filtering out noise in the AC voltage to provide a processed AC voltage; a boost type active power factor correction circuit, used for converting the processed AC voltage into a DC voltage, and then converting the DC voltage into a first pulsating DC voltage; an active clamp flyback converter circuit, used for converting the first pulsating DC voltage into the output voltage and providing a detection voltage related to the output voltage; a voltage stabilization feedback compensation circuit, used for selectively performing voltage stabilization feedback compensation on the output voltage with a first voltage stabilization feedback compensation bandwidth range or a second voltage stabilization feedback compensation bandwidth range; and A control circuit for: Outputting a first control signal that periodically switches between a first enabling potential and a first disabling potential to control the operation of the boost type active power factor correction circuit; Outputting a second control signal that periodically switches between a second enabling potential and a second disabling potential to control the operation of the active clamp flyback converter circuit; Determining a current operation mode of the active clamp flyback converter circuit according to the detection voltage; When it is determined according to the detection voltage that the active clamp flyback converter circuit operates in a first mode, controlling the voltage regulation feedback compensation circuit to perform voltage regulation feedback compensation on the output voltage within the first voltage regulation feedback compensation bandwidth range; and When it is determined according to the detection voltage that the active clamp flyback converter circuit operates in a second mode, the voltage regulation feedback compensation circuit is controlled to perform voltage regulation feedback compensation on the output voltage within the second voltage regulation feedback compensation bandwidth range, wherein: A first instantaneous output load of the power supply when the active clamp flyback converter circuit operates in the first mode is greater than a second instantaneous output load of the power supply when the active clamp flyback converter circuit operates in the second mode; and The first voltage regulation feedback compensation bandwidth range is greater than the second voltage regulation feedback compensation bandwidth range.

2. The power supply as claimed in claim 1, wherein the boost type active power factor correction circuit comprises: a rectifier, used to convert the processed AC voltage into the DC voltage; A boost inductor comprising: a first terminal coupled to the rectifier to receive the DC voltage; and a second end; A boost diode comprising: an anode coupled to the second end of the boost inductor; and a cathode coupled to the first pulsating DC voltage; a first energy storage capacitor, used to store energy of the first pulsating DC voltage, comprising: a first terminal coupled to the first pulsating DC voltage; and a second terminal coupled to a first ground potential; and A first power switch, comprising: a first terminal coupled between the second terminal of the boost inductor and the anode of the boost diode; a second terminal coupled to the first ground potential; and A control terminal is coupled to the control circuit to receive the first control signal.

3. The power supply as claimed in claim 1, wherein: The voltage stabilization feedback compensation circuit includes: A voltage stabilizer comprising a cathode terminal, an anode terminal and a reference terminal, for receiving a reference voltage related to the output voltage through the reference terminal and adjusting a compensation current flowing through the cathode terminal and the anode terminal according to a state of the reference voltage; A linear optical coupler, used to sense the variation of the compensation current, and convert an electrical energy related to the variation of the compensation current into a light energy, and then convert the light energy into a feedback current; a feedback capacitor for storing energy of the feedback current to provide a feedback voltage to the control circuit; A compensation capacitor, used to adjust the gain of the regulator, comprising: a first terminal coupled to the cathode terminal of the regulator; and A second terminal coupled to the reference terminal of the regulator; A first bandwidth limiting inductor, comprising: a first end; and a second terminal coupled to the second terminal of the compensation capacitor; and A first auxiliary switch, comprising: A first end coupled to the first end of the first bandwidth limiting inductor; a second terminal coupled to the first terminal of the compensation capacitor; and a control terminal, used to receive a third control signal; and The control circuit is also used to: When it is determined according to the detection voltage that the active clamp flyback converter circuit operates in the first mode, outputting the third control signal having a third disable potential to turn off the first auxiliary switch; as well as When it is determined according to the detection voltage that the active clamp flyback converter circuit operates in the second mode, the third control signal with a third enabling potential is output to turn on the first auxiliary switch so that the first bandwidth limiting inductor is connected in parallel with the compensation capacitor.

4. The power supply as claimed in claim 3, wherein the active clamp flyback conversion circuit comprises: A transformer, used for inducing the energy of the first pulsating DC voltage from a primary side to a secondary side to provide a second pulsating DC voltage, comprising: A primary side winding, disposed on the primary side, comprising a first striking end and a first non-strike end; and A secondary side winding is arranged on the secondary side, and includes a second dotted end and a second non-dotted end; an auxiliary winding, disposed on the primary side, with a first end coupled to the first end of the first bandwidth-limiting inductor, and a second end coupled to the second end of the first bandwidth-limiting inductor; A magnetizing inductor, comprising: A first end coupled to the first dot end; and A second terminal coupled to the first non-dot terminal; a second power switch, comprising: A first terminal coupled to the first non-dot terminal; a second terminal coupled to a first ground potential; and A control terminal, used for receiving the second control signal; a second energy storage capacitor, used for storing energy of the second pulsating DC voltage to supply the output voltage, comprising a first terminal and a second terminal; An output diode comprising: an anode coupled to the second non-dot terminal; and a cathode coupled to the first end of the second energy storage capacitor; and A detection resistor is coupled between the second end of the second energy storage capacitor and a second ground potential, and is used for providing the detection voltage related to the output voltage.

5. The power supply as claimed in claim 3, wherein the noise suppression circuit comprises: A first input terminal and a second input terminal, for receiving the AC voltage; a first output terminal and a second output terminal, used to output the processed AC voltage; An X capacitor, which includes: a first terminal coupled to the first input terminal; and a second terminal coupled to the second input terminal; A first Y capacitor, comprising: a first terminal coupled to the first output terminal; and A second terminal coupled to a ground terminal; A second Y capacitor comprising: a first terminal coupled to the second output terminal; and A second terminal coupled to the ground terminal; A first common mode inductor, comprising: a first terminal coupled to the first input terminal; and a second terminal coupled to the first output terminal; a second common mode inductor, comprising: a first terminal coupled to the second input terminal; and a second terminal coupled to the second output terminal; and A coupled inductor comprising: A first winding, disposed on a first side of the coupled inductor and connected in parallel to the first common mode inductor; a second winding, disposed on a second side of the coupled inductor and connected in parallel to the second common mode inductor; and A third winding is disposed on the first side of the coupled inductor and is connected in parallel to the first bandwidth limiting inductor.

6. The power supply as claimed in claim 3, wherein: The voltage stabilization feedback compensation circuit is further used to selectively perform voltage stabilization feedback compensation on the output voltage in a third voltage stabilization feedback compensation bandwidth range, and further comprises: A second bandwidth limiting inductor, comprising: a first end; and a second end coupled to the second end of the first bandwidth limiting inductor; and A second auxiliary switch, comprising: A first end coupled to the first end of the second bandwidth limiting inductor; a second end coupled to the first end of the first bandwidth limiting inductor; and a control terminal, used for receiving a fourth control signal; The control circuit is also used to: When it is determined according to the detection voltage that the active clamp flyback converter circuit operates in a third mode, the third control signal having the third enabling potential is output to turn on the first auxiliary switch, and the fourth control signal having a fourth enabling potential is output to turn on the second auxiliary switch, so that the first bandwidth limiting inductor and the second bandwidth limiting inductor are connected in parallel to the compensation capacitor; When the active clamp flyback converter circuit operates in the third mode, a third instantaneous output load of the power supply is greater than the second instantaneous output load and less than the first instantaneous output load; and The third voltage regulation feedback compensation bandwidth range is smaller than the first voltage regulation feedback compensation bandwidth range and larger than the second voltage regulation feedback compensation bandwidth range.

7. The power supply as claimed in claim 6, wherein: The active clamp flyback converter circuit comprises: A transformer, used for inducing the energy of the first pulsating DC voltage from a primary side to a secondary side to provide a second pulsating DC voltage, comprising: A primary side winding, arranged on the primary side, comprising a first striking end and a first non-strike end; A secondary side winding is arranged on the secondary side, and includes a second dotted end and a second non-dotted end; as well as an auxiliary winding, disposed on the primary side, with a first end coupled to the first end of the first bandwidth-limiting inductor, and a second end coupled to the second end of the first bandwidth-limiting inductor; A magnetizing inductor, comprising: A first end coupled to the first dot end; and A second terminal coupled to the first non-dot terminal; a second power switch, comprising: A first terminal coupled to the first non-dot terminal; A second terminal coupled to a first ground potential; as well as A control terminal, used for receiving the second control signal; A second energy storage capacitor, used for storing the energy of the second pulsating DC voltage to supply the output voltage, comprising a first terminal and a second terminal: An output diode comprising: an anode coupled to the second non-dot terminal; and a cathode coupled to the first end of the second energy storage capacitor; and a detection resistor, coupled between the second end of the second energy storage capacitor and a second ground potential, for providing the detection voltage related to the output voltage; and The noise suppression circuit includes: A first input terminal and a second input terminal, for receiving the AC voltage; a first output terminal and a second output terminal, used to output the processed AC voltage; An X capacitor, which includes: a first terminal coupled to the first input terminal; and a second terminal coupled to the second input terminal; A first Y capacitor, comprising: a first terminal coupled to the first output terminal; and A second terminal coupled to a ground terminal; A second Y capacitor comprising: a first terminal coupled to the second output terminal; and A second terminal coupled to the ground terminal; A first common mode inductor, comprising: a first terminal coupled to the first input terminal; and a second terminal coupled to the first output terminal; a second common mode inductor, comprising: a first terminal coupled to the second input terminal; and a second terminal coupled to the second output terminal; and A coupled inductor comprising: A first winding, disposed on a first side of the coupled inductor and connected in parallel to the first common mode inductor; a second winding, disposed on a second side of the coupled inductor and connected in parallel to the second common mode inductor; as well as A third winding is disposed on the first side of the coupled inductor and is connected in parallel to the second bandwidth-limited inductor.

8. The power supply according to claim 5 or 7, wherein: The noise suppression circuit is used to filter out a differential mode noise or a common mode noise in the AC voltage; The differential mode noise is the voltage noise between the first input terminal and the second input terminal; and The common mode noise is voltage noise transmitted to the ground terminal through the first input terminal or the second input terminal.

9. The power supply as claimed in claim 3, wherein the voltage stabilization feedback compensation circuit further comprises: A first voltage-dividing resistor, comprising: a first terminal coupled to the output voltage; and a second terminal, used for outputting the reference voltage; and A second voltage-dividing resistor, comprising: a first end coupled to the second end of the first voltage-dividing resistor; and A second terminal is coupled to the anode terminal of the regulator. 10 . The power supply as claimed in claim 3 , wherein the control circuit is further configured to adjust a duty cycle of the second control signal according to a value of the feedback voltage.

Images