Self-adaptive on-time circuit of DC-DC in PFM (Pulse Frequency Modulation) mode

Abstract

The invention relates to a self-adaptive on-time circuit of DC-DC in a PFM mode, and relates to the field of integrated circuits. According to the technical scheme, a current linearly related to an input voltage is generated through a current generation circuit, the current is mirrored to a self-adaptive voltage generation circuit, the self-adaptive voltage generation circuit is switched between a heavy-load mode and a light-load mode through enable signals EN2 and EN3, a small capacitor is used for charging in the heavy-load mode, a large capacitor is used for charging in the light-load mode, and the self-adaptive voltage generation circuit is switched between the light-load mode and the heavy-load mode. Different capacitance values are selected through the comparator according to different output voltages, and when charging reaches a set voltage value, the conduction time generating circuit works to output conduction time, so that the conduction time can be adaptively changed according to the change of the input voltage and different load modes, the loss caused by the change of the input voltage is reduced, and the efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an adaptive on-time circuit of a DC-DC in a PFM mode. Background Art

[0002] In electronic devices, each module circuit has different requirements for the power supply voltage, and a single battery cannot directly meet these diverse needs. Therefore, the power management system (PMS) has become the key to solving this problem. PMS can convert the original voltage provided by the battery into the stable voltage value required by each module to ensure that each circuit can obtain appropriate power support. As one of the core components of the power management chip, the DC-DC switching power supply stands out with its low power consumption, small size and high conversion efficiency compared to the traditional linear regulator (LDO) and charge pump DC / DC converter, and has become the mainstream choice in modern power management solutions. Especially in the application scenarios with a wide input voltage range and high current output, the advantages of DC-DC switching power supplies are more obvious. In addition, DC-DC switching power supplies support multiple modulation modes, such as PWM (pulse width modulation), PFM (pulse frequency modulation) and a hybrid mode of the two, to adapt to different load conditions and optimize the overall performance of the system.

[0003] The PFM mode is particularly suitable for light load conditions because it can significantly improve efficiency and speed up response when the load is small. However, in practical applications, the traditional constant on-time PFM has an obvious limitation: when the input voltage changes, the switching frequency also changes, which leads to a decrease in efficiency. To overcome this problem, adaptive on-time PFM was proposed and applied in practice. Unlike conventional constant on-time circuits, adaptive on-time PFM can dynamically adjust the on-time according to the input voltage, thereby avoiding the efficiency loss caused by frequency changes and further improving the system's operating efficiency. Specifically, please refer to Figure 2 , the conventional constant on-time circuit generates a voltage by charging the capacitor C with a fixed current I1, and compares it with the reference voltage VREF during the conduction phase of the DC-DC through the switch S0 to determine the fixed on-time. However, this method will bring certain switching losses under all working conditions, thus affecting the efficiency of the entire circuit. In contrast, the adaptive on-time PFM is more flexible and efficient. It can intelligently adjust the on-time according to the actual input voltage level to ensure the optimal conversion efficiency in the entire operating range. Summary of the invention

[0004] The object of the present invention is to provide an adaptive on-time circuit for a DC-DC in a PFM mode to solve the problems existing in the above-mentioned prior art.

[0005] To achieve the above object, the technical solution adopted by the present invention is: An adaptive on-time circuit of a DC-DC in a PFM mode, comprising: a current generating circuit, an adaptive voltage generating circuit connected to the current generating circuit, and an on-time generating circuit connected to the adaptive voltage generating circuit; Among them, the current generating circuit generates a current I1 proportional to the input voltage VIN through the Gm amplifier and inputs it into the adaptive voltage generating circuit. The adaptive voltage generating circuit selects the corresponding capacitor to participate in the work according to the load condition. The on-time generating circuit generates an adaptive on-time that follows the input voltage VIN and the load changes to achieve dynamic adjustment of the on-time.

[0006] In a possible implementation, the current generating circuit includes: A resistor R1, a first end of which is connected to an input voltage VIN; An NMOS tube M1, whose drain is connected to the second end of the resistor R1, and whose gate is connected to the enable signal EN1; A resistor R2, a first end of which is connected to the source of the NMOS transistor M1; and a resistor R3, a first end of which is connected to the second end of the resistor R2, and a second end of which is connected to GND; The input end of the Gm amplifier is connected between the second end of the resistor R2 and the first end of the resistor R3 , and the output end of the Gm amplifier inputs the current I1 to the adaptive voltage generating circuit.

[0007] In a possible implementation, when the enable signal EN1 is GND, the current generating circuit does not work; When the enable signal EN1 is VDD, the current generating circuit works normally, and the current I1 is proportional to the input voltage VIN through the resistor R1 , the resistor R2 , the resistor R3 and the Gm amplifier.

[0008] In a possible implementation, the adaptive voltage generating circuit includes: NMOS tube M2, whose drain and gate are connected to the output end of the Gm amplifier, and whose source is connected to GND; An NMOS tube M3, whose gate is connected to the output end of the Gm amplifier and whose source is connected to GND; A PMOS tube M4, whose drain and gate are connected to the drain of the NMOS tube M3, and whose source is connected to VDD; A PMOS transistor M5, whose gate is connected to the drain of the NMOS transistor M3, whose source is connected to VDD, whose drain is connected to the first end of the capacitor C1, and whose second end is connected to GND; An NMOS transistor M6, whose drain is connected to the drain of the PMOS transistor M5, whose source is connected to the first end of the capacitor C2, and whose second end is connected to GND; An NMOS transistor M7, whose drain is connected to the drain of the PMOS transistor M5, whose source is connected to the first end of the capacitor C3, and whose second end is connected to GND; An NMOS tube M8, whose drain is connected to the drain of the PMOS tube M5, whose source is connected to the first end of the capacitor C4, and whose second end is connected to GND; An NMOS tube M9, whose drain is connected to the drain of the PMOS tube M5, whose source is connected to the first end of the capacitor C5, and whose second end is connected to GND; A first comparator, whose inverting input terminal is connected to the output voltage Vout, whose non-inverting input terminal is connected to the voltage Vref1, and whose output terminal is connected to the gate of the NMOS tube M9; A second comparator, whose inverting input terminal is connected to the output voltage Vout, whose non-inverting input terminal is connected to the voltage Vref2, and whose output terminal is connected to the gate of the NMOS tube M8; A third comparator, whose inverting input terminal is connected to the output voltage Vout, whose non-inverting input terminal is connected to the voltage Vref3, and whose output terminal is connected to the gate of the NMOS tube M7; A fourth comparator, whose inverting input terminal is connected to the output voltage Vout, whose non-inverting input terminal is connected to the voltage Vref4, and whose output terminal is connected to the gate of the NMOS tube M6; An NMOS transistor M10, whose drain is connected to the source of the NMOS transistor M6, whose source is connected to the second end of the capacitor C2, and whose gate is connected to the enable signal EN2; An NMOS transistor M11, whose drain is connected to the source of the NMOS transistor M7, whose source is connected to the second end of the capacitor C3, and whose gate is connected to the enable signal EN2; An NMOS transistor M12, whose drain is connected to the source of the NMOS transistor M8, whose source is connected to the second end of the capacitor C4, and whose gate is connected to the enable signal EN2; and An NMOS transistor M13, whose drain is connected to the source of the NMOS transistor M9, whose source is connected to the second end of the capacitor C5, and whose gate is connected to the enable signal EN2; Wherein, the drain of the PMOS tube M5 is connected to the on-time generating circuit.

[0009] In a possible implementation, when the load is under heavy load, the enable signal EN2 is VDD, the enable signal EN3 is GND, and only the capacitor C1 is charged; When the load is light, the enable signal EN2 is GND, the enable signal EN3 is VDD, and the corresponding capacitor is selected to be turned on by comparing the output voltage Vout with different voltages Vref, so that an adaptive turn-on voltage proportional to the input voltage VIN is output.

[0010] In a possible implementation, the on-time generating circuit includes: a fifth comparator, whose non-inverting input terminal is connected to the voltage SW and the first end of the switch S1, and whose inverting input terminal is connected to the voltage VREF and the first end of the switch S0; and A sixth comparator, whose non-inverting input terminal is connected to the drain of the PMOS tube M5, whose inverting input terminal is connected to the switch S0 and the second end of the switch S1, and whose output terminal is the time Ton when the output pulse signal changes from low to high; The level detection end of the switch S0 is connected to the output end of the fifth comparator and the input end of the inverter, and the level detection end of the switch S1 is connected to the output end of the inverter.

[0011] In a possible implementation, it is characterized in that: When the switch S0 is at a high level, the switch S0 is closed; When the switch S1 is at a high level, the switch S1 is closed; The inverter is used to generate a delay in the DC-DC freewheeling conduction, thereby ensuring the generation of the on-time, and then outputting the adaptive on-time by comparing the adaptive on-voltage with the voltage VREF.

[0012] The beneficial effects brought about by the technical solution provided by the present invention include at least: The technical solution generates a current linearly related to the input voltage through a current generating circuit, and transmits the current to an adaptive voltage generating circuit through a current mirror. The adaptive voltage generating circuit switches between heavy load and light load modes through enable signals EN2 and EN3. In heavy load mode, a small capacitor is used for charging, and in light load mode, a large capacitor is used for charging. Different capacitance values ​​are selected according to different output voltages through a comparator. When the charging reaches the set voltage value, the on-time generating circuit works to output the on-time. Therefore, the on-time can be adaptively changed according to the change of input voltage and different load modes, thereby reducing the loss caused by the change of input voltage and improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0014] Figure 1 A schematic diagram of an adaptive on-time circuit of a DC-DC in a PFM mode provided by an exemplary embodiment of the present invention is shown.

[0015] Figure 2 A conventional constant on-time circuit schematic diagram provided by an exemplary embodiment of the present invention is shown.

[0016] In the figure: 1. Current generating circuit; 2. Adaptive voltage generating circuit; 3. On-time generating circuit; 21. a first comparator; 22. a second comparator; 23. a third comparator; 24. a fourth comparator; 31. Fifth comparator; 32. Sixth comparator; 33. Inverter. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0019] Figure 1 A schematic diagram of an adaptive on-time circuit of a DC-DC in a PFM mode provided by an exemplary embodiment of the present invention is shown. The adaptive on-time circuit of the DC-DC in the PFM mode comprises: a current generating circuit 1, an adaptive voltage generating circuit 2 connected to the current generating circuit 1, and an on-time generating circuit 3 connected to the adaptive voltage generating circuit 2; wherein the current generating circuit 1 generates a current I1 proportional to the input voltage VIN through a Gm amplifier and inputs the current I1 to the adaptive voltage generating circuit 2, the adaptive voltage generating circuit 2 selects a corresponding capacitor to participate in the operation according to the load condition, and the on-time generating circuit 3 generates an adaptive on-time that follows the input voltage VIN and the load changes, so as to realize dynamic adjustment of the on-time.

[0020] In an embodiment of the present application, after the adaptive voltage generating circuit 2 receives the current I1 from the current generating circuit 1, it dynamically selects an appropriate capacitor to participate in the work according to the current load condition to ensure that the output voltage is stable and responds to load changes. For example, under heavy load conditions, only a smaller capacitor participates in the work to provide a shorter on-time; under light load conditions, a larger or more capacitor may be added to extend the on-time, thereby achieving precise control of the on-time. This mechanism helps to reduce unnecessary switching actions, especially under light load or no-load conditions, thereby reducing switching losses and improving system efficiency. Finally, the on-time generating circuit 3 is based on the feedback of the comparator, and according to the working mode selected by the adaptive voltage generating circuit 2 and the actual needs of the load, it adjusts and generates an adaptive on-time that follows the input voltage VIN and the load changes. This means that whether it is under light load or heavy load conditions, the on-time can change with the change of the input voltage, ensuring the flexibility and efficiency of the system. In addition, this method can also effectively reduce ripple, improve output voltage accuracy, and further improve the overall power management performance.

[0021] In detail, the current generating circuit 1 includes: a resistor R1, an NMOS tube M1, a resistor R2, and a resistor R3, wherein the first end of the resistor R1 is connected to the input voltage VIN; the drain of the NMOS tube M1 is connected to the second end of the resistor R1, and the gate thereof is connected to the enable signal EN1; the first end of the resistor R2 is connected to the source of the NMOS tube M1; the first end of the resistor R3 is connected to the second end of the resistor R2, and the second end thereof is connected to GND; wherein the input end of the Gm amplifier is connected between the second end of the resistor R2 and the first end of the resistor R3, and the output end of the Gm amplifier inputs the current I1 to the adaptive voltage generating circuit 2. When the enable signal EN1 is GND, the current generating circuit 1 does not work; when the enable signal EN1 is VDD, the current generating circuit 1 works normally, and the current I1 is proportional to the input voltage VIN through the resistor R1, the resistor R2, the resistor R3, and the Gm amplifier.

[0022] In an embodiment of the present application, in the PFM mode, the adaptive on-time circuit design of the DC-DC converter is intended to optimize the efficiency and performance under different load conditions. The current generating circuit 1 generates a current I1 proportional to the input voltage VIN through the Gm amplifier, and inputs it into the adaptive voltage generating circuit 2. This process begins with the first end of the resistor R1 being connected to the input voltage VIN, and the drain of the NMOS tube M1 being connected to the second end of the resistor R1, and its gate being controlled by the enable signal EN1. When EN1 is low (GND), M1 is turned off and the current generating circuit does not work; when EN1 is high (VDD), M1 is turned on, and the current I1 begins to flow and forms a voltage divider network through resistors R2 and R3, and is finally output through the Gm amplifier.

[0023] Specifically, the adaptive voltage generating circuit 2 includes: an NMOS tube M2, an NMOS tube M3, a PMOS tube M4, a PMOS tube M5, an NMOS tube M6, an NMOS tube M7, an NMOS tube M8, an NMOS tube M9, a first comparator 21, a second comparator 22, a third comparator 23, a fourth comparator 24, an NMOS tube M10, an NMOS tube M11, an NMOS tube M12, and an NMOS tube M13. The drain and gate of the NMOS tube M2 are connected to the output end of the Gm amplifier, and the source thereof is connected to GND; the gate of the NMOS tube M3 is connected to the output end of the Gm amplifier, and the source thereof is connected to GND; the drain and gate of the PMOS tube M4 are connected to the drain of the NMOS tube M3. The gate of the PMOS tube M5 is connected to the drain of the NMOS tube M3, the source of the PMOS tube M5 is connected to VDD, the drain of the PMOS tube M5 is connected to the first end of the capacitor C1, and the second end of the capacitor C1 is connected to GND; the drain of the NMOS tube M6 is connected to the drain of the PMOS tube M5, the source of the NMOS tube M6 is connected to the first end of the capacitor C2, and the second end of the capacitor C2 is connected to GND; the drain of the NMOS tube M7 is connected to the drain of the PMOS tube M5, the source of the NMOS tube M7 is connected to the first end of the capacitor C3, and the second end of the capacitor C3 is connected to GND; the drain of the NMOS tube M8 is connected to the drain of the PMOS tube M5, the source of the NMOS tube M8 is connected to the first end of the capacitor C4, and the second end of the capacitor C4 is connected to GND; the drain of the NMOS tube M9 is connected to The drain of the PMOS tube M5 is connected, and its source is connected to the first end of the capacitor C5, and the second end of the capacitor C5 is connected to GND; the inverting input terminal of the first comparator 21 is connected to the output voltage Vout, the in-phase input terminal thereof is connected to the voltage Vref1, and the output terminal thereof is connected to the gate of the NMOS tube M9; the inverting input terminal of the second comparator 22 is connected to the output voltage Vout, the in-phase input terminal thereof is connected to the voltage Vref2, and the output terminal thereof is connected to the gate of the NMOS tube M8; the inverting input terminal of the third comparator 23 is connected to the output voltage Vout, the in-phase input terminal thereof is connected to the voltage Vref3, and the output terminal thereof is connected to the gate of the NMOS tube M7; the inverting input terminal of the fourth comparator 24 is connected to the output voltage Vout, and the in-phase input terminal thereof is connected to the voltage Vref1, and the output terminal thereof is connected to the gate of the NMOS tube M8; The non-inverting input terminal is connected to the voltage Vref4, and the output terminal is connected to the gate of the NMOS tube M6; the drain of the NMOS tube M10 is connected to the source of the NMOS tube M6, the source of the NMOS tube M10 is connected to the second end of the capacitor C2, and the gate of the NMOS tube M10 is connected to the enable signal EN2; the drain of the NMOS tube M11 is connected to the source of the NMOS tube M7, the source of the NMOS tube M10 is connected to the second end of the capacitor C3, and the gate of the NMOS tube M10 is connected to the enable signal EN2; the drain of the NMOS tube M12 is connected to the source of the NMOS tube M8, the source of the NMOS tube M10 is connected to the second end of the capacitor C4, and the gate of the NMOS tube M10 is connected to the enable signal EN2; the drain of the NMOS tube M13 is connected to the source of the NMOS tube M9, the source of the NMOS tube M10 is connected to the second end of the capacitor C5, and the gate of the NMOS tube M10 is connected to the enable signal EN2;The drain of the PMOS tube M5 is connected to the on-time generating circuit 3. When the load is under heavy load, the enable signal EN2 is VDD, the enable signal EN3 is GND, and only the capacitor C1 is charged; when the load is under light load, the enable signal EN2 is GND, the enable signal EN3 is VDD, and the corresponding capacitor is selected to be turned on by comparing the output voltage Vout with different voltages Vref, so that an adaptive on-voltage proportional to the input voltage VIN is output. ;

[0024] In an embodiment of the present application, the design of the adaptive voltage generating circuit 2 is intended to dynamically select a suitable capacitor to participate in the work according to the load conditions, so as to generate an adaptive on-time that follows the input voltage VIN. This process is completed through a series of NMOS and PMOS tubes and multiple comparators to ensure the stability and response speed of the output voltage. As part of the current mirror, the NMOS tubes M2 and M3 work together with the Gm amplifier to generate a current I1 that is proportional to the input voltage VIN. Here, the drain and gate of the NMOS tube M2 are connected to the output of the Gm amplifier, and its source is grounded, while the gate of the NMOS tube M3 is also connected to the output of the Gm amplifier, but its source is also grounded. This configuration ensures that the current I1 can accurately reflect the changes in the input voltage. PMOS tubes M4 and M5 form a current source, in which the drain and gate of PMOS tube M4 are connected to the drain of NMOS tube M3, and its source is connected to VDD; PMOS tube M5 passes the signal from M3 to the subsequent circuit, that is, its gate is connected to the drain of M3, the source is connected to VDD, and the drain is connected to one end of each capacitor C1-C5. This provides the necessary bias conditions for subsequent selective charging. Capacitors C1 to C5 are key components, which are activated or deactivated under different load conditions to adjust the on-time. When the load is heavy, only capacitor C1 is involved in the work because it is directly controlled by PMOS tube M5. In the case of light load, more capacitors (such as C2 to C5) can be activated by enabling signals EN2 (set to GND) and EN3 (set to VDD), and the selection of these capacitors depends on the comparison between the output voltage Vout and the reference voltages Vref1 to Vref4. Such a design allows the system to flexibly adjust the on-time according to actual load requirements, optimize efficiency and reduce unnecessary switching actions. The four comparators (21-24) respectively monitor the state of the output voltage Vout relative to different reference voltages Vref1 to Vref4, and control the corresponding NMOS tubes (M6 to M9) accordingly. For example, the first comparator 21 will check whether Vout is lower than Vref1. If so, the NMOS tube M9 will be turned off to prevent the capacitor C5 from charging further; on the contrary, if Vout is higher than Vref1, M9 will be turned on to allow C5 to continue charging. Similarly, the other comparators will also decide which capacitors should participate in the work according to their respective thresholds. NMOS tubes M10 to M13 are responsible for finally determining which capacitors actually participate in the setting of the conduction time. They are controlled by the enable signal EN2. When EN2 is at a low level, these NMOS tubes are in a cut-off state, and accordingly, only the capacitor C1 will be charged; when EN2 is at a high level, the NMOS tube is turned on, and more capacitors (such as C2 to C5) can be added to the circuit as needed.

[0025] Furthermore, the conduction time generating circuit 3 comprises: a fifth comparator 31 and a sixth comparator 32, wherein the non-inverting input terminal of the fifth comparator 31 is connected to the voltage SW and the first terminal of the switch S1, and the inverting input terminal thereof is connected to the voltage VREF and the first terminal of the switch S0; the non-inverting input terminal of the sixth comparator 32 is connected to the drain of the PMOS tube M5, the inverting input terminal thereof is connected to the switch S0 and the second terminal of the switch S1, and the output terminal thereof is the time Ton when the output pulse signal changes from low to high; wherein the level detection terminal of the switch S0 is connected to the output terminal of the fifth comparator 31 and the input terminal of the inverter 33, and the level detection terminal of the switch S1 is connected to the output terminal of the inverter 33. When the switch S0 is at a high level, the switch S0 is closed; when the switch S1 is at a high level, the switch S1 is closed; the inverter 33 is used to generate a delay of the DC-DC freewheeling conduction, thereby ensuring the generation of the conduction time, and then outputs the adaptive conduction time by comparing the adaptive conduction voltage with the voltage VREF.

[0026] In the embodiment of the present application, the on-time generating circuit 3 is designed to accurately control the on-time (Ton) of the power switch in the DC-DC converter, ensuring that it can be adaptively adjusted according to the changes in the input voltage VIN, load conditions and output voltage Vout. Specifically, the fifth comparator 31 and the sixth comparator 32 work together to achieve fine control of the on-time. The non-inverting input of the fifth comparator 31 is connected to the voltage SW (i.e., the switch node voltage) and the first end of the switch S1, while its inverting input is connected to the reference voltage VREF and the first end of the switch S0. This means that when the SW voltage exceeds VREF, the fifth comparator 31 will output a high-level signal. This signal is not only used to control the state of the switch S0, but also sent to the inverter 33 as an input. The non-inverting input of the sixth comparator 32 is connected to the drain of the PMOS tube M5, which represents the adaptive on-voltage provided by the adaptive voltage generating circuit 2; its inverting input is connected to the second end of the switches S0 and S1, which is actually monitoring the selected capacitor charging voltage. The task of the sixth comparator 32 is to compare the two voltages and trigger the change of the output pulse signal from low to high when it reaches the set threshold, marking the beginning of a fixed conduction time Ton. The states of switches S0 and S1 are controlled by the output of the fifth comparator 31 and the output of the inverter 33. Specifically, when switch S0 detects a high level, it will be closed to prevent current from flowing to the VREF terminal; similarly, when switch S1 detects a high level, it will also be closed to prevent current from flowing back to the SW terminal. This design ensures that the system can be correctly reset and prepared for the next comparison operation before each new conduction cycle begins. The inverter 33 plays a key role here. The delay it generates helps to ensure that the freewheeling transfer conduction process in the DC-DC converter is completed smoothly. By introducing this short time difference, instability caused by fast switching can be avoided while ensuring the accurate generation of the conduction time. Once the adaptive conduction voltage exceeds VREF, the sixth comparator 32 will output a rising edge signal indicating the end of the conduction time Ton.

[0027] To sum up, the technical solution generates a current linearly related to the input voltage through a current generating circuit, and transmits the current to an adaptive voltage generating circuit through a current mirror. The adaptive voltage generating circuit switches between heavy load and light load modes through enable signals EN2 and EN3. A small capacitor is used for charging in heavy load mode, and a large capacitor is used for charging in light load mode. Different capacitance values ​​are selected according to different output voltages through a comparator. When the charging reaches the set voltage value, the on-time generating circuit works to output the on-time. Therefore, the on-time can adaptively change according to the change of input voltage and different load modes, thereby reducing the loss caused by the input voltage change and improving efficiency.

[0028] It should be understood that the specific examples herein are only intended to help those skilled in the art to better understand the present disclosure, rather than to limit the scope of the present invention.

[0029] It is understood that in the various implementations of this specification, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the present disclosure.

[0030] It can be understood that the various implementation modes described in this specification can be implemented individually or in combination, and the present disclosure is not limited to this.

[0031] Unless otherwise stated, all technical and scientific terms used in this disclosure have the same meaning as those generally understood by those skilled in the art of the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms of "a", "above", and "the" used in this disclosure and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0032] The above is only a specific implementation of this specification, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in this specification, which should be included in the protection scope of this specification. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An adaptive on-time circuit for DC-DC in PFM mode, characterized in that: include: A current generating circuit (1), an adaptive voltage generating circuit (2) connected to the current generating circuit (1), and an on-time generating circuit (3) connected to the adaptive voltage generating circuit (2); The current generating circuit (1) generates a current I1 proportional to the input voltage VIN through a Gm amplifier and inputs the current I1 into the adaptive voltage generating circuit (2). The adaptive voltage generating circuit (2) selects a corresponding capacitor to participate in the operation according to the load condition. The on-time generating circuit (3) generates an adaptive on-time that follows the input voltage VIN and the load changes, so as to realize dynamic adjustment of the on-time.

2. The adaptive on-time circuit of DC-DC in PFM mode according to claim 1, characterized in that: The current generating circuit (1) comprises: A resistor R1, a first end of which is connected to an input voltage VIN; An NMOS tube M1, whose drain is connected to the second end of the resistor R1, and whose gate is connected to the enable signal EN1; A resistor R2, a first end of which is connected to the source of the NMOS transistor M1; and a resistor R3, a first end of which is connected to the second end of the resistor R2, and a second end of which is connected to GND; The input end of the Gm amplifier is connected between the second end of the resistor R2 and the first end of the resistor R3, and the output end of the Gm amplifier inputs the current I1 into the adaptive voltage generating circuit (2).

3. The adaptive on-time circuit of DC-DC in PFM mode according to claim 2, characterized in that: When the enable signal EN1 is GND, the current generating circuit (1) does not work; When the enable signal EN1 is VDD, the current generating circuit (1) operates normally, and the current I1 is proportional to the input voltage VIN through the resistor R1, the resistor R2, the resistor R3 and the Gm amplifier.

4. The adaptive on-time circuit of DC-DC in PFM mode according to claim 1, characterized in that: The adaptive voltage generating circuit (2) comprises: NMOS tube M2, whose drain and gate are connected to the output end of the Gm amplifier, and whose source is connected to GND; An NMOS tube M3, whose gate is connected to the output end of the Gm amplifier and whose source is connected to GND; A PMOS tube M4, whose drain and gate are connected to the drain of the NMOS tube M3, and whose source is connected to VDD; A PMOS transistor M5, whose gate is connected to the drain of the NMOS transistor M3, whose source is connected to VDD, whose drain is connected to the first end of the capacitor C1, and whose second end is connected to GND; An NMOS tube M6, whose drain is connected to the drain of the PMOS tube M5, whose source is connected to the first end of the capacitor C2, and whose second end is connected to GND; An NMOS transistor M7, whose drain is connected to the drain of the PMOS transistor M5, whose source is connected to the first end of the capacitor C3, and whose second end is connected to GND; An NMOS tube M8, whose drain is connected to the drain of the PMOS tube M5, whose source is connected to the first end of the capacitor C4, and whose second end is connected to GND; An NMOS transistor M9, whose drain is connected to the drain of the PMOS transistor M5, whose source is connected to the first end of the capacitor C5, and whose second end is connected to GND; A first comparator (21), whose inverting input terminal is connected to the output voltage Vout, whose non-inverting input terminal is connected to the voltage Vref1, and whose output terminal is connected to the gate of the NMOS transistor M9; A second comparator (22), whose inverting input terminal is connected to the output voltage Vout, whose non-inverting input terminal is connected to the voltage Vref2, and whose output terminal is connected to the gate of the NMOS transistor M8; A third comparator (23), whose inverting input terminal is connected to the output voltage Vout, whose non-inverting input terminal is connected to the voltage Vref3, and whose output terminal is connected to the gate of the NMOS transistor M7; A fourth comparator (24), whose inverting input terminal is connected to the output voltage Vout, whose non-inverting input terminal is connected to the voltage Vref4, and whose output terminal is connected to the gate of the NMOS transistor M6; An NMOS transistor M10, whose drain is connected to the source of the NMOS transistor M6, whose source is connected to the second end of the capacitor C2, and whose gate is connected to the enable signal EN2; An NMOS transistor M11, whose drain is connected to the source of the NMOS transistor M7, whose source is connected to the second end of the capacitor C3, and whose gate is connected to the enable signal EN2; An NMOS transistor M12, whose drain is connected to the source of the NMOS transistor M8, whose source is connected to the second end of the capacitor C4, and whose gate is connected to the enable signal EN2; and An NMOS transistor M13, whose drain is connected to the source of the NMOS transistor M9, whose source is connected to the second end of the capacitor C5, and whose gate is connected to the enable signal EN2; Wherein, the drain of the PMOS tube M5 is connected to the conduction time generating circuit (3).

5. The adaptive on-time circuit of DC-DC in PFM mode according to claim 4, characterized in that: When the load is under heavy load, the enable signal EN2 is VDD, the enable signal EN3 is GND, and only the capacitor C1 is charged; When the load is light, the enable signal EN2 is GND, the enable signal EN3 is VDD, and the corresponding capacitor is selected to be turned on by comparing the output voltage Vout with different voltages Vref, so that an adaptive turn-on voltage proportional to the input voltage VIN is output.

6. The adaptive on-time circuit of DC-DC in PFM mode according to claim 4, characterized in that: The on-time generating circuit (3) comprises: a fifth comparator (31), whose non-inverting input terminal is connected to the voltage SW and the first terminal of the switch S1, and whose inverting input terminal is connected to the voltage VREF and the first terminal of the switch S0; and A sixth comparator (32), whose non-inverting input terminal is connected to the drain of the PMOS tube M5, whose inverting input terminal is connected to the switch S0 and the second end of the switch S1, and whose output terminal is the time Ton when the output pulse signal changes from low to high; The level detection end of the switch S0 is connected to the output end of the fifth comparator (31) and the input end of the inverter (33), and the level detection end of the switch S1 is connected to the output end of the inverter (33).

7. The adaptive on-time circuit of DC-DC in PFM mode according to claim 6, characterized in that: When the switch S0 is at a high level, the switch S0 is closed; When the switch S1 is at a high level, the switch S1 is closed; The inverter (33) is used to generate a delay in the DC-DC freewheeling conduction, thereby ensuring the generation of the conduction time, and then outputting the adaptive conduction time by comparing the adaptive conduction voltage with the voltage VREF.

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