Same-frequency control circuit for controlling BUCK converter based on adaptive conduction time

Abstract

The invention belongs to the field of integrated circuit design, and comprises a switch module and a co-frequency control module, the switch module comprises a power switch tube, and the co-frequency control module comprises a turn-on time control circuit, a turn-off time control circuit, a logic circuit and a driving circuit; the turn-on time control circuit generates a first control signal for controlling the turn-on time of the power switch tube; the turn-off time control circuit generates a second control signal for controlling the turn-off time of the power switch tube; the logic circuit performs logic operation on the first control signal and the second control signal to generate a third control signal; the driving circuit generates a driving signal based on the third control signal; the switch module controls the power switch tube to be switched on and switched off periodically according to the corresponding switching frequency based on the driving signal so as to convert the input voltage of the input power supply into the output voltage. According to the BUCK converter, the same-frequency control circuit is introduced, so that the fluctuation of the switching frequency of the BUCK converter controlled by the self-adaptive conduction time when the load changes can be effectively reduced.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit design, and in particular relates to a same-frequency control circuit of a BUCK converter based on adaptive on-time control. Background Art

[0002] The traditional fixed on-time control BUCK converter has a constant on-time. When the input and output voltages change, the switching cycle will change. The adaptive on-time control BUCK converter can make up for this defect. The adaptive on-time control BUCK converter has the advantages of simple structure, fast transient response, and no need for slope compensation. It is widely used in portable electronic products, communication equipment, industrial automation equipment, automotive electronics and other fields.

[0003] The adaptive conduction circuit time control BUCK converter generates a signal to control the switch tube to turn on or off after calculating the sampled input voltage and output voltage, so that the control switch tube conduction time is inversely proportional to the input voltage and proportional to the output voltage. Therefore, in an ideal case, it can be considered that even if the input voltage and output voltage change, the operating frequency of the system remains constant. However, in practical applications, due to the on-resistance of the power switch tube, when the load current increases and the high-side power tube is turned on, the voltage drop of the high-side power tube increases, the rising slope of the inductor current decreases, and the on-time remains constant, so the peak-to-peak value of the inductor current decreases. When the low-side power switch tube is turned on, the on-resistance of the low-side power switch tube increases the falling slope of the inductor current and reduces the off-time, thereby reducing the switching cycle. That is, when the on-resistance is considered, the switching cycle will change with the load, which is not conducive to processing electromagnetic interference of a specific frequency, nor is it conducive to phase misalignment for on-chip integration or module integration of multiple chips.

[0004] Therefore, the related adaptive on-time control BUCK converter has the defect that the switching frequency fluctuates greatly with load changes. Summary of the invention

[0005] The purpose of the present application is to provide a same-frequency control circuit based on an adaptive on-time control BUCK converter, aiming to solve the problem that the switching frequency of the related adaptive on-time control BUCK converter fluctuates greatly when the load changes.

[0006] The embodiment of the present application provides a frequency-coordinating control circuit of a BUCK converter based on adaptive on-time control, including: a switch module and a frequency-coordinating control module, wherein the switch module includes a power switch tube, and the frequency-coordinating control module includes an on-time control circuit, an off-time control circuit, a logic circuit, and a drive circuit;

[0007] The on-time control circuit is configured to generate a first control signal for controlling the on-time of the power switch tube;

[0008] The off time control circuit is configured to generate a second control signal for controlling the off time of the power switch tube;

[0009] The logic circuit is configured to perform a logic operation on the first control signal and the second control signal to generate a third control signal;

[0010] The driving circuit is configured to generate a driving signal based on the third control signal;

[0011] The switch module is configured to control the power switch tube to be periodically turned on and off according to a corresponding switching frequency based on the driving signal, so as to convert an input voltage of an input power source into an output voltage.

[0012] In one embodiment, the switch module includes a switch circuit and a filter circuit, and the switch circuit includes a power switch tube;

[0013] The switch circuit is configured to control the power switch tube to be periodically turned on and off according to a corresponding switching frequency based on the drive signal, so as to convert the input voltage into a switch node signal;

[0014] The filter circuit is configured to filter the switch node signal and convert it into the output voltage.

[0015] In one embodiment, the switch circuit includes a high-side power switch tube and a low-side power switch tube, and the drive signal includes a first drive signal and a second drive signal;

[0016] The drain of the high-side power switch tube is connected to the input power supply, the gate of the high-side power switch tube is connected to the drive circuit, and the source of the high-side power switch tube is connected to the drain of the low-side power switch tube; the gate of the high-side power switch tube is configured to receive the first drive signal to control the on and off of the high-side power switch tube, and the source of the high-side power switch tube and the drain of the low-side power switch tube are used together as the input end of the filter circuit and are configured to output the switch node signal to the filter circuit;

[0017] The gate of the low-side power switch tube is connected to the drive circuit, and the source of the low-side power switch tube is connected to the power ground; the gate of the low-side power switch tube is configured to receive the second drive signal to control the conduction and shutdown of the low-side power switch tube.

[0018] In one of the embodiments, the filter circuit includes a filter inductor, a filter capacitor and a load resistor;

[0019] The source of the high-side power switch tube and the drain of the low-side power switch tube are connected in parallel to the first end of the filter inductor, and the second end of the filter inductor is connected to the output end of the switch module;

[0020] The first end of the filter capacitor and the first end of the load resistor are connected to the second end of the filter inductor, and the second end of the filter capacitor, the second end of the load resistor and the source of the low-side power switch tube are connected to the power ground.

[0021] In one embodiment, it also includes:

[0022] The synchronous clock signal generating circuit is connected to the conduction time control circuit and is configured to output a synchronous clock signal and a clock current signal.

[0023] In one of the embodiments, the on-time control circuit includes: a frequency locking control circuit, a first voltage-current conversion circuit, a current adding unit, a current operation circuit, an AC-DC conversion circuit, a capacitor unit, a controlled switch and a first comparator;

[0024] The frequency locking control circuit is configured to generate a first current signal based on the synchronous clock signal and the first driving signal;

[0025] The current adding unit is configured to add the first current signal and the clock current signal to obtain a second current signal;

[0026] The first voltage-current conversion circuit is configured to sample the input voltage and convert the sampled input voltage into a third current signal;

[0027] The current operation circuit is configured to receive the second current signal and the third current signal, and output a fourth current signal after operation;

[0028] The AC-to-DC circuit is configured to sample the switch node signal and convert the sampled switch node signal into a first voltage signal;

[0029] The first input terminal of the first comparator is connected to the output terminal of the AC-DC converter, the second input terminal of the first comparator is connected to the output terminal of the current operation circuit, and the output terminal of the first comparator is connected to the logic circuit, and is configured to receive the first voltage signal and the fourth current signal, and output the first control signal;

[0030] The first end of the controlled switch is connected to the output end of the current operation circuit, the second end of the controlled switch is connected to the power ground, and the third end of the controlled switch is connected to the drive circuit, and is configured to control its own switch state according to the first drive signal, open when the high-side power switch tube is turned on, and disconnect when the high-side power switch tube is turned off;

[0031] A first end of the capacitor unit is connected to a first end of the controlled switch, and a second end of the capacitor unit is connected to a power ground.

[0032] In one embodiment, the current operation circuit includes: a first NPN transistor, a second NPN transistor, a third NPN transistor, a fourth NPN transistor, a first PNP transistor, a first PMOS transistor, a second PMOS transistor, a first current source, and a second current source;

[0033] The collector of the first NPN transistor is connected to the base of the first PNP transistor and is configured to receive the second current signal together;

[0034] The base of the first NPN transistor is connected to the emitter of the second NPN transistor and is configured to jointly receive the third current signal;

[0035] The drain of the second PMOS tube is configured to output the fourth current signal;

[0036] The emitter of the first NPN transistor, the collector of the first PNP transistor, the emitter of the fourth NPN transistor and the first end of the second current source are grounded;

[0037] The base of the second NPN transistor, the base of the third NPN transistor and the emitter of the first PNP transistor are respectively connected to the first end of the first current source;

[0038] The collector of the second NPN tube, the collector of the third NPN tube, the source of the first PMOS tube, the second end of the first current source and the source of the second PMOS tube are respectively connected to a power supply;

[0039] The base of the fourth NPN transistor and the emitter of the third NPN transistor are respectively connected to the second end of the second current source;

[0040] The collector of the fourth NPN tube, the gate of the first PMOS tube, the drain of the first PMOS tube and the gate of the second PMOS tube are connected.

[0041] In one of the embodiments, the frequency lock control circuit includes a frequency detector, a charge pump, a low-pass filter, and a second voltage-current conversion circuit;

[0042] The phase frequency detector is configured to generate a charge pump control signal based on the synchronous clock signal and the first driving signal;

[0043] The charge pump is configured to charge and discharge based on the charge pump control signal;

[0044] The low-pass filter is configured to convert the current generated by the charge pump charging and discharging into a second voltage signal;

[0045] The second voltage-current conversion circuit is configured to convert the received second voltage signal into a first current signal.

[0046] In one of the embodiments, the off-time control circuit includes: an operational amplifier unit, a compensation network, a second comparator, a first sampling circuit and a second sampling circuit;

[0047] The first sampling circuit is configured to sample the output voltage to obtain an output sampling voltage;

[0048] The operational amplifier unit is configured to generate a third voltage signal based on the output sampling voltage and the first reference voltage;

[0049] The second sampling circuit is configured to sample the current of the inductor to obtain an inductor current sampling voltage;

[0050] The second comparator is configured to generate and output the second control signal based on the third voltage signal and the inductor current sampling voltage;

[0051] The compensation network is connected to the output terminal of the operational amplifier unit.

[0052] In one of the embodiments, the synchronous clock generating circuit includes: a third voltage-current conversion circuit, a current bias circuit and a clock generating circuit;

[0053] The third voltage-current conversion circuit is configured to generate a fifth current signal based on the second reference voltage;

[0054] The first output end of the current bias circuit is connected to the input end of the clock generating circuit, and the second output end of the current bias circuit is connected to the input end of the current adding unit, and is configured to bias the fifth current signal to obtain the clock current signal, and output the clock current signal;

[0055] The output end of the clock generation circuit is connected to the input end of the frequency locking control circuit, and is configured to generate the synchronous clock signal based on the clock current signal and output the synchronous clock signal.

[0056] An embodiment of the present application further provides an electronic device, which includes the above-mentioned frequency-coordinating control circuit based on adaptive on-time control of a BUCK converter.

[0057] The on-time control circuit in the embodiment of the present application generates a first control signal for controlling the on-time of the power switch tube; the off-time control circuit generates a second control signal for controlling the off-time of the power switch tube; the logic circuit performs a logic operation on the first control signal and the second control signal to generate a third control signal; the drive circuit generates a drive signal based on the third control signal; the switch module controls the power switch tube to periodically turn on and off according to the corresponding switching frequency based on the drive signal to convert the input voltage of the input power supply into the output voltage. By introducing a same-frequency control circuit, the present application can effectively reduce the fluctuation of the switching frequency of the adaptive on-time control BUCK converter when the load changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the related technologies or the embodiments of the present application, the drawings required for use in the description of the related technologies or the embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, not all embodiments. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0059] Figure 1 A structural schematic diagram of a same-frequency control circuit of a BUCK converter based on adaptive on-time control provided in an embodiment of the present application;

[0060] Figure 2 A detailed structural schematic diagram of a same-frequency control circuit based on adaptive on-time control of a BUCK converter provided in an embodiment of the present application;

[0061] Figure 3 A circuit schematic diagram of a switch module in a frequency control circuit of a BUCK converter based on adaptive on-time control provided in an embodiment of the present application;

[0062] Figure 4 A structural schematic diagram of a same-frequency control circuit of a BUCK converter based on adaptive on-time control provided in an embodiment of the present application;

[0063] Figure 5 A schematic diagram of a structure of an on-time control circuit in a same-frequency control circuit of a BUCK converter based on adaptive on-time control provided in an embodiment of the present application;

[0064] Figure 6A circuit schematic diagram of a current operation circuit in a frequency control circuit of a BUCK converter based on adaptive on-time control provided in an embodiment of the present application;

[0065] Figure 7 A structural schematic diagram of a frequency locking control circuit in a frequency control circuit of a BUCK converter based on adaptive on-time control provided in an embodiment of the present application;

[0066] Figure 8 A schematic diagram of a structure of an off-time control circuit in a frequency-coordinated control circuit of a BUCK converter based on adaptive on-time control provided in an embodiment of the present application;

[0067] Fig. 9 A schematic diagram of a structure of a synchronous clock signal generating circuit in a frequency control circuit of a BUCK converter based on adaptive on-time control provided in an embodiment of the present application;

[0068] Fig.10 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0069] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0070] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0071] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0072] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means one or more, unless otherwise clearly and specifically defined.

[0073] The traditional adaptive on-time control BUCK converter is affected by the on-resistance of the power switch tube, and the switching frequency will fluctuate greatly with the load current. In addition, the operating frequency range is relatively narrow, and the operating frequency cannot be flexibly configured according to actual application requirements.

[0074] In addition, the adaptive on-time control mode needs to collect output voltage information. The existing technology usually samples the output voltage directly. This sampling method will deteriorate the transient response when the load undergoes a transient jump. For example, when a heavy load jumps to a light load, the output voltage rises, and the system wants to reduce the duty cycle, but at this time the adaptive on-time will increase instead, which will cause the transient response speed to slow down.

[0075] Therefore, the present application proposes a same-frequency control circuit for adaptive on-time control of a BUCK converter to achieve a control effect of synchronization of a switching signal and a clock signal, so that the switching frequency of the BUCK converter can be controlled at a constant frequency under different input voltages, output voltages and different load conditions.

[0076] Figure 1 A structural schematic diagram of a same-frequency control circuit based on adaptive on-time control of a BUCK converter provided in an embodiment of the present application is shown. For ease of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0077] The same-frequency control circuit of the BUCK converter based on adaptive on-time control in this embodiment includes: a switch module 10 and a same-frequency control module 20, the switch module 10 includes a power switch tube, and the same-frequency control module 20 includes an on-time control circuit 201, an off-time control circuit 202, a logic circuit 203 and a drive circuit 204;

[0078] The on-time control circuit 201 is configured to generate a first control signal for controlling the on-time of the power switch tube;

[0079] The off time control circuit 202 is configured to generate a second control signal for controlling the off time of the power switch tube;

[0080] The logic circuit 203 is configured to perform a logic operation on the first control signal and the second control signal to generate a third control signal;

[0081] The driving circuit 204 is configured to generate a driving signal based on the third control signal;

[0082] The switch module 10 is configured to control the power switch tube to be periodically turned on and off according to a corresponding switching frequency based on a driving signal, so as to convert an input voltage of an input power source into an output voltage.

[0083] In detail, the input voltage of the input power supply can be converted into the output voltage by periodically turning on and off the power switch tube, and when the load changes, it will affect the switching cycle of the power switch tube, and then affect the switching frequency, so we need to control the switch at the same frequency. Furthermore, the on-time control circuit is used to control the on-time of the switch tube, and the off-time control circuit is used to control the off-time of the switch tube. Since there are more than one power switch tubes in the switch module, it is necessary to introduce a logic circuit to generate control signals for multiple power switch tubes through logical operations, and then convert the control signals into drive signals that can drive the corresponding power switch tubes through the drive circuit. Finally, the periodic on and off of the power switch tube is adjusted through the drive signal, so as to adjust the switching frequency of the power switch tube.

[0084] It can be understood that the above control signal contains information about the synchronous clock, and when the switching frequency of the power switch tube is adjusted by the driving signal, the switching frequency will be synchronously adjusted to the clock frequency, thereby achieving the same frequency control effect and realizing constant frequency control. The synchronous clock signal can be a clock from an external clock, or a clock signal generated by configuring an internal oscillator through an off-chip resistor. The operating frequency can be flexibly configured in different application scenarios, and it is easy to realize multi-phase parallel control of the BUCK converter.

[0085] exist Figure 1 Based on the same-frequency control circuit of the BUCK converter based on adaptive on-time control provided, the embodiment of the present application also provides a detailed structural schematic diagram of the same-frequency control circuit of the BUCK converter based on adaptive on-time control. For details, please refer to Figure 2 .

[0086] In one embodiment, the switch module 10 includes a switch circuit 101 and a filter circuit 102, and the switch circuit 101 includes at least one power switch tube;

[0087] The switch circuit 101 is configured to control the power switch tube to be periodically turned on and off according to a corresponding switching frequency, so as to convert the input voltage into a switch node signal;

[0088] The filter circuit 102 is configured to filter the switch node signal and convert it into an output voltage.

[0089] The present application also provides a circuit schematic diagram of a switch module in a frequency control circuit of a BUCK converter based on adaptive on-time control. Figure 3 .

[0090] In one embodiment, the switch circuit 101 includes a high-side power switch tube 1011 and a low-side power switch tube 1012, and the drive signal includes a first drive signal and a second drive signal;

[0091] The drain of the high-side power switch tube 1011 is connected to the input power supply, the gate of the high-side power switch tube 1011 is connected to the driving circuit 204, and the source of the high-side power switch tube 1011 is connected to the drain of the low-side power switch tube 1012; the gate of the high-side power switch tube 1011 is configured to receive a first driving signal to control the on and off of the high-side power switch tube 1011, and the source of the high-side power switch tube 1011 and the drain of the low-side power switch tube 1012 are used together as the input end of the filter circuit 102, and are configured to output the switch node signal to the filter circuit 102;

[0092] The gate of the low-side power switch tube 1012 is connected to the drive circuit 204, and the source of the low-side power switch tube 1012 is connected to the power ground; the gate of the low-side power switch tube 1012 is configured to receive a second drive signal to control the conduction and shutdown of the low-side power switch tube 1012.

[0093] like Figure 3 As shown, in one embodiment, the filter circuit 102 includes a filter inductor 1021, a filter capacitor 1022 and a load resistor 1023;

[0094] The source of the high-side power switch tube 1011 and the drain of the low-side power switch tube 1012 are connected in parallel to the first end of the filter inductor 1021, and the second end of the filter inductor 1021 is connected to the output end of the switch module 10;

[0095] The first end of the filter capacitor 1022 and the first end of the load resistor 1023 are connected to the second end of the filter inductor 1021, and the second end of the filter capacitor 1022, the second end of the load resistor 1023 and the source of the low-side power switch tube 1012 are connected to the power ground.

[0096] It can be understood that the above-mentioned BUCK converter includes a switching circuit consisting of at least one controllable switch. In this embodiment, the controllable switch consists of a high-side NMOS power switch tube and a low-side NMOS power switch tube. The input voltage signal is converted into a square wave signal, that is, the above-mentioned switch node signal, through periodic conduction and shutdown of the high-side power switch tube and the low-side power switch tube, and then through LC filtering to realize the conversion of the input voltage into the output voltage.

[0097] The present application also provides a schematic diagram of a structure of a frequency control circuit based on adaptive on-time control of a BUCK converter. Figure 4 .

[0098] like Figure 4 As shown, in one embodiment, it also includes: a synchronous clock signal generating circuit 205, which is connected to the conduction time control circuit 201 and is configured to output a synchronous clock signal and a clock current signal.

[0099] In detail, the on-time control circuit receives an input voltage signal V IN , switch node SW signal, high-side power switch tube drive control signal HG, synchronous clock signal CLK, clock current signal I CLK The on-time control circuit generates a logic signal T for controlling the on-time of the high-side power switch tube based on the received control signal. ON . Control signal T ON When it is at a high level, the control logic signal generated by the logic circuit is converted into a control signal HG with sufficient driving capability to control the high-side power switch tube to turn off and a control signal LG to control the low-side power switch tube to turn on.

[0100] The off time control circuit receives the output voltage feedback signal V FB , inductor current signal I L , the output feedback voltage and a reference voltage V REF The error is compared and amplified with the inductor current I L The sampling signal is compared to obtain the logic signal T that controls the off time of the high-side power switch tube. OFF When T OFF When it is at a high level, the control logic signal generated by the logic circuit is converted into a control signal HG with sufficient driving capability to control the high-side power switch tube to turn on, and the control signal LG to control the low-side power switch tube to turn off.

[0101] The synchronous clock signal generating circuit is used to generate the synchronous clock signal CLK and the clock current signal I CLK .

[0102] The present application also provides a schematic diagram of a structure of an on-time control circuit in a frequency control circuit of a BUCK converter based on adaptive on-time control. Figure 5 .

[0103] like Figure 5As shown, in one embodiment, the on-time control circuit 201 includes: a frequency locking control circuit 2011, a current adding unit 2012, a first voltage-current conversion circuit 2013, a current operation circuit 2014, an AC-DC conversion circuit 2015, a first comparator 2016, a controlled switch 2017 and a capacitor unit 2018;

[0104] The frequency locking control circuit 2011 is configured to generate a first current signal based on the synchronous clock signal and the first driving signal;

[0105] The current adding unit 2012 is configured to add the first current signal and the clock current signal to obtain a second current signal;

[0106] The first voltage-current conversion circuit 2013 is configured to sample the input voltage and convert the sampled input voltage into a third current signal;

[0107] The current operation circuit 2014 is configured to receive the second current signal and the third current signal, and output a fourth current signal after operation;

[0108] The AC-to-DC circuit 2015 is configured to sample the switch node signal and convert the sampled switch node signal into a first voltage signal;

[0109] A first input terminal of the first comparator 2016 is connected to the output terminal of the AC-DC converter, a second input terminal of the first comparator is connected to the output terminal of the current operation circuit, and an output terminal of the first comparator is connected to the logic circuit, and is configured to receive the first voltage signal and the fourth current signal, and output a first control signal;

[0110] A first end of the controlled switch 2017 is connected to the output end of the current operation circuit, a second end of the controlled switch is connected to the power ground, and a third end of the controlled switch is connected to the drive circuit, and is configured to control its own switch state according to the first drive signal, and is turned on when the high-side power switch tube is turned on, and is turned off when the high-side power switch tube is turned off;

[0111] A first end of the capacitor unit 2018 is connected to a first end of the controlled switch, and a second end of the capacitor unit is connected to a power ground.

[0112] In detail, the two input terminals of the frequency locking control circuit detect the phase difference between the synchronous clock signal CLK and the high-side power switch tube drive control signal HG, and convert the phase difference into the first current signal I CTRL , the first current signal and the clock current signal I CLK After adding, the second current signal I is obtained CTRL +I CLK , the second current signal I CTRL +ICLK The first voltage-current conversion circuit is used to sample the input voltage and convert it into a third current signal I VIN , the third current signal I VIN The current operation circuit receives the second current signal I CTRL +I CLK and the third current signal I VIN , and the second current signal I CTRL +I CLK and the third current signal I VIN After multiplication, the fourth current signal I is output ON .

[0113] It can be understood that the controlled switch also includes a third end as a control end, which is controlled by the high-side power switch tube drive signal HG. The controlled switch is turned on when the high-side power switch tube is turned on, and the controlled switch is turned off when the high-side power switch tube is turned off.

[0114] During the conduction period of the high-side power tube, the controlled switch is turned on, and the fourth current signal I ON Charge the capacitor unit until the voltage on the capacitor unit is equal to the first voltage signal V ON When the first comparator outputs the first control signal T ON After the subsequent logic circuit and drive circuit, the high-side power switch is turned off. The first voltage signal V ON The switch node signal SW is converted by the AC to DC circuit, and the first voltage signal V ON and output voltage V OUT Proportional, that is, V ON =K OUT ·V OUT :

[0115] That is, the on-time of the high-side power switch tube ON_time can be expressed as formula (1):

[0116]

[0117] This embodiment also provides a circuit schematic diagram of a current operation circuit in a frequency control circuit of a BUCK converter based on adaptive on-time control. Figure 6 .

[0118] like Figure 6 As shown, in one embodiment, the current operation circuit includes: a first NPN transistor QN1, a second NPN transistor QN2, a third NPN transistor QN3, a fourth NPN transistor QN4, a first PNP transistor QP1, a first PMOS transistor MP1, a second PMOS transistor MP2, a first current source I B1and the second current source I B2 ;

[0119] The collector of the first NPN transistor QN1 is connected to the base of the first PNP transistor QP1 and is configured to receive the second current signal together;

[0120] The base of the first NPN transistor QN1 is connected to the emitter of the second NPN transistor QN2 and is configured to receive the third current signal together;

[0121] The drain of the second PMOS tube MP2 is configured to output a fourth current signal;

[0122] The emitter of the first NPN transistor QN1, the collector of the first PNP transistor QP1, the emitter of the fourth NPN transistor QN4 and the second current source I B2 A first end of the grounded;

[0123] The base of the second NPN transistor QN2, the base of the third NPN transistor QN3 and the emitter of the first PNP transistor QP1 are respectively connected to the first end of the first current source;

[0124] The collector of the second NPN transistor QN2, the collector of the third NPN transistor QN3, the source of the first PMOS transistor MP1, the first current source I B1 The second end of and the source of the second PMOS tube MP2 are respectively connected to the power supply;

[0125] The base of the fourth NPN transistor QN4 and the emitter of the third NPN transistor QN3 are respectively connected to the second current source I B2 The second end of

[0126] The collector of the fourth NPN transistor QN4 , the gate of the first PMOS transistor MP1 , the drain of the first PMOS transistor MP1 , and the gate of the second PMOS transistor MP2 are connected.

[0127] Specifically, the base-collector voltage difference VBE1 of the first NPN transistor QN1 plus the base-collector voltage difference VBE2 of the second NPN transistor QN2 BE2 Equal to the base-collector voltage difference V of the third NPN tube QN3 BE3 Plus the base-collector voltage difference V of the third NPN tube QN3 BE3 , by the BJT base-collector voltage difference V BE and collector current I C The relationship between them can be concluded as follows:

[0128]

[0129] Thus, the fourth current signal I ON The expression is:

[0130]

[0131] Substituting formula (3) into formula (1), we get the conduction time of the high-side power switch tube:

[0132]

[0133] Among them I VIN It is the current signal sampled by the voltage-current conversion circuit after the input voltage is converted. VIN It can be expressed as:

[0134] I VIN =K IN ·V IN (5)

[0135] Where K IN is the sampling factor of the voltage-to-current conversion circuit.

[0136] Combining the relationship between the on-time of the high-side power switch tube of the BUCK converter and the switching frequency, as well as formula (4) and formula (5), the switching frequency expression is obtained as follows:

[0137]

[0138] Therefore, the signal generated by the frequency-locked control circuit participates in the regulation of the switching frequency in the control loop.

[0139] This embodiment also provides a structural schematic diagram of a frequency locking control circuit in a frequency control circuit of a BUCK converter based on adaptive on-time control. Figure 7 .

[0140] In one embodiment, the frequency locking control circuit 2011 includes a frequency detector 2011a, a charge pump 2011b, a low-pass filter 2011c and a second voltage-current conversion circuit 2011d;

[0141] The phase frequency detector 2011a is configured to generate a charge pump control signal based on the synchronous clock signal and the first driving signal;

[0142] The charge pump 2011b is configured to charge and discharge based on the charge pump control signal;

[0143] The low-pass filter 2011c is configured to convert the current generated by charging and discharging the charge pump into a second voltage signal;

[0144] The second voltage-current conversion circuit 2011d is configured to convert the received second voltage signal into a first current signal.

[0145] The frequency lock control circuit detects the phase difference between the synchronous clock signal and the driving control signal HG of the high-side power switch tube through a frequency detector and uses the information of the phase difference between the two to control the charging and discharging of the charge pump. The output current of the charge pump is converted into a second voltage signal Vc on a low-pass filter, and the second voltage signal Vc is converted into a first current signal I after passing through a second voltage-current conversion circuit. CTRL . When the phase of the synchronous clock signal CLK lags behind the phase of the driving control signal HG of the high-side power switch tube, the phase difference signal controls the charging charge of the charge pump to be greater than the discharging charge, the voltage Vc generated on the low-pass filter rises, and the first current signal also rises accordingly, and participates in the regulation of the switching frequency through the current operation circuit to increase the switching frequency. When the phase of the synchronous clock signal CLK leads the phase of the driving control signal HG of the high-side power switch tube, the phase difference signal controls the charging charge of the charge pump to be less than the discharging charge, the voltage Vc generated on the low-pass filter decreases, and the first current signal also decreases accordingly, and participates in the regulation of the switching frequency through the current operation circuit to reduce the switching frequency. Therefore, under the regulation of the frequency-locked control circuit, the operating frequency F of the system SW Eventually, the phase and frequency will be consistent with the synchronous clock CLK.

[0146] This embodiment also provides a structural schematic diagram of an off time control circuit in a frequency control circuit of a BUCK converter based on adaptive on time control. Figure 8 .

[0147] In one embodiment, the off time control circuit 202 includes: a first sampling circuit 2021, an operational amplifier unit 2022, a second sampling circuit 2023, a second comparator 2024 and a compensation network 2025;

[0148] The first sampling circuit 2021 is configured to sample the output voltage to obtain an output sampling voltage;

[0149] The operational amplifier unit 2022 is configured to generate a third voltage signal based on the output sampling voltage and the first reference voltage;

[0150] The second sampling circuit 2023 is configured to sample the current of the inductor to obtain an inductor current sampling voltage;

[0151] The second comparator 2024 is configured to generate and output a second control signal based on the third voltage signal and the inductor current sampling voltage;

[0152] The compensation network 2025 is connected to the output terminal of the operational amplifier unit.

[0153] In detail, the first input terminal of the operational amplifier unit receives the output voltage sampling signal V FB , the second input terminal receives the first reference voltage VREF1 The first output terminal is connected to the compensation network and the second input terminal of the second comparator, the first input terminal of the second comparator is connected to the first output terminal of the second sampling circuit, and the output terminal of the second comparator outputs the second control signal T OFF The first input terminal of the second sampling circuit inputs the inductor current signal I L .

[0154] Specifically, the operational amplifier unit detects the output sampling voltage V FB and the first reference voltage V REF1 The error between them is amplified to get V COMP Voltage, during the conduction period of the low-side power switch tube, the inductor current decreases until the inductor current sampling signal V SENSE Lower than V COMP The voltage is applied, and the second comparator output TOFF becomes a high level, which controls the low-side power switch tube to be turned off after passing through the subsequent logic circuit and drive circuit.

[0155] This embodiment also provides a structural schematic diagram of a synchronous clock signal generating circuit in a frequency control circuit of a BUCK converter based on adaptive on-time control. Fig. 9 .

[0156] In one embodiment, the synchronous clock signal generating circuit 205 includes: a third voltage-current conversion circuit 2051, a current bias circuit 2052 and a clock generating circuit 2053;

[0157] The third voltage-current conversion circuit 2051 is configured to generate a fifth current signal based on the second reference voltage;

[0158] A first output terminal of the current bias circuit 2052 is connected to an input terminal of the clock generating circuit 2053, and a second output terminal of the current bias circuit 2052 is connected to an input terminal of the current adding unit 2012, and is configured to bias the fifth current signal to obtain a clock current signal, and output the clock current signal;

[0159] The output terminal of the clock generation circuit 2053 is connected to the input terminal of the frequency locking control circuit 2011 , and is configured to generate a synchronous clock signal based on the clock current signal and output the synchronous clock signal.

[0160] It is understandable that the synchronous clock signal can be a clock from an external clock or a clock signal generated by configuring an internal oscillator through an off-chip resistor. The operating frequency can be flexibly configured in different application scenarios, and it is easy to realize multi-phase parallel control of the BUCK converter.

[0161] In detail, the third voltage-current conversion circuit in the synchronous clock signal generating circuit can be generated by a reference voltage and an on-chip resistor or by a reference voltage and an off-chip resistor, and can be flexibly configured according to actual use requirements. The current generated by the third voltage-current conversion circuit controls the clock signal frequency of the generating circuit after being biased by the current bias circuit, so the fifth current signal I CLK Proportional to the synchronous clock signal.

[0162] In summary, the same-frequency control circuit for adaptive on-time control of the BUCK converter provided in the embodiment of the present application detects the phase difference between the synchronous clock signal and the high-side power switch tube drive signal through a frequency detector and a phase detector, and uses the phase difference signal to control the charging and discharging of the charge pump to generate a voltage signal on the low-pass filter. The voltage signal with phase difference information is then converted into a current signal through a voltage-current conversion circuit to participate in the control operation of the on-time of the high-side power switch tube, thereby adjusting the switching frequency of the power switch tube, and achieving the control effect of synchronization of the switching frequency and the clock signal. The synchronous clock signal can be a clock signal generated by an internal oscillator or a clock signal from an external source, and can be flexibly configured according to the actual application scenario. By introducing the same-frequency control circuit, the present invention enables the BUCK converter based on the adaptive on-time architecture to solve the problem of switching frequency fluctuation in wide input and wide output scenarios in actual applications, and by sampling the SW node signal to reflect the output voltage, the system has a faster transient response when the load jumps.

[0163] Fig.10 A schematic diagram of an electronic device provided in an embodiment of the present application is shown, wherein the electronic device A includes a same-frequency control circuit 01 for controlling a BUCK converter based on adaptive on-time as described in any one of the above.

[0164] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0165] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0166] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A frequency control circuit for a BUCK converter based on adaptive on-time control, characterized in that: include: A switch module and a frequency control module, wherein the switch module includes a power switch tube, and the frequency control module includes an on-time control circuit, an off-time control circuit, a logic circuit and a drive circuit; The on-time control circuit is configured to generate a first control signal for controlling the on-time of the power switch tube; The off time control circuit is configured to generate a second control signal for controlling the off time of the power switch tube; The logic circuit is configured to perform a logic operation on the first control signal and the second control signal to generate a third control signal; The driving circuit is configured to generate a driving signal based on the third control signal; The switch module is configured to control the power switch tube to be periodically turned on and off according to a corresponding switching frequency based on the driving signal, so as to convert the input voltage of the input power supply into an output voltage.

2. The same frequency control circuit based on adaptive on-time control of BUCK converter according to claim 1, characterized in that: The switch module includes a switch circuit and a filter circuit, and the switch circuit includes a power switch tube; The switch circuit is configured to control the power switch tube to be periodically turned on and off according to a corresponding switching frequency based on the drive signal, so as to convert the input voltage into a switch node signal; The filter circuit is configured to filter the switch node signal and convert it into the output voltage.

3. The same frequency control circuit based on adaptive on-time control of BUCK converter according to claim 2, characterized in that: The switch circuit includes a high-side power switch tube and a low-side power switch tube, and the drive signal includes a first drive signal and a second drive signal; The drain of the high-side power switch tube is connected to the input power supply, the gate of the high-side power switch tube is connected to the drive circuit, and the source of the high-side power switch tube is connected to the drain of the low-side power switch tube; the gate of the high-side power switch tube is configured to receive the first drive signal to control the on and off of the high-side power switch tube, and the source of the high-side power switch tube and the drain of the low-side power switch tube are used together as the input end of the filter circuit and are configured to output the switch node signal to the filter circuit; The gate of the low-side power switch tube is connected to the drive circuit, and the source of the low-side power switch tube is connected to the power ground; the gate of the low-side power switch tube is configured to receive the second drive signal to control the conduction and shutdown of the low-side power switch tube.

4. The same frequency control circuit based on adaptive on-time control of BUCK converter according to claim 3, characterized in that: The filter circuit includes a filter inductor, a filter capacitor and a load resistor; The source of the high-side power switch tube and the drain of the low-side power switch tube are connected to the first end of the filter inductor, and the second end of the filter inductor is connected to the output end of the switch module; The first end of the filter capacitor and the first end of the load resistor are connected to the second end of the filter inductor, and the second end of the filter capacitor, the second end of the load resistor and the source of the low-side power switch tube are connected to the power ground.

5. The same frequency control circuit based on adaptive on-time control of BUCK converter according to claim 4, characterized in that: Also includes: The synchronous clock signal generating circuit is connected to the conduction time control circuit and is configured to output a synchronous clock signal and a clock current signal.

6. The same frequency control circuit based on adaptive on-time control of BUCK converter according to claim 5, characterized in that: The on-time control circuit comprises: a frequency locking control circuit, a first voltage-current conversion circuit, a current adding unit, a current operation circuit, an AC-to-DC circuit, a capacitor unit, a controlled switch and a first comparator; The frequency locking control circuit is configured to generate a first current signal based on the synchronous clock signal and the first driving signal; The current adding unit is configured to add the first current signal and the clock current signal to obtain a second current signal; The first voltage-current conversion circuit is configured to sample the input voltage and convert the sampled input voltage into a third current signal; The current operation circuit is configured to receive the second current signal and the third current signal, and output a fourth current signal after operation; The AC-to-DC circuit is configured to sample the switch node signal and convert the sampled switch node signal into a first voltage signal; The first input terminal of the first comparator is connected to the output terminal of the AC-DC converter, the second input terminal of the first comparator is connected to the output terminal of the current operation circuit, and the output terminal of the first comparator is connected to the logic circuit, and is configured to receive the first voltage signal and the fourth current signal, and output the first control signal; The first end of the controlled switch is connected to the output end of the current operation circuit, the second end of the controlled switch is connected to the power ground, and the third end of the controlled switch is connected to the drive circuit, and is configured to control its own switch state according to the first drive signal, open when the high-side power switch tube is turned on, and disconnect when the high-side power switch tube is turned off; A first end of the capacitor unit is connected to a first end of the controlled switch, and a second end of the capacitor unit is connected to a power ground.

7. The same frequency control circuit based on adaptive on-time control of BUCK converter according to claim 6, characterized in that: The current operation circuit includes: a first NPN transistor, a second NPN transistor, a third NPN transistor, a fourth NPN transistor, a first PNP transistor, a first PMOS transistor, a second PMOS transistor, a first current source and a second current source; The collector of the first NPN transistor is connected to the base of the first PNP transistor and is configured to receive the second current signal together; The base of the first NPN transistor is connected to the emitter of the second NPN transistor and is configured to jointly receive the third current signal; The drain of the second PMOS tube is configured to output the fourth current signal; The emitter of the first NPN transistor, the collector of the first PNP transistor, the emitter of the fourth NPN transistor and the first end of the second current source are grounded; The base of the second NPN transistor, the base of the third NPN transistor and the emitter of the first PNP transistor are respectively connected to the first end of the first current source; The collector of the second NPN tube, the collector of the third NPN tube, the source of the first PMOS tube, the second end of the first current source and the source of the second PMOS tube are respectively connected to a power supply; The base of the fourth NPN transistor and the emitter of the third NPN transistor are respectively connected to the second end of the second current source; The collector of the fourth NPN tube, the gate of the first PMOS tube, the drain of the first PMOS tube and the gate of the second PMOS tube are connected.

8. The same frequency control circuit based on adaptive on-time control of BUCK converter according to claim 6, characterized in that: The frequency lock control circuit includes a frequency detector, a charge pump, a low-pass filter and a second voltage-current conversion circuit; The phase frequency detector is configured to generate a charge pump control signal based on the synchronous clock signal and the first driving signal; The charge pump is configured to charge and discharge based on the charge pump control signal; The low-pass filter is configured to convert the current generated by the charge pump charging and discharging into a second voltage signal; The second voltage-current conversion circuit is configured to convert the second voltage signal into a first current signal.

9. The same frequency control circuit based on adaptive on-time control of BUCK converter according to claim 6, characterized in that: The off-time control circuit comprises: an operational amplifier unit, a compensation network, a second comparator, a first sampling circuit and a second sampling circuit; The first sampling circuit is configured to sample the output voltage to obtain an output sampling voltage; The operational amplifier unit is configured to generate a third voltage signal based on the output sampling voltage and the first reference voltage; The second sampling circuit is configured to sample the current of the inductor to obtain an inductor current sampling voltage; The second comparator is configured to generate and output the second control signal based on the third voltage signal and the inductor current sampling voltage; The compensation network is connected to the output terminal of the operational amplifier unit.

10. The same frequency control circuit based on adaptive on-time control of BUCK converter according to claim 5, characterized in that: The synchronous clock signal generating circuit comprises: a third voltage-current conversion circuit, a current bias circuit and a clock generating circuit; The third voltage-current conversion circuit is configured to generate a fifth current signal based on the second reference voltage; The first output end of the current bias circuit is connected to the input end of the clock generating circuit, and the second output end of the current bias circuit is connected to the input end of the current adding unit, and is configured to bias the fifth current signal to obtain the clock current signal, and output the clock current signal; The output end of the clock generation circuit is connected to the input end of the frequency locking control circuit, and is configured to generate the synchronous clock signal based on the clock current signal and output the synchronous clock signal.

11. An electronic device, characterized in that: The electronic device comprises a same-frequency control circuit based on adaptive on-time control of a BUCK converter as claimed in any one of claims 1 to 11.

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