Cross-coupled charge pump circuit, module and CIS module for CIS

Abstract

The present invention relates to the technical field of image sensor design, and specifically relates to a cross-coupled charge pump circuit, module and CIS module applied to CIS. The circuit of the present invention includes: a charge pump section, a leakage prevention switch section, and a compensation circuit section. The charge pump section adopts a cross-coupled design, and one auxiliary switch transistor MN7 is provided in the step-up path and one auxiliary switch transistor MN8 is provided in the step-down path; on the one hand, the leakage prevention switch section is used to control MN7 and MN8, which not only ensures the normal step-up of the charge pump section, but also keeps MN7-MN8 off during the charge recovery stage to avoid reverse backflow and reduce the output ripple; on the other hand, the compensation circuit section provides different compensation signals V F to the charge pump section at different stages, which not only ensures the normal step-up of the charge pump section, but also applies a V greater than VDD to the charge pump section during the charge recovery stage F to complete voltage compensation to improve the transient response.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensor design, and more specifically, to: 1. a cross-coupled charge pump circuit applied to CIS; 2. a cross-coupled charge pump module applied to CIS; 3. a CIS module integrating a cross-coupled charge pump module applied to CIS. Background Art

[0002] CMOS Image Sensor (CIS) has become the mainstream device in the imaging field with its significant advantages such as high integration and low cost. Nowadays, CIS is developing towards high sensitivity, high frame rate, high resolution, high dynamic range and high signal-to-noise ratio.

[0003] With the development of active pixels in CIS, the working mode of pixels has changed from global exposure to drum exposure. During the drum exposure process, the photons collected by the photodiode are converted into charges and stored in the storage capacitor through the transmission gate. During this process, the storage capacitor will disperse and transfer charges with the parasitic capacitance of the transmission gate, causing image tailing. A charge pump is added to boost the gate voltage of the transmission gate, but during the exposure process, there will also be charge transfer between the output filter capacitor of the charge pump and the load capacitor. The charge pump recovery time needs to be as short as possible during the time when the transmission gate is turned on. At the same time, the output ripple of the charge pump will add random noise to the pixel; if the ripple is too large, it will seriously affect the image quality.

[0004] Therefore, designing a charge pump with low output ripple and high transient response becomes the key to improving imaging quality. Summary of the invention

[0005] In view of the problem that the output ripple of the existing charge pump is relatively high and the transient response is relatively low, it is necessary to provide a cross-coupled charge pump circuit, module and CIS module applied to CIS.

[0006] The present invention is implemented by the following technical solutions:

[0007] In a first aspect, the present invention provides a cross-coupled charge pump circuit for CIS, wherein one working cycle T comprises: an early normal working stage, a middle charge recovery stage, and a late waiting stage.

[0008] The cross-coupled charge pump circuit applied to CIS includes: a charge pump part, an anti-leakage switch part, and a compensation circuit part.

[0009] The charge pump unit is used to boost the input signal Vin to obtain the output signal Vout1. The charge pump unit is a cross-coupled design, and its boost path is provided with an auxiliary switch tube MN7, and its lower boost path is provided with an auxiliary switch tube MN8.

[0010] The anti-leakage switch section is used to control the on-off of MN7-MN8. In the normal working stage, MN7-MN8 is controlled to be disconnected first and then turned on to ensure the normal boost of the charge pump section; in the charge recovery stage, MN7-MN8 is controlled to remain disconnected to avoid reverse reflux and reduce output ripple; in the waiting stage, MN7-MN8 is controlled to be turned on to wait for the next working cycle.

[0011] The compensation circuit part is used to provide a compensation signal V to the charge pump part. F Among them, V F In the normal working stage and waiting stage, the power supply VDD is used to ensure the normal voltage boost of the charge pump part; V F In the charge recovery phase, the output signal out is used to perform voltage compensation on the charge pump unit to improve transient response; out>VDD.

[0012] The implementation of the cross-coupled charge pump circuit applied to CIS is based on the method or process of an embodiment of the present disclosure.

[0013] In a second aspect, the present invention discloses a cross-coupled charge pump module applied to a CIS, which adopts the layout of the cross-coupled charge pump circuit applied to a CIS disclosed in the first aspect.

[0014] In a third aspect, the present invention discloses a CIS module, which integrates the cross-coupled charge pump module applied to CIS disclosed in the second aspect.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] 1. The charge pump unit of the present invention adopts a cross-coupling design, and an auxiliary switch tube MN7 is set in the boost path and an auxiliary switch tube MN8 is set in the lower boost path; on the one hand, the present invention adds an anti-leakage switch unit to control MN7 and MN8, which not only ensures the normal boost of the charge pump unit, but also keeps MN7-MN8 disconnected in the charge recovery stage to avoid reverse reflux and reduce output ripple; on the other hand, the present invention adds a compensation circuit unit to provide different compensation signals V to the charge pump unit at different stages F , which not only ensures the normal boost of the charge pump section, but also applies a V higher than VDD to the charge pump section during the charge recovery phase. F Voltage compensation is done to improve transient response.

[0017] 2. After simulation verification, the circuit of the present invention reduces output ripple, improves transient response, and also enhances the ability of the charge pump to boost voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0019] Figure 1 A circuit diagram of a cross-coupled charge pump circuit applied to a CIS provided in Embodiment 1 of the present invention;

[0020] Figure 2 for Figure 1 Circuit diagram of SC-CP;

[0021] Figure 3 for Figure 1 The timing control diagram of the cross-coupled charge pump circuit used in CIS;

[0022] Figure 4 is a circuit diagram of an existing traditional charge pump circuit;

[0023] Figure 5 for Figure 4 Timing control diagram of the traditional charge pump circuit;

[0024] Figure 6 Provided in Example 1 of the present invention Figure 4 Output ripple and transient response diagram of traditional charge pump circuit;

[0025] Figure 7 Provided in Example 1 of the present invention Figure 1 The output ripple and transient response diagram of the traditional charge pump circuit. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0029] Example 1

[0030] See also Figure 1 , Figure 2 , shows a specific circuit diagram of a cross-coupled charge pump circuit applied to CIS provided by this embodiment 1. From the functional point of view, the cross-coupled charge pump circuit applied to CIS includes three parts: a charge pump part, an anti-leakage switch part, and a compensation circuit part.

[0031] In simple terms, the charge pump part is used to boost the input signal Vin to obtain the output signal Vout1; the anti-leakage switch part is used to control the on-off of the two auxiliary switches MN7 and MN8 in the charge pump part; the compensation circuit part is used to provide the compensation signal V F .

[0032] Before introducing the circuit structure and principle in detail, see Figure 3 First, the composition of one working cycle T of the cross-coupled charge pump circuit applied to CIS is explained, which includes: an early normal working stage, a mid-term charge recovery stage, and a late waiting stage. In addition, the initial working moment (i.e., the start moment of the first working cycle) is time 0.

[0033] See also Figure 3 For any working cycle T after the initial working moment, a more detailed stage division can be performed:

[0034] ① The normal working stage includes: 6 working sub-stages WT1~WT6:

[0035] WT1 is measured from the start of the normal working phase, and the time span is t1;

[0036] WT2 is calculated from the end time of WT1, and the time span is t2-t1;

[0037] WT3 starts from the end time of WT2, and the time span is t3-t2;

[0038] WT4 starts from the end time of WT3, and the time span is t4-t3;

[0039] WT5 starts from the end time of WT4, and the time span is t5-t4;

[0040] WT6 starts from the end time of WT5, and the time span is T / 2-t5.

[0041] Among them, t1 to t5 represent stage times.

[0042] ②The charge recovery phase includes: 5 working sub-phases RT1~RT5:

[0043] RT1 starts from the end time of WT6, and the time span is t1;

[0044] RT2 starts from the end time of RT1, and the time span is t2-t1;

[0045] RT3 starts from the end time of RT2, and the time span is t3-t2;

[0046] RT4 starts from the end time of RT3, and the time span is t4-t3;

[0047] RT5 starts from the end time of RT4, and the time span is t5-t4.

[0048] ③ The waiting phase starts from the end time of RT5, and the time span is T / 2-t5.

[0049] The following is a circuit structure description of each part of the cross-coupled charge pump circuit used in CIS:

[0050] 1. The charge pump part adopts a cross-coupling design, and its boost path is provided with an auxiliary switch tube MN7, and the down-boost path is provided with an auxiliary switch tube MN8.

[0051] In the first embodiment, the charge pump unit can be designed to include: 4 NMOS transistors MN3-MN6, 2 auxiliary switch transistors MN7-MN8, 8 PMOS transistors MP1-MP8, 2 pump capacitors Cp1-Cp2, and 1 output filter capacitor Cout1.

[0052] See also Figure 1 , the connection method of the above components is as follows:

[0053] The source of MP1 is connected to V F , the gate is connected to the control signal CLK1;

[0054] The gate of MN3 is connected to V F , the drain is connected to the drain of MP1, and the source is grounded;

[0055] The source of MP2 is connected to V F , the gate is connected to the control signal CLK2;

[0056] The gate of MN4 is connected to CLK2, the drain is connected to the drain of MP2, and the source is grounded;

[0057] The source of MN5 is connected to Vin;

[0058] The source of MN7 is connected to the drain of MN5;

[0059] The source of MN6 is connected to Vin, and the gate is connected to the gate of MN7;

[0060] The source of MN8 is connected to the drain of MN6, and the gate is connected to the gate of MN7;

[0061] The source of MP3 is connected to the drain of MN7, and the gate is connected to the gate of MN5;

[0062] The drain of MP4 is connected to the source of MP3, and the source is connected to the substrate of MP3;

[0063] The source of MP5 is connected to the source of MP4, the drain is connected to the gate of MP4, and the gate is connected to the drain of MP4;

[0064] The source of MP6 is connected to the drain of MN8, and the gate is connected to the gate of MN6;

[0065] The drain of MP7 is connected to the source of MP6, and the source is connected to the substrate of MP6;

[0066] The source of MP8 is connected to the source of MP7, the drain is connected to the gate of MP7, and the gate is connected to the drain of MP7;

[0067] One end of Cp1 is connected to the drain of MP1 and MN3, and the other end is connected to the drain of MN7 and the source of MP3;

[0068] One end of Cp2 is connected to the drain of MP2 and MN4, and the other end is connected to the drain of MN8 and the source of MP6;

[0069] One end of Cout1 is connected to the drains of MP3, MP5, MP6, and MP8 and is used to output Vout1; the other end of Cout1 is grounded.

[0070] Among them, MN5, MP3, MP6, and MN6 are cross-coupled;

[0071] The drain of MN7 and the source of MP3 are connected to node A;

[0072] The gate of MN6 and the gate of MP6 are connected to node B;

[0073] The gate of MN5 and the gate of MP3 are connected to node C;

[0074] The drain of MN8 and the source of MP6 are connected to node D;

[0075] MN5, MN7, and MP3 constitute a boost path; MN6, MN8, and MP6 constitute a lower boost path.

[0076] That is, Vin can be boosted to Vout1 when the boost path is connected, or can be boosted to Vout1 when the down-boost path is connected.

[0077] 2. The anti-leakage switch is designed to control the on / off of MN7~MN8:

[0078] In the normal working stage, MN7~MN8 are controlled to be disconnected first and then turned on to ensure the normal voltage boost of the charge pump part;

[0079] In the charge recovery stage, MN7-MN8 are controlled to remain disconnected to avoid reverse flow and reduce output ripple.

[0080] In the waiting stage, MN7~MN8 are controlled to be turned on, waiting for the next working cycle to arrive.

[0081] In the first embodiment, the anti-leakage switch unit may be designed to include: two auxiliary switch tubes MN1 ˜ MN2 , two pumping capacitors Cp3 ˜ Cp4 , and two inverters INV5 ˜ INV6 .

[0082] See also Figure 1 , the connection method of the above components is as follows:

[0083] The source of MN1 is connected to the power supply VDD;

[0084] The source of MN2 is connected to VDD, the gate is connected to the drain of MN1, and the drain is connected to the gate of MN1 and the gate of MN7;

[0085] The input terminal of INV5 is connected to the control signal CLK3;

[0086] The input terminal of INV6 is connected to the control signal CLK4;

[0087] One end of Cp3 is connected to the output end of INV5, and the other end is connected to the drain of MN1;

[0088] One end of Cp4 is connected to the output end of INV6, and the other end is connected to the drain of MN2.

[0089] That is to say, the on or off of MN7 and MN8 is determined by the drain level of MN2.

[0090] 3. The compensation circuit is intended to provide a compensation signal V to the charge pump section. F .

[0091] ①V F In the normal working stage and waiting stage, the power supply is VDD to ensure the normal voltage boost of the charge pump part;

[0092] ②V F In the charge recovery phase, the output signal out is used to perform voltage compensation on the charge pump unit to improve transient response; out>VDD.

[0093] In the first embodiment, the compensation circuit portion may be designed to include: two inverters INV1 ˜ INV2 , two transmission gates G1 ˜ G2 , and one micro cross-coupled charge pump SC-CP.

[0094] See also Figure 1 , the connection method of the above components is as follows:

[0095] The input terminal of INV1 is connected to the control signal CLK5;

[0096] The input end of INV2 is connected to the output end of INV1;

[0097] G1 includes: 1 NMOS tube MN9, 1 PMOS tube MP9; the gate of MN9 is connected to the output end of INV1; the gate of MP9 is connected to the output end of INV2; the source of MN9 and MP9 is connected to the power supply VDD,

[0098] G2 includes: 1 NMOS tube MN10, 1 PMOS tube MP10; the gate of MN9 is connected to the output end of INV1; the gate of MP9 is connected to the output end of INV2; the source of MN9 and MP9 is connected to the output signal out of SC-CP;

[0099] The drains of MN9, MP9, MN10, and MP10 are connected to node F; F is used to output V F .

[0100] In simple terms: in the normal working stage and waiting stage, CLK5 = 0, G1 is turned on, G2 is turned off, and V F is VDD; in the charge recovery phase, CLK5 = 1, G1 is closed, G2 is opened, V F is out.

[0101] The SC-CP is used to generate an output signal out greater than VDD in the charge recovery phase. In the present embodiment 1, the SC-CP can be designed to include: 2 NMOS transistors N1-N2, 6 PMOS transistors P1-P6, 1 output capacitor Cout0, and 2 inverters INV3-INV4.

[0102] See also Figure 2 , the connection method of the above components is as follows:

[0103] The source of N1 is connected to VDD;

[0104] The source of N2 is connected to VDD, the gate is connected to the drain of N1, and the drain is connected to the gate of N1;

[0105] The gate of P1 is connected to the gate of N1, and the source is connected to the drain of N1;

[0106] The drain of P2 is connected to the source of P1, the gate is connected to the drain of P1, and the source is connected to the substrate of P1;

[0107] The source of P3 is connected to the source of P2, the gate is connected to the drain of P2, and the drain is connected to the drain of P1;

[0108] The gate of P4 is connected to the gate of N2, the source is connected to the drain of N2; the drain is connected to the drain of P3;

[0109] The drain of P5 is connected to the source of P4, the gate is connected to the drain of P4, and the source is connected to the substrate of P4;

[0110] The gate of P6 is connected to the drain of P5, the source is connected to the source of P5, and the drain is connected to the source of P4;

[0111] One end of Cp5 is connected to the drain of N1 and the source of P1, and the other end is connected to the output of INV3; the input of INV3 is connected to the control signal CLK1;

[0112] One end of Cp6 is connected to the drain of N2 and the source of P4, and the other end is connected to the output of INV4; the input of INV4 is connected to the control signal CLK2;

[0113] One end of Cout0 is connected to the drain of P1, the gate of P2, the drain of P3, the drain of P4, the drain of P5, and the gate of P6, and is used to output out; the other end of Cout0 is grounded.

[0114] In summary, the cross-coupled charge pump circuit used in CIS has five control signals CLK1 to CLK5. Figure 3 .

[0115] The following describes the working mode of the cross-coupled charge pump circuit applied to CIS in combination with the specific timing control of CLK1 to CLK5:

[0116] ①At the initial working moment, CLK1, CLK2, CLK3, CLK4, and CLK5 are all 0;

[0117] Then we have:

[0118] For the anti-leakage switch part, CLK3=CLK4=0, CLK3 charges Cp3 after being inverted by INV5, CLK4 charges Cp4 after being inverted by INV6, MN1 and MN2 are both turned on, the drains of MN2 and MN1 are 2VDD, and MN7 and MN8 are both turned on.

[0119] For the charge pump section, CLK1 = 0, MP1 is on, MN3 is off, V F MP1 charges Cp1, V A 、V B becomes V F ; CLK2 = 0, MP2 is on, MN4 is off, V F MP2 charges Cp2, V D 、V C becomes V F MN5 and MN6 are turned on, Vin is connected to A and D, V A 、V B 、V C 、V D becomes Vin+V F ; MP3 and MP6 are both disconnected.

[0120] For the compensation circuit, CLK1=CLK2=0, CLK1 charges Cp5 after being inverted by INV3, CLK2 charges Cp6 after being inverted by INV4, N1 and N2 are both turned on, the drain voltage of N1 and N2 is 2VDD, P1 and P4 are turned off, and out has no output; CLK5=0, MN9 and MP9 are both turned on, MN10 and MP10 are both turned off, V F =VDD.

[0121] ② In WT1: CLK1=0, CLK2=1, CLK3=1, CLK4=1, CLK5=0.

[0122] Then we have:

[0123] For the anti-leakage switch part, CLK3=1, INV5 output is 0, Cp3 discharges to INV5, reduces the drain voltage of MN1, and MN2 is disconnected; CLK4=1, INV6 output is 0, Cp4 discharges to INV6, reduces the drain voltage of MN2, and MN1, MN7, and MN8 are all disconnected.

[0124] For the charge pump section, CLK1 = 0, MP1 is on, MN3 is off, V F Charge Cp1, V A 、V B becomes Vin+V FMN6 is turned on, MP6 is turned off; CLK2 = 1, MP2 is turned off, MN4 is turned on, Cp2 discharges to the ground through MN4, V D 、V C Reduced, MN5 is disconnected, MP3 is turned on; Cp1 charges Cout1, A is connected to Vout1 through MP3; Vout1 becomes Vin+V F .

[0125] For the compensation circuit, CLK1=0, CLK3 charges Cp5 after being inverted by INV5, the drain voltage of N1 increases, N2 is turned on, and P4 is turned off; CLK2=1, the output of INV4 is 0, Cp6 discharges to INV4, the drain voltage of N2 decreases, N1 is turned off, and P1 is turned on; the drain voltage of N1 (2VDD) is transferred to out; CLK5=0, MN9 and MP9 are turned on, MN10 and MP10 are turned off, V F =VDD.

[0126] ③ At WT2: CLK1=0, CLK2=1, CLK3=0, CLK4=1, CLK5=0.

[0127] Then we have:

[0128] For the anti-leakage switch part, CLK3=0, INV5 output is 1, Cp3 is charged, the drain voltage of MN1 increases, MN2 is turned on, and VDD charges Cp4; CLK4=1, INV6 output is 0, Cp4 discharges to INV6, the drain voltage of MN2 decreases, and MN1, MN7, and MN8 are all disconnected.

[0129] For the charge pump section, CLK1 = 0, MP1 is on, MN3 is off, V F Charge Cp1, V A 、V B becomes Vin+V F MN6 is turned on, MP6 is turned off; CLK2 = 1, MP2 is turned off, MN4 is turned on, Cp2 discharges to the ground through MN4, V D 、V C Reduced, MN5 is disconnected, MP3 is turned on; Cp1 charges Cout1; A is connected to Vout1 through MP3; Vout1 becomes Vin+V F .

[0130] For the compensation circuit, CLK1=0, CLK1 charges Cp5 after being inverted by INV5, the drain voltage of N1 increases, N2 is turned on, and P4 is turned off; CLK2=1, the output of INV4 is 0, Cp6 discharges to INV4, the drain voltage of N2 decreases, N1 is turned off, and P1 is turned on; the drain voltage of N1 (2VDD) is transferred to out; CLK5=0, MN9 and MP9 are turned on, MN10 and MP10 are turned off, V F =VDD.

[0131] ④ In WT3: CLK1=0, CLK2=0, CLK3=0, CLK4=1, CLK5=0.

[0132] Then we have:

[0133] For the anti-leakage switch part, CLK3=0, INV5 output is 1, Cp3 is charged, the drain voltage of MN1 increases, MN2 is turned on, and VDD charges Cp4; CLK4=1, INV6 output is 0, Cp4 discharges to INV6, the drain voltage of MN2 decreases, and MN1, MN7, and MN8 are all disconnected.

[0134] For the charge pump section, CLK1 = 0, MP1 is on, MN3 is off, V F Charge Cp1, V A 、V B becomes Vin+V F MN6 is on, MP6 is off; CLK2 = 0, MP2 is on, MN4 is off, V F Charge Cp2, V D 、V C rises, MN5 turns on, MP3 turns off, and Cp1 stops discharging to Cout1.

[0135] For the compensation circuit, CLK1=CLK2=0, CLK1 charges Cp5 after being inverted by INV3, CLK2 charges Cp6 after being inverted by INV4, N1 and N2 are both turned on, the drain voltage of N1 and N2 is 2VDD, P1 and P4 are disconnected, and out has no output; CLK5=0, MN9 and MP9 are turned on, MN10 and MP10 are turned off, V F =VDD.

[0136] ⑤In WT4: CLK1=1, CLK2=0, CLK3=0, CLK4=1, CLK5=0.

[0137] Then we have:

[0138] For the anti-leakage switch part, CLK3=0, INV5 output is 1, Cp3 is charged, the drain voltage of MN1 increases, MN2 is turned on, and VDD charges Cp4; CLK4=1, INV6 output is 0, Cp4 discharges to INV6, the drain voltage of MN2 decreases, and MN1, MN7, and MN8 are all disconnected.

[0139] For the charge pump part, CLK1 = 1, MP1 is turned off, MN3 is turned on, Cp1 discharges to the ground through MN3, V A 、V B Lower, MN6 is off, MP6 is on; CLK2 = 0, MP2 is on, MN4 is off, V F Charge Cp2, V D 、V C becomes Vin+V F MN5 is turned on, MP3 is turned off; Cp2 charges Cout1; D is connected to Vout1 through MP6; Vout1 becomes Vin+V F .

[0140] For the compensation circuit, CLK1=1, the output of INV3 is 0, Cp5 discharges to INV3, the drain voltage of N1 decreases, N2 is turned off, and P4 is turned on; CLK2=0, CLK2 charges Cp6 after being inverted by INV4, the drain voltage of N2 increases, N1 is turned on, and P1 is turned off; the drain voltage of N2 (2VDD) is transferred to out through P4; CLK5=0, MN9 and MP9 are turned on, MN10 and MP10 are turned off, V F =VDD.

[0141] ⑥ At WT5: CLK1=1, CLK2=0, CLK3=1, CLK4=1, CLK5=0.

[0142] Then we have:

[0143] For the anti-leakage switch part, CLK3=1, INV5 output is 0, Cp3 discharges to INV5, reduces the drain voltage of MN1, and MN2 is disconnected; CLK4=1, INV6 output is 0, Cp4 discharges to INV6, reduces the drain voltage of MN2, and MN1, MN7, and MN8 are all disconnected.

[0144] For the charge pump part, CLK1 = 1, MP1 is turned off, MN3 is turned on, Cp1 discharges to the ground through MN3, V A 、V B Lower, MN6 is off, MP6 is on; CLK2 = 0, MP2 is on, MN4 is off, V F Charge Cp2, V D 、V C becomes Vin+VF MN5 is turned on, MP3 is turned off; Cp2 charges Cout1; D is connected to Vout1 through MP6; Vout1 becomes Vin+V F .

[0145] For the compensation circuit, CLK1=1, the output of INV3 is 0, Cp5 discharges to INV3, the drain voltage of N1 decreases, N2 is turned off, and P4 is turned on; CLK2=0, CLK2 charges Cp6 after being inverted by INV4, the drain voltage of N2 increases, N1 is turned on, and P1 is turned off; the drain voltage of N2 (2VDD) is transferred to out through P4; CLK5=0, MN9 and MP9 are turned on, MN10 and MP10 are turned off, V F =VDD.

[0146] ⑦ In WT6: CLK1=1, CLK2=0, CLK3=1, CLK4=0, CLK5=0.

[0147] Then we have:

[0148] For the anti-leakage switch part, CLK3=1, the output of INV3 is 0, Cp3 discharges to INV3, the drain voltage of MN1 decreases, and MN2 is disconnected; CLK4=0, CLK4 charges Cp4 after being inverted by INV6, the drain voltage of MN2 increases, and MN1, MN7, and MN8 are all turned on.

[0149] For the charge pump part, CLK1 = 1, MP1 is turned off, MN3 is turned on, Cp1 discharges to the ground through MN3, V A 、V B Lower, MN6 is off, MP6 is on; CLK2 = 0, MP2 is on, MN4 is off, V F Charge Cp2, V D 、V C becomes Vin+V F MN5 is turned on, MP3 is turned off; Cp2 charges Cout1; D is connected to Vout1 through MP6; Vout1 becomes Vin+V F .

[0150] At the same time, Vin charges Cp1 through MN5 and MN7, and the charging value is Vin. Cp1 discharges to the ground through MN3, and the discharge value is V F .

[0151] For the compensation circuit, CLK1=1, the output of INV3 is 0, Cp5 discharges to INV3, the drain voltage of N1 decreases, N2 is turned off, and P4 is turned on; CLK2=0, CLK2 charges Cp6 after being inverted by INV4, the drain voltage of N2 increases, N1 is turned on, and P1 is turned off; the drain voltage of N2 (2VDD) is transferred to out through P4; CLK5=0, MN9 and MP9 are turned on, MN10 and MP10 are turned off, V F =VDD.

[0152] ⑧At RT1: CLK1=1, CLK2=0, CLK3=1, CLK4=1, CLK5=1.

[0153] Then we have:

[0154] For the anti-leakage switch part, CLK3=1, INV5 output is 0, Cp3 discharges to INV5, reduces the drain voltage of MN1, and MN2 is disconnected; CLK4=1, INV6 output is 0, Cp4 discharges to INV6, reduces the drain voltage of MN2, and MN1, MN7, and MN8 are all disconnected.

[0155] For the charge pump part, CLK1 = 1, MP1 is turned off, MN3 is turned on, Cp1 discharges to the ground through MN3, V A 、V B Lower, MN6 is off, MP6 is on; CLK2 = 0, MP2 is on, MN4 is off, V F Charge Cp2, V D 、V C becomes Vin+V F MN5 is turned on, MP3 is turned off; Cp2 charges Cout1; D is connected to Vout1 through MP6; Vout1 becomes Vin+V F .

[0156] For the compensation circuit, CLK1=1, the output of INV3 is 0, Cp5 discharges to INV3, the drain voltage of N1 decreases, N2 is turned off, and P4 is turned on; CLK2=0, CLK2 charges Cp6 after being inverted by INV4, the drain voltage of N2 increases, N1 is turned on, and P1 is turned off; the drain voltage of N2 (2VDD) is transferred to out through P4; CLK5=1, MN9 and MP9 are turned off, MN10 and MP10 are turned on, V F =out.

[0157] ⑨At RT2: CLK1=1, CLK2=0, CLK3=0, CLK4=1, CLK5=1.

[0158] Then we have:

[0159] For the anti-leakage switch part, CLK3=0, INV5 output is 1, Cp3 is charged, the drain voltage of MN1 increases, MN2 is turned on, and VDD charges Cp4; CLK4=1, INV6 output is 0, Cp4 discharges to INV6, the drain voltage of MN2 decreases, and MN1, MN7, and MN8 are all disconnected.

[0160] For the charge pump part, CLK1 = 1, MP1 is turned off, MN3 is turned on, Cp1 discharges to the ground through MN3, V A 、V B Lower, MN6 is off, MP6 is on; CLK2 = 0, MP2 is on, MN4 is off, V F Charge Cp2, V D 、V C becomes Vin+V F MN5 is turned on, MP3 is turned off; Cp2 charges Cout1; D is connected to Vout1 through MP6; Vout1 becomes Vin+V F .

[0161] For the compensation circuit, CLK1=1, the output of INV3 is 0, Cp5 discharges to INV3, the drain voltage of N1 decreases, N2 is turned off, and P4 is turned on; CLK2=0, CLK2 charges Cp6 after being inverted by INV4, the drain voltage of N2 increases, N1 is turned on, and P1 is turned off; the drain voltage of N2 (2VDD) is transferred to out through P4; CLK5=1, MN9 and MP9 are turned off, MN10 and MP10 are turned on, V F =out.

[0162] ⑩At RT3: CLK1=0, CLK2=0, CLK3=0, CLK4=1, CLK5=1.

[0163] Then we have:

[0164] For the anti-leakage switch part, CLK3=0, INV5 output is 1, Cp3 is charged, the drain voltage of MN1 increases, MN2 is turned on, and VDD charges Cp4; CLK4=1, INV6 output is 0, Cp4 discharges to INV6, the drain voltage of MN2 decreases, and MN1, MN7, and MN8 are all disconnected.

[0165] For the charge pump section, CLK1 = 0, MP1 is on, MN3 is off, V F Charge Cp1, V A 、V B becomes Vin+V F MN6 is on, MP6 is off; CLK2 = 0, MP2 is on, MN4 is off, V F Charge Cp2, V D、V C becomes Vin+V F MN5 is turned on, MP3 is turned off; Cp2 charges Cout1; D is connected to Vout1 through MP6; Vout1 becomes Vin+V F .

[0166] For the compensation circuit, CLK1=CLK2=0, CLK1 charges Cp5 after being inverted by INV3, CLK2 charges Cp6 after being inverted by INV4, N1 and N2 are both turned on, the drain voltage of N1 and N2 is 2VDD, P1 and P4 are turned off, and out has no output; CLK5=1, MN9 and MP9 are turned off, MN10 and MP10 are turned on, V F =out.

[0167] At RT4: CLK1=0, CLK2=1, CLK3=0, CLK4=1, CLK5=1.

[0168] Then we have:

[0169] For the anti-leakage switch part, CLK3=0, INV5 output is 1, Cp3 is charged, the drain voltage of MN1 increases, MN2 is turned on, and VDD charges Cp4; CLK4=1, INV6 output is 0, Cp4 discharges to INV6, the drain voltage of MN2 decreases, and MN1, MN7, and MN8 are all disconnected.

[0170] For the charge pump section, CLK1 = 0, MP1 is on, MN3 is off, V F Charge Cp1, V A 、V B becomes Vin+V F MN6 is turned on, MP6 is turned off; CLK2 = 1, MP2 is turned off, MN4 is turned on, Cp2 discharges to the ground through MN4, V D 、V C Reduced, MN5 is disconnected, MP3 is turned on; Cp1 charges Cout1, A is connected to Vout1 through MP3; Vout1 becomes Vin+V F .

[0171] For the compensation circuit, CLK1=0, CLK3 charges Cp5 after being inverted by INV5, the drain voltage of N1 increases, N2 is turned on, and P4 is turned off; CLK2=1, the output of INV4 is 0, Cp6 discharges to INV4, the drain voltage of N2 decreases, N1 is turned off, and P1 is turned on; the drain voltage of N1 (2VDD) is transferred to out; CLK5=1, MN9 and MP9 are turned off, MN10 and MP10 are turned on, V F =out.

[0172] At RT5: CLK1=0, CLK2=1, CLK3=1, CLK4=1, CLK5=1.

[0173] Then we have:

[0174] For the anti-leakage switch part, CLK3=1, INV5 output is 0, Cp3 discharges to INV5, reduces the drain voltage of MN1, and MN2 is disconnected; CLK4=1, INV6 output is 0, Cp4 discharges to INV6, reduces the drain voltage of MN2, and MN1, MN7, and MN8 are all disconnected.

[0175] For the charge pump section, CLK1 = 0, MP1 is on, MN3 is off, V F Charge Cp1, V A 、V B becomes Vin+V F MN6 is turned on, MP6 is turned off; CLK2 = 1, MP2 is turned off, MN4 is turned on, Cp2 discharges to the ground through MN4, V D 、V C Reduced, MN5 is disconnected, MP3 is turned on; Cp1 charges Cout1, A is connected to Vout1 through MP3; Vout1 becomes Vin+V F .

[0176] For the compensation circuit, CLK1=0, CLK3 charges Cp5 after being inverted by INV5, the drain voltage of N1 increases, N2 is turned on, and P4 is turned off; CLK2=1, the output of INV4 is 0, Cp6 discharges to INV4, the drain voltage of N2 decreases, N1 is turned off, and P1 is turned on; the drain voltage of N1 (2VDD) is transferred to out; CLK5=1, MN9 and MP9 are turned off, MN10 and MP10 are turned on, V F =out.

[0177] In the waiting stage: CLK1=0, CLK2=1, CLK3=1, CLK4=0, CLK5=0.

[0178] Then we have:

[0179] For the anti-leakage switch part, CLK3=1, the output of INV3 is 0, Cp3 discharges to INV3, the drain voltage of MN1 decreases, and MN2 is disconnected; CLK4=0, CLK4 charges Cp4 after being inverted by INV6, the drain voltage of MN2 increases, and MN1, MN7, and MN8 are all turned on.

[0180] For the charge pump section, CLK1 = 0, MP1 is on, MN3 is off, V FCharge Cp1, V A 、V B becomes Vin+V F MN6 is turned on, MP6 is turned off; CLK2 = 1, MP2 is turned off, MN4 is turned on, Cp2 discharges to the ground through MN4, V D 、V C Reduced, MN5 is disconnected, MP3 is turned on; Cp1 charges Cout1, A is connected to Vout1 through MP3; Vout1 becomes Vin+V F .

[0181] For the compensation circuit, CLK1=0, CLK3 charges Cp5 after being inverted by INV5, the drain voltage of N1 increases, N2 is turned on, and P4 is turned off; CLK2=1, the output of INV4 is 0, Cp6 discharges to INV4, the drain voltage of N2 decreases, N1 is turned off, and P1 is turned on; the drain voltage of N1 (2VDD) is transferred to out; CLK5=0, MN9 and MP9 are turned on, MN10 and MP10 are turned off, V F =VDD.

[0182] In particular, it should be noted that:

[0183] 1. During the normal working stage and waiting stage:

[0184] When CLK1 = 0, CLK2 = 1, MP3 is turned on, MP6 is turned off, and A is connected to Vout1; if the substrate and source voltages of MP3 are inconsistent at this time, threshold loss will occur; and due to the existence of MP4 and MP5, if V A >Vout1, MP4 is turned on, making the substrate and source voltages of MP3 consistent, eliminating the threshold loss; if Vout1>V A , MP5 is turned on, making the substrate and source voltages of MP3 consistent, eliminating the threshold loss, and Vout1 becomes V A , the value is Vin+V F .

[0185] When CLK1=1, CLK2=0, MP6 is turned on, MP3 is turned off, and D is connected to Vout1. If the substrate and source voltages of MP6 are inconsistent at this time, threshold loss will occur. Due to the existence of MP7 and MP8, if V D > Vout1, MP7 is turned on, making the substrate and source voltages of MP6 consistent, eliminating the threshold loss; if V D <Vout1, MP8 is turned on, making the substrate and source voltages of MP6 consistent, eliminating the threshold loss, and making Vout1 become V D , the value is Vin+V F .

[0186] When CLK1=CLK2=0, MN5 and MN6 are turned on, V A 、V D Vin+V is greater than VDD F If the upper and lower boost paths are still turned on, the voltages of A and D will flow back to Vin, causing charge leakage in Cp1 and Cp2. However, due to the existence of MN7 and MN8, and the control of MN7 and MN8 being cut off through CLK3=1 and CLK4=0, reverse flow back to Vin is avoided to cause charge leakage and increase the output ripple.

[0187] 2. During the recovery phase:

[0188] CLK5 = 1, G1 is closed, G2 is open, and the circuit is equivalent to the parasitic capacitance Cload of the pixel transmission gate gate, which will exchange charge with Cout1, causing Vout1 to drop; but V F Become out: Since out>VDD, the charge pump unit recovery time can be shortened and the transient response can be improved.

[0189] The above process introduces in detail the working process of the cross-coupled charge pump circuit applied to CIS. It can be seen that it can achieve: 1. Normal boost of the charge pump; 2. Avoid reverse reflux to reduce output ripple; 3. Perform voltage compensation on the charge pump part to improve transient response.

[0190] Based on the above circuit design and corresponding timing control, low output ripple and high transient response of the charge pump are achieved.

[0191] Simulation Verification

[0192] This embodiment 1 introduces Figure 4 The existing traditional charge pump circuit and its timing control diagram are as follows Figure 5 shown.

[0193] The existing conventional charge pump circuit includes: 4 NMOS tubes N101-N104, 4 PMOS tubes P101-P104, two pump capacitors Cp101-Cp102, and 1 output filter capacitor Cout2; the specific connection relationship is as follows:

[0194] The source of P101 is connected to the input signal VDD, and the gate is connected to the control signal CLK101;

[0195] The drain of N101 is connected to the drain of P101, the gate is connected to the control signal CLK101, and the source is grounded;

[0196] The source of N102 is connected to the input signal VDD;

[0197] The source of P102 is connected to the drain of N102, and the gate is connected to the gate of N102;

[0198] The source of N103 is connected to the input signal VDD;

[0199] The source of P103 is connected to the drain of N103, the drain is connected to the drain of P102, and the gate is connected to the gate of N103;

[0200] The source of P104 is connected to the input signal VDD, and the gate is connected to the control signal CLK102;

[0201] The drain of N104 is connected to the drain of P104, the gate is connected to the control signal CLK102, and the source is grounded;

[0202] The drain of N102 and the source of P102 are connected to the node A1;

[0203] The gate of N103 and the gate of P103 are connected to the node B1;

[0204] The gate of N102 and the gate of P102 are connected to the node C1;

[0205] The drain of N103 and the source of P103 are connected to the node D1;

[0206] One end of Cp101 is connected to the drain of N101 and P101, and the other end is connected to the drain of N102 and the source of P102;

[0207] One end of Cp102 is connected to the drain of N103 and the source of P103, and the other end is connected to the drain of P104 and N104;

[0208] One end of Cout2 is connected to the drains of P102 and P103 and is used to output the output signal Vout2 , and the other end is grounded.

[0209] The performance of the above-mentioned existing traditional charge pump circuit is compared with that of the above-mentioned cross-coupled charge pump circuit applied to CIS, and the output ripple and transient response of the voltage output of the two are examined.

[0210] The specific simulation conditions are: based on 0.13um CMOS process, cycle is 25MHz, VDD is 2.8V, Vin is 1.8V, Cout1 and Cout2 are both 200pF, and tt process corner simulation is performed at room temperature, and the following is obtained: Figure 6 , Figure 7 Voltage output waveform.

[0211] Depend on Figure 6 , Figure 7 It can be seen that:

[0212] 1. The conventional charge pump circuit can only boost 2.8V to 3.5V, while the cross-coupled charge pump circuit applied to CIS proposed in the present invention can boost 1.8V to 4.5V.

[0213] 2. The output ripple of the traditional charge pump circuit reaches 505uVpp, while the output ripple of the cross-coupled charge pump circuit applied to CIS proposed by the present invention is reduced to 180uVpp; the recovery time of the traditional charge pump circuit is 1.5μs, while the recovery time of the cross-coupled charge pump circuit applied to CIS proposed by the present invention is 46ns.

[0214] The above results show that compared with the traditional charge pump circuit, the present invention: 1. The output ripple is greatly reduced and the recovery time is also greatly shortened (the transient response is greatly improved); 2. While reducing the output ripple and improving the transient response, the charge pump's ability to boost voltage is also improved.

[0215] Example 2

[0216] This embodiment 2 discloses a cross-coupled charge pump module applied to CIS, which adopts the layout of the cross-coupled charge pump circuit applied to CIS disclosed in embodiment 1. The mode of packaging into a module makes it easier to promote and apply the above circuit.

[0217] This embodiment 2 also discloses a CIS module, which includes the cross-coupled charge pump module for CIS disclosed above. Integrating the cross-coupled charge pump module for CIS into the CIS module also facilitates the promotion and application of the circuit.

[0218] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0219] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A cross-coupled charge pump circuit for CIS, characterized in that: One working cycle T includes: the normal working stage in the early stage, the charge recovery stage in the middle stage, and the waiting stage in the late stage; it includes: A charge pump unit, which is used to boost the input signal Vin to obtain an output signal Vout1; the charge pump unit is a cross-coupled design, and its boost path is provided with an auxiliary switch tube MN7, and its lower boost path is provided with an auxiliary switch tube MN8; The anti-leakage switch part is used to control the on-off of MN7~MN8; in the normal working stage, MN7~MN8 is controlled to be disconnected first and then turned on to ensure the normal boost of the charge pump part; in the charge recovery stage, MN7~MN8 is controlled to remain disconnected to avoid reverse backflow and reduce output ripple; in the waiting stage, MN7~MN8 is controlled to be turned on to wait for the next working cycle; as well as A compensation circuit section, which is used to provide a compensation signal V to the charge pump section F ; Among them, V F In the normal working stage and waiting stage, the power supply VDD is used to ensure the normal voltage boost of the charge pump part; V F In the charge recovery stage, the output signal is out, so as to perform voltage compensation on the charge pump part to improve the transient response; out>VDD; The compensation circuit section includes: 2 inverters INV1-INV2, 2 transmission gates G1-G2, and 1 micro cross-coupled charge pump SC-CP; The input terminal of INV1 is connected to the control signal CLK5; The input end of INV2 is connected to the output end of INV1; G1 includes: 1 NMOS tube MN9, 1 PMOS tube MP9; the gate of MN9 is connected to the output end of INV1; the gate of MP9 is connected to the output end of INV2; the source of MN9 and MP9 is connected to the power supply VDD, G2 includes: 1 NMOS tube MN10, 1 PMOS tube MP10; the gate of MN10 is connected to the output end of INV2; the gate of MP10 is connected to the output end of INV1; the source of MN9 and MP9 is connected to the output signal out of SC-CP; The drains of MN9, MP9, MN10, and MP10 are connected to node F; F is used to output V F ; Among them, in the normal working stage and waiting stage, CLK5=0, G1 is turned on, G2 is turned off, V F is VDD; In the charge recovery phase, CLK5 = 1, G1 is closed, G2 is opened, and V F is out; SC-CP includes: 2 NMOS tubes N1~N2, 6 PMOS tubes P1~P6, 1 output capacitor Cout0, and 2 inverters INV3~INV4; The source of N1 is connected to VDD; The source of N2 is connected to VDD, the gate is connected to the drain of N1, and the drain is connected to the gate of N1; The gate of P1 is connected to the gate of N1, and the source is connected to the drain of N1; The drain of P2 is connected to the source of P1, the gate is connected to the drain of P1, and the source is connected to the substrate of P1; The source of P3 is connected to the source of P2, the gate is connected to the drain of P2, and the drain is connected to the drain of P1; The gate of P4 is connected to the gate of N2, the source is connected to the drain of N2; the drain is connected to the drain of P3; The drain of P5 is connected to the source of P4, the gate is connected to the drain of P4, and the source is connected to the substrate of P4; The gate of P6 is connected to the drain of P5, the source is connected to the source of P5, and the drain is connected to the source of P4; One end of Cp5 is connected to the drain of N1 and the source of P1, and the other end is connected to the output of INV3; the input of INV3 is connected to the control signal CLK1; One end of Cp6 is connected to the drain of N2 and the source of P4, and the other end is connected to the output of INV4; the input of INV4 is connected to the control signal CLK2; One end of Cout0 is connected to the drain of P1, the gate of P2, the drain of P3, the drain of P4, the drain of P5, and the gate of P6, and is used to output out; the other end of Cout0 is grounded.

2. The cross-coupled charge pump circuit for CIS according to claim 1, characterized in that: The charge pump unit includes: 4 NMOS transistors MN3-MN6, 2 auxiliary switch transistors MN7-MN8, 8 PMOS transistors MP1-MP8, 2 pump capacitors Cp1-Cp2, and 1 output filter capacitor Cout1; The source of MP1 is connected to V F , the gate is connected to the control signal CLK1; The gate of MN3 is connected to V F , the drain is connected to the drain of MP1, and the source is grounded; The source of MP2 is connected to V F , the gate is connected to the control signal CLK2; The gate of MN4 is connected to CLK2, the drain is connected to the drain of MP2, and the source is grounded; The source of MN5 is connected to Vin; The source of MN7 is connected to the drain of MN5; The source of MN6 is connected to Vin, and the gate is connected to the gate of MN7; The source of MN8 is connected to the drain of MN6, and the gate is connected to the gate of MN7; The source of MP3 is connected to the drain of MN7, and the gate is connected to the gate of MN5; The drain of MP4 is connected to the source of MP3, and the source is connected to the substrate of MP3; The source of MP5 is connected to the source of MP4, the drain is connected to the gate of MP4, and the gate is connected to the drain of MP4; The source of MP6 is connected to the drain of MN8, and the gate is connected to the gate of MN6; The drain of MP7 is connected to the source of MP6, and the source is connected to the substrate of MP6; The source of MP8 is connected to the source of MP7, the drain is connected to the gate of MP7, and the gate is connected to the drain of MP7; One end of Cp1 is connected to the drain of MP1 and MN3, and the other end is connected to the drain of MN7 and the source of MP3; One end of Cp2 is connected to the drain of MP2 and MN4, and the other end is connected to the drain of MN8 and the source of MP6; One end of Cout1 is connected to the drains of MP3, MP5, MP6, and MP8, and is used to output Vout1; the other end of Cout1 is grounded; Among them, MN5, MP3, MP6, and MN6 are cross-coupled; The drain of MN7 and the source of MP3 are connected to node A; The gate of MN6 and the gate of MP6 are connected to node B; The gate of MN5 and the gate of MP3 are connected to node C; The drain of MN8 and the source of MP6 are connected to node D; MN5, MN7, and MP3 constitute a boost path; MN6, MN8, and MP6 constitute a lower boost path.

3. The cross-coupled charge pump circuit for CIS according to claim 2, characterized in that: The anti-leakage switch unit includes: two auxiliary switch tubes MN1-MN2, two pump capacitors Cp3-Cp4, and two inverters INV5-INV6; The source of MN1 is connected to the power supply VDD; The source of MN2 is connected to VDD, the gate is connected to the drain of MN1, and the drain is connected to the gate of MN1 and the gate of MN7; The input terminal of INV5 is connected to the control signal CLK3; The input terminal of INV6 is connected to the control signal CLK4; One end of Cp3 is connected to the output end of INV5, and the other end is connected to the drain of MN1; One end of Cp4 is connected to the output end of INV6, and the other end is connected to the drain of MN2.

4. The cross-coupled charge pump circuit for CIS according to claim 3, characterized in that: The initial working time of the cross-coupled charge pump circuit applied to the CIS is time 0; In any working cycle T after the initial working moment: The normal working phase includes: 6 working sub-phases WT1~WT6; The charge recovery phase includes: 5 working sub-phases RT1~RT5; Among them, WT1 is measured from the beginning of the normal working phase, and the time span is t1; WT2 is calculated from the end time of WT1, and the time span is t2-t1; WT3 starts from the end time of WT2, and the time span is t3-t2; WT4 starts from the end time of WT3, and the time span is t4-t3; WT5 starts from the end time of WT4, and the time span is t5-t4; WT6 starts from the end time of WT5, and the time span is T / 2-t5; RT1 starts from the end time of WT6, and the time span is t1; RT2 starts from the end time of RT1, and the time span is t2-t1; RT3 starts from the end time of RT2, and the time span is t3-t2; RT4 starts from the end time of RT3, and the time span is t4-t3; RT5 starts from the end time of RT4, and the time span is t5-t4; The waiting phase starts from the end time of RT5 and the time span is T / 2-t5.

5. The cross-coupled charge pump circuit for CIS according to claim 4, characterized in that: At the initial working moment, CLK1, CLK2, CLK3, CLK4, and CLK5 are all 0.

6. The cross-coupled charge pump circuit for CIS according to claim 5, characterized in that: In WT1, WT2, and WT3, CLK1=0; in WT4, WT5, WT6, RT1, and RT2, CLK1=1; in RT3, RT4, RT5, and the waiting phase, CLK1=0; In WT1 and WT2, CLK2=1; in WT3, WT4, WT5, WT6, RT1, RT2, and RT3, CLK2=0; in RT4, RT5, and the waiting phase, CLK2=1; At WT1, CLK3=1; at WT2, WT3, WT4, CLK3=0; at WT5, WT6, RT1, CLK3=1; at RT2, RT3, RT4, CLK3=0; at RT5, waiting stage, CLK3=1; In WT1, WT2, WT3, WT4, WT5, CLK4=1; in WT6, CLK4=0; in RT1, RT2, RT3, RT4, RT5, CLK4=1; in the waiting stage, CLK4=0; In WT1, WT2, WT3, WT4, WT5, and WT6, CLK5=0; in RT1, RT2, RT3, RT4, and RT5, CLK5=1; in the waiting phase, CLK5=0.

7. A cross-coupled charge pump module for CIS, characterized in that: It adopts the layout of the cross-coupled charge pump circuit applied to CIS as described in any one of claims 1-6.

8. A CIS module, characterized in that: It integrates the cross-coupled charge pump module applied to CIS as claimed in claim 7.

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