Envelope detection circuit and electronic tag

Abstract

The embodiment of the invention discloses an envelope detection circuit and an electronic tag, the envelope detection circuit comprises an antenna, a detection module, a load module and a power detection module, the input end of the detection module is used as the input end of the envelope detection circuit to be connected with the antenna, and the output end of the detection module is used as the output end of the envelope detection circuit to be connected with a post-stage circuit. The detection module is used for demodulating an envelope signal on a carrier; the input end of the power detection module is connected with the output end of the detection module, the output end of the power detection module is connected with the control end of the load module, and the power detection module is used for generating a control signal according to the power of the carrier so as to control different loads in the load module to access the output end of the detection module. According to the scheme, the conversion gain of the detection circuit can be reduced under high power, so that the output amplitude of the envelope signal output by the detection module is reduced, the phenomenon that the envelope signal is saturated and distorted after being amplified by a post-stage circuit is avoided, and meanwhile, the power range of the signal capable of being demodulated is also expanded.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of electronic tags, and in particular to an envelope detection circuit and an electronic tag. Background Art

[0002] With the development of Internet of Things technology, electronic tags have become an important part of the Internet of Things.

[0003] For electronic tags with high demodulation sensitivity, a baseband amplifier circuit needs to be added after the envelope detection circuit in the demodulation circuit of the tag to amplify the weak envelope signal output by the envelope detection circuit, so as to effectively compare the low-distortion baseband digital signal through the hysteresis comparator. For such high-sensitivity electronic tags, the power input dynamic range is not less than 40db. Under such a large dynamic range, the envelope signal demodulated by the conventional envelope detection circuit is prone to saturation distortion after passing through the baseband amplifier circuit, which reduces the communication performance. Summary of the invention

[0004] The embodiment of the present invention provides an envelope detection circuit and an electronic tag to prevent the envelope signal demodulated by the envelope detection circuit from being saturated and distorted after passing through a baseband amplification circuit.

[0005] According to one aspect of the present invention, there is provided an envelope detection circuit, comprising: an antenna, a detection module, a load module and a power detection module;

[0006] The input end of the detection module is connected to the antenna as the input end of the envelope detection circuit, and the output end of the detection module is connected to the subsequent circuit as the output end of the envelope detection circuit. The detection module is used to demodulate the envelope signal on the carrier;

[0007] The input end of the power detection module is connected to the output end of the detection module, and the output end of the power detection module is connected to the control end of the load module. The power detection module is used to generate a control signal according to the power of the carrier to control different loads in the load module to connect to the output end of the detection module.

[0008] Optionally, the load module includes a first load unit and a second load unit, and the output end of the power detection module includes a first output end and a second output end;

[0009] The first end of the first load unit is connected to a fixed voltage, the second end of the first load unit is connected to the output end of the detection module, and the control end of the first load unit is connected to the first output end of the power detection module;

[0010] The first end of the second load unit is connected to the fixed voltage, the second end of the second load unit is connected to the output end of the detection module, and the control end of the second load unit is connected to the second output end of the power detection module;

[0011] The first load unit and the second load unit are turned on in a time-sharing manner.

[0012] Optionally, the first load unit includes a first load and a first switch subunit, the first end of the first load is connected to the fixed voltage, the second end of the first load is connected to the first end of the first switch subunit, the second end of the first switch subunit is connected to the output end of the detection module, and the control end of the first switch subunit is connected to the first output end of the power detection module;

[0013] The second load unit comprises a second load and a second switch subunit, the first end of the second load is connected to the fixed voltage, the second end of the second load is connected to the first end of the second switch subunit, the second end of the second switch subunit is connected to the output end of the detection module, and the control end of the second switch subunit is connected to the second output end of the power detection module;

[0014] The impedance of the first load is smaller than the impedance of the second load.

[0015] Optionally, the first switch subunit includes a first transistor, and the second switch subunit includes a second transistor, the gate of the first transistor is connected to the first output end of the power detection module, the first electrode of the first transistor is connected to the second end of the first load, and the second electrode of the first transistor is connected to the output end of the detection module; the gate of the second transistor is connected to the second output end of the power detection module, the first electrode of the second transistor is connected to the second end of the second load, and the second electrode of the second transistor is connected to the output end of the detection module;

[0016] The first load includes a first resistor, and the second load includes a second resistor. The first end of the first resistor is connected to the fixed voltage, and the second end of the first resistor is connected to the first electrode of the first transistor. The first end of the second resistor is connected to the fixed voltage, and the second end of the second resistor is connected to the first electrode of the second transistor.

[0017] Optionally, the first switch subunit includes a first transistor, and the second switch subunit includes a second transistor, the gate of the first transistor is connected to the first output end of the power detection module, the first electrode of the first transistor is connected to the second end of the first load, and the second electrode of the first transistor is connected to the output end of the detection module; the gate of the second transistor is connected to the second output end of the power detection module, the first electrode of the second transistor is connected to the second end of the second load, and the second electrode of the second transistor is connected to the output end of the detection module;

[0018] The first load includes a third transistor, and the second load includes a fourth transistor. The first electrode of the third transistor is connected to the fixed voltage, the second electrode of the third transistor is connected to the first electrode of the first transistor, the gate of the third transistor is connected to the second electrode of the third transistor, the first electrode of the fourth transistor is connected to the fixed voltage, the second electrode of the fourth transistor is connected to the first electrode of the second transistor, and the gate of the fourth transistor is connected to the second electrode of the fourth transistor.

[0019] Optionally, the power detection module further includes a trigger end, the trigger end of the power detection module receives a power detection signal, and the power detection module is further configured to latch the power of the carrier in response to the power detection signal before a downlink signaling reception phase.

[0020] Optionally, the power detection module includes a comparison unit, a trigger unit and a signal processing unit;

[0021] The first input end of the comparison unit is connected to the output end of the detection module, the second input end of the comparison unit is connected to the reference voltage, the output end of the comparison unit is connected to the input end of the trigger unit, the control end of the trigger unit is connected to the power detection signal as the trigger end of the power detection module, the output end of the trigger unit is respectively connected to the input end of the signal processing unit and the control end of the first load unit, the output end of the signal processing unit is connected to the control end of the second load unit, the trigger unit is used to output a first control signal at the edge of the power detection signal according to the comparison value of the comparison unit, and lock the first control signal before the next same edge of the power detection signal comes, and the signal processing unit is used to convert the first control signal into a second control signal; wherein, the first control signal and the second control signal are opposite.

[0022] The comparison unit comprises a voltage comparator, a first input end of the voltage comparator is connected to the output end of the detection module, a second input end of the voltage comparator is connected to the reference voltage, and an output end of the voltage comparator serves as an output end of the comparison unit;

[0023] The trigger unit includes a trigger, and the signal processing unit includes an inverter. The clock end of the trigger is connected to the power detection signal, the input end of the trigger is connected to the output end of the voltage comparator, the output end of the trigger is connected to the input end of the inverter, and the output end of the inverter serves as the output end of the signal processing unit.

[0024] Optionally, the detection module includes a negative envelope detector.

[0025] According to another aspect of the present invention, an electronic tag is provided. The electronic tag includes the envelope detection circuit provided by any embodiment of the present invention.

[0026] The technical solution provided by the embodiment of the present invention detects the power of the carrier input by setting a power detection module to determine whether the current carrier input is in a high-power range or a low-power range, thereby adaptively adjusting the load at the output end of the detection module. Compared with the solution in the prior art that uses an envelope detection circuit with a fixed conversion gain to demodulate the input carrier, this solution can reduce the conversion gain of the detection circuit at high power, thereby reducing the output amplitude of the envelope signal output by the detection module, avoiding the phenomenon of saturation distortion of the envelope signal after amplification by the subsequent circuit, and at the same time expanding the power range of the signal that can be demodulated.

[0027] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A schematic structural diagram of an envelope detection circuit provided by an embodiment of the present invention;

[0030] Figure 2 A schematic structural diagram of another envelope detection circuit provided by an embodiment of the present invention;

[0031] Figure 3 A schematic structural diagram of another envelope detection circuit provided by an embodiment of the present invention;

[0032] Figure 4 A schematic structural diagram of another envelope detection circuit provided by an embodiment of the present invention;

[0033] Figure 5 A schematic structural diagram of another envelope detection circuit provided by an embodiment of the present invention;

[0034] Figure 6 A schematic structural diagram of another envelope detection circuit provided by an embodiment of the present invention;

[0035] Figure 7 A schematic structural diagram of another envelope detection circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] Figure 1 A schematic diagram of the structure of an envelope detection circuit provided by an embodiment of the present invention, referring to Figure 1 The envelope detection circuit provided in this embodiment includes an antenna 100, a detection module 110, a load module 120 and a power detection module 130. The input end of the detection module 110 is connected to the antenna 100 as the input end of the envelope detection circuit, and the output end of the detection module 110 is connected to the post-stage circuit 140 as the output end of the envelope detection circuit. The detection module 110 is used to demodulate the envelope signal on the carrier; the input end of the power detection module 130 is connected to the output end of the detection module 110, and the output end of the power detection module 130 is connected to the control end of the load module 120. The power detection module 130 is used to generate a control signal according to the power of the carrier to control different loads in the load module 120 to be connected to the output end of the detection module 110.

[0039] Specifically, the carrier with signaling modulation sent by the cellular base station can be received through the antenna 100, and the detection module 110 can decode the envelope signal modulated on the carrier. The detection module 110 transmits the demodulated envelope signal to the power detection module 130, and the power detection module 130 generates different control signals according to the power of the carrier. Here, the level of the envelope signal output by the detection module 110 is monotonically related to the power of the carrier input thereto. For example, when the carrier power is large, the level of the envelope signal is low. The power detection module 130 generates a control signal to control the load module 120 to connect a heavy load to the output end of the detection module 110, which is equivalent to reducing the conversion gain of the detection module 110, thereby reducing the output amplitude of the envelope signal, and avoiding obvious saturation distortion after amplification by the post-stage circuit 140. Among them, the post-stage circuit 140 can be a baseband amplifier circuit. When the carrier power is small, the level of the envelope signal is high, and the power detection module 130 generates a control signal to control the load module 120 to connect a light load to the output end of the detection module 110 to increase the output amplitude of the envelope signal, improve signal recognition, and avoid cutoff distortion.

[0040] The power of the carrier input may be determined to be high power or low power according to the interval in which the power of the carrier input is located. In other words, the power detection module 130 may determine the power of the carrier input by detecting the interval in which the level of the envelope signal is located.

[0041] The technical solution provided by the embodiment of the present invention detects the power of the carrier input by setting the power detection module 130 to determine whether the current carrier input is in a high power range or a low power range, thereby adaptively adjusting the load at the output end of the detection module 110. Compared with the solution in the prior art that uses an envelope detection circuit with a fixed conversion gain to demodulate the input carrier, this solution can reduce the conversion gain of the detection circuit at high power, thereby reducing the output amplitude of the envelope signal output by the detection module 110, avoiding the phenomenon of saturation distortion of the envelope signal after amplification by the subsequent circuit 140, and at the same time expanding the power range of the signal that can be demodulated.

[0042] Figure 2 A schematic diagram of another envelope detection circuit provided by an embodiment of the present invention, referring to Figure 2On the basis of the above embodiment, optionally, the load module 120 includes a first load unit 121 and a second load unit 122, the output end of the power detection module 130 includes a first output end and a second output end, the first end of the first load unit 121 is connected to the fixed voltage VCC, the second end of the first load unit 121 is connected to the output end of the detection module 110, and the control end of the first load unit 121 is connected to the first output end of the power detection module 130; the first end of the second load unit 122 is connected to the fixed voltage VCC, the second end of the second load unit 122 is connected to the output end of the detection module 110, and the control end of the second load unit 122 is connected to the second output end of the power detection module 130; wherein the first load unit 121 and the second load unit 122 are turned on in time sharing.

[0043] Specifically, the first load unit 121 and the second load unit 122 include different loads, and the power detection module 130 generates different control signals according to the power size of the carrier, and outputs them from the first output end and the second output end respectively. For example, the first output end of the power detection module 130 outputs the first control signal CS1 to the control end of the first load unit 121, and the second output end of the power detection module 130 outputs the second control signal CS2 to the control end of the second load unit 122. The first load unit 121 and the second load unit 122 are respectively turned on in time-sharing in response to the first control signal CS1 and the second control signal CS2 corresponding to each other, that is, when the first load unit 121 is turned on, the second load unit 122 is turned off; when the second load unit 122 is turned on, the first load unit 121 is turned off, so that different loads are connected to the output end of the detection module 110.

[0044] In an optional implementation manner provided in this embodiment, the load in each load unit can be selectively connected to the output end of the detection module 110 by means of a switch. Figure 3 A schematic diagram of another envelope detection circuit provided by an embodiment of the present invention, referring to Figure 3On the basis of the above embodiment, optionally, the first load unit 121 includes a first load 1201 and a first switch subunit 1202, the first end of the first load 1201 is connected to the fixed voltage VCC, the second end of the first load 1201 is connected to the first end of the first switch subunit 1202, the second end of the first switch subunit 1202 is connected to the output end of the detection module 110, and the control end of the first switch subunit 1202 is connected to the first output end of the power detection module 130; the second load unit 122 includes a second load 1203 and a second switch subunit 1204, the first end of the second load 1203 is connected to the fixed voltage VCC, the second end of the second load 1203 is connected to the first end of the second switch subunit 1204, the second end of the second switch subunit 1204 is connected to the output end of the detection module 110, and the control end of the second switch subunit 1204 is connected to the second output end of the power detection module 130.

[0045] The impedance of the first load 1201 is smaller than the impedance of the second load 1203. When the first switch subunit 1202 is turned on in response to the first control signal CS1 output by the power detection module 130, the first load 1201 is connected to the output end of the detection module 110, which is equivalent to connecting a light load to the detection module 110, so that the detection module 110 increases the output amplitude of the envelope signal. When the second switch subunit 1204 is turned on in response to the second control signal CS2 output by the power detection module 130, the second load 1203 is connected to the output end of the detection module 110, which is equivalent to connecting a heavy load to the detection module 110, so that the detection module 110 reduces the output amplitude of the envelope signal.

[0046] In one implementation, the load may include a resistor, and the switch subunit may include a transistor. Figure 4 A schematic diagram of another envelope detection circuit provided by an embodiment of the present invention, referring to Figure 4Optionally, the first switch subunit 1202 includes a first transistor M1, the second switch subunit 1204 includes a second transistor M2, the gate of the first transistor M1 is connected to the first output end of the power detection module 130, the first electrode of the first transistor M1 is connected to the second end of the first load 1201, and the second electrode of the first transistor M1 is connected to the output end of the detection module 110; the gate of the second transistor M2 is connected to the second output end of the power detection module 130, the first electrode of the second transistor M2 is connected to the second end of the second load 1203, and the second electrode of the second transistor M2 is connected to the output end of the detection module 110; the first load 1201 includes a first resistor R1, the second load 1203 includes a second resistor R2, the first end of the first resistor R1 is connected to the fixed voltage VCC, the second end of the first resistor R1 is connected to the first electrode of the first transistor M1, the first end of the second resistor R2 is connected to the fixed voltage VCC, and the second end of the second resistor R2 is connected to the first electrode of the second transistor M2.

[0047] The channel types of the first transistor M1 and the second transistor M2 may be the same or different, and may be specifically set according to the control signal output by the power detection module 130. The resistance value of the first resistor R1 is smaller than the resistance value of the second resistor R2.

[0048] In one implementation, the load may include a diode biased load, and the switch subunit may include a transistor. Figure 5 A schematic diagram of another envelope detection circuit provided by an embodiment of the present invention, referring to Figure 5 Optionally, the first switch subunit 1202 includes a first transistor M1, and the second switch subunit 1204 includes a second transistor M2. The gate of the first transistor M1 is connected to the first output terminal of the power detection module 130, the first electrode of the first transistor M1 is connected to the second terminal of the first load 1201, and the second electrode of the first transistor M1 is connected to the output terminal of the detection module 110; the gate of the second transistor M2 is connected to the second output terminal of the power detection module 130, the first electrode of the second transistor M2 is connected to the second terminal of the second load 1203, and the second electrode of the second transistor M2 is connected to the output terminal of the detection module 110. The first load 1201 includes a third transistor M3, and the second load 1203 includes a fourth transistor M4. The first electrode of the third transistor M3 is connected to the fixed voltage VCC, the second electrode of the third transistor M3 is connected to the first electrode of the first transistor M1, the gate of the third transistor M3 is connected to the second electrode of the third transistor M3, the first electrode of the fourth transistor M4 is connected to the fixed voltage VCC, the second electrode of the fourth transistor M4 is connected to the first electrode of the second transistor M2, and the gate of the fourth transistor M4 is connected to the second electrode of the fourth transistor M4.

[0049] The gate and the second electrode of the third transistor M3 are short-circuited to form a diode structure, and the gate and the second electrode of the fourth transistor M4 are short-circuited to form a diode structure. Due to the nonlinear characteristics of the diode bias load, its current changes exponentially with the voltage, which can better suppress the output amplitude of the envelope signal under high power.

[0050] Figure 6 A schematic diagram of another envelope detection circuit provided by an embodiment of the present invention, referring to Figure 6 On the basis of the above embodiments, optionally, the power detection module 130 also includes a trigger end, the trigger end of the power detection module 130 receives the power detection signal PS1, and the power detection module 130 is also used to respond to the power detection signal PS1 to latch the power of the carrier before the downlink signaling reception phase.

[0051] Specifically, when the tag chip is ready to receive the downlink signaling sent by the cellular base station, the power of the carrier can be detected by the power detection signal PS1 sent by the digital baseband module inside the tag chip to ensure that the subsequent signal reception process proceeds smoothly. Among them, the digital baseband module is mainly responsible for processing digital signals, covering many key operations such as signal encoding, decoding, modulation, and demodulation. When the system determines that it is about to enter the downlink signaling reception stage, the control logic inside the digital baseband module is started, so that it generates a pulse signal with a specific frequency, amplitude and width, that is, the power detection signal PS1. Under the action of the power detection signal PS1, the power detection module 130 detects the power of the carrier and latches the detected power value to prevent the downlink signaling from causing the power detection value to flip randomly (the level of the carrier modulated by the downlink signaling shows high and low changes, and the level of the envelope signal demodulated by the detection module 110 also changes high and low, resulting in the detected power value constantly flipping), affecting the control signal output by the power detection module 130, which is conducive to improving the stability of load access.

[0052] Continue to refer Figure 6The power detection module includes a comparison unit 1301, a trigger unit 1302 and a signal processing unit 1303. The first input end of the comparison unit 1301 is connected to the output end of the detection module 110, the second input end of the comparison unit 1301 is connected to the reference voltage VREF, the output end of the comparison unit 1301 is connected to the input end of the trigger unit 1302, the control end of the trigger unit 1302 is connected to the power detection signal PS1 as the trigger end of the power detection module 130, the output end of the trigger unit 1302 is respectively connected to the input end of the signal processing unit 1303 and the control end of the first load unit 121, the output end of the signal processing unit 1303 is connected to the control end of the second load unit 122, the trigger unit 1302 is used to output the first control signal CS1 according to the comparison value of the comparison unit 1301 at the edge of the power detection signal PS1, and lock the first control signal CS1 before the next same edge of the power detection signal PS1 comes, and the signal processing unit 1303 is used to convert the first control signal CS1 into the second control signal CS2.

[0053] Specifically, before the tag chip is ready to receive the downlink signaling sent by the cellular base station, the trigger unit 1302 receives the power detection signal PS1, and at the edge (rising edge or falling edge) of the power detection signal PS1, the comparison value after the comparison between the level output by the detection module 110 and the level of the reference voltage VREF by the comparison unit 1301 is output to form a first control signal CS1, and the first control signal CS1 is latched unchanged. The second control signal CS1 converted by the signal processing unit 1303 also remains unchanged. When the next same edge of the power detection signal PS1 comes, the power of the carrier is detected here, and the trigger unit PS1 refreshes the previous comparison value to form a new first control signal CS1. The new first control signal CS1 can be the same as the previous first control signal CS1 or different.

[0054] The first control signal CS1 and the second control signal CS2 are different. For example, the first control signal CS1 and the second control signal CS2 are opposite, so that the first load unit 121 and the second load unit 122 are turned on in a time-sharing manner.

[0055] Of course, in other embodiments, if the channel types of the first transistor M1 included in the first switch sub-unit 1202 and the second transistor M2 included in the second switch sub-unit 1204 are different, the first control signal CS1 and the second control signal CS2 may also be the same.

[0056] Figure 7 A schematic diagram of another envelope detection circuit provided by an embodiment of the present invention, referring to Figure 7On the basis of the above embodiment, optionally, the comparison unit 1301 includes a voltage comparator U1, a first input end of the voltage comparator U1 is connected to the output end of the detection module 110, a second input end of the voltage comparator U1 is connected to the reference voltage VREF, and the output end of the voltage comparator U1 is used as the output end of the comparison unit 1301. The trigger unit 1302 includes a trigger U2, and the signal processing unit 1303 includes an inverter U3, a clock end of the trigger U2 is connected to the power detection signal PS1, an input end of the trigger U2 is connected to the output end of the voltage comparator U1, an output end of the trigger U2 is connected to the input end of the inverter U3, and an output end of the inverter U3 is used as the output end of the signal processing unit 1303.

[0057] Optionally, the detection module 110 may include a negative envelope detector, the waveform of the envelope signal output by the detection module 110 is the inverse of the envelope waveform on the carrier. The greater the carrier power, the lower the level of the envelope signal output by the detection module 110.

[0058] refer to Figure 7 Taking the detection module 110 including a negative envelope detector as an example, the specific working principle of the envelope detection circuit provided in this embodiment is as follows:

[0059] Before the tag chip is ready to receive the downlink signaling sent by the cellular base station, the trigger U2 receives the power detection signal PS1, and outputs the comparison value between the level of the signal output by the detection module 110 (the signal output by the detection module 110 is the signal corresponding to the carrier that is not modulated by the downlink signaling) and the level of the reference voltage VREF at the falling edge of the power detection signal PS1. Before the next falling edge of the power detection signal PS1, the state of the trigger 2 will not change, thereby keeping the fixed comparison value output unchanged, that is, the first control signal CS1 will not change. The first control signal CS1 is formed into the second control signal CS2 after passing through the inverter U3. When the tag chip receives the downlink signaling sent by the cellular base station, the antenna 100 receives the modulated carrier input, and the detection module 110 demodulates the corresponding envelope signal. Since the trigger U2 has latched the power of the envelope signal, even if the output of the voltage comparator U1 changes, the first control signal CS1 remains unchanged.

[0060] When the carrier input power is relatively low, the level of the envelope signal output by the detection module 110 is higher than the level of the reference voltage VREF, and the voltage comparator U1 outputs a high level, that is, the first control signal CS1 output by the trigger U2 is a high level, and the second control signal CS2 output by the inverter U3 is a low level. Therefore, the first transistor M1 is turned on, the second transistor M2 is turned off (the first transistor M1 and the second transistor M2 are both N-type transistors), and the first resistor R1 (the first load 1201) is connected to the output end of the detection module 110. Since the first resistor R1 is a light load, the envelope signal output by the detection module 110 has a relatively large output amplitude.

[0061] When the carrier input power is large, the level of the envelope signal output by the detection module 110 is lower than the level of the reference voltage VREF, and the voltage comparator U1 outputs a low level, that is, the first control signal CS1 output by the trigger U2 is a low level, and the second control signal CS2 output by the inverter U3 is a high level. Therefore, the first transistor M1 is turned off, the second transistor M2 is turned on, and the second resistor R2 (the second load 1203) is connected to the output end of the detection module 110. Since the second resistor R2 is a heavy load, the envelope signal output by the detection module 110 has a smaller output amplitude.

[0062] The technical solution provided by the embodiment of the present invention detects the input power of the carrier, and when the input power is small, controls the load module 120 to access a light load through the power detection module 130, so that the detection module 110 can have a larger signal output amplitude under low power input; when the input power is large, controls the load module 120 to access a heavy load through the power detection module 130, so that the detection module 110 can have a smaller signal output amplitude under high power input, so that the envelope signal output by the detection module 110 will not be saturated and distorted after being amplified by the post-stage circuit 140, which is beneficial to improving communication performance. In addition, since the envelope signal output by the detection module 110 has a smaller signal output amplitude under high power, the input power of the carrier can be increased, which is beneficial to improving the power range that can be input to the carrier.

[0063] Optionally, an embodiment of the present invention further provides an electronic tag, which includes the envelope detection circuit provided by any embodiment of the present invention, so the electronic tag provided by this embodiment also has the beneficial effects described in any embodiment of the present invention. In this embodiment, the electronic tag can be a tag based on a passive Internet of Things, or a tag based on an active Internet of Things, and this embodiment does not limit this.

[0064] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0065] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An envelope detection circuit, characterized in that: include: Antenna, detection module, load module and power detection module; The input end of the detection module is connected to the antenna as the input end of the envelope detection circuit, and the output end of the detection module is connected to the subsequent circuit as the output end of the envelope detection circuit. The detection module is used to demodulate the envelope signal on the carrier; The input end of the power detection module is connected to the output end of the detection module, and the output end of the power detection module is connected to the control end of the load module. The power detection module is used to generate a control signal according to the power of the carrier to control different loads in the load module to connect to the output end of the detection module.

2. The envelope detection circuit according to claim 1, characterized in that: The load module includes a first load unit and a second load unit, and the output end of the power detection module includes a first output end and a second output end; The first end of the first load unit is connected to a fixed voltage, the second end of the first load unit is connected to the output end of the detection module, and the control end of the first load unit is connected to the first output end of the power detection module; The first end of the second load unit is connected to the fixed voltage, the second end of the second load unit is connected to the output end of the detection module, and the control end of the second load unit is connected to the second output end of the power detection module; The first load unit and the second load unit are turned on in a time-sharing manner.

3. The envelope detection circuit according to claim 2, characterized in that: The first load unit includes a first load and a first switch subunit, the first end of the first load is connected to the fixed voltage, the second end of the first load is connected to the first end of the first switch subunit, the second end of the first switch subunit is connected to the output end of the detection module, and the control end of the first switch subunit is connected to the first output end of the power detection module; The second load unit comprises a second load and a second switch subunit, the first end of the second load is connected to the fixed voltage, the second end of the second load is connected to the first end of the second switch subunit, the second end of the second switch subunit is connected to the output end of the detection module, and the control end of the second switch subunit is connected to the second output end of the power detection module; The impedance of the first load is smaller than the impedance of the second load.

4. The envelope detection circuit according to claim 3, characterized in that: The first switch subunit includes a first transistor, and the second switch subunit includes a second transistor, the gate of the first transistor is connected to the first output end of the power detection module, the first electrode of the first transistor is connected to the second end of the first load, and the second electrode of the first transistor is connected to the output end of the detection module; the gate of the second transistor is connected to the second output end of the power detection module, the first electrode of the second transistor is connected to the second end of the second load, and the second electrode of the second transistor is connected to the output end of the detection module; The first load includes a first resistor, and the second load includes a second resistor. The first end of the first resistor is connected to the fixed voltage, and the second end of the first resistor is connected to the first electrode of the first transistor. The first end of the second resistor is connected to the fixed voltage, and the second end of the second resistor is connected to the first electrode of the second transistor.

5. The envelope detection circuit according to claim 3, characterized in that: The first switch subunit includes a first transistor, and the second switch subunit includes a second transistor, the gate of the first transistor is connected to the first output end of the power detection module, the first electrode of the first transistor is connected to the second end of the first load, and the second electrode of the first transistor is connected to the output end of the detection module; the gate of the second transistor is connected to the second output end of the power detection module, the first electrode of the second transistor is connected to the second end of the second load, and the second electrode of the second transistor is connected to the output end of the detection module; The first load includes a third transistor, and the second load includes a fourth transistor. The first electrode of the third transistor is connected to the fixed voltage, the second electrode of the third transistor is connected to the first electrode of the first transistor, the gate of the third transistor is connected to the second electrode of the third transistor, the first electrode of the fourth transistor is connected to the fixed voltage, the second electrode of the fourth transistor is connected to the first electrode of the second transistor, and the gate of the fourth transistor is connected to the second electrode of the fourth transistor.

6. The envelope detection circuit according to claim 2, characterized in that: The power detection module also includes a trigger end, the trigger end of the power detection module receives a power detection signal, and the power detection module is further used to latch the power of the carrier in response to the power detection signal before the downlink signaling reception stage.

7. The envelope detection circuit according to claim 6, characterized in that: The power detection module includes a comparison unit, a trigger unit and a signal processing unit; The first input end of the comparison unit is connected to the output end of the detection module, the second input end of the comparison unit is connected to the reference voltage, the output end of the comparison unit is connected to the input end of the trigger unit, the control end of the trigger unit is connected to the power detection signal as the trigger end of the power detection module, the output end of the trigger unit is respectively connected to the input end of the signal processing unit and the control end of the first load unit, the output end of the signal processing unit is connected to the control end of the second load unit, the trigger unit is used to output a first control signal according to the comparison value of the comparison unit at the edge of the power detection signal, and lock the first control signal before the next same edge of the power detection signal comes, and the signal processing unit is used to convert the first control signal into a second control signal; The first control signal and the second control signal are opposite.

8. The envelope detection circuit according to claim 7, characterized in that: The comparison unit comprises a voltage comparator, a first input end of the voltage comparator is connected to the output end of the detection module, a second input end of the voltage comparator is connected to the reference voltage, and an output end of the voltage comparator serves as an output end of the comparison unit; The trigger unit includes a trigger, and the signal processing unit includes an inverter. The clock end of the trigger is connected to the power detection signal, the input end of the trigger is connected to the output end of the voltage comparator, the output end of the trigger is connected to the input end of the inverter, and the output end of the inverter serves as the output end of the signal processing unit.

9. The envelope detection circuit according to claim 1, characterized in that: The detection module includes a negative envelope detector.

10. An electronic tag, characterized in that: The invention comprises the envelope detection circuit as described in any one of claims 1 to 9.

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