Trimming system of operational amplifier and operational amplifier

Abstract

The invention relates to a trimming system of an operational amplifier and the operational amplifier, and relates to the technical field of electronic circuits. The trimming system of the operational amplifier comprises a trimming signal generation circuit and a current source calibration circuit. Wherein the trimming signal generation circuit comprises a fuse group, and a trimming signal group is output based on the on-off state of a plurality of fuses in the fuse group; and the current source calibration circuit adjusts the output of the current source according to the trimming signal group to obtain a bias signal. The output of the current source is adjusted through the current source calibration circuit according to the trimming signal group, so that the bias signal suitable for driving the amplifier to work is obtained, and the offset voltage of the amplifier is calibrated. And the fusing of the fuse only occurs in the trimming signal generation circuit, and the generation of the trimming signal group is not influenced by the tiny interference generated on the residual metal wire after the fuse is fused, so that the offset voltage is calibrated, and the working stability of the amplifier can be kept at the same time.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to an operational amplifier adjustment system and an operational amplifier. Background Art

[0002] An operational amplifier is a device that can amplify and output differential input signals while suppressing common-mode input signals. It has the characteristics of high gain, high input impedance and low output impedance, can provide a stable amplification factor, and can drive load resistance. Operational amplifiers are widely used in various analog circuits such as signal amplification, filtering, comparison, integration, differentiation, etc.

[0003] Offset voltage is one of the important indicators of operational amplifiers. Offset voltage refers to the voltage that is not equal to zero when the two input voltage signals of the operational amplifier are both zero. At present, the adjustment of offset voltage usually adopts the method of calibrating the current source in the operational amplifier. The preset fuse inside the current source can be directly blown by laser or current, and the resistance or connection relationship inside the current source can be changed so that the current source provides a suitable bias signal to provide a suitable operating point to the operational amplifier, thereby reducing the generation of offset voltage. However, after the fuse is blown, metal wire residue will be left inside the current source, making the metal wire in a suspended state and susceptible to interference, thereby affecting the stability of the operational amplifier. Therefore, how to maintain the stability of the operational amplifier while calibrating the offset voltage is a problem that needs to be solved urgently. Summary of the invention

[0004] An embodiment of the present application provides a trimming system for an operational amplifier, which maintains the stability of the operational amplifier while calibrating the offset voltage, so as to at least partially solve the above-mentioned technical problems.

[0005] In order to achieve the above-mentioned object, according to a first aspect of the present application, a trimming system for an operational amplifier is provided, comprising:

[0006] A trimming signal generating circuit includes a fuse group, and outputs a trimming signal group including multiple trimming signals based on the on and off states of a plurality of fuses in the fuse group;

[0007] The current source calibration circuit is connected to the trimming signal generating circuit and the current source, and adjusts the output of the current source according to the trimming signal group to obtain a bias signal.

[0008] Optionally, the trimming signal generating circuit includes a reference subcircuit and a plurality of follower subcircuits;

[0009] The reference subcircuit is connected to the current source, the voltage source and the ground, and is used to output a first reference signal and a second reference signal;

[0010] The follower sub-circuit is connected to the reference sub-circuit, the fuse and the current source calibration circuit, and generates a trimming signal according to the first reference signal, the second reference signal and the on-off state of the fuse.

[0011] Optionally, the reference subcircuit includes a first transistor and a second transistor;

[0012] The first transistor comprises a first electrode connected to the voltage source, a second electrode connected to the follower sub-circuit and the current source, and a control electrode;

[0013] The second transistor includes a grounded second electrode, a first electrode connected to the current source and the follower sub-circuit, and a control electrode.

[0014] Optionally, the follower sub-circuit includes a third transistor and a fourth transistor;

[0015] The third transistor includes a control electrode connected to the reference subcircuit to receive the first reference signal, a first electrode connected to a voltage source, and a second electrode connected to a first end of a fuse and the current source calibration circuit;

[0016] The fourth transistor includes a control electrode connected to the reference subcircuit to receive the second reference signal, a first electrode connected to the second end of the fuse, and a second electrode grounded.

[0017] Optionally, the current source calibration circuit includes a mirror subcircuit and a calibration subcircuit;

[0018] The mirror subcircuit is connected to the current source and generates a reference current based on the output of the current source;

[0019] The calibration subcircuit is connected to the mirror subcircuit and the trimming signal generating circuit, and adjusts the reference current according to the trimming signal group to obtain a bias signal.

[0020] Optionally, the calibration subcircuit is used to connect to the first amplifying branch and / or the second amplifying branch of the differential amplifier, and to output a bias signal to the first amplifying branch and / or the second amplifying branch to adjust the output of the first amplifying branch and / or the second amplifying branch.

[0021] Optionally, the mirror subcircuit includes a fifth transistor; the fifth transistor includes a control electrode and a first electrode connected to the current source and the calibration subcircuit, and a second electrode connected to ground.

[0022] Optionally, the calibration subcircuit includes a plurality of adjustment branches;

[0023] Each of the adjustment branches is connected to the mirror sub-circuit and the trimming signal generating circuit respectively, and generates an adjustment signal of a preset multiple of the reference current according to one trimming signal in the trimming signal group;

[0024] The bias signal is obtained by superimposing a plurality of the adjustment signals.

[0025] Optionally, the adjustment branch includes a sixth transistor and a seventh transistor;

[0026] The sixth transistor includes a control electrode connected to the trimming signal generating circuit, a first electrode connected to the differential amplifier, and a second electrode connected to the seventh transistor;

[0027] The seventh transistor includes a control electrode connected to the mirror sub-circuit, a first electrode connected to the second electrode of the sixth transistor, and a grounded second electrode.

[0028] Optional,

[0029] The trimming system further includes an offset detection circuit, which is connected to the differential amplifier and used to generate two test control signals according to the difference between the first test signal and the second test signal connected to the differential amplifier;

[0030] The two test control signals are respectively used to control the positive offset or negative offset of the output of the differential amplifier; when the output of the differential amplifier is zero, the difference between the first test signal and the second test signal is the offset voltage.

[0031] Optionally, the imbalance detection circuit includes a driving subcircuit and an output subcircuit;

[0032] The driving subcircuit is connected to the first input terminal and the second input terminal of the differential amplifier, and generates a driving signal according to the difference between the first test signal connected to the first input terminal and the second test signal connected to the second input terminal;

[0033] The output sub-circuit is connected to the driving sub-circuit and generates two test control signals according to the driving signal.

[0034] Optionally, the driving sub-circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;

[0035] The eighth transistor includes a control electrode connected to the first input terminal of the differential amplifier, a first electrode connected to the voltage source, and a second electrode connected to the twelfth transistor;

[0036] The ninth transistor includes a control electrode connected to the second input terminal of the differential amplifier, a first electrode connected to the first electrode of the eighth transistor, and a second electrode connected to the tenth transistor;

[0037] The tenth transistor includes a first electrode and a control electrode connected to the second electrode of the ninth transistor and the eleventh transistor, and a second electrode connected to the ground;

[0038] The eleventh transistor includes a control electrode connected to the control electrode and the first electrode of the tenth transistor, a first electrode connected to the output subcircuit, and a second electrode connected to ground;

[0039] The twelfth transistor includes a first electrode and a control electrode connected to the second electrode of the eighth transistor and the thirteenth transistor, and a second electrode connected to the ground;

[0040] The thirteenth transistor includes a control electrode connected to the control electrode and the first electrode of the twelfth transistor, a first electrode connected to the control electrode of the tenth transistor and the control electrode of the eleventh transistor, and a second electrode connected to the ground.

[0041] Optionally, the output sub-circuit includes a fourteenth transistor, a fifteenth transistor and a sixteenth transistor;

[0042] The fourteenth transistor includes a first electrode connected to the voltage source, a control electrode connected to the driving subcircuit and the fifteenth transistor and the sixteenth transistor, and a second electrode;

[0043] The fifteenth transistor includes a control electrode connected to the control electrode and the second electrode of the fourteenth transistor, a first electrode connected to the voltage source, and a second electrode connected to the differential amplifier;

[0044] The sixteenth transistor includes a control electrode connected to the control electrode and the second electrode of the fourteenth transistor, a first electrode connected to the voltage source, and a second electrode connected to the differential amplifier.

[0045] According to a second aspect of the present application, an operational amplifier is provided, comprising a first differential input pair of transistors, a second differential input pair of transistors, a first amplifying branch, a second amplifying branch, an output circuit, and a trimming system of the operational amplifier as described above;

[0046] The first amplifying branch is respectively connected to the first differential input pair of tubes, the second differential input pair of tubes and the trimming system of the operational amplifier;

[0047] The second amplifying branch is respectively connected to the first differential input pair of transistors, the second differential input pair of transistors, the trimming system of the operational amplifier and the output circuit.

[0048] In summary, in the embodiment of the present application, the trimming signal generating circuit outputs the trimming signal group to the current source calibration circuit through the on-off state of each fuse in the fuse group, so that the current source calibration circuit adjusts the output of the current source according to the trimming signal group to obtain a bias signal suitable for driving the amplifier to work, thereby achieving calibration of the amplifier's offset voltage. And because the blowing of the fuse only occurs in the trimming signal generating circuit, the tiny interference generated on the residual metal wire after the fuse is blown will not affect the generation of the trimming signal group, so that the current source calibration circuit can stably calibrate the output of the current source, thereby achieving calibration of the offset voltage while maintaining the stability of the amplifier's operation.

[0049] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0051] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0052] Figure 1 is a schematic diagram of a trimming system for an operational amplifier provided in an exemplary embodiment of the present disclosure;

[0053] Figure 2 is a connection structure diagram of a trimming signal generating circuit provided in an exemplary embodiment of the present disclosure;

[0054] Figure 3 is a connection structure diagram of a current source calibration circuit provided in an exemplary embodiment of the present disclosure;

[0055] Figure 4 is a schematic diagram of an operational amplifier provided in an exemplary embodiment of the present disclosure;

[0056] Figure 5 is a schematic diagram of an imbalance detection circuit provided in an exemplary embodiment of the present disclosure;

[0057] Figure 6 2 is a connection structure diagram of an imbalance detection circuit provided in an exemplary embodiment of the present disclosure.

[0058] Explanation of the reference numerals: 1. trimming signal generating circuit; 11. fuse group; 12. reference sub-circuit; 13. follower sub-circuit; 2. current source calibration circuit; 21. mirror sub-circuit; 22. calibration sub-circuit; 222. adjustment branch; 3. offset detection circuit; 31. drive sub-circuit; 32. output sub-circuit; 10. first differential input pair of tubes; 20. second differential input pair of tubes; 30. first amplifying branch; 40. second amplifying branch; 50. output circuit. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0060] According to the first aspect of the present application, referring to Figures 1 to 4 The present disclosure provides a trimming system for an operational amplifier, comprising a trimming signal generating circuit 1 and a current source calibration circuit 2. The trimming signal generating circuit 1 comprises a fuse group 11, and outputs a trimming signal group containing multiple trimming signals based on the on / off states of a number of fuses in the fuse group 11; the current source calibration circuit 2 is connected to the trimming signal generating circuit 1 and the current source, and adjusts the output of the current source according to the trimming signal group to obtain a bias signal.

[0061] As an example, each fuse in the fuse group 11 corresponds to one trimming signal in the output trimming signal group. For example, when the on-off state of the fuse is blown, a trimming signal in a high level state is output, and when the on-off state of the fuse is not blown, a trimming signal in a low level state is output. All trimming signals are combined according to the setting order of the fuses in the fuse group 11 to obtain a trimming signal group.

[0062] In the above embodiment, the trimming signal generating circuit 1 outputs the trimming signal group to the current source calibration circuit 2 through the on / off state of each fuse in the fuse group 11, so that the current source calibration circuit 2 adjusts the output of the current source according to the trimming signal group to obtain a bias signal suitable for driving the amplifier to work, thereby achieving calibration of the amplifier's offset voltage. In addition, since the blowing of the fuse only occurs in the trimming signal generating circuit 1, the tiny interference generated on the residual metal wire after the fuse is blown will not affect the generation of the trimming signal group, so that the current source calibration circuit 2 can stably calibrate the output of the current source, thereby achieving calibration of the offset voltage while maintaining the stability of the amplifier's operation.

[0063] Reference Figure 2In some embodiments, the trimming signal generating circuit 1 includes a reference subcircuit 12 and a plurality of follower subcircuits 13. The reference subcircuit 12 is connected to a current source, a voltage source and a ground, and is used to output a first reference signal and a second reference signal; the follower subcircuit 13 is connected to the reference subcircuit 12, a fuse and a current source calibration circuit 2, and generates a trimming signal according to the first reference signal, the second reference signal and the on / off state of the fuse.

[0064] As an example, the number of fuses in the fuse group 11, the number of trimming signals in the trimming signal group, and the number of follower sub-circuits 13 can be set to be consistent. Figure 2 For example, the fuse group 11 includes eight fuses, the trimming signals in the trimming signal group, and the follower sub-circuit 13. The fuse group 11 may include fuses Fuse1 to Fuse8, the trimming signal group may include trimming signals M1 to M8, and each follower sub-circuit 13 is connected to a corresponding fuse and outputs a trimming signal. For example, the first group of follower sub-circuits 13 is connected to the fuse Fuse1 and outputs the trimming signal M1.

[0065] In the above embodiment, the reference sub-circuit 12 outputs the first reference signal and the second reference signal to simultaneously provide the first reference signal and the second reference signal to multiple follower sub-circuits 13, and in combination with the on-off state of the fuse connected to each follower sub-circuit 13, outputs the trimming signal of the follower sub-circuit 13. In this way, the multiple follower sub-circuits 13 can generate multiple trimming signals to form a trimming signal group.

[0066] In some embodiments, the reference sub-circuit 12 includes a first transistor Q1 and a second transistor Q2; the first transistor Q1 includes a first electrode connected to a voltage source, a second electrode and a control electrode connected to the follower sub-circuit 13 and the current source; the second transistor Q2 includes a first electrode and a control electrode connected to the current source and the follower sub-circuit 13, and a second electrode connected to ground.

[0067] As an example, combining Figure 3 , IBIAS represents a current source, and VDD represents a voltage source. The first transistor Q1 may be a PMOS tube, and the first electrode, the control electrode, and the current source of the first transistor Q1 are connected to form an input tube in a current mirror structure, so as to convert the output of the current source into a first reference signal, and transmit it to the follower sub-circuit 13. The second transistor Q2 may be an NMOS tube, and the first electrode, the control electrode, and the current source of the second transistor Q2 are connected to form an input tube in a current mirror structure, so as to convert the output of the current source into a second reference signal, and transmit it to each follower sub-circuit 13.

[0068] In some embodiments, the follower sub-circuit 13 includes a third transistor Q3 and a fourth transistor Q4; the third transistor Q3 includes a control electrode connected to the reference sub-circuit 12 to receive a first reference signal, a first electrode connected to a voltage source, and a second electrode connected to a first end of a fuse and the current source calibration circuit 2; the fourth transistor Q4 includes a control electrode connected to the reference sub-circuit 12 to receive a second reference signal, a first electrode connected to a second end of the fuse, and a second electrode connected to ground.

[0069] As an example, the third transistor Q3 is a pull-up transistor, the third transistor Q3 can be a PMOS tube, the fourth transistor Q4 is a pull-down transistor, and the fourth transistor Q4 can be an NMOS tube. The third transistor Q3 forms a complete current mirror structure with the first transistor Q1, and the fourth transistor Q4 forms a current mirror structure with the second transistor Q2. In this way, the current flowing through each third transistor Q3 follows the current flowing through the first transistor Q1, and the current flowing through the fourth transistor Q4 follows the current flowing through the second transistor Q2.

[0070] As an example, when the on-off state of the fuse is blown, the third transistor Q3 and the fourth transistor Q4 are disconnected, and the third transistor Q3 pulls up the trimming signal to generate a trimming signal in a high-level state. When the on-off state of the fuse is not blown, the third transistor Q3 and the fourth transistor Q4 are connected through the fuse. Since the fourth transistor Q4 is an NMOS tube, its conduction ability is stronger than that of the third transistor Q3, so that the current output by the second electrode of the third transistor Q3 is pulled down to the ground, thereby outputting a trimming signal in a low-level state, achieving the effect of outputting trimming signals of different states according to the on-off state of the fuse.

[0071] In some embodiments, the current source calibration circuit 2 includes a mirror sub-circuit 21 and a calibration sub-circuit 22; wherein the mirror sub-circuit 21 is connected to the current source and generates a reference current based on the output of the current source; the calibration sub-circuit 22 is connected to the mirror sub-circuit 21 and the adjustment signal generating circuit 1, and adjusts the reference current according to the adjustment signal group to obtain a bias signal.

[0072] As an example, the trimming system of the operational amplifier can be applied to a differential amplifier; the differential amplifier includes a first amplifying branch 30 and a second amplifying branch 40. The calibration subcircuit 22 is connected to the first amplifying branch 30 and / or the second amplifying branch 40, and is used to output a bias signal to the first amplifying branch 30 and / or the second amplifying branch 40 to adjust the output of the first amplifying branch 30 and / or the second amplifying branch 40. When the offset voltage is greater than zero, the offset voltage can be reduced in the positive direction by increasing the bias signal output by the calibration subcircuit 22 to the first amplifying branch 30; when the offset voltage is less than zero, the offset voltage can be reduced in the negative direction by increasing the bias signal output by the calibration subcircuit 22 to the second amplifying branch 40.

[0073] As an example, in an ideal case, the first amplifying branch 30 and the second amplifying branch 40 should be completely symmetrical, and their outputs should also be equal. However, affected by factors such as the manufacturing process of components, the device parameters of the first amplifying branch 30 and the second amplifying branch 40 cannot be guaranteed to be completely consistent. For example, factors such as the threshold voltage, gain, and resistance performance of the transistors cause the amplification factors of the first amplifying branch 30 and the second amplifying branch 40 to be not completely equal, thereby generating an offset voltage. Therefore, the calibration subcircuit 22 can be set at the first amplifying branch 30 and the second amplifying branch 40 respectively, or the calibration subcircuit 22 can be set at only one of the first amplifying branch 30 and the second amplifying branch 40, so as to achieve adjustment of the output of the first amplifying branch 30 and / or the second amplifying branch 40.

[0074] Furthermore, since the fuses in the fuse group 11 are irreversible after being blown, the influence of the fuses after being blown by mistake can be offset by respectively providing a group of calibration sub-circuits 22 at the first amplifying branch 30 and the second amplifying branch 40. For example, when a fuse corresponding to the calibration sub-circuit 22 of the first amplifying branch 30 is blown by mistake, the same fuse can be blown in the calibration sub-circuit 22 of the second amplifying branch 40, so that the first amplifying branch 30 and the second amplifying branch 40 can maintain a relative balance.

[0075] Reference Figure 3 In some embodiments, the mirror subcircuit 21 includes a fifth transistor Q5; the fifth transistor Q5 includes a control electrode and a first electrode connected to the current source and the calibration subcircuit 22, and a second electrode connected to the ground.

[0076] As an example, the fifth transistor Q5 can be an NMOS tube, and the first electrode, control electrode and current source of the fifth transistor Q5 are interconnected to form an input tube in a current mirror structure to convert the output of the current source into a reference current and output the reference current to the calibration subcircuit 22.

[0077] Reference Figure 3In some embodiments, the calibration subcircuit 22 includes a plurality of adjustment branches 222; each adjustment branch 222 is respectively connected to the mirror subcircuit 21 and the trimming signal generating circuit 1, and generates an adjustment signal having a preset multiple of the reference current according to one trimming signal in the trimming signal group.

[0078] In some embodiments, the adjustment branch 222 includes a sixth transistor Q6 and a seventh transistor Q7; the sixth transistor Q6 includes a control electrode connected to the adjustment signal generating circuit 1, a first electrode connected to the differential amplifier, and a second electrode connected to the seventh transistor Q7; the seventh transistor Q7 includes a control electrode connected to the mirror sub-circuit 21, a first electrode connected to the second electrode of the sixth transistor Q6, and a second electrode connected to the ground.

[0079] The control electrode of the seventh transistor Q7 and the control electrode of the fifth transistor Q5 are connected to each other to form a complete current mirror structure. The adjustment signal output by the seventh transistor Q7 is a current signal, and its size is a preset multiple of the reference current output by the fifth transistor Q5. In the current mirror structure, by setting the size of the seventh transistor Q7, it is possible to output adjustment signals with different preset multiples. For example, the sizes of the seventh transistors Q7 in the multiple adjustment branches 222 are respectively set to one, two, four and eight times of the fifth transistor Q5, and the preset multiples are one, two, four and eight times, respectively.

[0080] As an example, the sixth transistor Q6 can be an NMOS tube. When the trimming signal is in a high-level state, the sixth transistor Q6 is turned on, and the adjustment branch 222 outputs an adjustment signal of a preset multiple of the reference current through the seventh transistor Q7. When the trimming signal is in a low-level state, the sixth transistor Q6 is turned off, and the adjustment branch 222 outputs an adjustment signal of a zero state. Among them, a bias signal can be obtained by superimposing multiple adjustment signals. For example, when fuses Fuse1 and Fuse3 are blown, the trimming signal generating circuit 1 outputs high-level trimming signals M1 and M3, and the trimming signals M1 and M3 respectively control the corresponding adjustment branches 222 to respectively output adjustment signals that are preset multiples of the reference current, and the bias signal is obtained after superposition.

[0081] As an example, combining Figure 3, the number of adjustment branches 222 and the number of fuses can be kept consistent. For example, a group of calibration sub-circuits 22 are respectively set at the first amplifying branch 30 and the second amplifying branch 40. The calibration sub-circuit 22 corresponding to the first amplifying branch 30 can be an adjustment branch 222 controlled by the trimming signals M1 to M4, and the calibration sub-circuit 22 corresponding to the second amplifying branch 40 can be an adjustment branch 222 controlled by the trimming signals M5 to M8. In this way, when it is necessary to adjust the output of the first amplifying branch 30, the corresponding trimming signals M1 to M4 can be output by blowing the fuses Fuse1 to Fuse4. When adjusting the output of the second amplifying branch 40, the corresponding trimming signals M5 to M8 can be output by blowing the fuses Fuse5 to Fuse8.

[0082] Reference Figure 5 In some embodiments, the differential amplifier includes a first input terminal for receiving a first test signal and a second input terminal for receiving a second test signal; the adjustment system also includes an offset detection circuit 3, which is connected to the differential amplifier and is used to generate two test control signals according to the difference between the first test signal and the second test signal; wherein the two test control signals are respectively used to control the positive offset or negative offset of the output of the differential amplifier; when the output of the differential amplifier is zero, the difference between the first test signal and the second test signal is the offset voltage.

[0083] As an example, the offset voltage is used to characterize the offset degree of the differential amplifier, and the trimming voltage generated by the offset detection circuit 3 helps to guide the blowing of the fuse.

[0084] In some embodiments, the offset detection circuit 3 includes a driving subcircuit 31 and an output subcircuit 32; the driving subcircuit 31 is connected to the first input terminal and the second input terminal of the differential amplifier, and generates a driving signal according to the difference between the first test signal and the second test signal; the output subcircuit 32 is connected to the driving subcircuit 31, and generates two test control signals according to the driving signal.

[0085] Reference Figure 6In some embodiments, the driving subcircuit 31 includes an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, and a thirteenth transistor Q13; the eighth transistor Q8 includes a control electrode connected to the first input terminal of the differential amplifier, a first electrode connected to the voltage source, and a second electrode connected to the twelfth transistor Q12; the ninth transistor Q9 includes a control electrode connected to the second input terminal of the differential amplifier, a first electrode connected to the first electrode of the eighth transistor Q8, and a second electrode connected to the tenth transistor Q10; the tenth transistor Q10 includes a second electrode connected to the ninth transistor Q9 and an eleventh transistor Q11 connected to the second input terminal of the differential amplifier, a first electrode connected to the voltage source, and a second electrode connected to the twelfth transistor Q12; the ninth transistor Q9 includes a control electrode connected to the second input terminal of the differential amplifier, a first electrode connected to the first electrode of the eighth transistor Q8, and a second electrode connected to the tenth transistor Q10; the tenth transistor Q10 includes a second electrode connected to the ninth transistor Q9 and an eleventh transistor Q13 connected to the twelfth transistor Q13; The transistor Q11 includes a first electrode and a control electrode connected to the control electrode and the first electrode of the tenth transistor Q10, a first electrode connected to the output subcircuit 32, and a second electrode connected to the ground; the twelfth transistor Q12 includes a first electrode and a control electrode connected to the second electrode of the eighth transistor Q8 and the thirteenth transistor Q13, and a second electrode connected to the ground; the thirteenth transistor Q13 includes a control electrode connected to the control electrode and the first electrode of the twelfth transistor Q12, a first electrode connected to the control electrode of the tenth transistor Q10 and the control electrode of the eleventh transistor Q11, and a second electrode connected to the ground.

[0086] Among them, the eighth transistor Q8 and the ninth transistor Q9 can be PMOS transistors, and the tenth transistor Q10, the eleventh transistor Q11, the twelfth transistor Q12 and the thirteenth transistor Q13 can be NMOS transistors. In addition, the tenth transistor Q10 and the eleventh transistor Q11 form a current mirror structure, so that the output of the eleventh transistor Q11 follows the tenth transistor Q10; the twelfth transistor Q12 and the thirteenth transistor Q13 form a current mirror structure, so that the output of the twelfth transistor Q12 follows the output of the thirteenth transistor Q13.

[0087] As an example, in the initial stage, the amplitudes of the first test signal and the second test signal are kept consistent, so that the eighth transistor Q8 and the ninth transistor Q9 are turned on, thereby turning on the twelfth transistor Q12 and the thirteenth transistor Q13. Then, the second test signal is gradually reduced, so that the conduction degree of the ninth transistor Q9 becomes larger, so that the tenth transistor Q10 and the eleventh transistor Q11 are gradually turned on, and the twelfth transistor Q12 and the thirteenth transistor Q13 are gradually turned off. At this time, the eleventh transistor Q11 is turned on to the ground, so that the output sub-circuit 32 is grounded through the eleventh transistor Q11, so that the output sub-circuit 32 forms a complete loop.

[0088] In some embodiments, the output subcircuit 32 includes a fourteenth transistor Q14, a fifteenth transistor Q15 and a sixteenth transistor Q16; the fourteenth transistor Q14 includes a first electrode connected to a voltage source, a control electrode connected to the driving subcircuit 31 and the fifteenth transistor Q15 and the sixteenth transistor Q16, and a second electrode; the fifteenth transistor Q15 includes a control electrode connected to the control electrode and the second electrode of the fourteenth transistor Q14, a first electrode connected to the voltage source, and a second electrode connected to the differential amplifier; the sixteenth transistor Q16 includes a control electrode connected to the control electrode and the second electrode of the fourteenth transistor Q14, a first electrode connected to the voltage source, and a second electrode connected to the differential amplifier.

[0089] As an example, the fourteenth transistor Q14, the fifteenth transistor Q15 and the sixteenth transistor Q16 can be PMOS transistors, and the fourteenth transistor Q14, the fifteenth transistor Q15 and the sixteenth transistor Q16 constitute a current mirror structure, which passes the driving signal of the control electrode of the fourteenth transistor Q14, and the outputs of the fifteenth transistor Q15 and the sixteenth transistor Q16 serve as output tubes, so that the amplitudes of the two control signals are always kept consistent, so as to adjust the output of the differential amplifier.

[0090] As an example, in the process of gradually decreasing the second test signal, the eleventh transistor Q11 is gradually turned on to the ground, so that the control electrode and the second electrode of the fourteenth transistor Q14 are pulled down to the ground, thereby increasing the conduction degree of the fourteenth transistor Q14, and the conduction degrees of the fifteenth transistor Q15 and the sixteenth transistor Q16 are increased following the fourteenth transistor Q14, so that the amplitudes of the first test signal and the second test signal output by the fifteenth transistor Q15 and the sixteenth transistor Q16 gradually increase, thereby linearly adjusting the output of the differential amplifier so as to adjust the output of the differential amplifier to zero.

[0091] Reference Figure 4 According to a second aspect of the present disclosure, an operational amplifier is provided, which includes a first differential input pair of tubes 10, a second differential input pair of tubes 20, a first amplifying branch 30, a second amplifying branch 40, an output circuit 50 and the above-mentioned operational amplifier adjustment system.

[0092] The first amplifying branch 30 is respectively connected to the first differential input pair of tubes 10, the second differential input pair of tubes 20 and the trimming system of the operational amplifier; the second amplifying branch 40 is respectively connected to the first differential input pair of tubes 10, the second differential input pair of tubes 20, the trimming system of the operational amplifier and the output circuit 50.

[0093] Combination Figure 4, the first differential input pair of transistors 10 may be a PMOS pair of transistors, including a seventeenth transistor Q17 and an eighteenth transistor Q18; the second differential input pair of transistors 20 may be an NMOS pair of transistors, including a nineteenth transistor Q19 and a twentieth transistor Q20. Among them, the control electrode of the seventeenth transistor Q17 and the control electrode of the nineteenth transistor Q19 are connected to each other to form an inverting input terminal, and the control electrode of the eighteenth transistor Q18 and the control electrode of the twentieth transistor Q20 are connected to each other to form a non-inverting input terminal. When the input voltage connected to the non-inverting input terminal or the reverse input terminal is close to the ground, the first differential input pair of transistors 10 starts to work; when the input voltage connected to the non-inverting input terminal or the reverse input terminal is close to the output of the voltage source, the second differential input pair of transistors 20 starts to work; and when the input voltage connected to the non-inverting input terminal or the reverse input terminal is at an intermediate value between the voltage source and the ground, the first differential input pair of transistors 10 and the second differential input pair of transistors 20 work simultaneously.

[0094] As an example, the first amplifying branch 30 and the second amplifying branch 40 can adopt a common source and common gate amplifying structure connected in series, respectively amplifying the input voltage connected to the in-phase input terminal or the reverse input terminal. The two test control signals output by the offset detection circuit 3 of the trimming system of the operational amplifier are respectively connected between the first differential input pair tube 10 and the first amplifying branch 30 and between the second differential input pair tube 20 and the output circuit 50.

[0095] The uniqueness of the operational amplifier has all the beneficial effects of the above-mentioned operational amplifier trimming system, which will not be described in detail in this disclosure.

[0096] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0097] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0098] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0099] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An operational amplifier trimming system, characterized in that: include: A trimming signal generating circuit includes a fuse group, and outputs a trimming signal group including multiple trimming signals based on the on and off states of a plurality of fuses in the fuse group; The current source calibration circuit is connected to the trimming signal generating circuit and the current source, and adjusts the output of the current source according to the trimming signal group to obtain a bias signal.

2. The operational amplifier trimming system according to claim 1, wherein: The trimming signal generating circuit includes a reference subcircuit and a plurality of follower subcircuits; The reference subcircuit is connected to the current source, the voltage source and the ground, and is used to output a first reference signal and a second reference signal; The follower sub-circuit is connected to the reference sub-circuit, the fuse and the current source calibration circuit, and generates the trimming signal according to the first reference signal, the second reference signal and the on-off state of the fuse.

3. The operational amplifier trimming system according to claim 2, wherein: The reference subcircuit includes a first transistor and a second transistor; The first transistor comprises a first electrode connected to the voltage source, a second electrode connected to the follower sub-circuit and the current source, and a control electrode; The second transistor includes a grounded second electrode, a first electrode connected to the current source and the follower sub-circuit, and a control electrode.

4. The operational amplifier trimming system according to claim 2, wherein: The follower sub-circuit includes a third transistor and a fourth transistor; The third transistor includes a control electrode connected to the reference subcircuit to receive the first reference signal, a first electrode connected to the voltage source, and a second electrode connected to the first end of the fuse and the current source calibration circuit; The fourth transistor includes a control electrode connected to the reference subcircuit to receive the second reference signal, a first electrode connected to the second end of the fuse, and a second electrode grounded.

5. The operational amplifier trimming system according to claim 1, wherein: The current source calibration circuit includes a mirror subcircuit and a calibration subcircuit; The mirror subcircuit is connected to the current source and generates a reference current based on the output of the current source; The calibration subcircuit is connected to the mirror subcircuit and the trimming signal generating circuit, and adjusts the reference current according to the trimming signal group to obtain a bias signal.

6. The operational amplifier trimming system according to claim 5, wherein: The calibration subcircuit is used to be connected to the first amplifying branch and / or the second amplifying branch of the differential amplifier, and is used to output the bias signal to the first amplifying branch and / or the second amplifying branch to adjust the output of the first amplifying branch and / or the second amplifying branch.

7. The operational amplifier trimming system according to claim 5, wherein: The mirror subcircuit includes a fifth transistor; the fifth transistor includes a control electrode and a first electrode connected to the current source and the calibration subcircuit, and a second electrode connected to the ground.

8. The operational amplifier trimming system according to claim 6, wherein: The calibration subcircuit includes a plurality of adjustment branches; Each of the adjustment branches is connected to the mirror sub-circuit and the trimming signal generating circuit respectively, and generates an adjustment signal of a preset multiple of the reference current according to one trimming signal in the trimming signal group; The bias signal is obtained by superimposing a plurality of the adjustment signals.

9. The operational amplifier trimming system according to claim 8, wherein: The adjustment branch includes a sixth transistor and a seventh transistor; The sixth transistor includes a control electrode connected to the trimming signal generating circuit, a first electrode connected to the differential amplifier, and a second electrode connected to the seventh transistor; The seventh transistor includes a control electrode connected to the mirror sub-circuit, a first electrode connected to the second electrode of the sixth transistor, and a grounded second electrode.

10. The operational amplifier trimming system according to claim 1, wherein: The trimming system further includes an offset detection circuit, which is connected to a differential amplifier and used to generate two test control signals according to a difference between a first test signal and a second test signal connected to the differential amplifier; The two test control signals are respectively used to control the positive offset or negative offset of the output of the differential amplifier; when the output of the differential amplifier is zero, the difference between the first test signal and the second test signal is the offset voltage.

11. The operational amplifier trimming system according to claim 10, wherein: The imbalance detection circuit includes a driving subcircuit and an output subcircuit; The driving subcircuit is connected to the first input terminal and the second input terminal of the differential amplifier, and generates a driving signal according to the difference between the first test signal connected to the first input terminal and the second test signal connected to the second input terminal; The output subcircuit is connected to the driving subcircuit and generates two test control signals according to the driving signal.

12. The operational amplifier trimming system according to claim 11, wherein: The driving sub-circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor; The eighth transistor includes a control electrode connected to the first input terminal of the differential amplifier, a first electrode connected to a voltage source, and a second electrode connected to the twelfth transistor; The ninth transistor includes a control electrode connected to the second input terminal of the differential amplifier, a first electrode connected to the first electrode of the eighth transistor, and a second electrode connected to the tenth transistor; The tenth transistor includes a first electrode and a control electrode connected to the second electrode of the ninth transistor and the eleventh transistor, and a second electrode connected to the ground; The eleventh transistor includes a control electrode connected to the control electrode and the first electrode of the tenth transistor, a first electrode connected to the output subcircuit, and a second electrode connected to ground; The twelfth transistor includes a first electrode and a control electrode connected to the second electrode of the eighth transistor and the thirteenth transistor, and a second electrode connected to the ground; The thirteenth transistor includes a control electrode connected to the control electrode and the first electrode of the twelfth transistor, a first electrode connected to the control electrode of the tenth transistor and the control electrode of the eleventh transistor, and a second electrode connected to the ground.

13. The operational amplifier trimming system according to claim 12, wherein: The output sub-circuit includes a fourteenth transistor, a fifteenth transistor and a sixteenth transistor; The fourteenth transistor includes a first electrode connected to the voltage source, a control electrode connected to the driving subcircuit and the fifteenth transistor and the sixteenth transistor, and a second electrode; The fifteenth transistor includes a control electrode connected to the control electrode and the second electrode of the fourteenth transistor, a first electrode connected to the voltage source, and a second electrode connected to the differential amplifier; The sixteenth transistor includes a control electrode connected to the control electrode and the second electrode of the fourteenth transistor, a first electrode connected to the voltage source, and a second electrode connected to the differential amplifier.

14. An operational amplifier, characterized in that: A trimming system for an operational amplifier comprising a first differential input pair of transistors, a second differential input pair of transistors, a first amplifying branch, a second amplifying branch, an output circuit, and the operational amplifier according to any one of claims 1 to 13; The first amplifying branch is respectively connected to the first differential input pair of tubes, the second differential input pair of tubes and the trimming system of the operational amplifier; The second amplifying branch is respectively connected to the first differential input pair of transistors, the second differential input pair of transistors, the trimming system of the operational amplifier and the output circuit.

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