Front-end reading circuit for energy spectrum measurement system of silicon carbide detector

Abstract

The invention relates to a front-end reading circuit for an energy spectrum measurement system of a silicon carbide detector, which comprises a detector equivalent output circuit, a charge sensitive amplifier circuit, a secondary pole zero cancellation circuit, a secondary active filter shaping circuit and a proportional operational amplifier circuit which are sequentially connected in an integrated manner. Specifically, the charge sensitive amplifier is used for amplifying a signal and keeping the integrity of the signal; the secondary pole zero cancellation circuit shortens the signal rising and falling time and improves the signal response speed by optimizing capacitance and resistance parameters; the secondary active filtering and shaping circuit is used for filtering and shaping the signal, so that the signal becomes a quasi-Gaussian voltage pulse signal which is easier to process; and the proportional operational amplifier circuit linearly amplifies the filtered signal to meet the precision requirement of energy spectrum measurement. According to the circuit design, through reasonable integration, a compact and simple structure is realized, the development cost is reduced, and the response speed, the stability and the measurement precision of the system are improved.

Description

Technical Field

[0001] The invention relates to the technical field of nuclear radiation detection, and in particular to a front-end readout circuit for a silicon carbide detector energy spectrum measurement system. Background Art

[0002] At present, there are relatively few studies on the front-end circuits of SiC detector energy spectrum measurement systems. Existing related technologies mainly focus on connecting the detector directly to the charge-sensitive preamplifier circuit composed of an operational amplifier, and do not use junction field effect transistors (JFETs). In these circuit designs, a combination of a first-order pole-zero cancellation circuit and an active filter circuit is usually used to process the signal. This type of design structure is common in the front-end circuits of conventional semiconductor nuclear radiation detectors, which are usually based on transistors and chip structures.

[0003] However, there are some problems with the existing detector front-end readout circuits in practical applications. Since the design of these circuits often leads to the broadening of pulse signals, the rise and fall times of the signals are too long, which in turn leads to the phenomenon of pulse signal accumulation. This not only affects the response speed of the system, but also makes the filter shaping effect poor and cannot effectively suppress noise. Therefore, the signal-to-noise ratio is low and cannot meet the requirements of high-precision and fast-response SiC detector energy spectrum measurement. These technical limitations make it impossible for existing front-end circuit designs to fully tap the potential of SiC detectors in energy spectrum measurement.

[0004] In view of the above problems, the present invention is proposed. Summary of the invention

[0005] The invention discloses a front-end readout circuit for a silicon carbide detector energy spectrum measurement system, aiming to solve the technical problems existing in the prior art.

[0006] The present invention provides a front-end readout circuit for a silicon carbide detector energy spectrum measurement system, comprising a detector equivalent output circuit, a charge sensitive amplifier circuit, a secondary pole-zero phase cancellation circuit, a secondary active filter shaping circuit and a proportional operational amplifier circuit, wherein the detector equivalent output circuit, the charge sensitive amplifier circuit, the secondary pole-zero phase cancellation circuit, the secondary active filter shaping circuit and the proportional operational amplifier circuit are sequentially connected in an integrated manner;

[0007] The detector equivalent output circuit is used to convert the radiation signal into a charge pulse signal;

[0008] The charge sensitive amplifier circuit is provided with a junction field effect transistor JFET and a first operational amplifier U1, the junction field effect transistor JFET and the first operational amplifier are connected to serve as a first pole amplifier circuit to amplify the charge signal and maintain signal integrity;

[0009] The two-stage pole-zero phase cancellation circuit includes a second operational amplifier U2, a third operational amplifier U3, a plurality of capacitors and a plurality of resistors. By adjusting the parameters of the two-stage operational amplifiers and the plurality of capacitors and resistors, the rise and fall time of the signal is reduced to achieve rapid narrowing of the pulse signal.

[0010] A secondary active filtering and shaping circuit is used to filter and shape the voltage signal output by the secondary pole-zero cancellation circuit;

[0011] The proportional operational amplifier circuit is used to linearly proportionally amplify the filtered signal output by the secondary active filter shaping circuit to meet the requirements of the silicon carbide detector energy spectrum measurement system.

[0012] As a preferred technical solution, the charge sensitive amplifier circuit also includes an AC coupling capacitor Cs, the output end of the detector equivalent output circuit is connected to the input end of the AC coupling capacitor Cs, and the output end of the AC coupling capacitor Cs is connected to the gate of the junction field effect transistor JFET.

[0013] As a preferred technical solution, the charge-sensitive amplifier circuit also includes a feedback resistor Rf and a feedback capacitor Cf. The feedback resistor Rf and the feedback capacitor Cf are connected in parallel and in parallel with the connected junction field effect transistor JFET and the line of the first operational amplifier U1. The output end of the first operational amplifier U1 is connected to the gate of the junction field effect transistor JFET via the feedback resistor Rf and the feedback capacitor Cf.

[0014] As a preferred technical solution, the charge-sensitive amplifier circuit also includes an eleventh resistor R11, a twelfth resistor R12 and a thirteenth resistor R13, the drain of the junction field effect transistor JFET is connected to the positive voltage source VCC through the eleventh resistor R11; one end of the twelfth resistor 12 is connected to the positive voltage source VCC, and the other end is connected to the thirteenth resistor R13, the other end of the thirteenth resistor R13 is grounded, and the first operational amplifier U1 is provided with a first positive input terminal and a first reverse input terminal, the first forward input terminal is connected to the drain of the junction field effect transistor JFET, and the first reverse input terminal is connected between the twelfth resistor R12 and the thirteenth resistor R13.

[0015] As a preferred technical solution, the two-stage pole-zero cancellation circuit includes a second operational amplifier U2, a third operational amplifier U3, a first capacitor C1, a second capacitor C2, a first resistor R1 and a third resistor R3. The first capacitor C1 is connected in parallel with the first resistor R1, the second capacitor is connected in parallel with the third resistor R3, and the parallel first capacitor C1 is connected in sequence with the first resistor R1, the second operational amplifier U2, the parallel second capacitor and the third resistor R3, and the third operational amplifier U3.

[0016] As a preferred technical solution, the second operational amplifier U2 includes a second positive input terminal and a second reverse input terminal, the output terminal of the first capacitor C1 and the first resistor R1 is connected to the second positive input terminal, and the second reverse input terminal is connected to the output terminal of the second operational amplifier U2; the third operational amplifier U3 includes a third positive input terminal and a third reverse input terminal, the output terminal of the second capacitor and the third resistor R3 is connected to the third positive input terminal, and the third reverse input terminal is connected to the output terminal of the third operational amplifier U3.

[0017] As a preferred technical solution, a first node is provided between the output end of the first capacitor C1 and the first resistor R1 and the second positive input end, and the secondary pole-zero cancellation circuit also includes a second resistor R2, one end of the second resistor R2 is connected to the first node, and the other end is grounded.

[0018] As a preferred technical solution, the secondary active filter shaping circuit includes a fourth capacitor C4, a fifth resistor R5, a sixth resistor R6 and a fourth operational amplifier U4, the fourth operational amplifier U4 includes a fourth positive input terminal and a fourth reverse input terminal, the fifth resistor R5 and the sixth resistor R6 are connected in series, the fifth resistor R5 is connected to the fourth positive input terminal via the sixth resistor R6, a third node is provided between the fifth resistor R5 and the sixth resistor R6, one end of the fourth capacitor C4 is connected to the third node, the other end of the fourth capacitor C4 is connected to the output terminal of the fourth operational amplifier U4, and the output terminal of the fourth operational amplifier U4 is connected to its fourth reverse input terminal.

[0019] As a preferred technical solution, a second node is provided between the sixth resistor R6 and the fourth positive input terminal, and the secondary active filtering shaping circuit further includes a third capacitor C3, one end of the third capacitor C3 is connected to the second node, and the other end is grounded.

[0020] As a preferred technical solution, the secondary active filter shaping circuit also includes a seventh resistor R7, an eighth resistor R8, a sixth capacitor C6 and a fifth operational amplifier U5, the fifth operational amplifier U5 includes a fifth positive input terminal and a fifth reverse input terminal, the seventh resistor R7 and the eighth resistor R8 are connected in series, the seventh resistor R7 is connected to the fifth positive input terminal via the eighth resistor R8, a fourth node is provided between the seventh resistor R7 and the eighth resistor R8, one end of the sixth capacitor C6 is connected to the fourth node, the other end of the sixth capacitor C6 is connected to the output terminal of the fifth operational amplifier U5, and the output terminal of the fifth operational amplifier U5 is connected to its fifth reverse input terminal.

[0021] As a preferred technical solution, a fifth node is provided between the eighth resistor R8 and the fifth positive input terminal, and the secondary active filtering shaping circuit further includes a fifth capacitor C5, one end of the fifth capacitor C5 is connected to the fifth node, and the other end is grounded.

[0022] As a preferred technical solution, the detector equivalent output circuit includes a power flow I2, a detector equivalent capacitor Cd and a detector equivalent resistor Rd, and the power flow I2, the detector equivalent capacitor Cd and the detector equivalent resistor Rd are connected in parallel.

[0023] As a preferred technical solution, the proportional operational amplifier circuit includes a ninth resistor R9, a tenth resistor R10 and a sixth operational amplifier U6, the sixth operational amplifier U6 includes a sixth positive input terminal and a sixth reverse input terminal, the sixth reverse input terminal is connected to the ninth resistor R9, and is grounded via the ninth resistor R9, a sixth node is provided between the sixth reverse input terminal and the ninth resistor R9, one end of the tenth resistor R10 is connected to the sixth node, and the other end is connected to the output terminal of the sixth operational amplifier U6.

[0024] The technical solution adopted by the present invention can achieve at least one of the following beneficial effects:

[0025] 1. The present invention converts the weak charge pulse signal output by the silicon carbide detector into a voltage pulse signal through an integrated front-end readout circuit, and achieves efficient conversion while ensuring the signal-to-noise ratio. By optimizing the design of the charge sensitive amplifier and the secondary pole-zero cancellation circuit, the signal noise interference is significantly reduced, the signal integrity and transmission quality are improved, and a more reliable signal basis is provided for the detector energy spectrum measurement.

[0026] 2. The present invention adopts a two-stage pole-zero phase cancellation circuit, utilizes a multi-stage operational amplifier and optimizes the parameters of resistors and capacitors, successfully reduces the rise and fall time of the pulse signal, and achieves rapid signal narrowing. This technology avoids the problem of pulse signal accumulation, effectively improves the response speed and data processing capability of the detector energy spectrum measurement system, and meets the needs of high-precision and rapid measurement.

[0027] 3. The two-stage active filter shaping circuit designed in the present invention can further filter and shape the rapidly narrowed voltage pulse signal into a quasi-Gaussian voltage pulse signal. This shaped signal is easier for subsequent systems to accurately collect and process, while ensuring the measurement accuracy and stability of the detector energy spectrum measurement system.

[0028] 4. The present invention connects the detector equivalent output circuit, charge sensitive amplifier, pole-zero phase cancellation circuit, active filter shaping circuit and proportional operational amplifier circuit in sequence through reasonable integrated circuit design, thus achieving high integration and simplification of functions. The circuit structure is compact and the design is clear, which is not only convenient for actual production and application, but also reduces the development cost, providing strong support for the promotion and popularization of related technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments, which constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions explain the present invention and do not constitute improper limitations on the present invention. In the drawings:

[0030] Figure 1 It is a schematic diagram of the principle of a front-end readout circuit for a silicon carbide detector energy spectrum measurement system of the present invention;

[0031] Figure 2 The present invention is an output signal pulse waveform diagram of a front-end readout circuit for a silicon carbide detector energy spectrum measurement system.

[0032] Description of reference numerals:

[0033] 1. Detector equivalent output circuit; 2. Charge sensitive amplifier circuit; 3. Secondary pole-zero cancellation circuit; 4. Secondary active filter shaping circuit; 5. Proportional operational amplifier circuit;

[0034] I2. Current source; Cd. Detector equivalent capacitance; Cs. AC coupling capacitance; Cf. Feedback capacitance; C1. First capacitance; C2. Second capacitance; C3. Third capacitance; C4. Fourth capacitance; C5. Fifth capacitance; C6. Sixth capacitance; U1. First operational amplifier; U2. Second operational amplifier; U3. Third operational amplifier; U4. Fourth operational amplifier; U5. Fifth operational amplifier; U6. Sixth operational amplifier; Rd. Detector equivalent resistance; Rf. Feedback resistance; R1. First resistance; R2. Second resistance; R3. Third resistance; R4. Fourth resistance; R5. Fifth resistance; R6. Sixth resistance; R7. Seventh resistance; R8. Eighth resistance; R9. Ninth resistance; R10. Tenth resistance; R11. Eleventh resistance; R12. Twelfth resistance; R13. Thirteenth resistance; VCC. Positive voltage source; VEE. Negative voltage source. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the specific embodiments of the present invention and the corresponding drawings. In the description of the present invention, it should be noted that the term "or" is usually used in the sense of including "and / or", unless the content clearly indicates otherwise.

[0036] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or a magnetic connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be internal communication between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. In addition, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0037] In addition, unless the steps are specifically described or must occur in sequence, the order of the above steps is not limited to the above list, and can be changed or rearranged according to the required design. And the above embodiments can be mixed and matched with each other or with other embodiments based on design and reliability considerations, that is, the technical features in different embodiments can be freely combined to form more embodiments.

[0038] Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] In order to solve the problems existing in the prior art, an embodiment of the present invention provides a front-end readout circuit for a silicon carbide detector energy spectrum measurement system, such as Figure 1 As shown, it includes a detector equivalent output circuit 1, a charge sensitive amplifier circuit 2, a secondary pole-zero phase cancellation circuit 3, a secondary active filter shaping circuit 4 and a proportional operational amplifier circuit 5 which are connected in sequence, and the above circuits are connected in an inheritance manner. Among them, the detector equivalent output circuit 1 is used to perform equivalent processing on the signal output of the detector, and by converting the radiation signal of the detector into a voltage signal, provide appropriate impedance matching and signal methods to ensure signal integrity and reduce noise interference. The charge sensitive amplifier circuit 2 is used to perform high-sensitivity preliminary amplification on the weak voltage signal output by the detector equivalent output circuit 1, while ensuring a low noise level and high linearity. The secondary pole-zero phase cancellation circuit 3 is used to further optimize the signal output by the charge sensitive amplifier circuit 2 to improve the dynamic response and energy spectrum measurement accuracy of the silicon carbide detector energy spectrum measurement system. The secondary active filter shaping circuit 4 is used to filter and shape the signal output by the secondary pole-zero phase cancellation circuit 3 to optimize the signal quality and energy spectrum resolution capability. The proportional operational amplifier circuit 5 is used to linearly proportionally amplify the filtered and shaped signal to ensure that the signal amplitude meets the needs of subsequent data acquisition and processing.

[0040] like Figure 1As shown, the detector equivalent output circuit 1 includes a current source I2, a detector equivalent capacitor Cd and a detector equivalent resistor Rd. The current source I2, the detector equivalent capacitor Cd and the detector equivalent resistor Rd are connected in parallel. When the detector is excited by the energy of the radiation, a weak charge signal proportional to the incident energy is generated. The signal is converted into a transient current signal through the power supply I2 of the equivalent output circuit 1; the detector equivalent capacitor Cd is used to simulate the parasitic capacitance of the detector, determines the dynamic response characteristics of the circuit, and reflects the detector's storage capacity for charge signals; the detector equivalent resistor Rd characterizes the resistance characteristics inside the detector, and its value affects the attenuation rate of the signal and the noise performance of the energy spectrum measurement system.

[0041] The charge sensitive amplifier circuit 2 is used as a first-stage amplifier circuit, including an AC coupling capacitor Cs, a junction field effect transistor JFET, a first operational amplifier U1, a feedback resistor Rf and a feedback capacitor Cf. Among them, the output end of the detector equivalent output circuit 1 is connected to the input end of the AC coupling capacitor Cs, and the output end of the AC coupling capacitor Cs is connected to the gate of the junction field effect transistor JFET. The feedback resistor Rf and the feedback capacitor Cf are connected in parallel, and are connected in parallel with the circuit line connecting the first operational amplifier U1 and the junction field effect transistor JFET. The output end of the first operational amplifier U1 is connected to the gate of the junction field effect transistor JFET after passing through the above-mentioned parallel feedback resistor Rf and feedback capacitor Cf. The input end of the first operational amplifier U1 includes a first positive input end and a first reverse input end. The first positive input end is connected to the drain of the junction field effect transistor JFET, and the first reverse input end is connected between the twelfth resistor R12 and the thirteenth resistor R13. The two power supply ends of the first operational amplifier U1 are connected to a 5V positive voltage source VCC and a -5V negative voltage source VEE respectively. One end of the twelfth resistor R12 is connected to the 5V positive voltage source VCC, and the other end is connected to the thirteenth resistor R13, and the other end of the thirteenth resistor R13 is grounded. The drain of the junction field effect transistor JFET is connected to the 5V positive voltage source VCC through the eleventh resistor R11, and the source is grounded. The introduction of the junction field effect transistor JFET in the charge sensitive amplifier circuit 2 can effectively reduce the load effect of the signal source, ensure that the weak signal is not significantly attenuated during the transmission process, and maintain the integrity of the signal.

[0042] The two-stage pole-zero phase cancellation circuit 3 includes a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a second operational amplifier U2 and a third operational amplifier U3, wherein the second operational amplifier U2 is provided with a second positive input terminal and a second reverse input terminal, and the third operational amplifier U3 is provided with a third positive input terminal and a third reverse input terminal. The first capacitor C1 and the first resistor R1 are connected in parallel, the output terminal of the first operational amplifier U1 is connected to the second positive input terminal of the second operational amplifier U2 after the first capacitor C1 and the first resistor R1 are connected in parallel, the second reverse input terminal of the second operational amplifier U2 is connected to its output terminal, and the two power supply terminals of the second operational amplifier U2 are connected to a 5V positive voltage source VCC and a -5V negative voltage source VEE, respectively. A first node is provided between the output terminal and the second positive input terminal of the first capacitor C1 and the first resistor R1 connected in parallel, one end of the second resistor R2 is connected to the first node, and the other end of the second resistor R2 is grounded. The second capacitor C2 and the third resistor R3 are connected in parallel, the output end of the second operational amplifier U2 is connected to the third positive input end of the third operational amplifier U3 after passing through the second capacitor C2 and the third resistor R3 connected in parallel, the third reverse input end of the third operational amplifier U3 is connected to its output end, and the two power supply ends of the third operational amplifier U3 are connected to the 5V positive voltage source VCC and the -5V negative voltage source VEE respectively. The parallel output end of the second capacitor C2 and the third resistor R3 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded.

[0043] The secondary active filter shaping circuit 4 includes a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a fourth operational amplifier U4 and a fifth operational amplifier U5, wherein the fourth operational amplifier U4 and the fifth operational amplifier U5 are respectively provided with a fourth positive input terminal, a fourth reverse input terminal, a fifth positive input terminal and a fifth reverse input terminal. Among them, the output terminal of the third operational amplifier U3 is connected to one end of the fifth resistor R5, the fifth resistor R5 is connected in series with the sixth resistor R6, and the other end of the fifth resistor R5 is connected to the fourth positive input terminal of the fourth operational amplifier U4 through the sixth resistor R6. A second node is provided between the sixth resistor R6 and the fourth positive input terminal of the fourth operational amplifier U4, one end of the third capacitor C3 is connected to the second node, and the other end is grounded. A third node is provided between the fifth resistor R5 and the sixth resistor R6, one end of the fourth capacitor C4 is connected to the third node, and the other end is connected to the output terminal of the fourth operational amplifier U4. The fourth inverting input terminal of the fourth operational amplifier U4 is connected to its output terminal, and the two power supply terminals of the fourth operational amplifier U4 are connected to the 5V positive voltage source VCC and the -5V negative voltage source VEE respectively. The secondary active filtering shaping circuit 4 can further filter the rapidly narrowed voltage pulse signal and shape it into a quasi-Gaussian voltage pulse signal.

[0044] The seventh resistor R7 is connected to the eighth resistor R8, one end of the seventh resistor R7 is connected to the output end of the fourth operational amplifier U4, and the other end is connected to the fifth positive input end of the fifth operational amplifier U5 through the eighth resistor R8. A fourth node is provided between the fourth resistor R7 and the eighth resistor R8, a fifth node is provided between the eighth resistor R8 and the fifth positive input end, one end of the fifth capacitor C5 is connected to the fifth node, and the other end is grounded; one end of the sixth capacitor C6 is connected to the fourth node, and the other end is connected to the output end of the fifth operational amplifier U5. The fifth direction input end of the fifth operational amplifier U5 is connected to its output end, and the two power supply ends of the fifth operational amplifier U5 are connected to the 5V positive voltage source VCC and the -5V negative voltage source VEE respectively.

[0045] The proportional operational amplifier circuit 5 includes a ninth resistor R9, a tenth resistor R10 and a sixth operational amplifier U6, wherein the sixth operational amplifier U6 is provided with a sixth positive input terminal and a sixth reverse input terminal. The output terminal of the fifth operational amplifier U5 is connected to the sixth positive input terminal of the sixth operational amplifier U6, the sixth reverse input terminal of the sixth operational amplifier U6 is connected to the ninth resistor R9 and is grounded via the ninth resistor R9, and the two power supply terminals of the sixth operational amplifier U6 are respectively connected to a 5V positive voltage source VCC and a -5V negative voltage source VEE. A sixth node is provided between the sixth reverse input terminal and the ninth resistor R9, one end of the tenth resistor R10 is connected to the sixth node, and the other end is connected to the output terminal of the sixth operational amplifier U6.

[0046] Through the above circuit design, the embodiment of the present invention realizes the complete processing link of the radiation signal from detection to high-precision energy spectrum measurement through four steps of signal conversion and primary amplification, dynamic optimization and pole-zero phase cancellation, signal filtering and shaping, and linear amplification and output, which significantly improves the performance and reliability of the energy spectrum measurement system of the silicon carbide detector. Among them, the signal conversion and primary amplification are specifically that the silicon carbide detector converts the received radiation signal into a weak charge pulse signal, and through the detector equivalent output circuit 1, the signal is converted into a transient current signal and impedance matching and signal integrity assurance are achieved; then, the charge sensitive amplifier circuit 2 converts the charge signal into a voltage signal, and uses the feedback capacitor Cf and the feedback resistor Rf to ensure high-sensitivity amplification, noise suppression and DC operating point stability. Dynamic optimization and pole-zero phase cancellation are specifically that the signal passes through the secondary pole-zero phase cancellation circuit 3, and by adjusting the parameters of the capacitor and the resistor, the rise and fall time of the signal is reduced, the pulse signal is quickly narrowed, and the dynamic response characteristics are optimized. Specifically, the signal filtering and shaping is that in the secondary active filtering shaping circuit 4, the signal shape is adjusted to a quasi-Gaussian pulse waveform through the precise configuration of multiple resistors and multiple capacitors, further improving the signal-to-noise ratio and energy spectrum resolution. Specifically, the linear amplification and output is that the proportional operational amplifier circuit 5 adjusts the output gain according to the set resistance ratio, and linearly proportionally amplifies the filtered signal so that its amplitude meets the requirements of subsequent data acquisition and processing.

[0047] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A front-end readout circuit for a silicon carbide detector energy spectrum measurement system, characterized in that: It includes a detector equivalent output circuit, a charge sensitive amplifier circuit, a secondary pole-zero phase cancellation circuit, a secondary active filter shaping circuit and a proportional operational amplifier circuit, wherein the detector equivalent output circuit, the charge sensitive amplifier circuit, the secondary pole-zero phase cancellation circuit, the secondary active filter shaping circuit and the proportional operational amplifier circuit are sequentially connected in an integrated manner; The detector equivalent output circuit is used to convert the radiation signal into a charge pulse signal; The charge sensitive amplifier circuit is provided with a junction field effect transistor JFET and a first operational amplifier U1, wherein the junction field effect transistor JFET is connected to the first operational amplifier and is used as a first pole amplifier circuit to amplify the charge signal and maintain signal integrity; The two-stage pole-zero phase cancellation circuit includes a second operational amplifier U2, a third operational amplifier U3, a plurality of capacitors and a plurality of resistors. By adjusting the parameters of the two-stage operational amplifier and the plurality of capacitors and resistors, the rise and fall time of the signal is reduced to achieve rapid narrowing of the pulse signal. The secondary active filtering and shaping circuit is used to filter and shape the voltage signal output by the secondary pole-zero cancellation circuit for output; The proportional operational amplifier circuit is used to linearly proportionally amplify the filtered signal output by the secondary active filtering shaping circuit to meet the requirements of the energy spectrum measurement system of the silicon carbide detector.

2. The front-end readout circuit according to claim 1, characterized in that: The charge sensitive amplifier circuit also includes an AC coupling capacitor Cs, the output end of the detector equivalent output circuit is connected to the input end of the AC coupling capacitor Cs, and the output end of the AC coupling capacitor Cs is connected to the gate of the junction field effect transistor JFET.

3. The front-end readout circuit according to claim 2, characterized in that: The charge-sensitive amplifier circuit also includes a feedback resistor Rf and a feedback capacitor Cf, which are connected in parallel and in parallel with the connected junction field effect transistor JFET and the first operational amplifier U1. The output end of the first operational amplifier U1 is connected to the gate of the junction field effect transistor JFET via the feedback resistor Rf and the feedback capacitor Cf.

4. The front-end readout circuit according to claim 3, characterized in that: The charge-sensitive amplifier circuit also includes an eleventh resistor R11, a twelfth resistor R12 and a thirteenth resistor R13. The drain of the junction field effect transistor JFET is connected to the positive voltage source VCC through the eleventh resistor R11; one end of the twelfth resistor 12 is connected to the positive voltage source VCC, and the other end is connected to the thirteenth resistor R13. The other end of the thirteenth resistor R13 is grounded. The first operational amplifier U1 is provided with a first positive input terminal and a first reverse input terminal. The first positive input terminal is connected to the drain of the junction field effect transistor JFET, and the first reverse input terminal is connected between the twelfth resistor R12 and the thirteenth resistor R13.

5. The front-end readout circuit according to claim 1, characterized in that: The secondary pole-zero cancellation circuit includes the second operational amplifier U2, the third operational amplifier U3, the first capacitor C1, the second capacitor C2, the first resistor R1 and the third resistor R3, the first capacitor C1 is connected in parallel with the first resistor R1, the second capacitor is connected in parallel with the third resistor R3, the first capacitor C1 in parallel is connected in sequence with the first resistor R1, the second operational amplifier U2, the second capacitor and the third resistor R3 in parallel, and the third operational amplifier U3.

6. The front-end readout circuit according to claim 5, characterized in that: The second operational amplifier U2 includes a second positive input terminal and a second reverse input terminal, the output terminal of the first capacitor C1 and the first resistor R1 is connected to the second positive input terminal, and the second reverse input terminal is connected to the output terminal of the second operational amplifier U2; the third operational amplifier U3 includes a third positive input terminal and a third reverse input terminal, the output terminal of the second capacitor and the third resistor R3 is connected to the third positive input terminal, and the third reverse input terminal is connected to the output terminal of the third operational amplifier U3.

7. The front-end readout circuit according to claim 6, characterized in that: A first node is provided between the output ends of the first capacitor C1 and the first resistor R1 and the second positive input end. The secondary pole-zero cancellation circuit further includes a second resistor R2. One end of the second resistor R2 is connected to the first node and the other end is grounded.

8. The front-end readout circuit according to claim 1, characterized in that: The secondary active filtering shaping circuit includes a fourth capacitor C4, a fifth resistor R5, a sixth resistor R6 and a fourth operational amplifier U4, the fourth operational amplifier U4 includes a fourth positive input terminal and a fourth reverse input terminal, the fifth resistor R5 and the sixth resistor R6 are connected in series, the fifth resistor R5 is connected to the fourth positive input terminal via the sixth resistor R6, a third node is provided between the fifth resistor R5 and the sixth resistor R6, one end of the fourth capacitor C4 is connected to the third node, the other end of the fourth capacitor C4 is connected to the output terminal of the fourth operational amplifier U4, and the output terminal of the fourth operational amplifier U4 is connected to the fourth reverse input terminal thereof.

9. The front-end readout circuit according to claim 8, characterized in that: A second node is provided between the sixth resistor R6 and the fourth positive input terminal. The secondary active filtering shaping circuit further includes a third capacitor C3. One end of the third capacitor C3 is connected to the second node, and the other end is grounded.

10. The front-end readout circuit according to claim 1, characterized in that: The secondary active filtering shaping circuit also includes a seventh resistor R7, an eighth resistor R8, a sixth capacitor C6 and a fifth operational amplifier U5. The fifth operational amplifier U5 includes a fifth positive input terminal and a fifth reverse input terminal. The seventh resistor R7 and the eighth resistor R8 are connected in series. The seventh resistor R7 is connected to the fifth positive input terminal via the eighth resistor R8. A fourth node is provided between the seventh resistor R7 and the eighth resistor R8. One end of the sixth capacitor C6 is connected to the fourth node. The other end of the sixth capacitor C6 is connected to the output terminal of the fifth operational amplifier U5. The output terminal of the fifth operational amplifier U5 is connected to the fifth reverse input terminal thereof.

11. The front-end readout circuit according to claim 10, characterized in that: A fifth node is provided between the eighth resistor R8 and the fifth positive input terminal. The secondary active filtering shaping circuit further includes a fifth capacitor C5. One end of the fifth capacitor C5 is connected to the fifth node, and the other end is grounded.

12. The front-end readout circuit according to any one of claims 1 to 11, characterized in that: The detector equivalent output circuit includes a power flow I2, a detector equivalent capacitor Cd and a detector equivalent resistor Rd, and the power flow I2, the detector equivalent capacitor Cd and the detector equivalent resistor Rd are connected in parallel.

13. The front-end readout circuit according to any one of claims 1 to 11, characterized in that: The proportional operational amplifier circuit comprises a ninth resistor R9, a tenth resistor R10 and a sixth operational amplifier U6, wherein the sixth operational amplifier U6 comprises a sixth positive input terminal and a sixth reverse input terminal, wherein the sixth reverse input terminal is connected to the ninth resistor R9 and is grounded via the ninth resistor R9, a sixth node is arranged between the sixth reverse input terminal and the ninth resistor R9, one end of the tenth resistor R10 is connected to the sixth node, and the other end is connected to the output terminal of the sixth operational amplifier U6.

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