Order-adjustable time domain pulse pressure filtering method after digital down-conversion down-sampling

Abstract

The invention belongs to the technical field of time domain pulse pressure filtering, and provides an order-adjustable time domain pulse pressure filtering method after digital down-conversion down-sampling. Comprising the steps of down-sampling frequency multiplication filter order writing, DDC down-sampling signal writing, RAM read-write time sequence sending, DDC down-sampling signal and down-sampling frequency multiplication filter order sending, configuration coefficient sending, DDC down-sampling signal calculation, convolution summation control signal sending and convolution summation. According to the invention, the order of the filter is dynamically adjusted through the RAM read-write control module and the order of the down-sampling frequency multiplication filter, the limitation of a traditional method on the fixed order is solved, and the application scene of the system is enriched; by associating the order of the down-sampling frequency multiplication filter with the down-sampling multiple of the DDC down-sampling signal, the stretching of the time window is realized, and the processing of larger-scale data under the same resource is realized.

Description

Technical Field

[0001] The invention relates to the technical field of time domain pulse compression filtering, and in particular to a time domain pulse compression filtering method with adjustable order after digital down-conversion and down-sampling. Background Art

[0002] Pulse compression is a basic operation in radar signal processing and has been widely used in the field of radar target detection and imaging. Pulse compression achieves intra-pulse coherent focusing of echo signal energy, and energy peaks appear at specific locations, corresponding to the target.

[0003] Time-domain pulse compression filtering is usually performed after digital down-conversion. For this common usage scenario, the current time-domain pulse compression filtering method may have some problems, such as the fixed order is difficult to flexibly adapt to different scenarios, resulting in a waste of computing resources; in addition, after digital down-conversion and downsampling, the traditional time-domain pulse compression filter cannot use matching downsampling multiples to fully utilize the computing cycle. These problems limit the signal processing effect in the time-domain pulse compression scenario. Summary of the invention

[0004] In order to overcome the shortcomings of the prior art, the purpose of the present invention is to provide a time-domain pulse compression filtering method with adjustable order after digital down-conversion downsampling, and dynamically adjust the filter order through a RAM read-write control module and a down-sampling frequency multiplication filter order, so as to solve the limitation of the traditional method on the fixed order and enrich the application scenarios of the system; by associating the down-sampling frequency multiplication filter order with the down-sampling multiple of the DDC down-sampling signal, the time window is stretched, and the processing of larger-scale data is achieved under the same resources.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A time-domain pulse compression filtering method with adjustable order after digital down-conversion and down-sampling, comprising:

[0007] Write the downsampling frequency multiplication filter order into the RAM read-write control module;

[0008] Write the DDC downsampled signal into the data buffer RAM;

[0009] Using the RAM read-write control module to send the RAM read-write timing to the data cache RAM;

[0010] Controlling the data cache RAM to send the DDC down-sampling signal and the down-sampling frequency multiplication filter order to the complex multiplier according to the RAM read and write timing;

[0011] Sending configuration coefficients to the complex multiplier using an external coefficient storage RAM;

[0012] Calculating the DDC down-sampling signal using the configuration coefficient and the down-sampling frequency multiplication filter order to obtain a complex multiplication result;

[0013] The complex multiplication result and the convolution summation control signal output by the RAM read-write control module are transmitted to the parallel convolution summation module;

[0014] The complex multiplication results are summed using the convolution sum control signal to obtain a filtering completion signal.

[0015] Preferably, the calculation formula of the complex multiplier is:

[0016]

[0017] Among them, y[n] is the complex multiplication result; h[k] is the configuration coefficient; M is the order of the downsampling frequency multiplication filter; X[nk] is the filter input; k is the index value; and n is the sample index.

[0018] Preferably, the storage bit width and the read bit width of the data cache RAM are 4 and 8 respectively.

[0019] Preferably, each group of the configuration coefficients includes: 8 coefficient values; the configuration coefficients are stored sequentially starting from address 0 in the external coefficient storage RAM.

[0020] Preferably, the data cache RAM comprises: a last_ptr address register with a bit width of 5; the 1-way bit width of the last_ptr address register is used to distinguish between the upper 4-way data addresses and the lower 4-way data addresses.

[0021] Preferably, the calculation formula for the downsampling frequency multiplication filter order is:

[0022] M = (D-2)*8;

[0023] Wherein, D is the downsampling multiple of the DDC downsampling signal.

[0024] The present invention discloses the following technical effects:

[0025] The invention provides a time-domain pulse compression filtering method with adjustable order after digital down-conversion downsampling. Through a RAM read-write control module and a down-sampling frequency multiplication filter order, the limitation of the traditional method on the fixed order is solved, and the filter order is dynamically adjusted; by associating the down-sampling frequency multiplication filter order with the down-sampling multiple of a DDC down-sampling signal, the problem of poor large-scale data processing capability of a conventional system is solved, and the stretching of the time window and the processing of larger-scale data under the same resources are realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0027] Figure 1 A schematic diagram of a time-domain pulse compression filtering process with adjustable order after digital down-conversion and down-sampling provided by an embodiment of the present invention;

[0028] Figure 2 A time-domain pulse compression filter system with adjustable order provided by an embodiment of the present invention;

[0029] Figure 3 A block diagram of an external coefficient storage RAM provided for an embodiment of the present invention;

[0030] Figure 4 A block diagram of a data cache RAM provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] The purpose of the present invention is to provide a time-domain pulse compression filtering method with adjustable order after digital down-conversion downsampling, which realizes dynamic adjustment of the filter order through a RAM read-write control module and a down-sampling frequency multiplication filter order, solves the limitation of the traditional method on the fixed order, and enriches the application scenarios of the system; by associating the down-sampling frequency multiplication filter order with the down-sampling multiple of the DDC down-sampling signal, the time window is stretched, and the processing of larger-scale data is realized under the same resources.

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] Figure 1 The schematic diagram of the time domain pulse compression filtering process with adjustable order after digital down-conversion and down-sampling provided by the embodiment of the present invention is as follows: Figure 1 As shown, the present invention provides a time-domain pulse compression filtering method with adjustable order after digital down-conversion and down-sampling, comprising:

[0035] Step 100: Write the downsampling frequency multiplication filter order into the RAM read-write control module;

[0036] Step 200: writing the DDC down-sampling signal into the data buffer RAM;

[0037] Step 300: using the RAM read / write control module to send the RAM read / write timing to the data cache RAM;

[0038] Step 400: Control the data cache RAM to send a DDC down-sampling signal and a down-sampling frequency multiplication filter order to the complex multiplier according to the RAM read and write timing;

[0039] Step 500: Send configuration coefficients to the complex multiplier using an external coefficient storage RAM;

[0040] Step 600: Calculate the DDC down-sampled signal using the configuration coefficient and the down-sampled frequency multiplication filter order to obtain a complex multiplication result;

[0041] Step 700: The complex multiplication result and the convolution summation control signal output by the RAM read-write control module are transmitted to the parallel convolution summation module;

[0042] Step 800: Use the convolution sum control signal to sum the complex multiplication results to obtain a filtering completion signal.

[0043] Furthermore, the calculation formula of the complex multiplier is:

[0044]

[0045] Where y[n] is the result of complex multiplication; h[k] is the configuration coefficient; M is the order of the downsampling multiplication filter; X[nk] is the filter input; k is the index value; and n is the sample index.

[0046] Specifically, the storage bit width and the read bit width of the data cache RAM are 4 and 8, respectively.

[0047] Preferably, each group of configuration coefficients includes: 8 coefficient values; the configuration coefficients are stored sequentially starting from address 0 in the external coefficient storage RAM.

[0048] Specifically, the data cache RAM includes: a last_ptr address register with a bit width of 5; the 1-way bit width of the last_ptr address register is used to distinguish between the upper 4-way data addresses and the lower 4-way data addresses.

[0049] Furthermore, the calculation formula for the downsampling frequency multiplication filter order is:

[0050] M = (D-2)*8;

[0051] Wherein, D is the downsampling multiple of the DDC downsampling signal.

[0052] Specifically, the time domain pulse compression filter is a FIR filter structure, and the algorithm formula is as follows:

[0053]

[0054] Furthermore, since the use scenarios of time-domain pulse compression are mostly high-frequency signals, multi-channel parallel design is often used in integrated circuit processing. Here, the design is carried out using 8-channel parallel time-domain pulse compression filter and 4-channel parallel DDC module as examples. Other parallel designs can be implemented with the same principle. In this embodiment, the time-domain pulse compression module uses a working clock with the same frequency as the DDC module, and D is set as the downsampling multiple of the DDC data. For each input of DDC data, the time-domain pulse compression filter can have D clock cycles to perform filtering calculations. Taking into account the splicing caused by the mismatch of input and output parallelism in engineering implementation, the first and last readings each waste a clock cycle. The maximum supported order of the time-domain pulse compression filter that can be implemented in the design of this article is:

[0055] M=(D-2)*8

[0056] M=(D-2)*8. For example, in the case of 48-fold downsampling, the maximum time-domain pulse compression order that can be supported is (48-2)*8.

[0057] Specifically, the coefficient storage RAM is described as follows: Because there are 8 parallel paths, each group of 8 coefficients is stored in the coefficient RAM in sequence starting from address 0. When reading coefficients, read from address 0 until M / 8 read configurations are completed.

[0058] refer to Figure 3 and Figure 4 , Data storage RAM description: Data is stored in RAM in a loop, each storage is 4 data bits wide, each read is 8 data bits wide, so a last_ptr address register is needed to store the earliest data address. This register needs to have 1 more bit than the address bit width to distinguish the high and low 4-way data addresses. Reading process: Starting from the earliest data last_ptr address, read M / 8 data in sequence. Each read data bit width is 8 data bits wide. Storage process: After the reading is completed, the latest received 4-way DDC down-sampling data is immediately stored in the earliest data address, and the storage data bit width is 4 data bits wide (it is necessary to determine whether to store in the high 4-way or the low 4-way according to the high and low 4-way flags of last_ptr), and this address becomes the address of the latest data. At the same time, add 1 to the value of the last_ptr register. Note: When reaching the data RAM boundary, the address needs to be rolled and updated (if n is the last address, then n+1 is updated to 0 address).

[0059] Specifically, the filtering calculation process: first, the filter order is determined according to the selected downsampling multiple. After the system is reset, the filter coefficient and filter order are configured in the system. When the DDC downsampling data is received, the calculation is started by sampling the rising edge of the valid data. First, the M-order coefficients are read in sequence from the 0 address of the coefficient RAM (because it is 8-way parallel, it is actually read M / 8 times). At the same time, the data previously cached in sequence in the data cache RAM is read in sequence. The read data and coefficients are sent to the complex multiplier for multiplication one by one. After one clock cycle, the multiplier outputs the multiplication result and sends it to the accumulator for accumulation, and the accumulated result is used as the filter output.

[0060] The beneficial effects of the present invention are as follows:

[0061] The present invention realizes dynamic adjustment of the filter order through the RAM read-write control module and the downsampling frequency multiplication filter order, solves the limitation of the traditional method on the fixed order, and enriches the application scenarios of the system; by associating the downsampling frequency multiplication filter order with the downsampling multiple of the DDC downsampling signal, the time window is stretched, and the processing of larger-scale data under the same resources is realized.

[0062] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0063] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A time-domain pulse compression filtering method with adjustable order after digital down-conversion and down-sampling, characterized in that: include: Write the downsampling frequency multiplication filter order into the RAM read-write control module; Write the DDC downsampled signal into the data buffer RAM; Using the RAM read-write control module to send the RAM read-write timing to the data cache RAM; Controlling the data cache RAM to send the DDC down-sampling signal and the down-sampling frequency multiplication filter order to the complex multiplier according to the RAM read and write timing; Sending configuration coefficients to the complex multiplier using an external coefficient storage RAM; Calculating the DDC down-sampling signal using the configuration coefficient and the down-sampling frequency multiplication filter order to obtain a complex multiplication result; The complex multiplication result and the convolution summation control signal output by the RAM read-write control module are transmitted to the parallel convolution summation module; The complex multiplication results are summed using the convolution sum control signal to obtain a filtering completion signal.

2. The method for time-domain pulse compression filtering with adjustable order after digital down-conversion and down-sampling according to claim 1, characterized in that: The calculation formula of the complex multiplier is: Among them, y[n] is the complex multiplication result; h[k] is the configuration coefficient; M is the order of the downsampling frequency multiplication filter; X[nk] is the filter input; k is the index value; and n is the sample index.

3. The method for time-domain pulse compression filtering with adjustable order after digital down-conversion and down-sampling according to claim 1, characterized in that: The storage bit width and read bit width of the data cache RAM are 4 and 8 respectively.

4. The method for time-domain pulse compression filtering with adjustable order after digital down-conversion and down-sampling according to claim 1, characterized in that: Each group of the configuration coefficients includes: 8 coefficient values; the configuration coefficients are stored sequentially starting from address 0 in the external coefficient storage RAM.

5. The method for time-domain pulse compression filtering with adjustable order after digital down-conversion and down-sampling according to claim 1, characterized in that: The data cache RAM includes: a last_ptr address register with a bit width of 5; the 1-way bit width of the last_ptr address register is used to distinguish between the upper 4-way data addresses and the lower 4-way data addresses.

6. The method for time-domain pulse compression filtering with adjustable order after digital down-conversion and down-sampling according to claim 2, characterized in that: The calculation formula of the downsampling frequency multiplication filter order is: M = (D-2)*8; Wherein, D is the downsampling multiple of the DDC downsampling signal.

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