Annular voltage-controlled oscillator with wide frequency range and low phase noise

Abstract

The invention discloses an annular voltage-controlled oscillator with a wide frequency range and low phase noise, a phase-locked loop, a chip and electronic equipment, and relates to the technical field of semiconductor chips, and the annular voltage-controlled oscillator with four paths of quadrature phase output is formed through two stages of delay units. The delay unit comprises a variable capacitor, a variable capacitor array and a fixed capacitor array; a wide frequency range is realized by adjusting the fixed capacitor array; the oscillation frequency of the annular voltage-controlled oscillator is further adjusted by adjusting the variable capacitance through the control voltage, and Kvco and Kpush of the annular voltage-controlled oscillator are effectively reduced by adjusting and selecting a proper variable capacitance value, so that the phase noise is reduced; and more stable Kvco in a full frequency band is obtained by cooperatively adjusting the variable capacitor array and the fixed capacitor array. According to the invention, a wide frequency range is realized, low Kvco, low Kpushing and low output noise are realized, and the difficulty of loop design and noise optimization of the phase-locked loop can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chips, and in particular to a ring voltage-controlled oscillator, a phase-locked loop, a chip and an electronic device with a wide frequency range and low phase noise. Background Art

[0002] In integrated circuit design, the clock is the key to synchronize the work of each module. The stability of the clock signal directly affects the performance and reliability of the entire system. Among them, the clock generator is usually implemented using a phase-locked loop circuit, and the voltage-controlled oscillator (VCO) is an important component of the phase-locked loop, which adjusts the oscillation frequency according to the input control voltage. According to the overall structure, the voltage-controlled oscillator can be divided into an inductor-capacitor type (LC VCO) and a ring voltage-controlled oscillator (Ring VCO). The phase-locked loop based on the Ring VCO structure is widely used as the system clock of integrated circuits due to its small area and low power consumption. It is used as an interface clock source in various communication protocol interfaces such as low-voltage differential signaling (LVDS), serial deserializer (serdes), mipi, USB, SATA, JESD204B, PCIE-Express Gen1-5, HDMI, etc.

[0003] Traditional Ring VCO is usually implemented in the form of controlling the power supply voltage of the inverter connected in a ring. In order to meet the wide frequency adjustment range, the traditional Ring VCO structure usually has a large gain coefficient (Kvco) and a large Kvco fluctuation range, which makes the phase noise of the Ring VCO larger. The sensitivity of the Ring VCO to power supply fluctuations, namely the RingVCO push (Kpushing), is positively correlated with Kvco. Therefore, when Kvco is larger, Kpushing is also larger, which will increase the contribution of power supply noise. Large Kvco and wide Kvco variation range will increase the difficulty of phase-locked loop parameter design and loop noise optimization. Large Kpushing will increase the difficulty of designing the linear regulator (LDO) powered by the Ring VCO. For example, it is necessary to design an LDO with extremely low noise output and high power supply voltage rejection ratio (PSRR) in the full frequency band according to the output noise index of the Ring VCO. Summary of the invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, the present invention provides a ring voltage-controlled oscillator with low phase noise over a wide frequency range. A two-stage delay unit constitutes a ring voltage-controlled oscillator with four-way orthogonal phase output. Variable capacitors, variable capacitor arrays and fixed capacitor arrays are used to coordinately adjust the delay unit of the ring voltage-controlled oscillator to achieve a wide frequency range while obtaining lower Kvco and Kpushing, thereby reducing phase noise and making Kvco more stable over the entire frequency band.

[0005] In a first aspect, an embodiment of the present invention provides a ring voltage-controlled oscillator with a wide frequency range and low phase noise, comprising: The ring voltage-controlled oscillator comprises two levels of delay units with the same structure, wherein the positive phase output of the first delay unit is connected to the positive phase input of the second delay unit, the negative phase output of the first delay unit is connected to the negative phase input of the second delay unit, the positive phase output of the second delay unit is connected to the negative phase input of the first delay unit, and the negative phase output of the second delay unit is connected to the positive phase input of the first delay unit, forming an oscillation loop, wherein the oscillation loop is provided with power supply voltage by a reference voltage source and a linear regulator; each level of the delay unit is connected to a control voltage and a digital control signal, and the control voltage and the digital control signal are used to adjust the oscillation frequency.

[0006] Optionally, in some embodiments of the present invention, the delay unit includes: a first inverter, a second inverter, a third inverter, a fourth inverter, a first variable capacitor, a second variable capacitor, a variable capacitor array and a fixed capacitor array; The input end of the first inverter is the positive phase input end of the delay unit, the output end of the first inverter is connected to the input end of the second inverter and the output end of the fourth inverter, the input end of the third inverter is the negative phase input end of the delay unit, the output end of the third inverter is connected to the output end of the second inverter and the input end of the fourth inverter, the output end of the second inverter is the positive phase output end of the delay unit, and the output end of the fourth inverter is the negative phase output end of the delay unit; the output end of the second inverter and the output end of the fourth inverter are connected in parallel: the first variable capacitor and the second variable capacitor, the variable capacitor array and the fixed capacitor array are connected in series, and the control voltage is connected to the first variable capacitor, the second variable capacitor and the variable capacitor array.

[0007] Furthermore, it also includes: The fixed capacitor array is used to obtain a wide frequency range; The control voltage adjusts the first variable capacitor, the second variable capacitor and the variable capacitor array to reduce the gain coefficient; The variable capacitor array and the fixed capacitor array are adjusted in coordination to ensure that the gain coefficient is constant over the entire frequency band.

[0008] Optionally, in some embodiments of the present invention, the variable capacitor array includes a plurality of variable capacitor groups with the same structure, and the variable capacitor group includes: a first switch, a second switch, a third variable capacitor and a fourth variable capacitor; The first end of the third variable capacitor is connected to the output end of the second inverter through the first switch, the first end of the fourth variable capacitor is connected to the output end of the fourth inverter through the second switch, and the second end of the third variable capacitor is connected to the second end of the fourth variable capacitor.

[0009] Optionally, in some embodiments of the present invention, the fixed capacitor array includes a plurality of fixed capacitor groups with the same structure, and the fixed capacitor group includes: a first fixed capacitor, a second fixed capacitor and a third switch; The first end of the first fixed capacitor is connected to the output end of the second inverter, the second end of the first fixed capacitor is connected to the second end of the second fixed capacitor through the third switch, and the second end of the second fixed capacitor is connected to the output end of the fourth inverter.

[0010] Optionally, in some embodiments of the present invention, an automatic frequency band selection architecture of a ring voltage controlled oscillator is further included, the automatic frequency band selection architecture comprising: a ring voltage controlled oscillator, a fixed voltage generation module, an automatic frequency calibration divider and a digital automatic frequency calibration module; The control voltage provided by the fixed voltage generation module is input to the delay unit of the ring voltage controlled oscillator, the ring voltage controlled oscillator starts to oscillate, and the output oscillation frequency signal is input to the digital automatic frequency calibration module after being divided by the automatic frequency calibration divider. The digital automatic frequency calibration module successively approximates the optimal digital control signal according to a given frequency target value, and outputs it to the ring voltage controlled oscillator to complete automatic calibration.

[0011] Optionally, in some embodiments of the present invention, the phase difference between the positive phase input and the positive phase output, and between the negative phase input and the negative phase output of each level of the delay unit is 90 degrees, and the phase difference between the positive phase input and the negative phase input, and between the positive phase output and the negative phase output of each level of the delay unit is 180 degrees.

[0012] In a second aspect, an embodiment of the present invention provides a phase-locked loop, which includes a phase detector, a loop filter, and a ring voltage-controlled oscillator as described in any one of the first aspects.

[0013] In a third aspect, an embodiment of the present invention provides a chip, wherein the chip includes the phase-locked loop described in the second aspect.

[0014] In a fourth aspect, an embodiment of the present invention provides an electronic device, wherein the electronic device comprises the chip described in the fourth aspect.

[0015] The present invention provides a ring voltage-controlled oscillator with a wide frequency range and low phase noise. The fixed capacitor array is used to adjust the frequency band to achieve a wide frequency range. The variable capacitor is adjusted by controlling the voltage to adjust the oscillation frequency of the ring voltage-controlled oscillator. The Kvco of the ring voltage-controlled oscillator can be effectively reduced by adjusting and selecting a suitable variable capacitor value, thereby reducing the phase noise. The advantage of low Kpushing can greatly reduce the noise and PSRR index requirements of the LDO. The variable capacitor array is used to compensate for the drastic change of Kvco caused by the fixed capacitor array, so that the full-band Kvco can be close to a fixed value and more stable, which can reduce the difficulty of phase-locked loop design and noise optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 This is a structural diagram of a ring voltage-controlled oscillator with a wide frequency range and low phase noise provided by an embodiment of the present application; Figure 2 This is a structural diagram of a delay unit of a ring voltage-controlled oscillator with a wide frequency range and low phase noise provided by an embodiment of the present application; Figure 3 This is an automatic frequency band selection architecture diagram of a ring voltage-controlled oscillator with a wide frequency range and low phase noise provided by an embodiment of the present application; Figure 4 This is a structural block diagram of a phase-locked loop provided by an embodiment of the present application; Figure 5 This is a structural block diagram of a chip provided by an embodiment of the present application; Figure 6 It is a structural block diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0019] It should be understood that although the terms first, second, third, etc. may be used to describe the acquisition modules in the embodiments of the present invention, the acquisition modules should not be limited to these terms. These terms are only used to distinguish the acquisition modules from each other.

[0020] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0021] It should be noted that the directional words such as "upper", "lower", "left", and "right" described in the embodiments of the present invention are described at the angles shown in the drawings and should not be understood as limiting the embodiments of the present invention. In addition, in the context, it should also be understood that when it is mentioned that an element is formed "on" or "under" another element, it can not only be formed directly "on" or "under" another element, but also be formed "on" or "under" another element indirectly through an intermediate element.

[0022] refer to Figure 1 , 2 The embodiment of the present invention provides a ring voltage controlled oscillator 1 with a wide frequency range and low phase noise. The ring voltage controlled oscillator 1 includes two stages of delay units with the same structure, forming four orthogonal phase outputs. The positive phase output end outp of the delay unit 11 is connected to the positive phase input end inp of the delay unit 12, the negative phase output end outn of the delay unit 11 is connected to the negative phase input end inn of the delay unit 12, the positive phase output end outp of the delay unit 12 is connected to the negative phase input end inn of the delay unit 11, and the negative phase output end outn of the delay unit 12 is connected to the positive phase input end inp of the delay unit 11 to form an oscillation loop. The oscillation loop is provided with power supply voltage by a reference voltage source 13 and a linear regulator 14; each stage of the delay unit is connected to a control voltage Vctrl and a digital control signal Band_sel <n:0>, control voltage Vctrl and digital control signal Band_sel <n:0>Used to adjust the oscillation frequency of the ring voltage controlled oscillator, Band_sel <n:0>Include: Band_sel <0> -Band_sel <n>There are n+1 digital control signals in total.

[0023] Among them, the phase difference between the positive phase input terminal inp and the positive phase output terminal outp of each delay unit, and between the negative phase input terminal inn and the negative phase output terminal outn is 90 degrees, and the phase difference between the positive phase input terminal inp and the negative phase input terminal inn of each delay unit, and between the positive phase output terminal outp and the negative phase output terminal outn is 180 degrees. Exemplarily, the initial voltage of each node of the ring voltage-controlled oscillator 1 oscillates stably at a frequency of 4 times the delay period under the interference of inherent or system noise, with reference to Figure 1 When the signal at node ck0 is high level, the signal is output to node ck90 after the first delay, the signal at node ck90 is output to node ck180 after the second delay, the signal at node ck180 is output to node ck270 after the third delay, and the signal at node 270 is fed back to node ck0 after the fourth delay, forming a positive feedback stable oscillation signal output.

[0024] Exemplary, reference Figure 2 , the circuit structure of each delay unit in the ring voltage controlled oscillator 1 is described below. Each delay unit may include but is not limited to inverter inv1, inverter inv2, inverter inv3, inverter inv4, variable capacitor CV1, variable capacitor CV2, variable capacitor array Var_bank and fixed capacitor array Fix Cap_bank.

[0025] The input end of the inverter inv1 is the positive input end inp of the delay unit, the output end of the inverter inv1 is connected to the input end of the inverter inv2 and the output end of the inverter inv4, the input end of the inverter inv3 is the negative input end inn of the delay unit, the output end of the inverter inv3 is connected to the output end of the inverter inv2 and the input end of the inverter inv4, the output end of the inverter inv2 is the positive output end outp of the delay unit, and the output end of the inverter inv4 is the negative output end outn of the delay unit; the output end of the inverter inv2 and the output end of the inverter inv4 are connected in parallel: the variable capacitor CV1 and the variable capacitor CV2 connected in series, the variable capacitor array Var_bank and the fixed capacitor array Fix Cap_bank, and the control voltage Vctrl is connected to the control end of the variable capacitor CV1, the variable capacitor CV2 and the variable capacitor array Var_bank.

[0026] Optionally, the variable capacitor array Var_bank includes a plurality of variable capacitor groups with the same structure, wherein the variable capacitor group includes: a switch S1, a switch S2, a variable capacitor CV3 and a variable capacitor CV4; The first end of the variable capacitor CV3 is connected to the output end of the inverter inv2 through the switch S1, the first end of the variable capacitor CV4 is connected to the output end of the inverter inv4 through the switch S2, and the second end of the variable capacitor CV3 is connected to the second end of the variable capacitor CV4. Exemplarily, this embodiment uses a 5-bit variable capacitor array, including 5 variable capacitor groups with the same structure, namely, 5 switches S1: S1.0-S1.4, 5 variable capacitors CV3: CV3.0-CV3.4, 5 switches S2: S2.0-S2.4, and 5 variable capacitors CV4: CV4.0-CV4.4.

[0027] Optionally, the fixed capacitor array Fix Cap_bank includes a plurality of fixed capacitor groups with the same structure, and the fixed capacitor group includes: a fixed capacitor C1, a fixed capacitor C2 and a switch S3; A first end of the fixed capacitor C1 is connected to the output end of the inverter inv2, a second end of the fixed capacitor C1 is connected to the second end of the fixed capacitor C2 through a switch S3, and a second end of the fixed capacitor C2 is connected to the output end of the inverter inv4; Exemplarily, this embodiment uses a 5-bit fixed capacitor array, including 5 fixed capacitor groups with the same structure, namely, 5 fixed capacitors C1: C1.0-C1.4, 5 fixed capacitors C2: C2.0-C2.4, and 5 switches S3: S3.0-S3.4.

[0028] refer to Figure 2 , the working principle of this embodiment is described. In this embodiment, when all the capacitors in the fixed capacitor array Fix Cap_bank are connected to the main circuit, the output oscillation frequency is the lowest, and when all the capacitors are disconnected, the output frequency is the highest, so as to realize the wide frequency range of the ring voltage-controlled oscillator. By controlling the number of switches S3 turned on to control the number of capacitors in the fixed capacitor array Fix Cap_bank connected to the main circuit, the switching of different sub-bands in the tuning range is realized; After a certain sub-band is selected by controlling the fixed capacitor array Fix Cap_bank, within the control voltage range corresponding to the current sub-band, the control voltage Vctrl is adjusted to input the variable capacitor CV1, the variable capacitor CV2 and the variable capacitor array Var_bank to adjust the variable capacitor value. Selecting a suitable variable capacitor value can achieve a lower Kvco, and Kpushing is also reduced accordingly, so that the ring voltage-controlled oscillator 1 can obtain a lower output phase noise; This embodiment also includes using a variable capacitor array Var_bank and a fixed capacitor array Fix Cap_bank for coordinated adjustment, and the variable capacitor array Var_bank is used to compensate for the drastic change of Kvco caused by the change of the fixed capacitor array Fix Cap_bank. For example, when the switch S3 gradually increases the number of conduction, the switches S1 and S2 also gradually increase the number of conduction, thereby increasing the change of the variable capacitance controlled by the control voltage Vctrl to avoid Kvco from decreasing as the number of fixed capacitor conduction increases. When the switch S3 gradually decreases the number of conduction, the switches S1 and S2 also reduce the number of conduction, thereby reducing the change of the variable capacitance controlled by the control voltage Vctrl to avoid Kvco from increasing as the number of fixed capacitor conduction decreases. As a result, Kvco can have a relatively constant value when it is in different sub-bands.

[0029] refer to Figure 3 The present embodiment also includes a ring voltage controlled oscillator automatic frequency band selection architecture 2, including a ring voltage controlled oscillator 1, a fixed voltage generation module 21, an automatic frequency calibration divider 22 and a digital automatic frequency calibration module 23. The control voltage Vctrl provided by the fixed voltage generation module 21 is input into the delay unit of the ring voltage controlled oscillator 1. The control voltage Vctrl is usually a control voltage of an intermediate frequency corresponding to a frequency band. The ring voltage controlled oscillator 1 starts to oscillate, and the output oscillation frequency signal is divided by the automatic frequency calibration divider 22 and then input into the digital automatic frequency calibration module 23 for further processing. The digital automatic frequency calibration module 23 analyzes and processes the output oscillation frequency signal according to the set frequency target value and the output oscillation frequency signal to output a digital control signal Band_sel <n:0>The phase-locked loop working frequency division signal is used as the reference frequency to input the digital automatic frequency calibration module 23, and the frequency target value is set to the product of the reference frequency and the frequency division number. The digital control signal Band_sel <n:0>The switch S3 control end of the fixed capacitor array Fix Cap_bank of the ring voltage controlled oscillator 1 is connected, and the number of switches turned on is changed to adjust the number of capacitors connected to the main circuit of the fixed capacitor array Fix Cap_bank, thereby changing the oscillation frequency of the ring voltage controlled oscillator 1. For example, this embodiment adopts a 5-bit fixed capacitor array, and the digital automatic frequency calibration module 23 outputs a digital control signal Band_sel<4:0> to the switch S3 control end of the ring voltage controlled oscillator 1. The digital control signal Band_sel <0> -Band_sel <4> Control switches S3.0-S3.4 respectively; when the oscillation frequency of the ring voltage controlled oscillator 1 is higher than the frequency target value and the difference between the two is greater than the preset value, increase the digital control signal Band_sel<4:0>, increase the number of capacitors connected to the main circuit in the fixed capacitor array Fix Cap_bank, and thus reduce the oscillation frequency; when the oscillation frequency of the ring voltage controlled oscillator 1 is lower than the frequency target value and the difference between the two is greater than the preset value, decrease the digital control signal Band_sel<4:0>, reduce the number of capacitors connected to the main circuit in the fixed capacitor array Fix Cap_bank, and thus increase the oscillation frequency; repeat the above steps, the digital automatic frequency calibration module 23 successively approaches the optimal digital control signal Band_sel<4:0> and inputs it into the ring voltage controlled oscillator 1, so that the difference between the oscillation frequency of the ring voltage controlled oscillator 1 and the frequency target value is lower than the preset value, and the automatic calibration is completed. Therefore, the ring voltage controlled oscillator 1 adjusts the input control voltage Vctrl to achieve automatic selection of the sub-band.

[0030] The embodiment of the present invention further provides a phase-locked loop 3, such as Figure 4 As shown, the phase-locked loop 3 includes but is not limited to a phase detector 31, a loop filter 32, and Figure 1 , 2 Corresponding to the ring voltage controlled oscillator 1 in the embodiment, Figure 3 This corresponds to the automatic frequency band selection architecture 2 in the embodiment.

[0031] The embodiment of the present invention further provides a chip 4, such as Figure 5 As shown, the chip 4 includes but is not limited to Figure 4 This corresponds to the phase-locked loop 3 in the embodiment.

[0032] The embodiment of the present invention further provides an electronic device 5, such as Figure 6 As shown, the electronic device 5 includes but is not limited to Figure 5 Corresponding to chip 4 in the embodiment.

[0033] The embodiment of the present invention provides a ring voltage-controlled oscillator with a wide frequency range and low phase noise. The ring voltage-controlled oscillator with four orthogonal phase outputs is formed by a two-stage delay unit. The present invention adjusts the fixed capacitor array to achieve a wide frequency range, and further adjusts the oscillation frequency of the ring voltage-controlled oscillator by controlling the voltage to adjust the variable capacitor. The adjustment and selection of a suitable variable capacitor value effectively reduce the Kvco and Kpushing of the ring voltage-controlled oscillator, thereby reducing the phase noise. The advantage of low Kpushing can also greatly reduce the noise and PSRR index requirements of the LDO, and reduce the difficulty and complexity of the phase-locked loop design. The present invention also compensates for the drastic changes in Kvco caused by the fixed capacitor array through the variable capacitor array, and coordinates the variable capacitor array and the fixed capacitor array to make the full-band Kvco approach a fixed value and be more stable, which can reduce the difficulty of the phase-locked loop design and noise optimization.

[0034] The above description is only a preferred embodiment of the present invention. Those skilled in the art should understand that the scope of disclosure involved in the present invention is not limited to the technical solution formed by a specific combination of the above technical features, but also should cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present invention (but not limited to) to form a technical solution. < / n>

Claims

1. A ring voltage-controlled oscillator with a wide frequency range and low phase noise, characterized in that: The ring voltage-controlled oscillator comprises two levels of delay units with the same structure, wherein the positive phase output of the first delay unit is connected to the positive phase input of the second delay unit, the negative phase output of the first delay unit is connected to the negative phase input of the second delay unit, the positive phase output of the second delay unit is connected to the negative phase input of the first delay unit, and the negative phase output of the second delay unit is connected to the positive phase input of the first delay unit, forming an oscillation loop, wherein the oscillation loop is provided with power supply voltage by a reference voltage source and a linear regulator; each level of the delay unit is connected to a control voltage and a digital control signal, and the control voltage and the digital control signal are used to adjust the oscillation frequency.

2. The ring voltage controlled oscillator with wide frequency range and low phase noise according to claim 1, characterized in that: The delay unit includes: a first inverter, a second inverter, a third inverter, a fourth inverter, a first variable capacitor, a second variable capacitor, a variable capacitor array and a fixed capacitor array; The input end of the first inverter is the positive phase input end of the delay unit, the output end of the first inverter is connected to the input end of the second inverter and the output end of the fourth inverter, the input end of the third inverter is the negative phase input end of the delay unit, the output end of the third inverter is connected to the output end of the second inverter and the input end of the fourth inverter, the output end of the second inverter is the positive phase output end of the delay unit, and the output end of the fourth inverter is the negative phase output end of the delay unit; the output end of the second inverter and the output end of the fourth inverter are connected in parallel: the first variable capacitor and the second variable capacitor, the variable capacitor array and the fixed capacitor array are connected in series, and the control voltage is connected to the first variable capacitor, the second variable capacitor and the variable capacitor array.

3. The ring voltage controlled oscillator with wide frequency range and low phase noise according to claim 2, characterized in that: Also includes: The fixed capacitor array is used to obtain a wide frequency range; The control voltage adjusts the first variable capacitor, the second variable capacitor and the variable capacitor array to reduce the gain coefficient; The variable capacitor array and the fixed capacitor array are adjusted in coordination to ensure that the gain coefficient is constant over the entire frequency band.

4. The ring voltage controlled oscillator with wide frequency range and low phase noise according to claim 2, characterized in that: The variable capacitor array includes a plurality of variable capacitor groups with the same structure, and the variable capacitor group includes: a first switch, a second switch, a third variable capacitor and a fourth variable capacitor; The first end of the third variable capacitor is connected to the output end of the second inverter through the first switch, the first end of the fourth variable capacitor is connected to the output end of the fourth inverter through the second switch, and the second end of the third variable capacitor is connected to the second end of the fourth variable capacitor.

5. The ring voltage controlled oscillator with wide frequency range and low phase noise according to claim 2, characterized in that: The fixed capacitor array includes a plurality of fixed capacitor groups with the same structure, and the fixed capacitor group includes: a first fixed capacitor, a second fixed capacitor and a third switch; The first end of the first fixed capacitor is connected to the output end of the second inverter, the second end of the first fixed capacitor is connected to the second end of the second fixed capacitor through the third switch, and the second end of the second fixed capacitor is connected to the output end of the fourth inverter.

6. The ring voltage controlled oscillator with wide frequency range and low phase noise according to claim 1, characterized in that: Also included is an automatic frequency band selection architecture of a ring voltage controlled oscillator, the automatic frequency band selection architecture comprising: a ring voltage controlled oscillator, a fixed voltage generation module, an automatic frequency calibration divider and a digital automatic frequency calibration module; The control voltage provided by the fixed voltage generation module is input to the delay unit of the ring voltage controlled oscillator, the ring voltage controlled oscillator starts to oscillate, and the output oscillation frequency signal is input to the digital automatic frequency calibration module after being divided by the automatic frequency calibration divider. The digital automatic frequency calibration module successively approximates the optimal digital control signal according to a given frequency target value, and outputs it to the ring voltage controlled oscillator to complete automatic calibration.

7. The ring voltage controlled oscillator with wide frequency range and low phase noise according to claim 1, characterized in that: The phase difference between the positive phase input and the positive phase output, and between the negative phase input and the negative phase output of each delay unit is 90 degrees, and the phase difference between the positive phase input and the negative phase input, and between the positive phase output and the negative phase output of each delay unit is 180 degrees.

8. A phase-locked loop, characterized in that: The phase-locked loop comprises a phase detector, a loop filter and a ring voltage-controlled oscillator with a wide frequency range and low phase noise as claimed in any one of claims 1 to 7.

9. A chip, characterized in that: The chip comprises the phase-locked loop as claimed in claim 8.

10. An electronic device, characterized in that: The electronic device comprises the chip according to claim 9.

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