Signal delay adjustment method, signal delay adjustment device and storage medium

Abstract

The invention provides a signal delay adjusting method, signal delay adjusting equipment and a storage medium. The method is applied to the field of chips. The method comprises the following steps: acquiring an initial delay value and an initial test result of a gear in a delay line; performing data expansion processing on the initial delay value and the initial test result to obtain a target delay value and a target test result corresponding to the target delay value; updating the target test result corresponding to the first delay value based on the target test result corresponding to the reference delay value to obtain an updated test result of the target delay value; the target delay value comprises a reference delay value and a first delay value; the target test result corresponding to the first delay value is an invalid value; the reference delay value is determined based on the first delay value and the unit time interval; and determining a target gear based on the target delay value and the updated test result, and controlling the delay line to be adjusted to the target gear. According to the method, signal delay adjustment can be carried out on the chip so as to reduce the bit error rate.

Description

Technical Field

[0001] The present application relates to the field of chips, and more specifically, to a signal delay adjustment method, a signal delay adjustment device and a storage medium. Background Art

[0002] When high-speed transmission is performed between chips, in order to achieve high-bandwidth, low-latency transmission, it is necessary to accurately control the data and clock signals at the sending and receiving ends. In order to ensure stable data sampling, the sampling clock and data at the receiving end need to maintain a certain phase relationship. Multi-chip interconnection often uses a clock-associated solution to help the receiving end accurately recover data from the clock signal transmitted from the sending end.

[0003] At present, it is often necessary to set various delays inside the transceiver to adjust the phase relationship between the clock and data, and traverse and detect the adjustable gears of the delay unit to find the best sampling gear. The method of traversing the gears one by one requires assuming that the relationship between the delay and the gear is linear or evenly distributed. However, in actual implementation, there may be large nonlinear jumps between different delay gears, resulting in the inability of a simple traversal method to accurately locate the best sampling window. This will cause a deviation between the detection result and the actual situation, thereby reducing the reliability of data sampling at the receiving end and increasing the bit error rate. Therefore, how to adjust the signal delay of the chip to reduce the bit error rate has become an urgent problem to be solved. Summary of the invention

[0004] The present application provides a signal delay adjustment method, a signal delay adjustment device and a storage medium. The method can adjust the signal delay of a chip to reduce the bit error rate.

[0005] In a first aspect, a signal delay adjustment method is provided, and the method is applied to a chip; the method comprises: Obtain the initial delay value and initial test result of the gear in the delay line; Performing data expansion processing on the initial delay value and the initial test result to obtain a target delay value and a target test result corresponding to the target delay value; wherein the number of the target delay values ​​is greater than the number of the initial delay values; The target test result corresponding to the first delay value is updated based on the target test result corresponding to the reference delay value to obtain an updated test result of the target delay value; wherein the target delay value includes the reference delay value and the first delay value; the target test result corresponding to the first delay value is an invalid value; the reference delay value is determined based on the first delay value and the unit time interval; Based on the target delay value and the updated test result, a target gear position is determined, and the delay line is controlled to be adjusted to the target gear position.

[0006] The above technical scheme obtains the initial delay value and initial test result of the gear in the delay line; performs data expansion processing on the initial delay value and the initial test result to obtain the target delay value and the target test result corresponding to the target delay value; updates the target test result corresponding to the first delay value based on the target test result corresponding to the reference delay value to obtain the updated test result of the target delay value; the target delay value includes the reference delay value and the first delay value; the target test result corresponding to the first delay value is an invalid value; the reference delay value is determined based on the first delay value and the unit time interval; based on the target delay value and the updated test result, the target gear is determined, and the delay line is controlled to be adjusted to the target gear; which is different from the prior art in which the delay unit is determined. Compared with traversing and detecting the adjustable gears of the element to find the optimal sampling gear, the present application, through a comprehensive analysis of the gear detection results in different UIs, can update the invalid value in the current UI to obtain an updated detection result of the target delay value when an invalid value (the target detection result corresponding to the first delay value) appears in one UI but is not an invalid value in another UI, thereby avoiding sampling inaccuracy caused by invalid values ​​in a single UI, and determining the target gear based on the updated detection result, thereby ensuring that the target gear is the optimal sampling phase position, thereby achieving reliable sampling of data, thereby reducing the bit error rate of the communication link under high-speed transmission, and improving the overall communication quality and system stability.

[0007] In addition, the method in this application is compatible with a variety of high-speed interconnection scenarios, whether it is die-to-die (D2D) interconnection in a multi-chip package or a high-speed interface within a single chip, it can directly utilize the existing delay line hardware structure, and only requires mapping and compensation algorithm implementation at the firmware or software level. The development and deployment costs are relatively low, and it has high portability and practical value.

[0008] In combination with the first aspect, in some possible implementations, updating the target test result corresponding to the first delay value based on the target test result corresponding to the reference delay value to obtain the updated test result of the target delay value includes: Determining whether a target test result corresponding to the reference delay value is a valid value; If it is a valid value, determining the target test result corresponding to the reference delay value as the updated test result corresponding to the first delay value; If it is an invalid value, the target test result corresponding to the first delay value is determined as the updated test result corresponding to the first delay value.

[0009] The above technical scheme determines whether the target test result corresponding to the reference delay value is a valid value; if it is a valid value, the target test result corresponding to the reference delay value is determined as the updated test result corresponding to the first delay value; if it is an invalid value, the target test result corresponding to the first delay value is determined as the updated test result corresponding to the first delay value; this scheme takes into account the actual situation that the delay adjustment range of the chip is greater than the length of one UI. Through comprehensive analysis of the gear detection results in different UIs, a "dead zone" area may appear in one UI, but when another UI is a valid area, the "dead zone" area is compensated, which can avoid the sampling inaccuracy caused by the "dead zone" area in a single UI, thereby improving the flexibility of the sampling clock phase selection and ensuring the accuracy of the target gear.

[0010] In combination with the first aspect and the above implementation manner, in some possible implementation manners, determining the target gear position based on the target delay value and the updated test result includes: Traversing the update test results to determine a maximum sampling window; Based on the maximum sampling window, selecting a target sampling delay value from the target delay values; The target gear position is determined based on the target sampling delay value.

[0011] The above technical scheme traverses the update test results, determines the maximum sampling window, selects the target sampling delay value from the target delay value based on the maximum sampling window, and determines the target gear based on the target sampling delay value; by compensating the target test result of the target delay value and determining the update test result, the number of invalid values ​​corresponding to the target delay value can be effectively reduced; on this basis, the target sampling delay value is determined in combination with the maximum sampling window in the target delay value, which can ensure the accuracy of the target sampling delay value and thus ensure the accuracy of the target gear.

[0012] In combination with the first aspect and the above implementation manner, in some possible implementation manners, the method further includes: determining whether the starting delay value in the target delay value is within the candidate sampling window; The selecting a target sampling delay value from the target delay values ​​based on the maximum sampling window includes: If the starting delay value is within the candidate sampling window, determining the target sampling delay value based on a first window length of the candidate sampling window and a second window length of the maximum sampling window; If the starting delay value is outside the candidate sampling window, the central delay value of the maximum sampling window is determined as the target sampling delay value.

[0013] The above technical scheme determines whether the starting delay value in the target delay value is within the candidate sampling window. If the starting delay value is within the candidate sampling window, the target sampling delay value is determined based on the first window length of the candidate sampling window and the second window length of the maximum sampling window. If the starting delay value is outside the candidate sampling window, the central delay value of the maximum sampling window is determined as the target sampling delay value. By combining whether there is a candidate sampling window at the starting delay value in the target delay value, when there is a candidate sampling window, the target sampling delay value is comprehensively determined in combination with the candidate sampling window and the maximum sampling window, so as to avoid the omission of the optimal sampling window due to the length of the sampling window when the optimal sampling window is located at the starting delay value, so as to ensure the accuracy of the positioning of the optimal sampling window, thereby ensuring the accuracy of the target sampling delay value.

[0014] In combination with the first aspect and the foregoing implementation manner, in some possible implementation manners, determining the target sampling delay value based on the first window length of the candidate sampling window and the second window length of the maximum sampling window includes: Based on the second window length, determining a reference window length; wherein the reference window length is greater than or equal to half of the second window length; If the first window length is less than or equal to the reference window length, determining the central delay value of the maximum sampling window as the target sampling delay value; If the first window length is greater than the reference window length, a delay value that is a difference between the upper edge delay value of the candidate sampling window and the reference window length is determined as the target sampling delay value.

[0015] The above technical solution determines whether the starting delay value in the target delay value is within the candidate sampling window; if the starting delay value is outside the candidate sampling window, the center delay value of the maximum sampling window is determined as the target sampling delay value; if the starting delay value is within the candidate sampling window, the reference window length is determined based on the second window length; if the first window length is less than or equal to the reference window length, the center delay value of the maximum sampling window is determined as the target sampling delay value; if the first window length is greater than the reference window length, the difference delay value between the upper edge delay value of the candidate sampling window and the reference window length is determined as the target sampling delay value; by An inference mechanism is proposed for the relationship between the candidate sampling window starting from the starting delay value of the target delay value and the gear position. Due to the finiteness of the eye width of the eye diagram, when it is detected that there is a valid sampling window (candidate sampling window) starting from 0 (the starting delay value of the target delay value) and the length of the candidate sampling window is greater than the reference window length, the candidate sampling window is the best sampling window in the target delay value; on this basis, the target sampling delay value is determined, which can reduce the dependence on the nonlinear relationship between the gear position and the delay value and the invalid value area corresponding to the target delay value, ensure the accuracy of the target sampling delay value, and then improve the accuracy of the target gear position and reduce the bit error rate.

[0016] In combination with the first aspect and the above implementation manner, in some possible implementation manners, performing data expansion processing on the initial delay value and the initial test result to obtain a target delay value and a target test result corresponding to the target delay value includes: Determining a target common divisor of the initial delay value; Performing data expansion processing on the initial delay value with the target common divisor as a step length to obtain the target delay value; Based on the initial test result and the initial delay value, a target test result corresponding to the target delay value is determined.

[0017] The above technical scheme performs data expansion processing on the initial delay value with the target common divisor of the initial delay value as the step size to obtain the target delay value, and determines the target test result corresponding to the target delay value based on the initial test result and the initial delay value; by performing data expansion on the initial delay value, the nonlinear jump position of the delay value can be accurately determined, and on this basis, the accuracy of determining the optimal sampling window can be improved, thereby improving the accuracy of the target gear position.

[0018] In combination with the first aspect and the above implementation manner, in some possible implementation manners, determining the target test result corresponding to the target delay value based on the initial test result and the initial delay value includes: Determine a target difference between a first initial delay value and a second initial delay value; wherein the first initial delay value and the second initial delay value are used to indicate any adjacent delay values ​​of the initial delay values; If the target difference is less than or equal to the preset difference, the reference test result is determined as the target test result corresponding to the target delay value between the first initial delay value and the second initial delay value; wherein the reference test result is the initial test result corresponding to the first initial delay value or the initial test result corresponding to the second initial delay value; If the target difference is greater than a preset difference, an invalid value is determined as a target test result corresponding to the target delay value between the first initial delay value and the second initial delay value.

[0019] The above technical scheme determines the target difference between the first initial delay value and the second initial delay value; if the target difference is less than or equal to the preset difference, the reference test result is determined as the target test result corresponding to the target delay value between the first initial delay value and the second initial delay value, and the reference test result is the initial test result corresponding to the first initial delay value or the initial test result corresponding to the second initial delay value; so that when the target difference is less than or equal to the preset difference, the target detection result corresponding to the target delay value can be directly supplemented, and the target detection result corresponding to the delay value with a smaller difference can be estimated; if the target difference is greater than the preset difference, the invalid value is determined as the target test result corresponding to the target delay value between the first initial delay value and the second initial delay value; when the target difference is greater than the preset difference, the "dead zone" of the chip adjustable delay is accurately determined by the target difference between the delay values; on this basis, the target detection result in the "dead zone" area is compensated to improve the capture capability of the sampling window, thereby improving the accuracy of the target gear.

[0020] In combination with the first aspect and the above implementations, in some possible implementations, obtaining the initial delay value of the gear in the delay line includes: Determine the target unit for the initial gear; Obtaining the accumulated delay value of the target unit and a second delay value corresponding to the initial gear position; The sum of the accumulated delay value and the second delay value is determined as the initial delay value corresponding to the initial gear position; wherein the initial gear position is used to indicate any gear position in the delay line.

[0021] The above technical solution obtains the accumulated delay value of the target unit where the initial gear is located and the second delay value corresponding to the initial gear, and determines the sum of the accumulated delay value and the second delay value as the initial delay value corresponding to the initial gear; by determining the initial delay value of the initial gear in the delay value, the gear domain is converted into the time domain, so that the mapping relationship between the gear and the delay value can be accurately determined.

[0022] In a second aspect, a signal delay adjustment device is provided, comprising a memory and a processor, the memory being used to store executable program code; the processor being used to call and run the executable program code from the memory, so that the signal delay adjustment device executes the signal delay adjustment method in the above-mentioned first aspect or any possible implementation method of the first aspect.

[0023] In a third aspect, a computer-readable storage medium is provided, which stores a computer program code. When the computer program code runs on a computer, the computer executes the signal delay adjustment method in the above-mentioned first aspect or any possible implementation of the first aspect.

[0024] In a fourth aspect, a computer program product is provided, which includes: a computer program code, which, when executed on a computer, enables the computer to execute the signal delay adjustment method in the first aspect or any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic flow chart of a signal delay adjustment method provided in an embodiment of the present application; Figure 2 is a schematic flow chart of a data expansion method provided in an embodiment of the present application; Figure 3 It is a schematic diagram of the corresponding relationship between a delay value and a detection result provided in an embodiment of the present application; Figure 4 is a schematic flow chart of a method for determining a target gear position provided in an embodiment of the present application; Figure 5 It is a structural schematic diagram of a signal delay adjustment device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solution in the present application will be described clearly and in detail below in conjunction with the accompanying drawings. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B: "and / or" in the text is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0027] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as suggesting or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0028] It is understandable that when high-speed transmission is performed between chips, in order to achieve high-bandwidth, low-latency transmission, it is necessary to accurately control the data and clock signals at the transmitting and receiving ends. In order to ensure stable data sampling, it is necessary to maintain a certain phase relationship between the sampling clock and the data at the receiving end.

[0029] In related technologies, multi-chip interconnection often uses a clock-with-path method to help the receiving end accurately recover data from the clock signal transmitted from the sending end. However, in the specific implementation process, various delays are often required inside the transceiver to adjust the phase relationship between the clock and the data, and the adjustable gear (tap) of the delay unit (delay line) is traversed and detected to find the best sampling gear. The method of traversing one by one needs to assume that the relationship between the delay and the gear is linear or evenly distributed. However, in actual implementation, there may be large nonlinear jumps between different delay gears, resulting in the inability of simple traversal methods to accurately locate the best sampling window. This will cause a deviation between the detection result and the actual situation, thereby reducing the reliability of receiving a single pair of data sampling and increasing the bit error rate.

[0030] It should be noted that the gear position in the delay line is used to adjust the delay amount, that is, different gear positions in the delay line correspond to different delay amounts.

[0031] In a multi-chip interconnect architecture, in order to ensure the synchronization of data and clock, an embedded clock solution is often used to send the clock signal of the transmitter together with the data to the receiver, and restore the appropriate sampling clock at the receiver. Usually, in order to accurately sample the data at the receiver, it is necessary to fine-grainedly adjust the phase relationship between the clock and data inside the transceiver. Therefore, one or more adjustable delay lines are often set in the hardware to change the arrival time of the clock or data by selecting different discrete "gears".

[0032] However, in actual implementation, the delay line does not show linear increments between gears, especially when there are obvious jumps between adjacent gears. The simple method of traversing gears will result in the inability to accurately locate the best sampling gear, resulting in a higher bit error rate.

[0033] In view of this, the present application provides a signal delay adjustment method, a signal delay adjustment device and a storage medium. The method can adjust the signal delay of the chip to reduce the bit error rate. Figure 1 It is a schematic flowchart of a signal delay adjustment method provided in an embodiment of the present application.

[0034] For example, Figure 1 The signal delay adjustment method shown is applied to the chip.

[0035] For example, Figure 1 As shown, the signal delay adjustment method 100 includes the following processes: S110, obtaining the initial delay value and initial test result of the gear in the delay line.

[0036] For example, in a multi-chip interconnection architecture, the microcontroller unit (MCU) of the main control chip in the multi-chip is usually used as the controller to control the signal delay adjustment process. Each chip has a transmitting end and a receiving end. The MCU controls the multi-chip to start initialization, that is, any two chips start to send the first stage signal, and the process of the receiving end is controlled by the MCU, thereby completing the signal delay adjustment.

[0037] For example, a chip has different manifestations in different application scenarios. For example, it is manifested as a chip in a chip application scenario, as a bare die in a bare die application scenario, and as a chiplet (or chiplet) in a chiplet application scenario.

[0038] Exemplarily, the transmission clock and the accompanying clock of all lanes (lanes) of the transmitting end are output from the same internal phase-locked loop. Specifically, the clock signal is distributed to the transmission clock and each lane through the clock distribution unit, and the receiving end receives the accompanying clock. After entering the chip, the accompanying clock also passes through different clock distribution units and enters different channels as the sampling clock of the channel. This ensures that the clock signals of all channels in the transmitting end and the receiving end have the same clock source, ensuring the synchronization of the clock.

[0039] In addition, each channel is equipped with an adjustable delay line, which can make fine delay adjustments to the clock signal, thereby adjusting the phase relationship between the sampling clock and the data.

[0040] It is understood that the delay line is a component or device used to control the delay time of an electrical signal. The delay line can delay the arrival time of the input signal for a certain period of time before outputting it. The delay line includes multiple gears, and the delay values ​​corresponding to each gear are different.

[0041] Exemplarily, the initial delay value and initial test result of the gear in the delay line are obtained. The delay line includes multiple gears, and each gear corresponds to an initial delay value, that is, the delay line can adjust the delay value of the gear control signal. Each gear corresponds to an initial test result of the communication link, and the initial test result is used to indicate the communication quality of the communication link. It can be understood that the gear in the delay line has a corresponding relationship with the initial delay value, that is, each gear corresponds to an initial delay value, and the gear in the delay line has a corresponding relationship with the initial test result, that is, each gear corresponds to an initial test result, and each initial delay value corresponds to an initial test result.

[0042] Exemplarily, the initial test result may be a bit error rate detection result of a communication link. When the bit error rate of the communication link is less than or equal to a preset bit error rate, the initial test result corresponding to the gear is determined to be 1; when the bit error rate of the communication link is greater than the preset bit error rate, the initial test result corresponding to the gear is determined to be 0. It is understood that the initial test result shown above is only one possible application method in practical applications, and the specific representation method of the initial test result can be determined according to actual conditions, and is not specifically limited here.

[0043] S120, performing data expansion processing on the initial delay value and the initial test result to obtain a target delay value and a target test result corresponding to the target delay value.

[0044] Exemplarily, the number of target delay values ​​is greater than the number of initial delay values, the number of target test results is greater than the number of initial test results, and each target delay value in the target delay values ​​corresponds to a target test result.

[0045] Exemplarily, a target common divisor of the initial delay value is determined, data expansion processing is performed on the initial delay value with the target common divisor as a step size to obtain a target delay value, and based on the initial test result and the initial delay value, a target test result corresponding to the target delay value is determined.

[0046] For example, the initial delay values ​​include 0ps, 1.1ps, 2.2ps, 3.3ps, 4.4ps, 5.5ps, 6.6ps, 7.7ps and 12.7ps; the initial test results include test result 0 corresponding to 0ps, test result 1 corresponding to 1.1ps, test result 1 corresponding to 2.2ps, test result 1 corresponding to 3.3ps, test result 1 corresponding to 4.4ps, test result 1 corresponding to 5.5ps, test result 1 corresponding to 6.6ps, test result 0 corresponding to 7.7ps, and test result 0 corresponding to 12.7.

[0047] Further, the initial delay value is subjected to data expansion processing, and the target delay values ​​obtained include 0ps, 0.1ps, 0.2ps, 0.3ps, 0.4ps, 0.5ps, 0.6ps, 0.7ps...12.1ps, 12.2ps, 12.3ps, 12.4ps, 12.5ps, 12.6ps, 12.7ps. In addition, each target delay value in the target delay value corresponds to a target detection result.

[0048] Exemplarily, the target detection result corresponding to the delay value that overlaps with the initial delay value in the target delay value is equal to the initial detection result corresponding to the initial delay value; for example, the target detection result of the target delay value of 2.2ps is the initial detection result 1 corresponding to the initial delay value of 2.2ps. The target detection result corresponding to the delay value that does not overlap with the initial delay value in the target delay value is determined with reference to the initial detection result of the adjacent initial delay value. For example, the target detection result corresponding to the target delay value of 2.3ps to 3.2ps is 1 (the initial detection result corresponding to the initial delay value of 2.2ps, or the initial detection result corresponding to the initial delay value of 3.3ps).

[0049] Of course, when the target difference between adjacent initial delay values ​​is greater than the preset difference, the target detection result corresponding to the delay value between the adjacent initial delay values ​​is determined to be an invalid value. For example, the invalid value can be represented by 2. For example, if the target difference between the target delay values ​​7.8ps and 12.6ps is greater than 1.1ps, it is determined that the target detection results corresponding to the target delay values ​​7.8ps to 12.6ps are all invalid values.

[0050] Optionally, the preset difference may be 1.1 ps.

[0051] Optionally, the target detection result includes a valid value and an invalid value, and the valid value may be 0 or 1.

[0052] The above technical scheme performs data expansion processing on the initial delay value with the target common divisor of the initial delay value as the step size to obtain the target delay value, and determines the target test result corresponding to the target delay value based on the initial test result and the initial delay value; by performing data expansion on the initial delay value, the nonlinear jump position of the delay value can be accurately determined, and on this basis, the accuracy of determining the optimal sampling window can be improved, thereby improving the accuracy of the target gear position.

[0053] S130, updating the target test result corresponding to the first delay value based on the target test result corresponding to the reference delay value to obtain an updated test result of the target delay value.

[0054] Exemplarily, the target delay value includes a reference delay value and a first delay value; the target test result corresponding to the first delay value is an invalid value; and the reference delay value is determined by the first delay value and the unit time interval.

[0055] Exemplarily, the length of a bit period of a unit interval (UI) signal is half of the signal period. Specifically, the length of the UI is determined according to the transmission rate of the signal, that is, the length of the UI = 1 / (2f), where f is the transmission rate of the signal.

[0056] It should be noted that the frequency of modern high-speed interfaces is very high, and the chip's adjustment range for delay often exceeds the length of one UI. Once a large jump or "dead zone" occurs in the delay line, the ideal sampling point may not be found in some UIs, but stable sampling can be achieved in another UI. If you only rely on the test results under a single UI, more feasible sampling intervals may be ignored, thereby losing the opportunity to further optimize the reception quality. "Dead zone" refers to an area within a certain UI of the signal where the target delay value in the "dead zone" is an invalid value due to poor signal quality (such as low signal amplitude, high noise, severe jitter, etc.).

[0057] In order to avoid the test results under a single UI failing to find the ideal sampling point, the "dead zone" detection results can be compensated across UIs. Specifically, if a "dead zone" appears in the current UI interval, but it does not appear as a "dead zone" in another UI, the detection results of multiple UIs are combined, and the capture capability of the sampling window is improved by interpolation or compensation.

[0058] It can be understood that the delay value in the “dead zone” area is the first delay value.

[0059] Exemplarily, the target delay value includes a reference delay value and a first delay value, the reference delay value is a delay value that is n UIs apart from the first delay value, and since the first delay value is located in the "dead zone", the target test result corresponding to the first delay value is an invalid value, while the target detection result corresponding to the reference delay value may be a valid value (0 or 1), and of course, the target detection result corresponding to the reference delay value may also be an invalid value. Furthermore, by performing comprehensive compensation through the detection results of multiple UIs, the target detection result corresponding to the target delay value can be updated to obtain an updated detection result corresponding to the target delay value.

[0060] S140, determining a target gear position based on the target delay value and the updated test result, and controlling the delay line to adjust to the target gear position.

[0061] For example, a sampling window is determined based on the updated test result, a target sampling delay value is selected from the target delay value based on the sampling window, a target gear is determined based on the target sampling delay value, and the delay line is controlled to adjust to the target gear. This can avoid the offset caused by nonlinear or uneven distribution, and accurately map the continuous delay value measured or calculated in real time to the nearest discrete gear (target gear), which is convenient for configuration and implementation in the hardware system.

[0062] It is understandable that, when the target gear is determined, the target gear is set in the communication link of the receiving chip to obtain the optimal sampling phase setting, thereby being able to adjust the signal delay of the chip, improve the stability of the link and reduce the bit error rate.

[0063] Exemplarily, the test results are traversed and updated to determine the maximum sampling window, and based on the maximum sampling window, a target sampling delay value is selected from the target delay values, and based on the target sampling delay value, a target gear is determined.

[0064] In one example, when determining the updated test results corresponding to the target delay value, the maximum sampling window in the target delay value is determined by traversing the updated test results, and the central delay value of the maximum sampling window is determined, the central delay value is determined as the target sampling delay value, and then the target gear corresponding to the target sampling delay value is determined.

[0065] Exemplarily, the center delay value is used to indicate the delay value corresponding to the center position of the maximum sampling window.

[0066] The above technical scheme traverses the update test results, determines the maximum sampling window, selects the target sampling delay value from the target delay value based on the maximum sampling window, and determines the target gear based on the target sampling delay value; by compensating the target test result of the target delay value and determining the update test result, the number of invalid values ​​corresponding to the target delay value can be effectively reduced; on this basis, the target sampling delay value is determined in combination with the maximum sampling window in the target delay value, which can ensure the accuracy of the target sampling delay value and thus ensure the accuracy of the target gear.

[0067] In order to improve the accuracy of the target sampling delay value, it should also be considered whether the candidate sampling window starting from 0 is the optimal sampling window. Due to the effectiveness of the eye width of the eye diagram, when the candidate sampling window is larger than half of the maximum sampling window, the candidate sampling window is the optimal sampling window in the eye diagram.

[0068] In another example, it is determined whether the starting delay value in the target delay value is within the candidate sampling window. If the starting delay value in the target delay value is within the candidate sampling window, the target sampling delay value is determined based on the first window length of the candidate sampling window and the second window length of the maximum sampling window. If the starting delay value in the target delay value is outside the candidate sampling window, the center delay value of the maximum sampling window is determined as the target sampling delay value, and based on the target sampling delay value, the target gear is determined.

[0069] For example, determine whether there is a candidate sampling window starting from 0 in the target delay value. When there is no candidate sampling window starting from 0 in the target delay value, the maximum sampling window in the target delay value is the optimal sampling window, and the central delay value of the maximum sampling window is determined as the target sampling delay value; when there is a candidate sampling window starting from 0 in the target delay value, the optimal sampling window between the candidate sampling window and the maximum sampling window is determined according to the length of the candidate sampling window and the length of the maximum sampling window. On this basis, determine the target sampling delay value, thereby determining the target gear position, which can ensure the accuracy of the target gear position.

[0070] The above technical scheme determines whether the starting delay value in the target delay value is within the candidate sampling window. If the starting delay value is within the candidate sampling window, the target sampling delay value is determined based on the first window length of the candidate sampling window and the second window length of the maximum sampling window. If the starting delay value is outside the candidate sampling window, the central delay value of the maximum sampling window is determined as the target sampling delay value. By combining whether there is a candidate sampling window at the starting delay value in the target delay value, when there is a candidate sampling window, the target sampling delay value is comprehensively determined in combination with the candidate sampling window and the maximum sampling window, so as to avoid the omission of the optimal sampling window due to the length of the sampling window when the optimal sampling window is located at the starting delay value, so as to ensure the accuracy of the positioning of the optimal sampling window, thereby ensuring the accuracy of the target sampling delay value.

[0071] Furthermore, if the starting delay value in the target delay value is within the candidate sampling window, the reference window length is determined based on the second window length, and the reference window length is greater than or equal to half of the second window length; if the first window length is less than or equal to the reference window length, the center delay value of the maximum sampling window is determined as the target sampling delay value; if the first window length is greater than the reference window length, the difference delay value between the upper edge delay value of the candidate sampling window and the reference window length is determined as the target sampling delay value.

[0072] For example, when there is a candidate sampling window starting from 0 in the target delay value, half of the maximum sampling window length is determined as the reference window length, and it is determined whether the first window length of the candidate sampling window is greater than the reference window length; when the first window length of the candidate sampling window is less than or equal to the reference window length, the maximum sampling window is determined to be the optimal sampling window, and the center delay value of the maximum sampling window is determined as the target sampling delay value; when the first window length of the candidate sampling window is greater than the reference window length, the candidate sampling window is determined to be the optimal sampling window, and the difference delay value between the upper edge delay value of the candidate sampling window and the reference window length is determined as the target sampling delay value, thereby ensuring the accuracy of the target sampling delay value on the basis of ensuring the accuracy of the optimal sampling window positioning.

[0073] The above technical scheme obtains the initial delay value and initial test result of the gear in the delay line; performs data expansion processing on the initial delay value and the initial test result to obtain the target delay value and the target test result corresponding to the target delay value; updates the target test result corresponding to the first delay value based on the target test result corresponding to the reference delay value to obtain the updated test result of the target delay value; the target delay value includes the reference delay value and the first delay value; the target test result corresponding to the first delay value is an invalid value; the reference delay value is determined based on the first delay value and the unit time interval; based on the target delay value and the updated test result, the target gear is determined, and the delay line is controlled to be adjusted to the target gear; which is different from the prior art in which the delay unit is determined. Compared with traversing and detecting the adjustable gears of the element to find the optimal sampling gear, the present application, through a comprehensive analysis of the gear detection results in different UIs, can update the invalid value in the current UI to obtain an updated detection result of the target delay value when an invalid value (the target detection result corresponding to the first delay value) appears in one UI but is not an invalid value in another UI, thereby avoiding sampling inaccuracy caused by invalid values ​​in a single UI, and determining the target gear based on the updated detection result, thereby ensuring that the target gear is the optimal sampling phase position, thereby achieving reliable sampling of data, thereby reducing the bit error rate of the communication link under high-speed transmission, and improving the overall communication quality and system stability.

[0074] In addition, the method in this application is compatible with a variety of high-speed interconnection scenarios, whether it is die-to-die (D2D) interconnection in a multi-chip package or a high-speed interface within a single chip, it can directly utilize the existing delay line hardware structure, and only requires mapping and compensation algorithm implementation at the firmware or software level. The development and deployment costs are relatively low, and it has high portability and practical value.

[0075] Compared with the prior art in which the gears are traversed one by one to find the best sampling gear, the present application maps the link information from the gear domain to the absolute time domain (determines the initial delay value of the gear in the delay line and performs data expansion processing), and compensates the link detection results of the "dead zone" area in the absolute time domain after the data expansion processing through the link detection results corresponding to other UIs, so as to achieve data compensation for the situation where a "dead zone" area appears in one UI but is a valid area in another UI, and can avoid the sampling inaccuracy caused by the "dead zone" area in a single UI, thereby obtaining an updated test result of the target delay value; on this basis, the situation where a candidate window exists in the initial phase is judged (the candidate sampling window starting from 0 in the target delay value is judged), to ensure the accuracy of the optimal sampling window, and to improve the accuracy of the optimal sampling point (target sampling delay value), thereby achieving reliable sampling of data and improving the overall communication quality and system stability.

[0076] It should be noted that the method of the following embodiment can be used as Figure 1 The refinement of step S110 in the illustrated embodiment.

[0077] Exemplarily, all gears in the delay line are traversed to determine the initial test results of the communication link corresponding to each gear. Specifically, taking the delay line adjusted to the initial gear (the initial gear is any gear in the delay line) as an example, the detection result of the communication link corresponding to the initial gear is determined, and the bit error rate of the communication link within the preset period is determined. When the bit error rate of the communication link within the preset period is less than or equal to the preset bit error rate, the initial detection result of the initial gear is determined to be 1; when the bit error rate of the communication link within the preset period is greater than the preset bit error rate, the initial detection result of the initial gear is determined to be 0.

[0078] Exemplarily, all gears in the delay line are traversed to determine the initial delay value corresponding to each gear. Specifically, the target unit of the initial gear is determined, the accumulated delay value of the target unit and the second delay value corresponding to the initial gear are obtained, and the sum of the accumulated delay value and the second delay value is determined as the initial delay value corresponding to the initial gear.

[0079] It should be noted that the initial gear is used to indicate any gear in the delay line. Due to the limitation of the delay line structure, every 8 gears are a structural unit, and the overall delay value corresponding to each structural unit is the same; for example, the overall delay value can be 12ps.

[0080] Exemplarily, the expression of the initial delay value can be expressed as follows:

[0081] Wherein, n represents the initial gear position; Indicates the initial delay corresponding to the initial gear position; Indicates that n / 8 is rounded down to an integer, which is used to calculate the target unit of the initial gear; t represents the overall delay value of the structural unit; n mod 8 represents the remainder of n divided by 8 (ranging from 0 to 7); represents a table lookup operation, and selects the corresponding second delay value according to the remainder. When , the corresponding second delay value is t3.

[0082] When determining the target unit of the initial gear, the cumulative delay value of the target unit is determined by multiplying the target unit and the overall delay value of the structural unit ( ); and determine the second delay value corresponding to the initial gear position according to the table lookup operation, and determine the sum of the accumulated delay value and the second delay value as the initial delay value corresponding to the initial gear position.

[0083] The above technical scheme obtains the accumulated delay value of the target unit where the initial gear is located and the second delay value in the target unit, and determines the sum of the accumulated delay value and the second delay value as the initial delay value corresponding to the initial gear; by determining the initial delay value of the initial gear in the delay value, the gear domain is converted into the time domain, so that the mapping relationship between the gear and the delay value can be accurately determined.

[0084] Figure 2 It is a schematic flow chart of a data expansion method provided in an embodiment of the present application.

[0085] For example, Figure 2 As shown, the data expansion method 200 includes the following processes S210-S260, and steps S210-S260 can be used as Figure 1 The refinement of step S120 in the illustrated embodiment.

[0086] S210, determining a target common divisor of the initial delay value.

[0087] Exemplarily, when the initial delay value is determined, an initial common divisor of the initial delay value is determined, and a target common divisor is obtained by selecting from the initial common divisors.

[0088] Optionally, the target common divisor may be the greatest common divisor of the initial delay values, and the target common divisor may be the least common divisor of the initial delay values. The target common divisor may be determined according to actual conditions and is not specifically limited here.

[0089] S220, performing data expansion processing on the initial delay value with the target common divisor as a step length to obtain a target delay value.

[0090] Exemplarily, the initial delay value is expanded with the target common divisor as the step size, and the target delay value can be obtained, and the number of the target delay values ​​is greater than the number of the initial delay values. For example, the initial delay values ​​include 0ps, 1.1ps, 2.2ps, 3.3ps, 4.4ps, 5.5ps, 6.6ps, 7.7ps and 12.7ps, and the initial delay value is expanded with 0.1ps as the step size, and the target delay values ​​include 0ps, 0.1ps, 0.2ps, 0.3ps...12.5ps, 12.6ps and 12.7ps.

[0091] Furthermore, the initial delay value is subjected to data expansion processing with the target common divisor as a step length to obtain the target delay value, and then the target test result corresponding to the target delay value is determined based on the initial test result and the initial delay value.

[0092] The above technical scheme performs data expansion processing on the initial delay value with the target common divisor of the initial delay value as the step size to obtain the target delay value, and determines the target test result corresponding to the target delay value based on the initial test result and the initial delay value; by performing data expansion on the initial delay value, the nonlinear jump position of the delay value can be accurately determined, and on this basis, the accuracy of determining the optimal sampling window can be improved, thereby improving the accuracy of the target gear position.

[0093] S230: Determine a target difference between the first initial delay value and the second initial delay value.

[0094] Exemplarily, the first initial delay value and the second initial delay value are used to indicate any adjacent delay value in the initial delay value, and a target difference between the first initial delay value and the second initial delay value is determined, and the target difference is used to indicate the absolute value of the difference between the first initial delay value and the second initial delay value. For example, the initial delay values ​​include 0ps, 1.1ps, 2.2ps, 3.3ps, 4.4ps, 5.5ps, 6.6ps, 7.7ps and 12.7ps, the first initial delay value is 1.1ps, and the second initial delay value is 2.2ps, then the target difference is 1.1.

[0095] S240, determine whether the target difference is greater than a preset difference; if not, execute S250; if so, execute S260.

[0096] Optionally, the preset difference may be 1.1, 1.2, etc. The preset difference may be determined according to actual conditions and is not specifically limited here.

[0097] Exemplarily, a target difference between a first initial delay value and a second initial delay value is determined, and it is determined whether the target difference is greater than a preset difference, so that when the target difference is less than or equal to the preset difference, the target detection result corresponding to the target delay value between the first initial delay value and the second initial delay value is supplemented; when the target difference is greater than the preset difference, an invalid value is determined as the target detection result corresponding to the target delay value between the first initial delay value and the second initial delay value.

[0098] S250: Determine the reference test result as a target test result corresponding to a target delay value between the first initial delay value and the second initial delay value.

[0099] Exemplarily, the reference test result is an initial test result corresponding to the first initial delay value or an initial test result corresponding to the second initial delay value. For example, the reference test result is an initial test result corresponding to the first initial delay value; or, the reference test result is an initial test result corresponding to the second initial delay value.

[0100] Exemplarily, when the target difference is less than or equal to the preset difference, the reference test result is determined as the target detection result corresponding to the target delay value between the first initial delay value and the second initial delay value. For example, the initial delay values ​​include 0ps, 1.1ps, 2.2ps, 3.3ps, 4.4ps, 5.5ps, 6.6ps, 7.7ps and 12.7ps, the first initial delay value is 1.1ps, the second initial delay value is 2.2ps, and the target difference is equal to the preset difference, and the reference test result is the initial test result corresponding to the first initial delay value; when the extension step is 0.1, the target delay value between the first initial delay value and the second initial delay value includes 1.2ps. , 1.3ps, 1.4ps, 1.5ps, 1.6ps, 1.7ps, 1.8ps, 1.9ps, 2ps and 2.1ps, when the initial test result corresponding to the first initial delay value is 1, the target test results corresponding to the target delay values ​​(1.2ps, 1.3ps, 1.4ps, 1.5ps, 1.6ps, 1.7ps, 1.8ps, 1.9ps, 2ps and 2.1ps) between the first initial delay value and the second initial delay value are all 1.

[0101] S260: Determine the invalid value as a target test result corresponding to a target delay value between the first initial delay value and the second initial delay value.

[0102] Exemplarily, when the target difference is greater than the preset difference, the invalid value is determined as the target test result corresponding to the target delay value between the first initial delay value and the second initial delay value. For example, the initial delay values ​​include 0ps, 1.1ps, 2.2ps, 3.3ps, 4.4ps, 5.5ps, 6.6ps, 7.7ps and 12.7ps, the first initial delay value is 7.7ps, the second initial delay value is 12.7ps, and the target difference is greater than the preset difference, and the reference test result is the initial test result corresponding to the first initial delay value; when the extension step is 0.1, the target delay value between the first initial delay value and the second initial delay value includes 7.8ps, 7.9ps, 8ps, 8.1ps...12.7ps, then the target test results corresponding to the target delay values ​​(7.8ps, 7.9ps, 8ps, 8.1ps...12.7ps) between the first initial delay value and the second initial delay value are all invalid values.

[0103] The above technical scheme determines the target difference between the first initial delay value and the second initial delay value; if the target difference is less than or equal to the preset difference, the reference test result is determined as the target test result corresponding to the target delay value between the first initial delay value and the second initial delay value, and the reference test result is the initial test result corresponding to the first initial delay value or the initial test result corresponding to the second initial delay value; so that when the target difference is less than or equal to the preset difference, the target detection result corresponding to the target delay value can be directly supplemented, and the target detection result corresponding to the delay value with a smaller difference can be estimated; if the target difference is greater than the preset difference, the invalid value is determined as the target test result corresponding to the target delay value between the first initial delay value and the second initial delay value; when the target difference is greater than the preset difference, the "dead zone" of the chip adjustable delay is accurately determined by the target difference between the delay values; on this basis, the target detection result in the "dead zone" area is compensated to improve the capture capability of the sampling window, thereby improving the accuracy of the target gear.

[0104] Figure 3 It is a schematic diagram of the corresponding relationship between a delay value and a detection result provided in an embodiment of the present application.

[0105] For example, Figure 3 (a) in FIG. 1 is a schematic diagram showing the corresponding relationship between the initial delay value and the initial detection result. Figure 3 (b) in FIG. 1 is a schematic diagram showing the corresponding relationship between the target delay value and the target detection result.

[0106] For example, Figure 3 The correspondence between the delay value and the detection result shown is explained based on the correspondence between the time axis of the delay value and the detection result on the time axis.

[0107] For example, Figure 3As shown in (a), the gears of the delay line include 0, 1, 2, 3, 4, 5, 6, 7 and 8; the initial delay value corresponding to 0 is 0ps, the initial delay value corresponding to 1 is 1.1ps, the initial delay value corresponding to 2 is 2.2ps, the initial delay value corresponding to 3 is 3.3ps, the initial delay value corresponding to 4 is 4.4ps, the initial delay value corresponding to 5 is 5.5ps, the initial delay value corresponding to 6 is 6.6ps, and the initial delay value corresponding to 7 is 7.7. ps, the initial delay value corresponding to gear 8 is 12.7ps; the initial detection result of the communication link in gear 0 is 0, the initial detection result of the communication link in gear 1 is 1, the initial detection result of the communication link in gear 2 is 1, the initial detection result of the communication link in gear 3 is 1, the initial detection result of the communication link in gear 4 is 1, the initial detection result of the communication link in gear 5 is 1, the initial detection result of the communication link in gear 6 is 1, the initial detection result of the communication link in gear 7 is 0, and the initial detection result of the communication link in gear 8 is 0.

[0108] For example, Figure 3 As shown in (b), the initial delay value is expanded with a step size of 0.1, and the target delay values ​​include 0ps, 0.1ps, 0.2ps, 0.3ps, 0.4ps, 0.5ps, 0.6ps, 0.7ps...12.1ps, 12.2ps, 12.3ps, 12.4ps, 12.5ps, 12.6ps, 12.7ps. The target delay value includes the initial delay value. Any adjacent delay value in the initial delay value is used as a reference point. Any adjacent delay value in the initial delay value is respectively the first initial delay value. An initial delay value and a second initial delay value are determined, and a target difference between the first initial delay value and the second initial delay value is determined, and whether the target difference is greater than a preset difference. When the target difference is less than or equal to the preset difference, the initial detection result corresponding to the smaller delay value between the first initial delay value and the second initial delay value is determined as the target detection result of the target delay value between the first initial delay value and the second initial delay value; when the target difference is greater than the preset difference, an invalid value is determined as the target detection result of the target delay value between the first initial delay value and the second initial delay value.

[0109] For example, the preset difference is 1.1, and the target detection result of the target delay value between 0ps and 1.1ps (0.1ps, 0.2ps, 0.3ps, 0.4ps, 0.5ps, 0.6ps, 0.7ps, 0.8ps, 0.9ps, 1ps) is determined to be 0 (the initial detection result corresponding to 0); the target detection result of the target delay value between 1.1ps and 2.2ps is determined to be 1 (the initial detection result corresponding to 1.1ps); the target detection result of the target delay value between 2.2ps and 3.3ps is determined to be 1 (the initial detection result corresponding to 2.2ps). the target detection result for the target delay value between 3.3ps and 4.4ps is determined as 1 (the initial detection result corresponding to 3.3ps); the target detection result for the target delay value between 4.4ps and 5.5ps is determined as 1 (the initial detection result corresponding to 4.4ps); the target detection result for the target delay value between 5.5ps and 6.6ps is determined as 1 (the initial detection result corresponding to 5.5ps); the target detection result for the target delay value between 6.6ps and 7.7ps is determined as 1 (the initial detection result corresponding to 6.6ps).

[0110] The difference between 7.7ps and 12.7ps is greater than the preset difference of 1.1, so the target detection result of the target delay value between 7.7ps and 12.7ps is determined to be 2 (invalid value). It can be understood that setting the invalid value to 2 is only one method that may be used in practical applications. The specific method of expressing the invalid value can be determined according to the actual situation and is not specifically limited here.

[0111] It should be noted that the method of the following embodiment can be used as Figure 1 The refinement of step S130 in the illustrated embodiment.

[0112] Exemplarily, determine whether the target test result corresponding to the reference delay value is a valid value. When the target detection result corresponding to the reference delay value is a valid value, the target test result corresponding to the reference delay value is determined as the updated test result corresponding to the first delay value; when the target detection result corresponding to the reference delay value is an invalid value, the target test result corresponding to the first delay value is determined as the updated test result corresponding to the first delay value.

[0113] It can be understood that the target delay value includes a reference delay value and a first delay value; the delay value in the "dead zone" area is the first delay value, and the target test result corresponding to the first delay value is an invalid value; the reference delay value is determined based on the first delay value and the unit time interval, and the reference delay value is a delay value that is n UIs long from the first delay value, and the target detection result corresponding to the reference delay value may be a valid value (0 or 1), of course, the target detection result corresponding to the reference delay value may also be an invalid value.

[0114] Exemplarily, when the target detection result is a valid value, the target detection result can be 0, or the target detection result can be 1; when the target detection result is an invalid value, the current target delay value is used to indicate that the delay line cannot accurately detect a valid result, resulting in the target detection result being an invalid value.

[0115] It should be noted that compensation is performed through the detection results of multiple UIs to update the target detection result corresponding to the target delay value, and then the updated detection result corresponding to the target delay value is obtained. The number of sampling windows in the updated detection result may be greater than the number of sampling windows in the target detection result.

[0116] Specifically, for the first delay value in the "dead zone" area, determine whether the target detection result corresponding to the reference delay value that is n UIs apart from the first delay value is a valid value. When the target detection result corresponding to the reference delay value is a valid value, the target detection result corresponding to the reference delay value is determined as the updated detection result corresponding to the first delay value; when the target detection result corresponding to the reference delay value is an invalid value, the target detection result corresponding to the first delay value is determined as the updated detection result corresponding to the first delay value. For the third delay value in the valid area (the area in the target delay value except the "dead zone"), the target detection result corresponding to the third delay value is determined as the updated detection result corresponding to the third delay value.

[0117] The above technical scheme determines whether the target test result corresponding to the reference delay value is a valid value; if it is a valid value, the target test result corresponding to the reference delay value is determined as the updated test result corresponding to the first delay value; if it is an invalid value, the target test result corresponding to the first delay value is determined as the updated test result corresponding to the first delay value; this scheme takes into account the actual situation that the delay adjustment range of the chip is greater than the length of one UI. Through comprehensive analysis of the gear detection results in different UIs, a "dead zone" area may appear in one UI, but when another UI is a valid area, the "dead zone" area is compensated, which can avoid the sampling inaccuracy caused by the "dead zone" area in a single UI, thereby improving the flexibility of the sampling clock phase selection and ensuring the accuracy of the target gear.

[0118] Figure 4 It is a schematic flowchart of a method for determining a target gear provided in an embodiment of the present application.

[0119] For example, Figure 4 As shown, the method 400 for determining the target gear position includes the following processes S410-S480, and steps S410-S480 can be used as Figure 1 The refinement of step S140 in the illustrated embodiment.

[0120] S410, traverse and update the test results to determine the maximum sampling window.

[0121] Exemplarily, when the update test result corresponding to the target delay value is determined, the update test results are traversed to determine the initial sampling window, and the largest one among the initial sampling windows is determined as the maximum sampling window.

[0122] Exemplarily, the maximum sampling window is used to indicate a sampling window with the largest window length in the initial sampling windows.

[0123] It can be understood that the sampling window refers to the optimal time interval selected by the receiver for capturing data within a UI.

[0124] S420, determining whether the starting delay value in the target delay value is within the candidate sampling window; if not, executing S430; if yes, executing S440.

[0125] Exemplarily, it is determined whether the starting delay value in the target delay value is within the candidate sampling window. When the starting delay value is within the candidate sampling window, it indicates that the starting delay value has a sampling window.

[0126] Exemplarily, the candidate sampling window is used to indicate a sampling window in the target delay value.

[0127] It should be noted that in digital communication, the eye diagram is a graphical representation method used to evaluate signal quality. The eye diagram is formed by superimposing the signal waveforms of multiple bit periods. It looks like an "eye", hence the name eye diagram. The eye width refers to the size of the eye opening in the horizontal direction, that is, the horizontal distance from the left to the right side of the eye diagram. The eye width reflects the time stability and timing tolerance of the signal. A larger eye width means more time margin near the sampling point, which makes it easier for the receiver to capture the signal at the correct time point, thereby improving the reliability of communication.

[0128] Exemplarily, the sampling window can be located at any position in the eye diagram. Since the length of the sampling window is limited by the width of the eye diagram, by determining whether the starting delay value is within the candidate sampling window and confirming the candidate sampling window, the candidate sampling window where the starting delay value is located is avoided from being ignored, thereby ensuring the accuracy of the target sampling delay value.

[0129] S430: Determine the central delay value of the maximum sampling window as the target sampling delay value.

[0130] Exemplarily, it is determined whether the starting delay value in the target delay value is within the candidate sampling window. When the starting delay value in the target delay value is outside the candidate sampling window, the central delay value of the maximum sampling window is determined as the target sampling delay value.

[0131] Exemplarily, the center delay value is used to indicate the delay value at the center position of the maximum sampling window. Specifically, the center position of the maximum sampling window is determined, and the delay value at the center position is determined as the center delay value.

[0132] S440: Determine a reference window length based on the second window length.

[0133] Exemplarily, it is determined whether the starting delay value in the target delay value is within the candidate sampling window. When the starting delay value in the target delay value is within the candidate sampling window, the reference window length is determined based on the second window length of the maximum sampling window.

[0134] For example, half of the second window length of the maximum sampling window is determined as the reference window length.

[0135] S450, determine whether the first window length is greater than the reference window length; if not, execute S460; if yes, execute S470.

[0136] Exemplarily, based on the second window length of the maximum sampling window, the reference window length is determined, it is determined whether the first window length of the candidate sampling window is greater than the reference window length, and the target sampling delay value is determined based on the comparison result between the first window length of the candidate sampling window and the reference window length.

[0137] S460: Determine the central delay value of the maximum sampling window as the target sampling delay value.

[0138] Exemplarily, when the first window length of the candidate sampling window is less than or equal to the reference window length, the central delay value of the maximum sampling window is determined as the target sampling delay value.

[0139] S470: Determine the difference delay value between the upper edge delay value of the candidate sampling window and the reference window length as the target sampling delay value.

[0140] Exemplarily, when the first window length of the candidate sampling window is greater than the reference window length, the difference delay value between the upper edge delay value of the candidate sampling window and the reference window length is determined as the target sampling delay value.

[0141] It should be noted that the candidate sampling window includes an upper edge delay value and a lower edge delay value, and the upper edge delay value is greater than the lower edge delay value. The difference delay value between the upper edge delay value of the candidate sampling window and the reference window length is a starting delay value greater than the target delay value and less than the delay value of the upper edge delay value.

[0142] For example, the candidate sampling window is [0, 1.1 ps], the upper edge delay value of the candidate sampling window is 1.1 ps, the lower edge delay value of the candidate sampling window is 0, and when the reference window length is 0.5 ps, the target sampling delay value is 0.6 ps.

[0143] S480, determining a target gear position based on the target sampling delay value.

[0144] Exemplarily, when the target sampling delay value is determined, the target sampling delay value is converted into a gear position to obtain a target gear position.

[0145] It can be understood that the target sampling delay value is used to indicate the best sampling point in the target delay value; however, adjusting the delay value through the delay line cannot accurately adjust to the best sampling point. Therefore, by determining the gear position closest to the best sampling point and determining the gear position as the target gear position, the control delay value is adjusted to the target gear position, which can ensure that the adjusted communication link has a lower bit error rate during data transmission, while improving communication quality and system stability.

[0146] For example, the expression of the target gear can be expressed as follows:

[0147] Among them, Tap represents the target gear position, represents the target sampling delay value; t represents the overall delay value of the structural unit; Express Round down to the nearest integer, used to calculate the target sampling delay value. Indicates mapping continuous value x to discrete labels The value closest to ; for example, when x is closest to hour, The value of ; Indicates table lookup operation, select the corresponding value gear according to the remainder. For example, when , the corresponding numerical gear is 3.

[0148] When determining the target sampling delay value, the large structural unit of the target sampling delay value is determined by the overall delay value of the structural unit ( ), each large structure unit contains 8 gears. The total number of gears accumulated before the large structure unit is determined by multiplying the large structure unit by 8; and the number of gears in the structure unit where the target sampling delay value is located is determined according to the table lookup operation, and the sum of the total number of gears and the number of gears in the structure unit is determined as the target gear corresponding to the target sampling delay value.

[0149] The above technical solution determines whether the starting delay value in the target delay value is within the candidate sampling window; if the starting delay value is outside the candidate sampling window, the center delay value of the maximum sampling window is determined as the target sampling delay value; if the starting delay value is within the candidate sampling window, the reference window length is determined based on the second window length; if the first window length is less than or equal to the reference window length, the center delay value of the maximum sampling window is determined as the target sampling delay value; if the first window length is greater than the reference window length, the difference delay value between the upper edge delay value of the candidate sampling window and the reference window length is determined as the target sampling delay value; by An inference mechanism is proposed for the relationship between the candidate sampling window starting from the starting delay value of the target delay value and the gear position. Due to the finiteness of the eye width of the eye diagram, when it is detected that there is a valid sampling window (candidate sampling window) starting from 0 (the starting delay value of the target delay value) and the length of the candidate sampling window is greater than the reference window length, the candidate sampling window is the best sampling window in the target delay value; on this basis, the target sampling delay value is determined, which can reduce the dependence on the nonlinear relationship between the gear position and the delay value and the invalid value area corresponding to the target delay value, ensure the accuracy of the target sampling delay value, and then improve the accuracy of the target gear position and reduce the bit error rate.

[0150] It should be understood that the above examples are intended to help those skilled in the art understand the embodiments of the present application, rather than to limit the embodiments of the present application to the specific numerical values ​​or specific scenarios illustrated. Those skilled in the art can obviously make various equivalent modifications or changes based on the above examples, and such modifications or changes also fall within the scope of the embodiments of the present application.

[0151] Combination of the above Figures 1 to 4 The signal delay adjustment method provided by the embodiment of the present application is described in detail; Figure 5 The signal delay adjustment device embodiment of the present application is described in detail. It should be understood that the signal delay adjustment device in the embodiment of the present application can execute various methods of the aforementioned embodiment of the present application, that is, the specific working process of the following various products can refer to the corresponding process in the aforementioned method embodiment.

[0152] Figure 5 It is a structural schematic diagram of a signal delay adjustment device provided in an embodiment of the present application.

[0153] For example, Figure 5 As shown, the signal delay adjustment device 500 includes: a memory 510 and a processor 520, wherein the memory 510 stores an executable program code 530, and the processor 520 is used to call and execute the executable program code 530 to perform a signal delay adjustment method.

[0154] Exemplarily, the memory 510 can be used to store relevant programs of the signal delay adjustment method provided in the embodiment of the present application; the processor 520 can call the relevant programs of the signal delay adjustment method stored in the memory 510 to execute the signal delay adjustment method of the embodiment of the present application; for example, obtain the initial delay value and the initial test result of the gear in the delay line; perform data expansion processing on the initial delay value and the initial test result to obtain the target delay value and the target test result corresponding to the target delay value; wherein, the number of target delay values ​​is greater than the number of initial delay values; based on the target test result corresponding to the reference delay value, the target test result corresponding to the first delay value is updated to obtain an updated test result of the target delay value; wherein, the target delay value includes a reference delay value and a first delay value; the target test result corresponding to the first delay value is an invalid value; the reference delay value is determined based on the first delay value and the unit time interval; based on the target delay value and the updated test result, the target gear is determined, and the delay line is controlled to adjust to the target gear.

[0155] This embodiment can divide the functional modules according to the above method example. For example, each functional module can be corresponded, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0156] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, which will not be repeated here.

[0157] In the case of an integrated unit, the device may include a processing module and a storage module. The processing module may be a processor or a controller, which may implement or execute various exemplary logic blocks, modules and circuits shown in combination with the disclosure of the present application. The processor may also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc. The storage module may be a memory.

[0158] In addition, the device provided in the embodiments of the present application may specifically be a chip, a component or a module, and the chip may include a connected processor and a memory; wherein the memory is used to store instructions, and when the processor calls and executes the instructions, the chip can execute a signal delay adjustment method provided in the above embodiments.

[0159] The present application also provides a computer-readable storage medium, in which a computer program code is stored. When the computer program code is executed on a computer, the computer executes the above-mentioned related method steps to implement a signal delay adjustment method provided in the above-mentioned embodiment. Among them, computer-readable storage media may include, but are not limited to, any type of disk, including floppy disks, optical disks, Digital Video Discs (DVDs), Compact Disc Read-Only Memory (CD-ROMs), microdrives and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAMs), Erasable Programmable Read-Only Memory (EPROMs), Electrically Erasable Programmable Read Only Memory (EEPROMs), Dynamic Random Access Memory (DRAMs), Video Random Access Memory (VRAMs), flash memory devices, magnetic cards or optical cards, nanosystems (including molecular memory ICs), or any type of medium or device suitable for storing instructions and / or data.

[0160] The present application also provides a computer program product. When the computer program product runs on a computer, the computer is enabled to execute the above-mentioned related steps to implement a signal delay adjustment method provided in the above-mentioned embodiment.

[0161] Among them, the computer-readable storage medium, computer program product or chip provided in this application is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be repeated here.

[0162] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0163] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0164] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A signal delay adjustment method, characterized in that: The method is applied to a chip; the method comprises: Obtain the initial delay value and initial test result of the gear in the delay line; Performing data expansion processing on the initial delay value and the initial test result to obtain a target delay value and a target test result corresponding to the target delay value; wherein the number of the target delay values ​​is greater than the number of the initial delay values; The target test result corresponding to the first delay value is updated based on the target test result corresponding to the reference delay value to obtain an updated test result of the target delay value; wherein the target delay value includes the reference delay value and the first delay value; the target test result corresponding to the first delay value is an invalid value; the reference delay value is determined based on the first delay value and the unit time interval; Based on the target delay value and the updated test result, a target gear position is determined, and the delay line is controlled to be adjusted to the target gear position.

2. The method according to claim 1, characterized in that The updating of the target test result corresponding to the first delay value based on the target test result corresponding to the reference delay value to obtain the updated test result of the target delay value includes: Determining whether a target test result corresponding to the reference delay value is a valid value; If it is a valid value, determining the target test result corresponding to the reference delay value as the updated test result corresponding to the first delay value; If it is an invalid value, the target test result corresponding to the first delay value is determined as the updated test result corresponding to the first delay value.

3. The method according to claim 1, characterized in that The determining the target gear position based on the target delay value and the updated test result includes: Traversing the update test results to determine a maximum sampling window; Based on the maximum sampling window, selecting a target sampling delay value from the target delay values; The target gear position is determined based on the target sampling delay value.

4. The method according to claim 3, characterized in that The method further comprises: Determine whether the starting delay value in the target delay value is within the candidate sampling window; The selecting a target sampling delay value from the target delay values ​​based on the maximum sampling window includes: If the starting delay value is within the candidate sampling window, determining the target sampling delay value based on a first window length of the candidate sampling window and a second window length of the maximum sampling window; If the starting delay value is outside the candidate sampling window, the central delay value of the maximum sampling window is determined as the target sampling delay value.

5. The method according to claim 4, characterized in that The determining the target sampling delay value based on the first window length of the candidate sampling window and the second window length of the maximum sampling window includes: Based on the second window length, determining a reference window length; wherein the reference window length is greater than or equal to half of the second window length; If the first window length is less than or equal to the reference window length, determining the central delay value of the maximum sampling window as the target sampling delay value; If the first window length is greater than the reference window length, a delay value that is a difference between the upper edge delay value of the candidate sampling window and the reference window length is determined as the target sampling delay value.

6. The method according to claim 1, characterized in that The performing data expansion processing on the initial delay value and the initial test result to obtain a target delay value and a target test result corresponding to the target delay value includes: Determining a target common divisor of the initial delay value; Performing data expansion processing on the initial delay value with the target common divisor as a step length to obtain the target delay value; Based on the initial test result and the initial delay value, a target test result corresponding to the target delay value is determined.

7. The method according to claim 6, characterized in that The determining, based on the initial test result and the initial delay value, a target test result corresponding to the target delay value comprises: Determine a target difference between a first initial delay value and a second initial delay value; wherein the first initial delay value and the second initial delay value are used to indicate any adjacent delay values ​​of the initial delay values; If the target difference is less than or equal to the preset difference, the reference test result is determined as the target test result corresponding to the target delay value between the first initial delay value and the second initial delay value; wherein the reference test result is the initial test result corresponding to the first initial delay value or the initial test result corresponding to the second initial delay value; If the target difference is greater than a preset difference, an invalid value is determined as a target test result corresponding to the target delay value between the first initial delay value and the second initial delay value.

8. The method according to claim 1, characterized in that The step of obtaining the initial delay value of the gear position in the delay line includes: Determine the target unit for the initial gear; Obtaining the accumulated delay value of the target unit and a second delay value corresponding to the initial gear position; The sum of the accumulated delay value and the second delay value is determined as the initial delay value corresponding to the initial gear position; wherein the initial gear position is used to indicate any gear position in the delay line.

9. A signal delay adjustment device, characterized in that: include: A memory for storing executable program codes; A processor, configured to call and run the executable program code from the memory, so that the signal delay adjustment device executes the signal delay adjustment method as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the signal delay adjustment method according to any one of claims 1 to 8 is implemented.

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