A level conversion circuit, a power supply chip and an electronic device

Abstract

The present invention provides a level conversion circuit, a power supply chip and an electronic device. The set terminal of the first RS flip-flop is connected to a power-on reset signal, and the first RS flip-flop is correspondingly connected to the second RS flip-flop; the first ends of the first pull-down unit and the second pull-down unit are used to connect to a low-voltage domain control signal; the second end of the first pull-down unit is connected between the positive output terminal of the first RS flip-flop and the set terminal of the second RS flip-flop, and the third end of the first pull-down unit is grounded; the second end of the second pull-down unit is connected between the inverted output terminal of the first RS flip-flop and the reset terminal of the second RS flip-flop, and the third end of the second pull-down unit is grounded. By switching the states of the first pull-down unit and the second pull-down unit, the states of the first RS flip-flop and the second RS flip-flop are adjusted, so as to achieve the purpose of quickly changing the high-voltage domain control signal, and make the voltage of the output switch signal controlled by the high-voltage domain control signal rise or fall faster.

Description

Technical Field

[0001] The present invention relates to the field of power supplies, and more particularly, to a level conversion circuit, a power supply chip, and an electronic device. Background Art

[0002] In the field of switching power supply design, such as the design of high-voltage high-power non-isolated power supply chips (also known as BUCK chips), high-voltage devices are used in the power stage, such as upper and lower power transistors and the drive circuit of the upper power transistor, etc., which belong to the high-voltage domain; the logic control module uses low-voltage devices, which belong to the low-voltage domain. For the transmission of control signals between the high-voltage domain and the low-voltage domain, a level conversion circuit is required.

[0003] With the development of technology, the switching frequency is getting higher and higher, and the requirement for efficiency is also getting higher and higher. This requires a faster switching rate of the power transistor, so as to ensure a faster rise and fall rate of the output switching signal voltage (also known as SW). How to design a level conversion circuit that meets this requirement has become one of the difficult problems concerned by those skilled in the art. Summary of the Invention

[0004] The purpose of the present invention is to provide a level conversion circuit, a power supply chip, and an electronic device to improve the above problems.

[0005] To achieve the above purpose, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, an embodiment of the present invention provides a level conversion circuit, which includes: a first RS flip-flop, a second RS flip-flop, a first pull-down unit, and a second pull-down unit;

[0007] The set terminal of the first RS flip-flop is used to access a power-on reset signal. The positive output terminal of the first RS flip-flop is connected to the set terminal of the second RS flip-flop, the negative output terminal of the first RS flip-flop is connected to the reset terminal of the second RS flip-flop, and the positive output terminal of the second RS flip-flop serves as the output terminal of the level conversion circuit;

[0008] The first ends of the first pull-down unit and the second pull-down unit are used to access low-voltage domain control signals;

[0009] The second end of the first pull-down unit is connected between the positive output terminal of the first RS flip-flop and the set terminal of the second RS flip-flop, and the third end of the first pull-down unit is grounded;

[0010] The second end of the second pull-down unit is connected between the negative output terminal of the first RS flip-flop and the reset terminal of the second RS flip-flop, and the third end of the second pull-down unit is grounded.

[0011] In the level conversion circuit provided by the embodiment of the present invention, the states of the first RS flip-flop and the second RS flip-flop are adjusted by switching the states of the first pull-down unit and the second pull-down unit, so as to achieve the purpose of quickly changing the high-voltage domain control signal (PWM_HV), so that the output switch signal voltage (SW) controlled by the high-voltage domain control signal (PWM_HV) can rise or fall faster.

[0012] Optionally, the first pull-down unit is used to switch to the conducting state when the rising edge of the low-voltage domain control signal is sampled, and the duration of the conducting state is a first preset duration, so that the positive output terminal of the second RS flip-flop outputs a high-level high-voltage domain control signal;

[0013] The second pull-down unit is used to switch to the conducting state when the falling edge of the low-voltage domain control signal is sampled, and the duration of the conducting state is a second preset duration, so that the positive output terminal of the second RS flip-flop outputs a low-level high-voltage domain control signal.

[0014] Optionally, the first pull-down unit includes a rising-edge sampling circuit, a first driving circuit, and a first pull-down transistor;

[0015] The input terminal of the rising-edge sampling circuit serves as the first terminal of the first pull-down unit, the output terminal of the rising-edge sampling circuit is connected to the input terminal of the first driving circuit, the output terminal of the first driving circuit is connected to the first terminal of the first pull-down transistor, the second terminal of the first pull-down transistor serves as the second terminal of the first pull-down unit, and the third terminal of the first pull-down transistor serves as the third terminal of the first pull-down unit;

[0016] The rising-edge sampling circuit is used to sample the rising edge of the low-voltage domain control signal, and when the rising edge of the low-voltage domain control signal is sampled, it outputs a first high-pulse signal to the first driving circuit, and the pulse width of the first high-pulse signal is the first preset duration;

[0017] The first driving circuit is used to output a driving signal to the first pull-down transistor when receiving the first high-pulse signal, so that the first pull-down transistor switches to the conducting state.

[0018] Since the first preset duration is less than the high-level duration of the low-voltage domain control signal, the first pull-down transistor will not be in the conducting state all the time during the high-level duration of the low-voltage domain control signal, which can reduce power consumption. The first preset duration is greater than the rising-edge change duration of the output switch signal voltage, so that the output switch signal voltage can complete the jump smoothly.

[0019] Optionally, the second pull-down unit includes a falling-edge sampling circuit, a second driving circuit, and a second pull-down transistor;

[0020] The input terminal of the falling-edge sampling circuit serves as the first terminal of the second pull-down unit. The output terminal of the falling-edge sampling circuit is connected to the input terminal of the second driving circuit. The output terminal of the second driving circuit is connected to the first terminal of the second pull-down transistor. The second terminal of the second pull-down transistor serves as the second terminal of the second pull-down unit, and the third terminal of the second pull-down transistor serves as the third terminal of the second pull-down unit;

[0021] The falling-edge sampling circuit is configured to sample the falling edge of the low-voltage domain control signal. When the falling edge of the low-voltage domain control signal is sampled, a second high-pulse signal is output to the second driving circuit, and the pulse width of the second high-pulse signal is the second preset duration;

[0022] The second driving circuit is configured to output a driving signal to the second pull-down transistor when receiving the second high-pulse signal, so that the second pull-down transistor is switched to the conducting state.

[0023] Since the second preset duration is less than the low-level duration of the low-voltage domain control signal, the second pull-down transistor will not be in the conducting state all the time during the low-level duration of the low-voltage domain control signal, which can reduce power consumption. The second preset duration is greater than the voltage falling-edge change duration of the output switching signal, so as to ensure that the output switching signal voltage can complete the jump smoothly.

[0024] Optionally, the level conversion circuit further includes a first diode and a second diode;

[0025] The positive electrodes of the first diode and the second diode are used to connect to the output switching signal voltage;

[0026] The negative electrode of the first diode is connected between the positive output terminal of the first RS flip-flop and the set terminal of the second RS flip-flop;

[0027] The negative electrode of the second diode is connected between the negative output terminal of the first RS flip-flop and the reset terminal of the second RS flip-flop.

[0028] The first diode and the second diode play a protective role, clamping the lowest voltage of the V21 / V22 node at (SW - VD), where VD is the forward conduction voltage of the first diode and the second diode, so as to prevent the first pull-down unit or the second pull-down unit from pulling down the V21 / V22 node to 0, causing the low-voltage devices in the high-voltage domain to bear the high voltage of 0 - BST and resulting in device breakdown.

[0029] In a second aspect, an embodiment of the present invention provides a power supply chip, which includes a third switching transistor, a third driving circuit, a first capacitor, and the above-mentioned level conversion circuit;

[0030] The output terminal of the level conversion circuit is connected to the input terminal of the third driving circuit. The output terminal of the third driving circuit is connected to the first end of the third switching tube. The second end of the third switching tube is used to access the high-voltage domain electrical signal, and the third end of the third switching tube is used to connect to the subsequent circuit;

[0031] The low-level terminal of the third driving circuit and one end of the first capacitor are connected to the third end of the third switching tube, and the other end of the first capacitor is connected to the high-level terminal of the third driving circuit;

[0032] The signal accessed by the low-level terminal of the third driving circuit is the output switch signal voltage, and the signal accessed by the high-level terminal of the third driving circuit is the bootstrap voltage. The bootstrap voltage = the output switch signal voltage + the preset voltage;

[0033] The high-level terminals of the first RS flip-flop and the second RS flip-flop access the bootstrap voltage, and the low-level terminals of the first RS flip-flop and the second RS flip-flop access the output switch signal voltage.

[0034] In a third aspect, an embodiment of the present invention provides an electronic device, including: the above-mentioned power supply chip.

[0035] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other relevant drawings can also be obtained based on these drawings.

[0037] Figure 1 It is a schematic structural diagram of the level conversion circuit provided by the embodiment of the present invention.

[0038] Figure 2 It is a schematic structural diagram of the power supply chip provided by the embodiment of the present invention.

[0039] Figure 3 It is a schematic diagram of the working signals of the level conversion circuit provided by the embodiment of the present invention.

[0040] In the figure: 10 - the first RS flip-flop; 20 - the second RS flip-flop; 30 - the first pull-down unit; 31 - the rising-edge sampling circuit; 40 - the second pull-down unit; 41 - the falling-edge sampling circuit. Detailed Embodiments

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and illustrated herein generally may be arranged and designed in a variety of different configurations.

[0042] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but is merely representative of selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0043] It should be noted that: like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it does not require further definition and explanation in subsequent drawings. Also, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive distinction and cannot be construed as indicating or implying relative importance.

[0044] Moreover, the term "comprising", "including", or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0045] The following will describe in detail some embodiments of the present invention with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments may be combined with each other.

[0046] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of the level conversion circuit provided by the embodiment of the present invention. The level conversion circuit includes: a first RS flip-flop 10, a second RS flip-flop 20, a first pull-down unit 30, and a second pull-down unit 40.

[0047] As Figure 1 shown, the level conversion circuit is divided into a high-voltage domain (SW-BST) and a low-voltage threshold (0-VCC).

[0048] The set terminal of the first RS flip-flop 10 is used to connect to a power-on reset signal (POR). The positive output terminal of the first RS flip-flop 10 is connected to the set terminal of the second RS flip-flop 20. The negative output terminal of the first RS flip-flop 10 is connected to the reset terminal of the second RS flip-flop 20. The reset terminal of the first RS flip-flop 10 is connected to the positive output terminal of the first RS flip-flop 10. The positive output terminal of the second RS flip-flop 20 serves as the output terminal of the level conversion circuit.

[0049] The first end of the first pull-down unit 30 and the first end of the second pull-down unit 40 are used to connect to a low-voltage domain control signal (PWM_LV).

[0050] The second end of the first pull-down unit 30 is connected between the positive output terminal of the first RS flip-flop 10 and the set terminal of the second RS flip-flop 20, and the third end of the first pull-down unit 30 is grounded.

[0051] The second end of the second pull-down unit 40 is connected between the negative output terminal of the first RS flip-flop 10 and the reset terminal of the second RS flip-flop 20, and the third end of the second pull-down unit 40 is grounded.

[0052] In an alternative embodiment, the high-level terminals of the first RS flip-flop 10 and the second RS flip-flop 20 are connected to a bootstrap voltage (BST), and the low-level terminals of the first RS flip-flop 10 and the second RS flip-flop 20 are connected to an output switch signal voltage (SW), where the bootstrap voltage (BST) = the output switch signal voltage (SW) + a preset voltage.

[0053] In an alternative embodiment, the first pull-down unit 30 is used to switch to a conducting state when the rising edge of the low-voltage domain control signal is sampled, and the duration of the conducting state is a first preset duration, so that the positive output terminal of the second RS flip-flop 20 outputs a high-level high-voltage domain control signal (PWM_HV).

[0054] The second pull-down unit 40 is used to switch to a conducting state when the falling edge of the low-voltage domain control signal is sampled, and the duration of the conducting state is a second preset duration, so that the positive output terminal of the second RS flip-flop 20 outputs a low-level high-voltage domain control signal (PWM_HV).

[0055] Wherein, the first preset duration is greater than the circuit propagation delay + the rising edge change duration of the output switch signal voltage, and less than or equal to the high-level duration of the low-voltage domain control signal; the second preset duration is greater than the circuit propagation delay + the falling edge change duration of the output switch signal voltage, and less than or equal to the low-level duration of the low-voltage domain control signal.

[0056] In the level conversion circuit provided by the embodiment of the present invention, by switching the states of the first pull-down unit and the second pull-down unit, the states of the first RS flip-flop and the second RS flip-flop are adjusted, so as to achieve the purpose of quickly changing the high-voltage domain control signal (PWM_HV), and make the output switch signal voltage (SW) controlled by the high-voltage domain control signal (PWM_HV) rise or fall faster.

[0057] It should be noted that after the high-voltage domain control signal (PWM_HV) becomes high level, the output switch signal voltage (SW) rises rapidly, and after the high-voltage domain control signal (PWM_HV) becomes low level, the output switch signal voltage (SW) drops rapidly.

[0058] As Figure 1 shown, at the beginning of power-on, when the loop has not started working and the low-voltage domain control signal (PWM_LV) remains low level, the initial state of the high-voltage domain is as follows:

[0059] The initial state of the power-on reset signal (POR) is low level, that is, the set terminal of the first RS flip-flop 10 is low level L, the positive output terminal of the first RS flip-flop 10 is high level H, that is, V21 is high level H, the reset terminal of the first RS flip-flop 10 is high level H, and the inverted output terminal of the first RS flip-flop 10 is low level L, that is, V22 is low level L;

[0060] The set terminal of the second RS flip-flop 20 is high level H (the same as V21), the reset terminal of the second RS flip-flop 20 is low level L, the inverted output terminal of the second RS flip-flop 20 is high level H, and the positive output terminal of the second RS flip-flop 20 is low level L, that is, at this time the high-voltage domain control signal (PWM_HV) is low level L.

[0061] Optionally, the transition time of the power-on reset signal (POR) is earlier than the arrival time of the first rising edge of the low-voltage domain control signal (PWM_LV). After the power-on reset signal (POR) jumps to high level, the power-on reset signal (POR) remains high level thereafter. The set terminal of the first RS flip-flop 10 is high level H, the positive output terminal of the first RS flip-flop 10 is high level H, that is, V21 is high level H, the reset terminal of the first RS flip-flop 10 is high level H, and the inverted output terminal of the first RS flip-flop 10 is low level L, that is, V22 is low level L;

[0062] The set terminal of the second RS flip-flop 20 is high level H (the same as V21), the reset terminal of the second RS flip-flop 20 is low level L, the inverted output terminal of the second RS flip-flop 20 is high level H, and the positive output terminal of the second RS flip-flop 20 is low level L, that is, at this time the high-voltage domain control signal (PWM_HV) is low level L.

[0063] When the first pull-down unit 30 is turned on and the second pull-down unit 40 is turned off, that is, V21 is pulled to the low level L, the set terminal of the second RS flip-flop 20 is at the low level L (the same as V21), and the positive output terminal of the second RS flip-flop 20 is at the high level H, that is, the high-voltage domain control signal (PWM_HV) is at the high level H; the positive output terminal of the first RS flip-flop 10 is pulled to the low level L, the reset terminal of the first RS flip-flop 10 also becomes the low level L, and the negative output terminal of the first RS flip-flop 10 is at the high level H, that is, V22 is at the high level H, the reset terminal of the second RS flip-flop 20 is at the high level H, and the negative output terminal of the second RS flip-flop 20 is at the low level L. In this case, even when the first pull-down unit 30 returns to the off state and the second pull-down unit 40 remains off, the states of V21, V22, and the high-voltage domain control signal (PWM_HV) will be latched through the two RS flip-flops.

[0064] When the first pull-down unit 30 is turned off and the second pull-down unit 40 is turned on, that is, V22 is pulled to the low level L, the reset terminal of the second RS flip-flop 20 is at the low level L (the same as V22), and the negative output terminal of the second RS flip-flop 20 is at the high level H.

[0065] The negative output terminal of the first RS flip-flop 10 is at the low level L, the positive output terminal of the first RS flip-flop 10 is at the high level H, that is, V21 is at the high level H, the set terminal of the second RS flip-flop 20 is at the high level H, so the positive output terminal of the second RS flip-flop 20 is at the low level L. In this case, even when the first pull-down unit 30 remains off and the second pull-down unit 40 returns to the off state, the states of V21, V22, and the high-voltage domain control signal (PWM_HV) will be latched through the two RS flip-flops.

[0066] Please continue to refer to Figure 1 The first pull-down unit 30 includes a rising-edge sampling circuit 31, a first driving circuit U1, and a first pull-down transistor Q1. Among them, the rising-edge sampling circuit 31 and the first driving circuit U1 are low-voltage devices, and the first pull-down transistor Q1 is a high-voltage device.

[0067] It should be noted that the first pull-down transistor Q1 needs to have a small on-resistance, so the channel width W of the first pull-down transistor Q1 needs to be large enough, which will cause the gate (G) parasitic capacitance to increase. In this case, in order to achieve the purpose of fast switching, it is necessary to set the first driving circuit U1.

[0068] The input terminal of the rising-edge sampling circuit 31 serves as the first end of the first pull-down unit 30 (connected to the low-voltage domain control signal PWM_LV). The output terminal of the rising-edge sampling circuit 31 is connected to the input terminal of the first driving circuit U1. The output terminal of the first driving circuit U1 is connected to the first end of the first pull-down transistor Q1. The second end of the first pull-down transistor Q1 serves as the second end of the first pull-down unit 30 (connected between the positive output terminal of the first RS flip-flop 10 and the set terminal of the second RS flip-flop 20). The third end of the first pull-down transistor Q1 serves as the third end of the first pull-down unit 30 (grounded).

[0069] The rising-edge sampling circuit 31 is used to sample the rising edge of the low-voltage domain control signal. When the rising edge of the low-voltage domain control signal is sampled, a first high pulse signal is output to the first driving circuit U1. The pulse width of the first high pulse signal is a first preset duration, where the first preset duration is less than the high-level duration of the low-voltage domain control signal and greater than the rising-edge change duration of the output switch signal voltage.

[0070] The first driving circuit U1 is used to output a driving signal to the first pull-down transistor Q1 when receiving the first high pulse signal, so that the first pull-down transistor Q1 is switched to the conducting state.

[0071] Because the first preset duration is less than the high-level duration of the low-voltage domain control signal, the first pull-down transistor Q1 will not always be in the conducting state during the high-level duration of the low-voltage domain control signal, which can reduce power consumption. The first preset duration is greater than the rising-edge change duration of the output switch signal voltage, so as to ensure that the output switch signal voltage can complete the jump smoothly.

[0072] Please continue to refer to Figure 1 , the second pull-down unit 40 includes a falling-edge sampling circuit 41, a second driving circuit U2, and a second pull-down transistor Q2; among them, the falling-edge sampling circuit 41 and the second driving circuit U are low-voltage devices, and the second pull-down transistor Q2 is a high-voltage device.

[0073] The input terminal of the falling-edge sampling circuit 41 serves as the first end of the second pull-down unit 40 (connected to the low-voltage domain control signal). The output terminal of the falling-edge sampling circuit 41 is connected to the input terminal of the second driving circuit U2. The output terminal of the second driving circuit U2 is connected to the first end of the second pull-down transistor Q2. The second end of the second pull-down transistor Q2 serves as the second end of the second pull-down unit 40 (connected between the inverted output terminal of the first RS flip-flop 10 and the reset terminal of the second RS flip-flop 20). The third end of the second pull-down transistor Q2 serves as the third end of the second pull-down unit 40 (grounded).

[0074] The falling-edge sampling circuit 41 is used to sample the falling edge of the low-voltage domain control signal. When the falling edge of the low-voltage domain control signal is sampled, a second high pulse signal is output to the second driving circuit U2. The pulse width of the second high pulse signal is a second preset duration, where the second preset duration is greater than the falling-edge change duration of the output switch signal voltage and less than the low-level duration of the low-voltage domain control signal.

[0075] The second driving circuit U2 is used to output a driving signal to the second pull-down transistor Q2 when receiving the second high pulse signal, so that the second pull-down transistor Q2 is switched to the conducting state.

[0076] Because the second preset duration is less than the low-level duration of the low-voltage domain control signal, the second pull-down transistor Q2 will not always be in the conducting state during the low-level duration of the low-voltage domain control signal, which can reduce power consumption. The second preset duration is greater than the falling-edge change duration of the output switch signal voltage, so as to ensure that the output switch signal voltage can complete the jump smoothly.

[0077] In an alternative embodiment, the input terminals of the first driving circuit U1 and the second driving circuit U2 can be directly connected to the low-voltage domain control signal PWM_LV. The first preset duration is equal to the high-level duration of the low-voltage domain control signal, and the second preset duration is equal to the low-level duration of the low-voltage domain control signal.

[0078] In an alternative embodiment, the on-resistance of the first pull-down transistor Q1 and the on-resistance of the second pull-down transistor Q2 are less than or equal to 1 / N of the on-resistance of the first RS flip-flop 10 (the first NAND gate M1 or the second NAND gate M2 therein), where N is a preset value (which can be but is not limited to 10 or a number greater than 10). Thus, the driving capabilities of the first pull-down transistor Q1 and the second pull-down transistor Q2 are much greater than those of the first RS flip-flop 10 (the first NAND gate M1 or the second NAND gate M2 therein).

[0079] Analysis shows that after the rising edge of the low-voltage domain control signal (PWM_LV) arrives, the high-voltage domain control signal (PWM_HV) will become high level, and at this time the output switch signal voltage (SW) rises rapidly. During the rapid rise of the output switch signal voltage (SW), due to the equivalent pull-up resistance of the first RS flip-flop 10 (the second NAND gate M2 therein) and the parasitic capacitance to ground of the second pull-down transistor Q2, the rising speed of the voltage at the V22 node is slower than that of the output switch signal voltage (SW), and it may present a low-level situation relative to the (SW--BST) voltage domain. Since the driving capability of the first pull-down transistor Q1 is much greater than that of the first RS flip-flop 10, the low-level state of V21 will not change, and the output state of the second RS flip-flop 20 will not change either, thus ensuring the stable state of the high-voltage domain control signal (PWM_HV) and preventing misflipping.

[0080] Regarding the structure of the RS flip-flop, an alternative embodiment is provided in an embodiment of the present invention. Please continue to refer to Figure 1 , the first RS flip-flop 10 includes a first NAND gate M1 and a second NAND gate M2.

[0081] The first input terminal of the first NAND gate M1 serves as the set terminal of the first RS flip-flop 10 (for accessing the power-on reset signal POR), the second input terminal of the first NAND gate M1 is connected to the output terminal of the second NAND gate M2, and the output terminal of the first NAND gate M1 serves as the positive output terminal of the first RS flip-flop 10 (connected to the set terminal of the second RS flip-flop 20).

[0082] The first input terminal of the second NAND gate M2 and the second input terminal of the second NAND gate M2 (the reset terminal of the first RS flip-flop 10) are connected to the output terminal of the first NAND gate M1, and the output terminal of the second NAND gate M2 serves as the negative output terminal of the first RS flip-flop 10 (connected to the reset terminal of the second RS flip-flop 20).

[0083] Please continue to refer to Figure 1 , the second RS flip-flop 20 includes a third NAND gate M3 and a fourth NAND gate M4.

[0084] The first input terminal of the third NAND gate M3 serves as the set terminal of the second RS flip-flop 20 (connected to the positive output terminal of the first RS flip-flop 10), the second input terminal of the third NAND gate M3 is connected to the output terminal of the fourth NAND gate M4, and the output terminal of the third NAND gate M3 serves as the positive output terminal of the second RS flip-flop 20.

[0085] The first input terminal of the fourth NAND gate M4 is connected to the output terminal of the third NAND gate M3, and the second input terminal of the fourth NAND gate M4 serves as the reset terminal of the second RS flip-flop 20 (connected to the negative output terminal of the first RS flip-flop 10).

[0086] In an alternative implementation, the high-level terminals of the first RS flip-flop 10 and the second RS flip-flop 20 are connected to the bootstrap voltage, the low-level terminals of the first RS flip-flop 10 and the second RS flip-flop 20 are connected to the output switch signal voltage, and the bootstrap voltage = output switch signal voltage + preset voltage. Specifically, the high-level terminals of the first NAND gate M1, the second NAND gate M2, the third NAND gate M3, and the fourth NAND gate M4 are connected to the bootstrap voltage, and the low-level terminals of the first NAND gate M1, the second NAND gate M2, the third NAND gate M3, and the fourth NAND gate M4 are connected to the output switch signal voltage.

[0087] Please continue to refer to Figure 1, in an alternative embodiment, the level conversion circuit further includes a first diode D1 and a second diode D2.

[0088] The anodes of the first diode D1 and the second diode D2 are used to access the output switch signal voltage (SW).

[0089] The cathode of the first diode D1 is connected between the positive output terminal of the first RS flip - flop 10 and the set terminal of the second RS flip - flop 20.

[0090] The cathode of the second diode D2 is connected between the negative output terminal of the first RS flip - flop 10 and the reset terminal of the second RS flip - flop 20.

[0091] The first diode D1 and the second diode D2 play a protective role, clamping the lowest voltage of the V21 / V22 node at (SW - VD), where VD is the forward conduction voltage of the first diode D1 and the second diode D2, thereby preventing the first pull - down unit 30 or the second pull - down unit 40 from pulling the V21 / V22 node down to 0, causing the low - voltage devices in the high - voltage domain to withstand the high voltage of 0 - BST and resulting in device breakdown.

[0092] In an alternative embodiment, the first NAND gate M1, the second NAND gate M2, the third NAND gate M3, the fourth NAND gate M4, the first diode D1, and the second diode D2 are all low - voltage devices in the high - voltage isolation region.

[0093] The embodiment of the present invention also provides a power supply chip. Please refer to Figure 2 , Figure 2 is the structural schematic diagram of the power supply chip provided by the embodiment of the present invention. The power supply chip includes a third switching transistor Q3, a third driving circuit U3, a first capacitor C1, and the above - mentioned level conversion circuit.

[0094] The output terminal of the level conversion circuit is connected to the input terminal of the third driving circuit U3. The output terminal of the third driving circuit U3 is connected to the first end of the third switching transistor Q3. The second end of the third switching transistor Q3 is used to access the high - voltage domain electrical signal (VIN), and the third end of the third switching transistor Q3 is used to connect to the subsequent circuit.

[0095] The low - level terminal of the third driving circuit U3 and one end of the first capacitor C1 are connected to the third end of the third switching transistor Q3, and the other end of the first capacitor C1 is connected to the high - level terminal of the third driving circuit U3.

[0096] The signal accessed by the low - level terminal of the third driving circuit U3 is the output switch signal voltage, and the signal accessed by the high - level terminal of the third driving circuit U3 is the bootstrap voltage, where the bootstrap voltage = output switch signal voltage+preset voltage.

[0097] The high-level terminal of the first RS flip-flop 10 and the high-level terminal of the second RS flip-flop 20 are connected to the bootstrap voltage (BST), and the low-level terminal of the first RS flip-flop 10 and the low-level terminal of the second RS flip-flop 20 are connected to the output switch signal voltage (SW).

[0098] It should be understood that when the high-voltage domain control signal (PWM_HV) output by the level conversion circuit is high, the third drive circuit U3 outputs a control signal to control the third switch Q3 to be in the on state, and the output switch signal voltage (SW) starts to rise until it is equal to the high-voltage domain electrical signal (VIN). When the high-voltage domain control signal (PWM_HV) output by the level conversion circuit is low, the third drive circuit U3 outputs a control signal to control the third switch Q3 to be in the off state, and the output switch signal voltage (SW) starts to decrease until it drops to 0V.

[0099] Please refer to Figure 3 , Figure 3 which is a schematic diagram of the working signals of the level conversion circuit provided by the embodiment of the present invention. Among them, T1 represents the first preset duration, T2 represents the second preset duration, PWM_LV represents the low-voltage domain control signal, R_PWM_LV represents the first high pulse signal, F_PWM_LV represents the second high pulse signal, PWM_HV represents the high-voltage domain control signal, BST represents the bootstrap voltage, and SW represents the output switch signal voltage.

[0100] The embodiment of the present invention also provides an electronic device, including: the above-mentioned power supply chip.

[0101] The electronic device can be, but is not limited to, a mobile phone, a computer, a server, and other intelligent terminals.

[0102] In summary, a level conversion circuit, a power supply chip and an electronic device provided by an embodiment of the present invention. The set terminal of the first RS flip-flop is connected to a power-on reset signal. The positive output terminal of the first RS flip-flop is connected to the set terminal of the second RS flip-flop. The negative output terminal of the first RS flip-flop is connected to the reset terminal of the second RS flip-flop. The positive output terminal of the second RS flip-flop serves as the output terminal of the level conversion circuit. The first ends of the first pull-down unit and the second pull-down unit are used to connect to a low-voltage domain control signal. The second end of the first pull-down unit is connected between the positive output terminal of the first RS flip-flop and the set terminal of the second RS flip-flop, and the third end of the first pull-down unit is grounded. The second end of the second pull-down unit is connected between the negative output terminal of the first RS flip-flop and the reset terminal of the second RS flip-flop, and the third end of the second pull-down unit is grounded. By switching the states of the first pull-down unit and the second pull-down unit, the states of the first RS flip-flop and the second RS flip-flop are adjusted, so as to achieve the purpose of quickly changing the high-voltage domain control signal, and make the voltage of the output switch signal controlled by the high-voltage domain control signal rise or fall faster.

[0103] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0104] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, it is intended to include all changes falling within the meaning and scope of the equivalent elements of the claims in the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.

Claims

1. A level conversion circuit, characterized in that, The level conversion circuit includes: a first RS flip-flop, a second RS flip-flop, a first pull-down unit, and a second pull-down unit; The set terminal of the first RS flip-flop is used to access a power-on reset signal. The positive output terminal of the first RS flip-flop is connected to the set terminal of the second RS flip-flop. The negative output terminal of the first RS flip-flop is connected to the reset terminal of the second RS flip-flop. The positive output terminal of the second RS flip-flop serves as the output terminal of the level conversion circuit; The first ends of the first pull-down unit and the second pull-down unit are used to access a low-voltage domain control signal; The second end of the first pull-down unit is connected between the positive output terminal of the first RS flip-flop and the set terminal of the second RS flip-flop, and the third end of the first pull-down unit is grounded; The second end of the second pull-down unit is connected between the negative output terminal of the first RS flip-flop and the reset terminal of the second RS flip-flop, and the third end of the second pull-down unit is grounded; The first pull-down unit is used to switch to a conducting state when the rising edge of the low-voltage domain control signal is sampled, and the duration of the conducting state is a first preset duration, so that the positive output terminal of the second RS flip-flop outputs a high-level high-voltage domain control signal; The second pull-down unit is used to switch to a conducting state when the falling edge of the low-voltage domain control signal is sampled, and the duration of the conducting state is a second preset duration, so that the positive output terminal of the second RS flip-flop outputs a low-level high-voltage domain control signal.

2. The level conversion circuit according to claim 1, wherein The first pull-down unit includes a rising-edge sampling circuit, a first driving circuit, and a first pull-down transistor; The input terminal of the rising-edge sampling circuit serves as the first end of the first pull-down unit. The output terminal of the rising-edge sampling circuit is connected to the input terminal of the first driving circuit. The output terminal of the first driving circuit is connected to the first end of the first pull-down transistor. The second end of the first pull-down transistor serves as the second end of the first pull-down unit. The third end of the first pull-down transistor serves as the third end of the first pull-down unit; The rising-edge sampling circuit is used to sample the rising edge of the low-voltage domain control signal. When the rising edge of the low-voltage domain control signal is sampled, a first high pulse signal is output to the first driving circuit, and the pulse width of the first high pulse signal is a first preset duration; The first driving circuit is used to output a driving signal to the first pull-down transistor when receiving the first high pulse signal, so that the first pull-down transistor switches to a conducting state.

3. The level conversion circuit according to claim 1, wherein The second pull-down unit includes a falling-edge sampling circuit, a second driving circuit, and a second pull-down transistor; The input terminal of the falling-edge sampling circuit serves as the first end of the second pull-down unit. The output terminal of the falling-edge sampling circuit is connected to the input terminal of the second driving circuit. The output terminal of the second driving circuit is connected to the first end of the second pull-down transistor. The second end of the second pull-down transistor serves as the second end of the second pull-down unit. The third end of the second pull-down transistor serves as the third end of the second pull-down unit; The falling-edge sampling circuit is used to sample the falling edge of the low-voltage domain control signal. When the falling edge of the low-voltage domain control signal is sampled, a second high-pulse signal is output to the second driving circuit, and the pulse width of the second high-pulse signal is a second preset duration; The second driving circuit is used to output a driving signal to the second pull-down transistor when receiving the second high-pulse signal, so that the second pull-down transistor is switched to the conducting state.

4. The level conversion circuit according to claim 1, characterized in that The first RS flip-flop includes a first NAND gate and a second NAND gate; The first input terminal of the first NAND gate serves as the set terminal of the first RS flip-flop, the second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate, and the output terminal of the first NAND gate serves as the positive output terminal of the first RS flip-flop; The first input terminal and the second input terminal of the second NAND gate are connected to the output terminal of the first NAND gate, and the output terminal of the second NAND gate serves as the negative output terminal of the first RS flip-flop.

5. The level conversion circuit according to claim 1, wherein The second RS flip-flop includes a third NAND gate and a fourth NAND gate; The first input terminal of the third NAND gate serves as the set terminal of the second RS flip-flop, the second input terminal of the third NAND gate is connected to the output terminal of the fourth NAND gate, and the output terminal of the third NAND gate serves as the positive output terminal of the second RS flip-flop; The first input terminal of the fourth NAND gate is connected to the output terminal of the third NAND gate, and the second input terminal of the fourth NAND gate serves as the reset terminal of the second RS flip-flop.

6. The level conversion circuit according to claim 1, wherein The high-level terminals of the first RS flip-flop and the second RS flip-flop are connected to the bootstrap voltage, the low-level terminals of the first RS flip-flop and the second RS flip-flop are connected to the output switch signal voltage, and the bootstrap voltage = the output switch signal voltage + a preset voltage.

7. The level conversion circuit according to claim 1, wherein The level conversion circuit further includes a first diode and a second diode; The positive electrodes of the first diode and the second diode are used to connect to the output switch signal voltage; The negative electrode of the first diode is connected between the positive output terminal of the first RS flip-flop and the set terminal of the second RS flip-flop; The negative electrode of the second diode is connected between the negative output terminal of the first RS flip-flop and the reset terminal of the second RS flip-flop.

8. A power supply chip, characterized in that, The power supply chip includes a third switching transistor, a third driving circuit, a first capacitor, and the level conversion circuit according to any one of claims 1 to 7; The output terminal of the level conversion circuit is connected to the input terminal of the third driving circuit, the output terminal of the third driving circuit is connected to the first terminal of the third switching transistor, the second terminal of the third switching transistor is used to connect to the high-voltage domain electrical signal, and the third terminal of the third switching transistor is used to connect to the subsequent circuit; The low-level terminal of the third driving circuit and one end of the first capacitor are connected to the third terminal of the third switching transistor, and the other end of the first capacitor is connected to the high-level terminal of the third driving circuit; The signal connected to the low-level terminal of the third driving circuit is the output switch signal voltage, and the signal connected to the high-level terminal of the third driving circuit is the bootstrap voltage, where the bootstrap voltage = the output switch signal voltage + a preset voltage; The high-level terminals of the first RS flip-flop and the second RS flip-flop are connected to the bootstrap voltage, and the low-level terminals of the first RS flip-flop and the second RS flip-flop are connected to the output switch signal voltage.

9. An electronic device, characterized in that, Comprising: The power supply chip according to claim 8.

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