Frequency-adjustable reference signal output method and system based on FPGA and medium
Through the FPGA-based adjustable frequency reference signal output method, various frequency reference signals are generated synchronously by FPGA and constant temperature crystal oscillator, solving the problem of low frequency output accuracy, inability to configure and delay adjustment in the prior art, and achieving high-precision and flexible frequency reference signal output.
Patent Information
- Application Number
- CN202411971422.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-18
AI Technical Summary
The prior art has several problems with frequency output, including the lack of reference reference resulting in low output accuracy, single frequency cannot be configured, randomly unacceptable at the rising edge of the clock with 1PPS, and the inability to adjust the output clock delay.
The adjustable frequency reference signal output method based on FPGA is adopted, and the 1PPS reference signal is demodulated by receiving the satellite signal, the constant temperature crystal oscillator is calibrated, and its frequency is synchronized to the satellite. The FPGA is used to synchronize with the local 1PPS according to the received output frequency count value, generating various frequency reference signals.
It realizes flexible output of various frequency reference signals, with synchronization accuracy higher than 10ns, and the rising edge of the clock is aligned with the reference 1PPS, which improves sampling accuracy and can adjust the output delay in both forward and reverse direction.
Smart Images
Figure CN119853673A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of reference signal output, and in particular to an adjustable frequency reference signal output method, system and medium based on FPGA. Background Art
[0002] At present, the time and frequency industry has increasingly higher requirements for time output accuracy. Different application scenarios require different high-precision time frequencies for terminal sampling, including but not limited to 1Hz, 5Hz, 10Hz, 100Hz and 1KHz.
[0003] The industry mostly uses fixed frequency crystals or digital phase-locked loops to configure the corresponding frequency for frequency output, but the generated frequency signal has the following problems: 1. There is no reference benchmark and the output accuracy is not high; 2. The frequency is single and cannot be configured at will; 3. The position of the clock rising edge is random and cannot be aligned with the 1PPS rising edge, affecting the sampling accuracy; 4. The output clock delay cannot be adjusted. Summary of the invention
[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide an adjustable frequency reference signal output method, system and medium based on FPGA.
[0005] The object of the present invention is achieved through the following technical solutions: The first aspect of the present invention provides: a method for outputting an adjustable frequency reference signal based on FPGA, comprising the following steps: S1: The receiver receives satellite signals and demodulates the 1PPS reference signal; S2: The CPU receives the 1PPS reference signal, completes the time difference measurement between the 1PPS reference signal and the local 1PPS, calibrates the constant temperature crystal oscillator, and completes the training of the constant temperature crystal oscillator to synchronize its frequency with the satellite; S3: CPU sends the output frequency count value to FPGA; S4: FPGA uses constant temperature crystal oscillator counting to synchronize the received output frequency count value with the local 1PPS to generate various frequency reference signals.
[0006] Preferably, the CPU is controlled via a serial port or a network port to output the output frequency count value to the FPGA via an SPI bus.
[0007] Preferably, the S4 further comprises the following steps: S41: FPGA converts the received data into serial-to-parallel data and locks it into the register; S42: After receiving the 1PPS synchronization signal, the FPGA clears the current counter. At this time, the adjustable frequency reference signal outputs a high level aligned with the rising edge of the 1PPS synchronization signal. S43: FPGA counts through the constant temperature crystal oscillator. When the count value is equal to the output frequency count value written by the CPU, the adjustable frequency reference signal is output in reverse and the count value is cleared; repeat the execution, and generate alternation of high and low levels at fixed intervals to obtain the required various frequency reference signals.
[0008] Preferably, the frequency of the constant temperature crystal oscillator is 10 MHz.
[0009] Preferably, the CPU adjusts the temperature-controlled crystal oscillator voltage control to achieve ns-level adjustment of the output delay, or the CPU adjusts the 1PPS synchronization signal to achieve us-level adjustment of the output delay.
[0010] Preferably, the output delay adjustment in ns level comprises the following steps: ARM controls the frequency of the constant temperature crystal oscillator through DAC output voltage control. Taking the initial frequency as the reference, when the constant temperature crystal oscillator frequency is adjusted to less than the initial frequency, the adjusted frequency rising edge will gradually move forward. When the constant temperature crystal oscillator frequency is adjusted to return to the initial frequency, the forward-shifted phase is the adjusted phase. Conversely, if the frequency is increased and then restored, the phase will be shifted backward.
[0011] Preferably, the output delay us level adjustment comprises the following steps: The phase of the frequency reference signal is adjusted by adjusting the rising edge phase of the output 1PPS synchronization signal through ARM.
[0012] The second aspect of the present invention provides: an FPGA-based adjustable frequency reference signal output system, used to implement any of the above-mentioned FPGA-based adjustable frequency reference signal output methods, comprising: The CPU is connected to the receiver, the constant temperature crystal oscillator and the FPGA, and the constant temperature crystal oscillator is connected to the FPGA.
[0013] The third aspect of the present invention provides: a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by a processor, any of the above-mentioned FPGA-based adjustable frequency reference signal output methods is implemented.
[0014] The beneficial effects of the present invention are: 1) Various frequency reference signals can be flexibly output.
[0015] 2) The output synchronization accuracy is high, with the accuracy better than 10ns.
[0016] 3) The rising edge of the clock is aligned with the rising edge of the reference 1PPS to improve sampling accuracy; 4) Output delay can be adjusted forward and reverse according to cable delay. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is a flow chart of an adjustable frequency reference signal output method based on FPGA; Figure 2 This is a schematic diagram of S4 signal output; Figure 3 This is a schematic diagram of S43 signal output; Figure 4 This is a schematic diagram of output delay adjustment in ns level; Figure 5 This is the block diagram of the FPGA-based adjustable frequency reference signal output system. DETAILED DESCRIPTION
[0018] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.
[0019] See also Figure 1-Figure 5 The first aspect of the present invention provides: a method for outputting an adjustable frequency reference signal based on FPGA, comprising the following steps: S1: The receiver receives satellite signals and demodulates the 1PPS reference signal; S2: The CPU receives the 1PPS reference signal, completes the time difference measurement between the 1PPS reference signal and the local 1PPS, calibrates the constant temperature crystal oscillator, and completes the training of the constant temperature crystal oscillator to synchronize its frequency with the satellite; S3: CPU sends the output frequency count value to FPGA; S4: FPGA uses constant temperature crystal oscillator counting to synchronize the received output frequency count value with the local 1PPS to generate various frequency reference signals.
[0020] In this embodiment, the CPU sends a specific count value of the output frequency signal to the FPGA via the SPI bus, and the FPGA performs serial-to-parallel conversion on the received SPI data and locks the data into a register.
[0021] In some embodiments, the CPU is controlled via a serial port or a network port to output the output frequency count value to the FPGA via a SPI bus.
[0022] In some embodiments, the S4 further comprises the following steps: S41: FPGA converts the received data into serial-to-parallel data and locks it into the register; S42: After receiving the 1PPS synchronization signal, the FPGA clears the current counter. At this time, the adjustable frequency reference signal outputs a high level aligned with the rising edge of the 1PPS synchronization signal. S43: FPGA counts through the constant temperature crystal oscillator. When the count value is equal to the output frequency count value written by the CPU, the adjustable frequency reference signal is output in reverse and the count value is cleared; repeat the execution, and generate alternation of high and low levels at fixed intervals to obtain the required various frequency reference signals.
[0023] In this embodiment, the output frequency count value cnt for: , where clk is the frequency of the required reference signal, such as Figure 3 As shown, when it is necessary to output a 1KHz frequency reference signal, using a 10Mhz clock count, the CPU needs to write a count value of 5000, and the FPGA counts at 10MHz. When the count value is equal to the register value written by the CPU, the current state is reversed. For example, when the current state is high, when cnt counts = 5000, the high level is reversed to low, and the count is cleared; when cnt counts = 5000 again, the low level is reversed to high, and the count is cleared; in this way, the preset frequency signal can be generated by alternating high and low levels at fixed intervals.
[0024] In some embodiments, the frequency of the constant temperature crystal oscillator is 10 MHz.
[0025] In some embodiments, the CPU adjusts the temperature-controlled crystal oscillator voltage control to achieve ns-level adjustment of the output delay, or the CPU adjusts the 1PPS synchronization signal to achieve us-level adjustment of the output delay.
[0026] In some embodiments, the output delay ns level adjustment comprises the following steps: ARM controls the frequency of the constant temperature crystal oscillator through DAC output voltage control. Taking the initial frequency as the reference, when the constant temperature crystal oscillator frequency is adjusted to less than the initial frequency, the adjusted frequency rising edge will gradually move forward. When the constant temperature crystal oscillator frequency is adjusted to return to the initial frequency, the forward-shifted phase is the adjusted phase. Conversely, if the frequency is increased and then restored, the phase will be shifted backward.
[0027] In this embodiment, if Figure 4 As shown in the figure, the ns-level adjustment is mainly completed through the 10M phase adjustment of the constant temperature crystal oscillator. The constant temperature crystal oscillator frequency will produce a certain frequency deviation as the voltage control changes. ARM controls the crystal oscillator frequency through the DAC output voltage control. When the initial frequency is 10MHz, the constant temperature crystal oscillator frequency is adjusted to less than 10MHz based on the initial frequency. The adjusted frequency rising edge will gradually move forward. When the constant temperature crystal oscillator frequency is adjusted to 10MHz, the forward phase is the adjusted phase. On the contrary, the phase can be shifted backward by increasing the frequency and then restoring it.
[0028] In some embodiments, the output delay us level adjustment comprises the following steps: The phase of the frequency reference signal is adjusted by adjusting the rising edge phase of the output 1PPS synchronization signal through ARM.
[0029] In this embodiment, the us-level adjustment mainly utilizes the 1pps output phase adjustment. Inside the FPGA, 1pps is used as a reference for the rising edge. The output clock will clear the counter when the 1pps rising edge arrives, and the output clock rising edge will be aligned with the 1PPS rising edge. Therefore, ARM adjusts the rising edge phase of the output 1PPS to achieve the adjustment of the frequency reference signal phase.
[0030] The second aspect of the present invention provides: an FPGA-based adjustable frequency reference signal output system, used to implement any of the above-mentioned FPGA-based adjustable frequency reference signal output methods, comprising: The CPU is connected to the receiver, the constant temperature crystal oscillator and the FPGA, and the constant temperature crystal oscillator is connected to the FPGA.
[0031] The third aspect of the present invention provides: a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by a processor, any of the above-mentioned FPGA-based adjustable frequency reference signal output methods is implemented.
[0032] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.
Claims
1. A method for outputting an adjustable frequency reference signal based on FPGA, characterized in that: The following steps are involved: S1: The receiver receives satellite signals and demodulates the 1PPS reference signal; S2: The CPU receives the 1PPS reference signal, completes the time difference measurement between the 1PPS reference signal and the local 1PPS, calibrates the constant temperature crystal oscillator, and completes the training of the constant temperature crystal oscillator to synchronize its frequency with the satellite; S3: CPU sends the output frequency count value to FPGA; S4: FPGA uses constant temperature crystal oscillator counting to synchronize the received output frequency count value with the local 1PPS to generate various frequency reference signals.
2. The method for outputting an adjustable frequency reference signal based on FPGA according to claim 1, characterized in that: The CPU is controlled through the serial port or network port to output the output frequency count value to the FPGA through the SPI bus.
3. The method for outputting an adjustable frequency reference signal based on FPGA according to claim 1, characterized in that: The S4 further comprises the following steps: S41: FPGA converts the received data into serial-to-parallel data and locks it into the register; S42: After receiving the 1PPS synchronization signal, the FPGA clears the current counter. At this time, the adjustable frequency reference signal outputs a high level aligned with the rising edge of the 1PPS synchronization signal. S43: FPGA counts through the constant temperature crystal oscillator. When the count value is equal to the output frequency count value written by the CPU, the adjustable frequency reference signal is output in reverse and the count value is cleared; repeat the execution, and generate alternation of high and low levels at fixed intervals to obtain the required various frequency reference signals.
4. The method for outputting an adjustable frequency reference signal based on FPGA according to any one of claims 1 to 3, characterized in that: The frequency of the constant temperature crystal oscillator is 10 MHz.
5. The method for outputting an adjustable frequency reference signal based on FPGA according to any one of claims 1 to 3, characterized in that: The CPU can adjust the temperature-controlled crystal oscillator voltage control to achieve ns-level adjustment of the output delay, or the CPU can adjust the 1PPS synchronization signal to achieve us-level adjustment of the output delay.
6. The method for outputting an adjustable frequency reference signal based on FPGA according to claim 5, characterized in that: The output delay ns level adjustment comprises the following steps: ARM controls the frequency of the constant temperature crystal oscillator through DAC output voltage control. Taking the initial frequency as the reference, when the constant temperature crystal oscillator frequency is adjusted to less than the initial frequency, the adjusted frequency rising edge will gradually move forward. When the constant temperature crystal oscillator frequency is adjusted to return to the initial frequency, the forward-shifted phase is the adjusted phase. Conversely, if the frequency is increased and then restored, the phase will be shifted backward.
7. The method for outputting an adjustable frequency reference signal based on FPGA according to claim 5, characterized in that: The output delay us level adjustment comprises the following steps: The phase of the frequency reference signal is adjusted by adjusting the rising edge phase of the output 1PPS synchronization signal through ARM.
8. An adjustable frequency reference signal output system based on FPGA, characterized in that: The method for outputting an adjustable frequency reference signal based on FPGA according to any one of claims 1 to 7 comprises: The CPU is connected to the receiver, the constant temperature crystal oscillator and the FPGA, and the constant temperature crystal oscillator is connected to the FPGA.
9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by the processor, the FPGA-based adjustable frequency reference signal output method as described in any one of claims 1 to 7 is implemented.