Clock and data recovery circuit and method for performing clock and data recovery

Abstract

A clock and data recovery circuit includes a frequency tracking loop and a phase tracking circuit. The frequency tracking loop includes an injection locked oscillator configured to adjust an oscillation frequency to generate an output signal, receive an input data signal, and extract an output clock from the input data signal, where the output signal has a frequency tracking a reference clock frequency. The phase tracking circuit is coupled to the frequency tracking loop and includes a phase interpolator and a finite state machine. The phase interpolator is used for receiving an output clock and adjusting the phase of the output clock according to an input program code to generate a sampling clock for sampling a signal to generate an anti-serialized signal. The finite-state machine is coupled to the phase interpolator and is used for outputting the program code to the phase interpolator according to the anti-serialization signal of the multiplexer so as to adjust the phase of the output clock.

Description

Technical Field

[0001] The present invention relates to a clock and data recovery (CDR) circuit, and in particular to a CDR circuit capable of achieving fast locking within a wide bandwidth range. Background Art

[0002] A passive optical network (PON) is a fiber-optic communication technology in which a single optical fiber provides a broadband network accessed from a central office node (also called an optical line terminal (OLT)) to multiple end-users (also called optical network units (ONUs)). A network is called a passive network when there is no power requirement or active electronic components to transmit signals through it. Data is usually transmitted in bursts over the network using high-speed serial links. Since data is transmitted without an accompanying clock, a clock must be extracted from the serial data for further processing.

[0003] Passive optical networks therefore use clock and data recovery circuits to extract a clock from the burst data, where the clock is used to lock the data. Existing clock and data recovery architectures require hundreds to thousands of unit intervals (UI) to achieve lock, but burst data needs to be locked within tens of unit intervals to maintain correct operation.

[0004] In order to solve this problem, the prior art proposes a burst mode clock and data recovery circuit, wherein the burst mode clock and data recovery circuit has multiple independent frequency tracking loops including multiple gated voltage control oscillators (GVCOs). Clock and data recovery is achieved in two steps, wherein the frequency of the clock is tracked in the first step, and the phase lock between the clock and the data is achieved in the second step. This existing burst mode clock and data recovery circuit can achieve a fast lock time to meet the requirements of the optical line terminal standard, but it has a limited control range and cannot support a wide range of data rates.

[0005] Phase interpolator (PI) based clock and data recovery circuits are also based on burst mode, but they use an external clock that is already locked to the target frequency. In this way, no independent frequency tracking loop is required, and phase locking is achieved by a finite element machine for phase tracking. Phase interpolator based clock and data recovery circuits can support a wide range of frequencies, but even the fastest finite element machines still require hundreds of unit intervals to achieve phase lock.

[0006] Therefore, a novel clock and data recovery circuit that can support a wide range of frequencies and achieve fast lock time is highly desired to simultaneously meet the requirements of passive optical fiber networks and optical fiber line terminals. Summary of the invention

[0007] Therefore, one of the objectives of the present invention is to provide a clock and data recovery circuit and a method for performing clock and data recovery to solve the above-mentioned problem.

[0008] According to one embodiment of the present invention, a clock and data recovery circuit is provided. The clock and data recovery circuit includes a frequency tracking loop and a phase tracking circuit. The frequency tracking loop is used to generate an output signal frequency locked with a reference clock, and includes an injection locked oscillator. The injection locked oscillator is used to receive a voltage control signal generated according to the reference clock, adjust an oscillation frequency to generate an output signal, receive an input data signal, and extract an output clock from the input data signal, wherein the output signal has a frequency that tracks the frequency of the reference clock. The phase tracking circuit is coupled to the frequency tracking loop and includes a phase interpolator and a finite state machine. The phase interpolator is coupled to the injection locked oscillator, and is used to receive the output clock and adjust a phase of the output clock according to an input program code to generate a sampling clock for sampling a signal to generate a deserialized signal. The finite state machine is coupled to the phase interpolator, and is used to output a program code to the phase interpolator according to a deserialized signal of a multiplexer to adjust the phase of the output clock. The phase tracking circuit further includes the multiplexer, wherein the multiplexer is coupled to the finite state machine and has a first input for receiving a clock signal and a second input for receiving data. When a selected data signal input to the multiplexer is at a low level, the multiplexer outputs a clock signal to the finite state machine.

[0009] The clock and data recovery circuit further includes a high-gain low-jitter amplifier coupled between the multiplexer and the injection-locked oscillator, wherein when the selected data signal input to the multiplexer is at a low level, the multiplexer outputs a clock signal to the high-gain low-jitter amplifier, and the high-gain low-jitter amplifier amplifies the clock signal and inputs it to the injection-locked oscillator as an input data signal. The high-gain low-jitter amplifier is enabled by an enable signal.

[0010] The clock and data recovery circuit further includes a sampler, a latch and a deserializer. The sampler is coupled between the multiplexer and the phase interpolator, and is used to receive a clock signal and sample the clock signal according to the sampling clock to generate a sampled signal. The latch is coupled between the sampler and the phase interpolator, and is used to latch the sampled signal according to the sampling clock to generate a latched signal. The deserializer is coupled between the latch and the finite state machine, and is used to deserialize the latched signal to generate a deserialized signal, and output the deserialized signal to the finite state machine. The finite state machine generates a program code to the phase interpolator according to a sign of the deserialized signal for adjusting the phase of the output clock in a first direction relative to the deserialized signal, wherein when the sign of the deserialized signal changes, the program code is stored as a first program code, and the finite state machine generates a program code to the phase interpolator according to the sign of the deserialized signal for adjusting the phase of the output clock in a second direction relative to the deserialized signal; and when the sign of the deserialized signal changes, the program code is stored as a second program code, and the finite state machine generates a final program code, wherein the final program code is a sum of the first program code and the second program code divided by two. When the selected data signal is a high level, the multiplexer outputs the second input and the phase interpolator adjusts the phase of the output clock from the injection locked oscillator according to the final program code.

[0011] The frequency tracking loop further includes a frequency detector, a charge pump, a low pass filter and a divide-by-N feedback divider. The frequency detector is used to receive a reference clock and a clock pair, and to generate a plurality of lead or lag signals according to a frequency comparison result between the reference clock and the clock pair. The charge pump is coupled to the frequency detector, and is used to generate and transmit a voltage control signal to the injection locked oscillator according to the plurality of lead or lag signals. The low pass filter is coupled between the injection locked oscillator and the phase interpolator, and is used to perform a low pass filter on the output clock. The divide-by-N feedback divider is coupled between the low pass filter and the frequency detector, and is used to generate a clock pair according to the output clock.

[0012] According to one embodiment of the present invention, a method for clock and data recovery is provided. The method includes: generating a voltage control signal according to a reference clock; adjusting a frequency of an oscillator according to the voltage control signal to generate an output signal, wherein the output signal has a frequency that tracks the frequency of the reference clock; receiving an input data signal and extracting an output clock from the input data signal using an oscillator; sampling the input data signal according to a sampling clock to generate a deserialized signal; generating a program code according to the deserialized signal; and adjusting a phase of the output clock according to the program code to generate the sampling clock.

[0013] The step of receiving the input data signal further includes: when a selected data signal is at a low level, outputting a clock signal; and amplifying the clock signal to generate the input data signal. The method further includes: sampling the clock signal according to the sampling clock to generate a sampled signal; latching the sampled signal according to the sampling clock to generate a latched signal; and deserializing the latched signal to generate a deserialized signal.

[0014] The step of generating a program code according to the deserialized signal includes: generating a program code according to a sign of the deserialized signal for adjusting the phase of the output clock in a first direction relative to the deserialized signal; storing the program code as a first program code when the sign of the deserialized signal changes; generating a program code according to the sign of the deserialized signal for adjusting the phase of the output clock in a second direction relative to the deserialized signal; storing the program code as a second program code when the sign of the deserialized signal changes; and generating a final program code, wherein the final program code is a result of dividing a sum of the first program code and the second program code by two.

[0015] The steps of generating a voltage control signal according to a reference clock include: receiving a reference clock and a clock pair; generating a plurality of leading or lagging signals according to a frequency comparison result between the reference clock and the clock pair; performing a low-pass filter on the output clock; dividing the output clock by N to generate a clock pair; and generating a voltage control signal according to the plurality of leading or lagging signals. When a selected data signal is at a high level, the method further includes: outputting a data signal; and adjusting the phase of the output clock according to the final program code. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. 4 is a schematic diagram of a clock and data recovery circuit according to an embodiment of the present invention.

[0017] Figure 2It is a schematic diagram of the phase relationship among a first clock signal, a first data signal, a second clock signal and a second data signal before phase locking.

[0018] Figure 3 is a flow chart of a method according to an embodiment of the present invention.

[0019] Figure 4A The diagram is a schematic diagram of determining a first edge and a second edge of a second data signal according to a second clock signal.

[0020] Figure 4B After phase locking has been achieved Figure 4A A schematic diagram of a second clock signal and a second data signal is shown. DETAILED DESCRIPTION

[0021] In order to solve the above problems, the present invention provides a burst mode clock and data recovery (CDR) circuit, which uses a frequency tracking loop including an injection locked voltage control oscillator (ILO). In addition, phase locking is achieved during the training phase by a phase interpolator (PI) and a finite state machine (FSM). As a result, the burst mode clock and data recovery circuit of the present invention can support a wide range of frequencies and can achieve phase locking in less than 40 unit intervals (UI).

[0022] Figure 1 FIG. 1 is a schematic diagram of a clock and data recovery circuit 100 according to an embodiment of the present invention. Figure 1 As shown, the clock and data recovery circuit 100 includes a frequency detector (FD) 111 (for simplicity, the Figure 1 FD), charge pump (CP) 113 (for brevity, Figure 1 CP), an injection-locked voltage-controlled oscillator 115 (for simplicity, Figure 1 ), a resistor-capacitor (RC) low pass filter 119 and a divide by N feedback divider 117 .

[0023] The frequency tracking loop is used to track the frequency relative to a reference clock (for simplicity, Figure 1 Initially, only the reference clock is input to the frequency tracking loop, that is, the high gain low jitter amplifier 121 coupled to the injection locked voltage controlled oscillator 115 (for simplicity, in Figure 1 DATA CML2 CMOS) (for brevity, in Figure 1 The frequency detector 111 receives a reference clock which may be generated by an external phase locked loop (PLL) and receives a clock pair CLKI and CLKQ from a divide-by-N feedback divider 117. By comparing the frequencies between the reference clock and the clock pair, the frequency detector 111 may generate and transmit a plurality of up or down signals (for simplicity, in Figure 1 The charge pump 113 may output a voltage control signal VCTRL representing the frequency difference to the injection locked voltage controlled oscillator 115 according to the plurality of advance or lag signals. The oscillation frequency of the injection locked voltage controlled oscillator 115 may be controlled by the voltage control signal VCTRL so that the oscillation frequency of the injection locked voltage controlled oscillator 115 tracks with the frequency of the reference clock. When an enable signal is input to the high gain low jitter amplifier 121, the frequency tracking loop may operate independently.

[0024] During a training mode, the enable signal input to the high-gain low-jitter amplifier 121 switches from a low level (low) to a high level (high), so that the data injected into the injection-locked voltage-controlled oscillator 115 will be input to the multiplexer (MUX) 133 of the clock and data recovery circuit 100 (for simplicity, in Figure 1 A clock signal CLK1 is extracted from the data signal DATA1 and propagated through the frequency tracking loop. The voltage control signal VCTRL controls the oscillation frequency of the injection locked voltage controlled oscillator 115 so that the phase of the extracted clock matches the phase of the reference clock. The clock signal CLK1 is transmitted to the divide-by-N feedback divider 117 and the phase interpolator 123 (for simplicity, the clock signal CLK1 is not shown in FIG. 1 ) via the resistor-capacitor low-pass filter 119. Figure 1 marked as "PI" in the

[0025] An injection locked oscillator is composed of multiple delay stages (like a ring oscillator), where a capacitor is coupled between two of the delay stages. Data is injected into the capacitor, and a control signal representing the frequency of the reference clock is input to a previous delay stage. The output of the delay stage will be an oscillating signal, the purpose of which is to achieve phase lock between the injected data and the extracted clock. When data is injected into the capacitor, the output of the capacitor will be a short pulse, which shorts the output of the previous delay stage, thereby causing the phase of the oscillating signal to shift to align with the data, so the speed of phase locking is quite fast.

[0026] The lower half of the clock and data recovery circuit 100 includes a multiplexer 133 and a receiver (RX) analog front end (AFE) circuit 131, wherein the multiplexer 133 receives a half-rate clock signal from a phase-locked loop (which may be the same phase-locked loop that provides a reference clock to the frequency tracking loop or a different phase-locked loop), the receiver analog front end circuit 131 receives a plurality of RXP / N signals and outputs the plurality of RXP / N signals to the multiplexer 133 as data, and a selected data signal (for simplicity, in Figure 1 The data signal (marked as "SELECT DATA" in the figure) is input to the multiplexer 133. When the data signal = 0 is selected, the multiplexer 133 outputs a half-rate clock (i.e., during the training mode), and when the data signal = 1 is selected, the multiplexer 133 outputs the data (i.e., during normal operation). The output of the multiplexer 133 is input to the high-gain, low-jitter amplifier 121. When the enable signal is high, the high-gain, low-jitter amplifier 121 amplifies the data signal for injection into the injection-locked voltage-controlled oscillator 115. When the enable signal is low, only the frequency tracking loop operates. The reason for using the high-gain, low-jitter amplifier 121 is that data may experience some losses during propagation through a circuit, and if the data signal is not amplified, it may not be possible to effectively short-circuit the outputs of multiple delay stages within the injection-locked voltage-controlled oscillator 115.

[0027] like Figure 1 As shown, the data received by the injection locked voltage controlled oscillator 115 is the data signal DATA1 and the extracted clock is the clock signal CLK1, wherein the data signal DATA1 and the clock signal CLK1 are in Figure 1The clock signal CLK1 is used to sample and latch the data for deserialization and output. The sampling operation and latching operation are respectively performed by a sampler (such as a sense amplifier) ​​141 and a latch 143 (for simplicity, the above description is omitted in the figure). Figure 1 The sampler 141 and the latch 143 both receive the extracted clock signal as input. The sampled data is transmitted to the deserializer 145. However, due to propagation delay, the data (e.g., data signal DATA2) received by the sampler 141 is delayed relative to the data signal DATA1 and is Figure 1 The clock signal CLK2 at point 2 in FIG. 1 is also delayed relative to the clock signal CLK1. In addition, the clock signal CLK2 is out of phase with the data signal DATA2.

[0028] Figure 2 Schematic diagram of the phase relationship between the clock signal CLK1, the data signal DATA1, the clock signal CLK2 and the data signal DATA2 before phase locking. Figure 2 As shown in FIG. 1 , Δ1 is the delay between the starting point of the data signal DATA1 and the starting point of the data signal DATA2, and Δ2 is the delay between the starting point of the data signal DATA1 and the rising edge of the clock signal CLK2. When Δ2 is unknown, it is quite difficult to directly use the clock signal CLK2 to phase lock the data signal DATA2. Therefore, the clock and data recovery circuit 100 uses a phase interpolator 123 and a finite state machine (FSM; for simplicity, the phase interpolator 123 is used in the clock and data recovery circuit 100. Figure 1 The phase interpolator 123 and the finite state machine 125 can be used to shift the clock signal CLK2 relative to the data signal DATA2 to find the two edges of the data. In order to obtain the maximum timing margin, the receiver should be located at the center of the eye diagram of the sampled multiple data bits, that is, the clock edge relative to the multiple data bits determines the performance of the link.

[0029] The phase interpolator 123 receives the clock signal CLK1 from the resistor-capacitor low-pass filter 119, where the clock signal CLK1 is input to the sampler 141 and the latch 143 as the clock signal CLK2 due to propagation delay. The finite state machine 125 receives the deserialized data (i.e., multiple zeros or multiple ones) from the deserializer 145 and is operated by inputting an input program code, where the input program code delays the output of the phase interpolator 123 by one clock. The delay amount is determined by the equation T0+Tp / Ns, where Tp is the clock period and Ns is the number of steps used to control the phase interpolator 123. Two edges of the data signal DATA2 (e.g., edge EDGE1 and edge EDGE2) need to be found, where edge EDGE1 corresponds to the starting point of the data and edge EDGE2 corresponds to the ending point of the data. The finite state machine 125 changes a program code of the phase interpolator 123 to shift the clock signal CLK2 to the left or right to find the two data edges, wherein the two data edges can be determined according to the output of the deserializer 145. If the rising edge of the clock signal occurs when the data signal is at a high level, the deserializer 145 will output multiple 1s. When the edge of the data is reached, the sampled data will shift between multiple 0s and multiple 1s due to jitter. When the clock signal CLK2 is further shifted in the same direction, the sampled signal will become multiple 0s only when the data is at a low level (i.e., the edge has been reached). Therefore, according to the output of the deserializer 145, the finite state machine 125 can know whether an edge of the data has been reached, and store a corresponding program code for shifting the clock signal CLK2 to align with the edge for input to the phase interpolator 123.

[0030] Figure 4A and Figure 4B The diagram shows how the clock signal CLK2 is shifted relative to the data signal DATA2 by the input program code from the finite state machine 125 to find the two edges of the data, and how a resulting program code is generated that can fix the rising edge of the clock signal CLK2 at the center of the eye diagram of the data signal DATA2. Figure 4A It shows how to find the edge of the data signal DATA2 relative to the rising edge of the clock signal CLK2. The finite state machine 125 inputs a program code "--" to perform a left shift operation on the clock signal CLK2 until the edge EDGE1 is found. The program code at this time is stored as program code "A". Then, the finite state machine 125 inputs a program code "++" to perform a right shift operation on the clock signal CLK2 until the edge EDGE2 is found. The program code at this time is stored as program code "B".

[0031] Ideally, the clock signal CLK2 is locked in the middle of the data signal DATA2, so the required program code is "(A+B) / 2" (i.e., the sum of the program code "A" and the program code "B" divided by two) and is input to the phase interpolator 123, which shifts the clock signal CLK2 so that the rising edge of the clock signal CLK2 is directly located in the middle of the data signal DATA2. During normal operation of the clock and data recovery circuit 100, this program code can be used directly, and at this time, the training is completed, and the selected data signal input to the multiplexer 133 can be switched to a high level to output the data from the receiver analog front-end circuit 131.

[0032] Figure 3 is a flow chart of the method according to an embodiment of the present invention.

[0033] In step 300, the power is turned on.

[0034] In step 302, EN=0, SELECT DATA=0, waiting for frequency lock.

[0035] In step 304, it is determined whether the frequency locking is completed, if yes, proceed to step S306; if no, return to step S302.

[0036] In step 306, EN=1, SELECT DATA=0, the phase of the clock and data recovery circuit is locked to the half-rate clock at point 1.

[0037] In step 308, a phase shift operation is performed on the clock and data recovery circuit at point 2 due to propagation delay.

[0038] In step 310 , the finite state machine changes the program code to shift the clock signal CLK2 left / right and find the edge of the data signal DATA2 .

[0039] In step 312, a program code "--" is input.

[0040] In step 314 , it is determined whether edge EDGE1 is found. If so, the process proceeds to step 316 ; if not, the process returns to step 312 .

[0041] In step 316, program code "A" is stored.

[0042] In step 318, program code "++" is input.

[0043] In step 320 , it is determined whether edge EDGE2 is found. If so, the process proceeds to step 322 ; if not, the process returns to step 318 .

[0044] In step 322, program code "B" is stored.

[0045] In step 324, program code "(A+B) / 2" is input.

[0046] In step 326 , the clock signal CLK2 is moved to the center of the data signal DATA2 .

[0047] In step 328, training is completed; SELECT DATA=1; the clock and data recovery circuit is ready to receive the RXP / N signal.

[0048] By means of the clock and data recovery circuit and related method of the present invention, a clock can be extracted and fast locking can be achieved within a wideband rate range, which enables the clock and data recovery circuit of the present invention to be applied to optical fiber communication technology of passive optical fiber networks.

[0049] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0050] Reference numerals

[0051] 100: Clock and data recovery circuit

[0052] 111: Frequency detector

[0053] 113: Charge Pump

[0054] 115: Injection-locked voltage-controlled oscillator

[0055] 117: Divide-by-N Feedback Divider

[0056] 119: Resistor-Capacitor Low-Pass Filter

[0057] 121: High Gain Low Jitter Amplifier

[0058] 123: Phase Interpolator

[0059] 125: Finite State Machine

[0060] 131: Receiver Analog Front-End Circuit

[0061] 133: Multitasker

[0062] 141: Sampler

[0063] 143: Latch

[0064] 145: Deserializer

[0065] REF CLK: Reference clock

[0066] UP: Advance signal

[0067] DOWN: Lagging signal

[0068] VCTRL: voltage control signal

[0069] CLK1, CLK2: clock signal

[0070] DATA1, DATA2: data signal

[0071] EN: Enable signal

[0072] RXP / N: RXP / N signal

[0073] SELECT DATA: Select data signal

[0074] 300, 302, 304, 306, 308, 310, 312, 314, 316, 318, 320, 322, 324, 326, 328: Steps

[0075] EDGE1, EDGE2: Edge

Claims

1. A clock and data recovery circuit, comprising: A frequency tracking loop is used to generate an output signal frequency locked with a reference clock, and comprises: an injection locked oscillator for receiving a voltage control signal generated according to the reference clock, adjusting an oscillation frequency to generate an output signal, receiving an input data signal, and extracting an output clock from the input data signal, wherein the output signal has a frequency that tracks the frequency of the reference clock; and A phase tracking circuit is coupled to the frequency tracking loop and includes: a phase interpolator coupled to the injection locked oscillator and configured to receive the output clock and adjust a phase of the output clock according to an input program code to generate a sampling clock for sampling a signal to generate a deserialized signal; and A finite state machine is coupled to the phase interpolator and is used to output a program code to the phase interpolator according to the deserialized signal of a multiplexer to adjust the phase of the output clock.

2. The clock and data recovery circuit according to claim 1, wherein the phase tracking circuit further comprises: The multiplexer is coupled to the finite state machine and has a first input for receiving a clock signal and a second input for receiving data, wherein when a selected data signal input to the multiplexer is a low level, the multiplexer outputs the clock signal to the finite state machine.

3. The clock and data recovery circuit according to claim 2, further comprising: an amplifier coupled between the multiplexer and the injection locked oscillator; When the selected data signal input to the multiplexer is at a low level, the multiplexer outputs the clock signal to the amplifier, and the amplifier amplifies the clock signal and inputs it to the injection locked oscillator as the input data signal.

4. The clock and data recovery circuit as claimed in claim 3, wherein the amplifier is enabled by an enable signal.

5. The clock and data recovery circuit according to claim 2, further comprising: a sampler coupled between the multiplexer and the phase interpolator and configured to receive the clock signal and sample the clock signal according to the sampling clock to generate a sampled signal; a latch coupled between the sampler and the phase interpolator and used to latch the sampled signal according to the sampling clock to generate a latched signal; and A deserializer is coupled between the latch and the finite state machine and is used for deserializing the latched signal to generate a deserialized signal and outputting the deserialized signal to the finite state machine.

6. The clock and data recovery circuit according to claim 5, wherein the finite state machine generates the program code to the phase interpolator according to a sign of the deserialized signal for adjusting the phase of the output clock in a first direction relative to the deserialized signal; when the sign of the deserialized signal changes, the program code is stored as a first program code, and the finite state machine generates the program code to the phase interpolator according to the sign of the deserialized signal for adjusting the phase of the output clock in a second direction relative to the deserialized signal; and when the sign of the deserialized signal changes, the program code is stored as a second program code, and the finite state machine generates a final program code, wherein the final program code is a result of dividing a sum of the first program code and the second program code by two.

7. The clock and data recovery circuit according to claim 1, wherein the frequency tracking loop further comprises: a frequency detector for receiving the reference clock and a clock pair and generating a plurality of leading or lagging signals according to a frequency comparison result between the reference clock and the clock pair; a charge pump coupled to the frequency detector and used to generate and transmit the voltage control signal to the injection locked oscillator according to the plurality of leading or lagging signals; a low-pass filter coupled between the injection-locked oscillator and the phase interpolator and used for performing low-pass filtering on the output clock; as well as A divide-by-N feedback frequency divider is coupled between the low-pass filter and the frequency detector and is used to generate the clock pair according to the output clock.

8. The clock and data recovery circuit according to claim 6, wherein when the selected data signal is at a high level, the multiplexer outputs the second input and the phase interpolator adjusts the phase of the output clock from the injection locked oscillator according to the final program code.

9. A method for clock and data recovery, comprising: Generating a voltage control signal according to a reference clock; adjusting a frequency of an oscillator according to the voltage control signal to generate an output signal, wherein the output signal has a frequency that tracks the frequency of the reference clock; receiving an input data signal and extracting an output clock from the input data signal using the oscillator; Sampling the input data signal according to a sampling clock to generate a deserialized signal; generating a program code according to the deserialized signal; and A phase of the output clock is adjusted according to the program code to generate the sampling clock.

10. The method according to claim 9, wherein the step of receiving the input data signal further comprises: When a selected data signal is at a low level, a clock signal is output; and The clock signal is amplified to generate the input data signal.

11. The method according to claim 10, further comprising: Sampling the clock signal according to the sampling clock to generate a sampled signal; latching the sampled signal according to the sampling clock to generate a latched signal; and The latched signal is deserialized to generate the deserialized signal.

12. The method according to claim 9, wherein the step of generating the program code according to the deserialized signal comprises: generating the program code according to a sign of the deserialized signal for adjusting the phase of the output clock in a first direction relative to the deserialized signal; When the sign of the deserialized signal changes, storing the program code as a first program code; generating the program code for adjusting the phase of the output clock in a second direction relative to the deserialized signal according to the sign of the deserialized signal; When the sign of the deserialized signal changes, storing the program code as a second program code; as well as A final program code is generated, wherein the final program code is a result of dividing a sum of the first program code and the second program code by two.

13. The method according to claim 9, wherein the step of generating the voltage control signal according to the reference clock comprises: receiving the reference clock and a clock pair; generating a plurality of leading or lagging signals according to a frequency comparison result between the reference clock and the clock pair; Performing low-pass filtering on the output clock; Dividing the output clock by N to generate the clock pair; as well as The voltage control signal is generated according to the plurality of leading or lagging signals.

14. The method according to claim 12, wherein when a selected data signal is at a high level, the method further comprises: outputting a data signal; and The phase of the output clock is adjusted according to the final program code.

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